hwmv2: Introduce Hardware model version 2 and convert devices
This is a squash of the ``collab-hwm`` branch which converts all
in-tree boards to hardware model version 2 including build system
changes, board updates and soc conversions.
This squash is a combination of the following commits:
ca214745a1 soc: Remove soc_legacy folder and move ARM Kconfig
f12cb0979f scripts: ci: check_compliance: remove HWMv1 checks
1807bcf4d4 boards: mimx8mq_evk: port to HWMv2
3ec2299c62 soc: nxp: port imx8mq SOC to HWMv2
8ea02f4e63 boards: verdin_imx8mp: convert to HVMv2
f2eb7652ce boards: phyboard_pollux: move to HVMv2
ab509a5ee0 boards: nxp: mimx8mp_evk: port M7 core to HWMv2
06ad037f99 soc: nxp: imx8mp: port M7 core to HWMv2
3f9e706859 boards: mimx8mm_phyboard: convert to HVMv2
204372d264 boards: imx8mm_evk: port CM4 core to HWMv2
f82c961a46 soc: nxp: imx8mm: port iMX8MM M4 core to HVMv2
6987b2e305 boards: pico_pi: convert to HVMv2
84484e6707 boards: warp7: convert to HWMv2
ae443d1e3c boards: meerkat96: port to HWMv2
e3629c64e6 boards: colibri_imx7d: port to HWMv2
fc835d893d soc: nxp: convert iMX7 Dual core to HWMv2
29ef2f23eb boards: udoo_neo_full: convert to HWMv2
fd49b1749e soc: nxp: convert iMX6 SoloX core to HWMv2
1e59b7a3fd soc: nxp: imxrt11xx: only set
CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION for M7
69bb0eb258 hwmv2: MAINTAINERS: Fix NXP maintainer yaml
1c4458890f boards: firefly: roc_rk3568_pc: Fix SMP configuration
651a4370ad boards: Fix variants and revisions
196cfda66d tests/samples: Drop default revision identifiers
6ec6b1d75a boards: Drop revision from twister identifiers for
default revisions
b774cdd59f scripts: utils: board_v1_to_v2: drop board_legacy prefix
7aa36e6640 boards: riscv: esp32c3_luatos_core: make usb variant
fe25709a9c twister: add unit_testing soc and board
f88f211b4e scripts: ci: check_compliance: improve the "not sorted"
command
b21a455dfb bluetooth: controller: Fix openisa checks
fdc76c48a7 workflow: compliance: Add rename limit
14ecafc67d dts: bindings: vendor-prefixes: Sort entries
dbc366c3c7 soc: nxp: lpc: Move wrong configurations
8e02c08f96 maintainers: Fix invalid paths
b1b85e2495 boards: up: Fix spaces
58cc4013b3 maintainers: Fix xen path
66ce5c0b09 boards/soc: Add missing copyright headers
bb47243254 boards: qemu: x86: Remove pointless file
2e816a8a3a samples: tests: update esp32-based board naming
9aeab17139 samples: tests: remove platform_exclude of esp32 boards
a4fe97b9de boards: shields: m5stack_core2_ext: update board name
615fcab94a samples: ipm_esp32: fix board labels and skip testing
7752f69b7f boards: legacy: remove index entry for xtensa/riscv
boards.
3eba827956 MAINTAINERS: update Espressif entries
914362bbd5 boards: xtensa: yd_esp32: Convert to v2
a62278fd23 boards: xtensa: xiao_esp32s3: Convert to v2
b6a11ccec4 boards: xtensa: olimex_esp32_evb: Convert to v2
c1067c16d2 boards: xtensa: odroid_go: Convert to v2
b8340b0109 boards: xtensa: m5stickc_plus: Convert to v2
9d81e417be boards: xtensa: m5stack_stamps3: Convert to v2
c296672720 boards: xtensa: m5stack_core2: Convert to v2
fada12aa9d boards: xtensa: m5stack_atoms3_lite: Convert to v2
fe37ebac1e boards: xtensa: m5stack_atoms3: Convert to v2
d32828fe6a boards: xtensa: kincony_kc868_a32: Convert to v2
5afba7855b boards: xtensa: heltec_wireless_stick_lite_v3: Convert to
v2
ca48c17723 boards: xtensa: heltec_wifi_lora32_v2: Convert to v2
db1fd4d229 boards: xtensa: esp32s3_luatos_core: Convert to v2
a78b2552eb boards: xtensa: esp32s3_devkitm: Convert to v2
cc96061d96 boards: xtensa: esp32s2_saola: Convert to v2
ed854e05d1 boards: xtensa: esp32s2_lolin_mini: Convert to v2
4fa1ae8110 boards: xtensa: esp32s2_franzininho: Convert to v2
5543040a18 boards: xtensa: esp_wrover_kit: Convert to v2
2335ae79b3 boards: xtensa: esp32_ethernet_kit: Convert to v2
f910b7ad4f boards: xtensa: esp32_devkitc_wrover: Convert to v2
32104db555 boards: xtensa: esp32_devkitc_wroom: Convert to v2
e23a41200d boards: riscv: icev_wireless: Convert to v2
3c670e4e53 boards: riscv: xiao_esp32c3: Convert to v2
fc7c6a060b boards: riscv: stamp_c3: Convert to v2
22c2edb89c boards: riscv: esp32c3_luatos_core: Convert to v2
0a96dcb778 boards: riscv: esp32c3_devkitm: Convert to v2
be1ee1c446 vendors: update vendors lists
5e6c62137f soc: espressif_esp32: Port to HWMv2
037a3b52a4 boards: Raspberry Pi pico pwm led adjustment
7277cae6fa samples: blinky_pwm: enable pwm_leds in rpi_pico overlay
da3e49d34e boards: nxp: update selection of
FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
bc8424dd3b soc: nxp: imxrt: move FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
to SOC level
041cb52939 soc: brcm: bcm_vk: Rename to bcnvk
576b43a95c soc: Fix SOC_FAMILY name mismatches
e8f3e6494d hwmv2: boards: intel: adsp: Fix runner after paths
renamed
550399e927 boards: weact: stm32g431_core: Add wrongly deleted file
back
08708c909e tests: drivers: flash: Renamed missed board rename
06dac41e68 hwmv2: Convert Seagate Faze board to hwmv2
dd8f842b40 hwmv2: nxp: update MAINTAINER paths for hwmv2
b4d1c04978 hwmv2: lpc: updated overlay and conf files in samples and
tests
067c69089e boards: nxp: convert lpcxpresso55s69 to hwmv2
097205b40a hwmv2: Global fix of lpc54114_m4 overlay and conf files
d8cfa6fb29 boards: nxp: convert lpcxpresso54114 to hwmv2
c29ed228c6 boards: nxp: convert lpcxpresso55s36 to hwmv2
88cfd3d6ac boards: nxp: convert lpcxpresso55s28 to hwmv2
ad30c940ee boards: nxp: convert lpcxpresso55s16 to hwmv2
9e5a10ec80 boards: nxp: convert lpcxpresso55s06 to hwmv2
5650c83268 boards: nxp: convert lpcxpresso51u68 to hwmv2
82cf44be45 boards: nxp: convert lpcxpresso11u68 to hwmv2
1a9c405a6f soc: nxp: convert LPC SOC family to hardware model V2
f2b536d253 boards: intel: doc: hwmv2: Fix some renamed paths
5ee6058710 samples/tests: Use board revisions
b76687602f boards: Add yaml files for boards missing revisions
32ae4918d0 boards: nordic: Fix board names
cc1dabca65 MAINTAINERS: Update for renamed folders
a37ddce659 soc: xilinx: Rename to xlnx
a1393a07f6 soc: xenvm: Rename to xen
813ed00f67 soc: raspberry_pi: Rename to raspberrypi
71317d6798 soc: cadence: Rename to cdns
8cb0c51ec6 soc: broadcom: Rename to brcm
2b9db15c69 soc: andes: Rename to andestech
0101216ce1 soc: altera: Rename to altr
4b4c3ca65d boards: wurth_elektronik: Rename to we
cdc3ef499f boards: ublox: Rename to u-blox
cabdd4ad05 boards: space_cubics: Rename to sc
4b5bd7ae8a boards: seeed_studio: Rename to seeed
a992785ceb boards: raspberry_pi: Rename to raspberrypi
3c1cdc20fe boards: laird_connect: Rename to lairdconnect
291c7cde2b boards: cadence: Rename to cdns
95db897526 boards: broadcom: Rename to brcm
0a47b94879 boards: beagleboard: Change to beagle
9f9f221c24 boards: andes: Rename to andestech
e7869ca38a boards: altera: Rename to altr
bf2fb5eca3 various: Change SOC_FAMILY_NRF to SOC_FAMILY_NORDIC_NRF
e25730ba56 modules: tf-m: Rename from nordic_nrf to nordic
9e3466606a boards: nordic_nrf: Rename to nordic
09a398dcc8 soc: nordic_nrf: Rename to nordic
cb8ffc74f8 boards: renode: Add documentation index
2291ff4b55 boards: arm: riscv32_virtual: Convert to v2
484b7f1996 soc: riscv_renode_virtual: Port to HWMv2
cc5c2fb0c7 soc: raspberry_pi: Fix SOC_SERIES and SOC mismatch
59cb580513 soc: arm: designstart: Fix SOC_SERIES and SOC mismatch
aa9e0de7af samples: Fix invalid links
a1480cf1cf maintainers: Fix paths
0d719e004b boards: Update documentation links
eb5c3e6f79 boards: wurth_elektronik: Drop duplicate prefix
a34a3640b7 boards: waveshare: Drop duplicate prefix
cf50e950e7 boards: weact: Drop duplicate prefix
737cfb548f boards: sparkfun: Drop duplicate prefix
505494c97a boards: segger: Drop duplicate prefix
4eaf69f37a boards: ruuvi: Drop duplicate prefix
a1335caeae boards: ronoth: Drop duplicate prefix
a9f7f30bf6 boards: raytac: Drop duplicate prefix
80db4c81b3 boards: qemu: Drop duplicate prefix
433d7e9976 boards: particle: Drop duplicate prefix
4ea79d19e7 boards: olimex: Drop duplicate prefix
fd4ae6f6a8 boards: mikroe: Drop duplicate prefix
36080549bd boards: khados: Drop duplicate prefix
169bf8ae1d boards: intel: Drop duplicate prefix
25f04d5222 boards: holyiot: Drop duplicate prefix
11c2af0de8 boards: google: Drop duplicate prefix
d5128f4016 boards: ebyte: Drop duplicate prefix
44fbc68cad boards: dragino: Drop duplicate prefix
f7fe431b44 boards: contextual_electronics: Drop duplicate prefix
9094fea63b boards: circuit_dojo: Drop duplicate prefix
b632acc1fc boards: blue_clover: Drop duplicate prefix
1a3316ebdc boards: bbc: Drop duplicate prefix
71c0344f8c boards: arduino: Drop duplicate prefix
f0176fc25f boards: altera: Drop duplicate prefix
36b920ed0f boards: adi: Drop duplicate prefix
22520368d9 boards: adafruit: Drop duplicate prefix
296acfb2bc boards: actinius: Drop duplicate prefix
55063380b7 boards: 96boards: Drop duplicate prefix
1f93394b55 boards: nxp: convert mimxrt595_evk to hardware model v2
e7a4fd2ec1 soc: nxp: rt5xx: convert RT5xx SOC to HWMv2
01942f1d11 twister: normalize platform name when storing files/data
477c8b84dd twister: tests: test with slashes in platform names
64e3e816c4 soc: Add include guards
3a7aa2fa49 gitignore: update the compliance file list
84e1c17ad9 scripts: ci: check_compliance: add a check for board yml
file
a90f53ad57 boards: sync up the vendor tags and vendor-list
af9aa65299 dts: vendor-prefixes: add keep-sorted markers
50f0bf05a3 dts: vendor-prefixes: sort the vendor list
a10b614aa4 dts: vendor-prefixes: ensure all prefixes are lowercase
5abe735e93 manifest: update SOF sha for NXP HWMv2
9ab8f64ca9 modules: rename SOC_FAMILY_IMX
483ff8dd4d modules: mcux: remove SOC_FAMILY_NXP_ADSP
f113dd5342 samples: update board name
39b31287d9 boards: nxp: Convert i.MX ADSP boards to hardware model
v2
1511e356a2 soc: nxp: Port i.MX ADSP family to hardware model v2
c91e25ab47 soc: mec: rename all mec1501x reference to mec15xx
1c231fd939 hwmv2: boards: Convert IMXRT boards
417cff1e60 hwmv2: soc: Port IMXRT family to HWMV2
28d4e41b1b hwmv2: clean up arm64 soc and board empty directory
2b520f83cb hwmv2: port NXP SoC LS1046A to V2
bf7899c645 hwmv2: port nxp_ls1046ardb board to V2
33f7b61866 samples/tests: Rename numaker boards
8f20ea6e93 boards: nuvoton: numaker_pfm: Split into 2 boards
7cf4ff43a1 drivers: pinctrl: imx: align with hwm v2
c68e1fea4e drivers: clock_control: ccm_rev2: align with hwm v2
update
3b49014a0f hwmv2: move imx8mn EVK board to V2
14f344eeab hwmv2: move imx8mp EVK board to V2
40f3f8f22d hwmv2: move imx8mm EVK board to V2
10bf79ea51 hwmv2: move imx8m soc for a-core to V2
8727d5ca80 hwmv2: move imx93 EVK board to V2
c81ef01563 hwmv2: move imx93 soc to V2
5836c1b699 modules: mcux: introduce CONFIG_MCUX_CORE_SUFFIX
338f6f2bf1 doc: update board porting guide to match new hardware
model
9639a1b5dc soc: silabs: drop useless defconfigs
981807444e soc: silabs: introduce SOC_GECKO_SDID
5d07e82485 soc: silabs: SOC_FAMILY_* replace SOC_GECKO_SERIES*
2fd081ac86 soc: silabs: align comments with soc tree
66d425f571 soc: silabs: split in families
5bd38f47a9 arch: arch: kconfig: Fix wrong placement of endmenu
00c6ef25be tests/samples: Rename overlay files for renamed boards
0c639b8378 boards: Fix bools and selections
c2ef907d1d drivers: flash: it8xxx2: Add missing Kconfigs
553de2ebc9 soc: ite: ec: it8xxx2: Fix SOC_SERIES being in wrong file
b8ec0080c2 boards: Documentation link fixes
eb7025e50f tests: Update board names for hwmv2
10ef3d4bd2 boards: silab: Add documentation index file
ba9fdaa1d6 boards: arm: efr32_radio: Convert to v2
86c8d4a0ca boards: arm: efm32pg_stk3402a: Convert to v2
575ac5cafb manifest: Update hal_silabs
87b2907304 boards: arm: efr32_thunderboard: Convert to v2
14b30055ab boards: arm: efr32mg_sltb004a: Convert to v2
0012bfc15d boards: arm: efr32xg24_dk2601b: Convert to v2
f526225ead boards: arm: efm32wg_stk3800: Convert to v2
19e7df29df boards: arm: efm32pg_stk3401a: Convert to v2
0bd7d963d6 boards: arm: efm32hg_slstk3400a: Convert to v2
795a90f9bf boards: arm: efm32gg_stk3701a: Convert to v2
43d5540be7 boards: arm: efm32gg_slwstk6121a: Convert to v2
065148d856 boards: arm: efm32gg_sltb009a: Convert to v2
1dc9a8aa17 soc: silabs_exx32: Port to HWMv2
763571e878 tests: Expand names
dae301b8a3 boards: xen: xenvm: Expand name
19e60eef36 boards: qemu: qemu_cortex_a53: Expand names
a0a7c30f28 soc: intel: intel_adsp: Fix issues
df9a4223fe scripts: ci: introduce soc name check in check_compliance
ed401abaff soc: emsdsp: align SoC name defined in soc.yml to Kconfig
SOC setting
fc78e5eaa4 MAINTAINERS: update RISC-V arch area paths
4e586958ff boards: convert QEMU RISC-V 64 bit board to Zephyr HWMv2
f4c31a2b86 boards: convert QEMU RV32E board to Zephyr HWMv2
5b2ffc652b boards: convert QEMU RISC-V 32 bit board to Zephyr HWMv2
5db061a4c6 soc/riscv: convert the QEMU virt RISCV-32 SoC to HWMv2
6547845e9d boards: convert SparkFun RED-V Things Plus to Zephyr
HWMv2
95a1f96399 boards: convert SiFive HiFive Unmatched to Zephyr HWMv2
e563eb0a62 soc/sifive/sifive_freedom: add SiFive Freedom FU740 SoC
8914bc58b6 boards: convert SiFive HiFive Unleashed to Zephyr HWMv2
7e8de1e781 soc/sifive/sifive_freedom: add SiFive Freedom U540 SoC
bfcc2ed18f boards: convert SiFive HiFive1 Rev. B to Zephyr HWMv2
330fc38f9f boards: convert SiFive HiFive1 to Zephyr HWMv2
b9e06f4c38 soc/sifive/sifive_freedom: add SiFive Freedom E310 SoC
4b90b30b9d scripts: west_commands: completion: Add hwmv2 complete to
fish
0f6842e2fa scripts: west_commands: completion: Add hwmv2 complete to
zsh
b2af1e1737 scripts: west: list_boards: Fix hwmv2 output
686a4b78b8 scripts: west_commands: completion: Add hwmv2 complete to
bash
396b6bb856 soc: nxp: fix typo in SoC name
765299c627 soc: broadcom: align SoC names defined in soc.yml to
Kconfig SOC setting
7efd46eb41 soc: arm: align SoC names defined in soc.yml to Kconfig
SOC setting
505cbc5c42 soc: mec: align SoC names defined in soc.yml to Kconfig
SOC setting
951a140701 soc: ti: define SOC name in Kconfig
a795d28810 snippets: Initial HWMv2 support
f9a957e6f6 boards: nordic: nrf9160dk: Fix missing nrf52840 config
df994e7ee8 soc: xilinx: zync7000: Remove xilinx from soc series name
8dfabd56ca soc: cypress: Add protection guard to file
447b951593 tests: kernel: tickless: Remove old board name
bad5dfa71f boards: nordic: nrf5340dk: Fix board names
ad2e863f39 soc: atmel: Use new family prefix
3f08e714b2 soc: intel_adsp: hwmv2: Align SOC_SERIES_INTEL_ACE name
and value
6734597a76 soc: intel_adsp_cavs: hwmv2: Align SOC_SERIES name and
value
2908af0bcc boards: nrf51dk/dongle: change SoC to nRF51822
d1ceb29fca soc: align CONFIG_SOC values to match soc.yml names
4768ccaf70 tests: drivers: gpio: gpio_api_1pin: exclude hifive1
ebdb0879ad boards: nxp: s32z2xxdc2: convert to hwmv2
ae82580d08 boards: nxp: mr_canhubk3: convert to hwmv2
c5f0defbae boards: nxp: ucans32k1sic: convert to hwmv2
1e46cabce6 soc: nxp: convert NXP S32 family to hwmv2
f2f85133f2 soc: stm32: Rename series path
86642f4e78 soc: stm32: Rename Kconfig SOC_SERIES symbols
c61e807896 soc: stm32: Cleanup Kconfig.defconfig files
ca46c8abc9 tests: Fix board names
fbfed5f48f maintainers: Update synopsys entries
8cd8b1cc47 boards: synopsys: Add documentation index
6f6cc57a04 boards: arc: hsdk4xd: Convert to v2
c4c14a54ca soc: snps_arc_hsdk4xd: Port to HWMv2
06c2054e5c boards: arc: iotdk: Convert to v2
ff0e0fce1b soc: snps_arc_iot: Port to HWMv2
334264c46a boards: arc: emsdp: Convert to v2
8b947a0e91 soc: snps_emsdp: Port to HWMv2
990417bbde tests: Update board names for hwmv2
e12719154a boards: arc: em_starterkit: Convert to v2
437a430fbe soc: snps_emsk: Port to HWMv2
f93387f968 boards: arc: hsdk: Convert to v2
1cf2498b13 soc: snps_arc_hsdk: Port to HWMv2
47abe81256 boards: arc: nsim: Convert to v2
1e33786dc4 soc: snps_nsim: Port to HWMv2
7f081914db boards: arc: qemu_arc: Convert to v2
bc97349dbd soc: snps_qemu: Port to HWMv2
a9902ff58e boards: Use zephyr_file for file links
126e1a4e72 boards: Fix invalid documentation links
899f0257c3 boards: stm32wb: Restore missing .defconfig files
790c10b1ee soc: x86/atom: imply mmu, do not select it
faee62088d boards: x86: remove qemu_x86_tiny_768
c34d186a57 x86: atom: remove soc.h with unused content
1be3a9e9d3 x86: remove legacy ia32, use atom instead
60e6b400f9 boards: qemu: move qemu_x86 -> x86
c4fbac27e8 boards: infineon: Add documentation index
b4dd29a9c4 maintainers: Update paths for hwmv2
380f5fdb2b boards: cypress: Add documentation index
9de981be05 boards: arm: xmc47_relax_kit: Convert to v2
6394e8a348 boards: arm: xmc45_relax_kit: Convert to v2
04dbf17e19 soc: xmc_4xxx: Port to HWMv2
c9731f1bce boards: arm: cy8cproto_063_ble: Convert to v2
53d41869d1 boards: arm: cy8cproto_062_4343w: Convert to v2
46c4f01427 boards: arm: cy8ckit_062s4: Convert to v2
d285e19cf2 boards: arm: cy8ckit_062_wifi_bt: Convert to v2
2bebd7298c boards: arm: cy8ckit_062_ble: Convert to v2
af243274c2 soc: psoc6 and psoc_6: Port to HWMv2
105a2bae84 cmake: modules: boards: Fix board deprecation for HWMv2
dca54e000a cmake: modules: boards: Enhance board aliases for HWMv2
fc314e8e3f cmake: modules: boards: Fix BOARD_ALIAS
9a7c2ce6d5 soc: gaisler: Move Kconfig file
1ac56d0501 soc: soc_legacy: mips: Remove out file
c054381a7a boards: adjust few boards/ paths
4d93b8d9fd boards: convert all microchip MEC boards to hwmv2
ab2fcb1245 soc: convert microchip_mec to hwmv2
ead4b57a7b soc: arm64: intel_socfpga: hwmv2: Rename SoCs
d4c143d306 MAINTAINERS: intel_socfpga: Adjust to HWMv2 move
70a66ac03a boards: arm64: intel_socfpga: Move boards to
subdirectories
8a85c07799 boards: arm64: intel_socfpga_agilex5_socdk: move to HWMv2
8c253a99fc boards: arm64: intel_socfpga_agilex_socdk: move to HWMv2
ab883b8019 soc: arm64: intel_socfpga: Move and convert to HWMv2
7c8b7a153b soc: arm: intel_socfpga_std: Rename with HWMv2
8dc2b911f6 soc: board: intel_socfpga_std: Align names to 'Cyclone V'
402366117a soc: arm: intel_socfpga_std: Align board subdirectory
f0a8d12745 boards: arm: cyclonev_socdk: Move to HWMv2
2271f17a86 soc: arm: intel_socfpga_std: Move and convert to HWMv2
841c2a9d99 boards: riscv: beaglev_fire: Convert to v2
3b314531ab boards: riscv: mpfs_icicle: Convert to v2
d4ea2bf70b boards: riscv: m2gl025_miv: Convert to v2
5256e9fcc3 soc: microchip_miv: Port to HWMv2
18e5cf1d51 maintainers: Update path for hwmv2
eab8628f98 boards: arm: qemu_cortex_m3: Convert to v2
1532f2fee1 soc: ti_lm3s6965: Port to HWMv2
430ca6a475 maintainers: Update ambiq paths
a9b9b41b91 boards: ambiq: Add index
db0271ecbb boards: arm: apollo4p_blue_kxr_evb: Convert to v2
957e2b2061 boards: arm: apollo4p_evb: Convert to v2
5a90a44454 soc: ambiq: Port to HWMv2
a20c113fbd boards: nxp: convert ip_k66f to hwmv2
34e3852a54 boards: nxp: convert usb_kw24d512 to hwmv2
20ad604de6 boards: nxp: convert twr_kv58f220m to hwmv2
2e2a7b7656 boards: nxp: twr_ke18f: convert to hwmv2
f7dcc2eb5e boards: nxp: convert rddrone_fmuk66 to hwmv2
b58e90a2e9 boards: nxp: convert hexiwear to hwmv2
aae6e9e454 boards: nxp: frdm_kw41z: convert to hwmv2
1d3baac2d6 boards: nxp: convert frdm_kl25z to hwmv2
3b1d21483f boards: nxp: frdm_k82f: port to hwmv2
6046e6ded9 boards: nxp: port frdm_k64f to hwmv2
0a7bf9fd79 boards: nxp: port frdm_k22f to hwmv2
dce697c823 boards: nxp: add toctree placeholder
666a353409 soc: nxp: kinetis: convert kinetis SOC family to hardware
model V2
89f0a6034b maintainers: Update paths for renesas boards/socs
004bd43c48 tests/samples/snippets: Update board names for hwmv2
a6d756923d boards: arm and arm64: rcar_h3ulcb: Convert to v2
3801216b8d boards: arm64: rcar_salvator_xs_m3: Convert to v2
b7cc30aaea boards: arm: rcar_h3_salvatorx_cr7: Convert to v2
866427ea29 boards: arm: arduino_uno_r4: Convert to v2
2689b3f0ee soc: ra: Port to HWMv2
e7ebc727c8 boards: arm: da1469x_dk_pro: Convert to v2
903265b2bb boards: arm: da14695_dk_usb: Convert to v2
529a78ed51 soc: smartbond: Port to HWMv2
97cf636ae0 boards: arm: rcar_spider_cr52: Convert to v2
6d0c53f3a1 soc: rcar: Port to HWMv2
44e0aa0668 soc: renesas: rzt2m: Move folder structure for more SoCs
85238fc205 boards: misc: Fixed STM32 based boards doc links
dffc08af56 boards: riscv: niosv_m: move and convert to HWMv2
545093abe4 boards: riscv: niosv_g: move and convert to HWMv2
ecfa192f1b soc: riscv: intel_niosv: move and convert to HWMv2
fd1e8cdc30 hwmv2: sof: intel_adsp: submanifest provisional link
8bf067e625 doc: boards: intel_adsp: Re-order pages
4833275ccd MAINTAINERS: intel_adsp: Adjust to HWMv2 move
b9a70e5ea2 soc: intel_adsp: tools: pylint compliance workaround
18c70cc4bf hwmv2: tests: boards: intel_adsp: Adjust board names
ca52baf9de hwmv2: boards: intel_adsp: Overhaul board configurations
d1b3bcce64 soc: boards: xtensa: intel_adsp_ace: Rename with HWMv2
f362a8ae2c doc: soc: boards: intel_adsp_cavs25: Rename with HWMv2
51dee5da92 tests: samples: boards: intel_adsp_cavs25: Rename with
HWMv2
e66c35e0d0 boards: xtensa: intel_adsp_cavs25: Rename board with
HWMv2
d1491a4810 soc: boards: xtensa: intel_adsp_cavs25: Rename with HWMv2
fa0fca79c4 scripts: west: runners: intel_adsp: Adjust path to HWMv2
acd18bfaf7 boards: xtensa: intel_adsp_ace20_lnl: move and convert to
HWMv2
546c94b958 boards: xtensa: intel_adsp_ace15_mtpm: move and convert
to HWMv2
8aab718c3e boards: xtensa: intel_adsp_cavs25_tgph: change to board
variant
30f17424a4 boards: xtensa: intel_adsp_cavs25: move and convert to
HWMv2
35a97cb524 soc: xtensa: intel_adsp: HWMv2 workaround for SOF config
fdc20fdff6 soc: xtensa: intel_adsp: move and convert to HWMv2
22dc2b6391 cmake: improved board handling for revisions
2f1e33a2e6 cmake: improve arch error message for invalid arch
selection
c47c37d3db sample: basic: blinky_pwm: Exclude rpi_pico w variant
7a788b9a18 boards: raspberry_pi: rpi_pico: Use full name for w
variant
7046b92d41 tests: atmel_sam: adc: Fix sam4e_xpro adc build
253ee9638c tests: atmel_sam0: Update platform name
ccb4c63324 samples: atmel_sam0: Update platform name
2d4acf9230 boards: arduino_nano_33_iot: Convert to HWMv2
a60d28969a boards: arduino_mkrzero: Convert to HWMv2
0409e51d3f boards: arduino_zero: Convert to HWMv2
1b2528df1b boards: wio_terminal: Convert to HWMv2
af1096e7ca boards: ev11l78a: Convert to HWMv2
0b1db9c53d boards: adafruit_trinket_m0: Convert to HWMv2
e9874671e2 boards: adafruit_itsybitsy_m4_express: Convert to HWMv2
ba6c014071 boards: adafruit_grand_central_m4_express: Convert to
HWMv2
33ad4a51ca boards: adafruit_feather_m0_lora: Convert to HWMv2
9812f3d54e boards: adafruit_feather_m0_basic_proto: Convert to HWMv2
c76b1fbeca boards: serpente: Convert to HWMv2
649789e433 boards: seeeduino_xiao: Convert to HWMv2
6b3bdb7364 boards: same54_xpro: Convert to HWMv2
93dda5ee4b boards: samr34_xpro: Convert to HWMv2
e48e1f5d5b boards: samc21n_xpro: Convert to HWMv2
f11cf73df1 boards: saml21_xpro: Convert to HWMv2
ac73ed6dcd boards: samd20_xpro: Convert to HWMv2
0fdbe3552e boards: samd21_xpro: Convert to HWMv2
854cff3905 boards: samr21_xpro: Convert to HWMv2
a87ea5bc0a soc: atmel: sam0: Port to HWMv2
706e5d27cd boards: riscv: neorv32: Convert to v2
d1edcdd088 soc: neorv32: Port to HWMv2
0f7add89ca boards: native_sim/posix: Add 64bit versions as variants
b6edad8d68 soc: soc_legacy: remove the arm/st_stm32 folder
c58e0822a6 boards: Convert nucleo_f207zg to HWM v2
b987093a80 soc: v2: stm32: Migrate STM32F2 series
2096fd4652 samples: bluetooth: hci_uart: Fix wrongly converted board
names
830f9c5a82 MAINTAINERS: Update Atmel entries
527cd9d8cd CODEOWNERS: Update Atmel entries
83af7d0c1c samples: atmel_sam: Update platform name
fd9b84d457 tests: atmel_sam: Update platform name
3c72fe863c boards: arduino_due: Convert to HWMv2
37dfacbf9e boards: RoboKit1: Convert to HWMv2
1108d7b0ed boards: sam_v71_xult: Convert to HWMv2
bed44a5c28 boards: sam_e70_xplained: Convert to HWMv2
40448c5a9f boards: sam4s_xplained: Convert to HWMv2
31273692c0 boards: sam4l_ek: Convert to HWMv2
35b5d33ef0 boards: sam4e_xpro: Convert to HWMv2
3b84b9910a soc: atmel: Port SAM family to HWMv2
da00d0e7b9 boards: Convert nucleo_wba55cg to HWM v2
fb2103f89e boards: Convert nucleo_wba52cg to HWM v2
1f9a533fbc soc: st: stm32: Migrate STM32WBA series
3f92f65b28 boards: fix documentation for alientek and blues boards
7646b74aaf boards: stm32l4: doc: add zephyr_file to defconfig path
fea54ddcd9 boards: Convert adi_eval_adin2111ebz to HWM v2
d47f1878b1 boards: Convert adi_eval_adin1110ebz to HWM v2
ae42be236b boards: Convert swan_r5 to HWM v2
83bd1a9ecc boards: Convert stm32l4r9i_disco to HWM v2
39c26f09ed boards: Convert stm32l496g_disco to HWM v2
29d03c970b boards: Convert stm32l476g_disco to HWM v2
74acec315c boards: Convert sensortile_box to HWM v2
fee6d8676e boards: Convert pandora_stm32l475 to HWM v2
008b5d9392 boards: Convert nucleo_l4r5zi to HWM v2
24e357d623 boards: Convert nucleo_l4a6zg to HWM v2
2c5f9dcce0 boards: Convert nucleo_l496zg to HWM v2
4da061646f boards: Convert nucleo_l476rg to HWM v2
15956a69b8 tests: drivers: flash: stm32: update platform name
80324f7707 boards: Convert nucleo_l452re_p to HWM v2
9893e0d111 boards: Convert nucleo_l452re to HWM v2
46f92b227b boards: Convert nucleo_l433rc_p to HWM v2
ed5d1bb4cd boards: Convert nucleo_l432kc to HWM v2
325f95ec20 boards: Convert nucleo_l412rb_p to HWM v2
d055676307 boards: Convert disco_l475_iot1 to HWM v2
c7a415d92c boards: Convert b_l4s5i_iot01a to HWM v2
d15144f582 soc: st: stm32: Migrate STM32L4 series
a63ff71bcb boards: nrf_bsim: Add new nrf5340 board definitions
b53c6f412c boards: nrf_bsim: Remove redundant option setting
83eb4fc069 MAINTAINERS: intel_ish: Adjust to HWMv2 move
715685b19f boards: x86: intel_ish: move and convert intel_ish boards
to HWMv2
5b9ef94106 soc: x86: intel_ish: move and convert to HWMv2
12b297707a boards: Convert stm32wb5mmg to HWM v2
cdcea932bc boards: Convert stm32wb5mm_dk to HWM v2
0a3ae2b223 boards: Convert nucleo_wb55rg to HWM v2
20b4ce17d5 soc: st: stm32: Migrate STM32WB series
47c65400d6 soc: st: stm32: fix stm32l0 family
59ec56f9e6 boards: Convert stm32h573i_dk to HWM v2
dc5977dbba boards: Convert nucleo_h563zi to HWM v2
a6e4928543 soc: st: stm32: Migrate STM32H5 series
99f248e048 soc: stm32u5: Fix references after conversion to hw
modelv2
15f16834e6 boards: Convert stm32u5a9j_dk to HWM v2
c1ee449ef1 boards: Convert sensortile_box_pro to HWM v2
db4deddf9d boards: Convert nucleo_u5a5zj_q to HWM v2
2fd3ed43d2 boards: Convert nucleo_u575zi_q to HWM v2
902fceb173 boards: Convert b_u585i_iot02a to HWM v2
d716ca1a10 soc: st: Migrate stm32u5 series to new hw model
b7abc89428 hwmv2: boards: x86: doc: Adjust common docs to new
locations
69b334f54b MAINTAINERS: Change paths to native and nrf*bsim boards
614611a528 boards: nrf*_bsim: Convert to HW model v2
5821b9ec2e board: native_sim/posix: Convert to hwmv2
04cbad174e soc: native: Convert to HWMv2
24ca0febfc boards: nrf_bsim: Fix path to pinctrl_soc.h
9a32559a2d cmake: FindHostTools: Fix for hwmv2 for host based
targets
c4b11e0251 boards: longan_nano: port to HWMv2
97edd05be3 boards: gd32vf103c_starter: port to HWMv2
9cf624c410 boards: gd32vf103v_eval: port to HWMv2
b40bf25e5e soc: gd_gd32: reorganize folders
71600d7e95 soc: gd_gd32: move pinctrl_soc.h content back to soc
folder
2bd84a1bc5 soc: gd_gd32: port gd32vf103 series to HWMv2
9dc342143b boards: doc: fix a bunch of broken reference
10392d693d doc: boards: split out shields
b2def8ed3a boards: acrn: fix title
bf7d3efe78 boards: riscv: tlsr9518adk80d: Convert to v2
c579770e1d soc: telink_tlsr: Port to HWMv2
9131540109 soc: stm32h7: Couple of tests fixes following migration
2efcefc089 boards: Convert stm32h7b3i_dk to HWM v2
d9b295a85b boards: Convert stm32h750b_dk to HWM v2
a2f56bdcd5 boards: Convert stm32h747i_disco to HWM v2
00314155df boards: Convert stm32h735g_disco to HWM v2
b08819dff7 boards: Convert nucleo_h7a3zi_q to HWM v2
56456c16e5 boards: Convert nucleo_h753zi to HWM v2
91f9198dc4 boards: Convert nucleo_h745zi_q to HWM v2
96f1bafbf9 boards: Convert nucleo_h743zi to HWM v2
b290f25baa boards: Convert nucleo_h723zg to HWM v2
9fbe6bf191 boards: Convert fk7b0m1_vbt6 to HWM v2
44bcfe57c7 boards: Convert arduino_portenta_h7 to HWM v2
4c86af7eae boards: Convert arduino_opta_m4 to HWM v2
b4f852f738 boards: Convert arduino_giga_r1 to HWM v2
bac9789264 soc: st: Migrate stm32h7 series to new hw model
a954e1722d boards: stm32l0: Cleanup board _defconfig files after
migration
7e8515b241 boards: Convert ronoth_lodev to HWM v2
25246c21ef boards: Convert nucleo_l073rz to HWM v2
09396eb2e6 boards: Convert nucleo_l053r8 to HWM v2
70c004fd83 boards: Convert nucleo_l031k6 to HWM v2
e3daa98e79 boards: Convert nucleo_l011k4 to HWM v2
a2de60c6da boards: Convert dragino_nbsn95 to HWM v2
e877ce9cec boards: Convert dragino_lsn50 to HWM v2
2b50218c23 boards: Convert b_l072z_lrwan1 to HWM v2
4a65f55916 soc: st: Migrate stm32l0 series to new hw model
cc6e6be01f boards: fix few leftover ITE board references
a837303268 soc: stm32: Protect Kconfig symbols by SOC_FAMILY_STM32
88e5959f17 hwm2: Fix unit_testing: it is also a legacy board by now
95e06e8663 cmake: Fix uses of old SOC path
d517d3cc24 soc: set linker script for ra4m1
68f9aeddab soc: ite: add SOC_SERIES_ITE_IT8XXX2 guards around ITE
options
ccf4f48f01 boards: convert ite boards to hwmv2
4a6e286a3b soc: convert ite_ec to hwmv2
12e375f826 doc: handle arch / soc / board docs in new hardware model
b4db917de9 boards: Add documentation index files
d6e0d27efe samples: bluetooth: hci_uart: Fix wrong named files
bc16a7a727 tests: Update board names for hwmv2
2834883843 boards: riscv: rv32m1_vega: Convert to v2
9c68231ba9 soc: openisa_rv32m1: Port to HWMv2
986e9619fd soc: starfive_jh71xx: Port to HWMv2
e82932e787 boards: riscv: litex_vexriscv: Convert to v2
cb9339f88f soc: litex_vexriscv: Port to HWMv2
1cd4c34654 boards: riscv: opentitan_earlgrey: Convert to v2
92eadf06b8 soc: opentitan: Port to HWMv2
a8659e170b boards: riscv: titanium_ti60_f225: Convert to v2
359133d725 soc: efinix_sapphire: Port to HWMv2
6d466429ed soc: soc_legacy: riscv: litex_vexriscv: Add updated paths
a1ff441eb3 boards: riscv: adp_xc7k_ae350: Convert to v2
ef82a8255c soc: ae350: Port to HWMv2
282204758a samples: boards: stm32: ccm: fix include path
8ca9341195 samples: basic: threads: fix broken reference
8a947f446d boards: nrf52840dk: fix rst syntax
324cb41153 boards: nordic_nrf: fix broken references
963c74df1c boards: intel_(ish|adl|ehl|rpl), up_squared: fix include
paths
8d518ce504 boards: legacy: drop empty folders
0fef0cef5b boards: mps2: fix table formatting
e52ccc244f boards: add HWMv2 board index
c7426eca5e boards: arm: add legacy tag
1eba9d8a8f boards: acrn: create vendor folder
8d92edc727 tests: kernel: Adjust qemu_x86_tiny_768 configuration
HWMv2
75117d1b2d scripts: ensure posix path is used with --cmakeformat
0b0384b56a maintainers: update paths after HWMv2 changes
c1b77b223d boards: arm: pan1783: Convert to v2
91a077b2ab boards: posix: nrf_bsim: Update paths
413b6c2a40 cmake: modules: configuration_files: Add board identifier
overlay file
4f572ba24f treewide: Update board names for hwmv2
cb348c7edf boards: arm: nrf54l15pdk_nrf54l15: Convert to v2
811ad90566 boards: arm: nrf54h20pdk_nrf54h20: Convert to v2
d44ef90cf8 soc: nordic_nrf: Migrate nRF54H/nRF54L to v2 and fix nrf
c860f205de boards: arm: nrf9151dk_nrf9151: Convert to v2
fba98a1763 soc: nordic_nrf: Migrate nRF9151 to v2
5c156a2d35 boards: arm: 96b_carbon_nrf51: Convert to v2
cfc47a3a4b boards: arm: nrf9161dk_nrf9161: Convert to v2
37129b4e44 boards: arm: nrf9131ek_nrf9131: Convert to v2
a923beba5d boards: arm: bl5340_dvk: Convert to v2
d242b2703b boards: arm: raytac_mdbt53v_db_40_nrf5340: Convert to v2
9c80d4e644 boards: arm: raytac_mdbt53_db_40: Convert to v2
28268c4938 boards: arm: nrf5340_audio_dk_nrf5340: Convert to v2
33ad2b5bc6 boards: arm: thingy53_nrf5340: Convert to v2
40daa94f2d boards: arm: nrf9160_innblue22: Convert to v2
2b0dbb9d51 boards: arm: nrf9160_innblue21: Convert to v2
ee6f7697ac boards: arm: sparkfun_thing_plus_nrf9160: Convert to v2
594e4bad6b boards: arm: circuitdojo_feather_nrf9160: Convert to v2
a5803ba099 boards: arm: actinius_icarus: Convert to v2
db8c275456 boards: arm: actinius_icarus_bee: Convert to v2
30177cf53d boards: arm: actinius_icarus_som: Convert to v2
486504cf24 boards: arm: actinius_icarus_som_dk: Convert to v2
dd0672a64c boards: arm: nrf9160dk_*: Convert to v2
c1565b3d14 boards: arm: xiao_ble: Convert to v2
6dd2723314 boards: arm: qemu_cortex_m0: Convert to v2
ee1ce24a42 boards: arm: bbc_microbit: Convert to v2
1952d559f2 boards: arm: rm1xx_dvk: Convert to v2
9e12c3d8bd boards: arm: nrf51dongle_nrf51422: Convert to v2
0ffbc1da33 boards: arm: nrf51_blenano: Convert to v2
be52dfb7b6 boards: arm: nrf51_vbluno51: Convert to v2
4c29d1827f boards: arm: nrf51_ble400: Convert to v2
5b4a9556fd boards: arm: raytac_mdbt53_db_40_nrf5340: Fix typo
69e5d87a15 boards: arm: contextualelectronics_abc: Convert to v2
5e4ace1bbe boards: arm: degu_evk: Convert to v2
2762460a64 boards: arm: pan1781_evb: Convert to v2
fdc3913e76 boards: arm: ubx_evkninab1_nrf52832: Convert to v2
9c9c3a09a1 boards: arm: holyiot_yj16019: Convert to v2
109edc296f boards: arm: blueclover_plt_demo_v2_nrf52832: Convert to
v2
7bfcdbbe8f boards: arm: decawave_dwm1001_dev: Convert to v2
0fbb543983 boards: arm: acn52832: Convert to v2
073e0f8080 boards: arm: we_proteus2ev_nrf52832: Convert to v2
197a19f396 boards: arm: ebyte_e73_tbb_nrf52832: Convert to v2
1616fc8ae5 boards: arm: nrf52_vbluno52: Convert to v2
5622077738 boards: arm: nrf52_sparkfun: Convert to v2
a6289516e4 boards: arm: 96b_nitrogen: Convert to v2
439d836883 boards: arm: nrf52_blenano2: Convert to v2
16e65f09c4 boards: arm: arduino_nicla_sense_me: Convert to v2
862efd5a21 boards: arm: thingy52_nrf52832: Convert to v2
dede0f6cd3 boards: arm: nrf52_adafruit_feather: Convert to v2
91e864ea29 boards: arm: nrf52832_mdk: Convert to v2
47ec3e416b boards: arm: ruuvi_ruuvitag: Convert to v2
52f797a227 boards: arm: pinetime_devkit0: Convert to v2
433db339f9 boards: arm: ubx_evkannab1_nrf52832: Convert to v2
a646d3f2d5 boards: arm: ubx_bmd300eval_nrf52832: Convert to v2
d0d434bf86 cmake: print identifier instead of variant
c3f5ed8157 boards: arm: we_proteus3ev_nrf52840: Convert to v2
eecff8ee7a boards: arm: nrf52840_mdk_usb_dongle: Convert to v2
34507614f6 boards: arm: nrf52840_mdk: Convert to v2
f02b56cb96 boards: arm: nrf52840_blip: Convert to v2
600c55c92a boards: arm: nrf52840_papyr: Convert to v2
f294bfc5e4 boards: arm: reel_board: Convert to v2
882524d2a0 boards: arm: nrf21540dk_nrf52840: Convert to v2
4bce0e9b39 boards: arm: nrf52840dongle_nrf52840: Convert to v2
d0229c771f boards: arm: particle_argon: Convert to v2
23a0570e64 boards: arm: particle_boron: Convert to v2
b6d3e1764f boards: arm: particle_xenon: Convert to v2
499f3e7902 boards: arm: rak5010_nrf52840: Convert to v2
9ae6b1804d boards: arm: rak4631_nrf52840: Convert to v2
fe2c90da5c boards: arm: pinnacle_100_dvk: Convert to v2
3d4d46698c boards: arm: ubx_evkninab3_nrf52840: Convert to v2
b1afbf0158 boards: arm: ubx_bmd380eval_nrf52840: Convert to v2
9f9897c872 boards: arm: ubx_bmd345eval_nrf52840: Convert to v2
f7fb2030c7 boards: arm: ubx_bmd340eval_nrf52840: Convert to v2
7186432662 boards: arm: raytac_mdbt50q_db_40_nrf52840: Convert to v2
32c4bdc0c4 boards: arm: pan1780_evb: Convert to v2
7b64c638a8 boards: arm: pan1770_evb: Convert to v2
156ee8ad8a boards: arm: mg100: Convert to v2
3d33dadeb0 boards: arm: arduino_nano_33_ble: Convert to v2
4fee7371d2 boards: arm: adafruit_itsybitsy_nrf52840: Convert to v2
ad37a0c222 boards: arm: adafruit_feather_nrf52840: Convert to v2
cf85b7169f boards: arm: bt510: Convert to v2
44b67ac430 boards: arm: bt610: Convert to v2
7dbb65d371 boards: arm: ubx_evkninab4_nrf52833: Convert to v2
5e79cb957d boards: arm: raytac_mdbt50q_db_33_nrf52833: Convert to v2
12bd83a218 boards: arm: pan1782_evb: Convert to v2
1a135ec352 boards: arm: bbc_microbit_v2: Convert to v2
4dbe97e5ea boards: arm: nrf52833dk: Convert to v2
d632b90043 boards: arm: ubx_bmd360eval_nrf52811: Convert to v2
cc1a30f24b boards: arm: we_ophelia1ev_nrf52805: Convert to v2
df0df9000b boards: arm: ubx_bmd330eval_nrf52810: Convert to v2
d2c7972a9a boards: arm: nrf52dk: Convert to v2
202c2bf447 boards: arm: bl654_sensor_board: Convert to v2
c3e36f2042 boards: arm: bl654_usb: Convert to v2
b9dd58aea1 boards: arm: bl654_dvk: Convert to v2
0e1898b093 boards: arm: bl653_dvk: Convert to v2
286f4a7524 boards: arm: bl652_dvk: Convert to v2
d1709cdb37 boards: update nRF51dk board to board scheme v2.
8f040cff2c boards: Update nrf5340dk_nrf5340 to HWMv2 scheme
8c90fae8e0 boards: update nRF52840dk_nrf52840/nrf52811 board to
board scheme v2.
c828dcc60e boards: common: openocd-nrf5: Add HWMv2 support
c79f1b0d94 kconfig: soc: adopt Nordic SoC series to support hw model
v2 scheme
3584b30fc1 tests: Update board names for hwmv2
94024d940e boards: arm: arty_a7: Convert to v2
8053c3a8df boards: arm: scobc_module1: Convert to v2
d5473b76fe soc: designstart: Port to HWMv2
f5792b05e7 boards: arm: fvp_baser_aemv8r_aarch32: Convert to v2
ff202daa8e soc: fvp_aemv8r_aarch32: Port to HWMv2
e66cbc2945 boards: arm: v2m_musca_s1: Convert to v2
33b47b2edb boards: arm: v2m_musca_b1: Convert to v2
baeebd31d2 soc: musca: Port to HWMv2
73b257a3f9 boards: arm: v2m_beetle: Convert to v2
85de0888ec soc: beetle: Port to HWMv2
867960a891 manifest: Update modules
6ca677ed3a boards: arm: mps2: Convert to v2
bcf4ad19d4 twister: build_dir: convert / to _ to support hwmv2
0ac386683f soc: Kconfig.v2: Add SOC_PART_NUMBER
9242c3c78f soc: stm32: soc.yml: reorder series
248d17f160 boards: stm32: cleanup
0a67265e99 boards: stm32: fix for boards with revisions
f8d44317ee soc: stm32l5: Rename overlays for nucleo_l552ze_q ns
target.
400343d17e soc: stm32: Set default on USE_DT_CODE_PARTITION
d783ef549a soc: stm32l5: Update stm32l5 non secure targets in
various places
643aeac552 boards: Convert stm32l562e_dk to HWM v2
e601d64344 boards: Convert nucleo_l552ze_q to HWM v2
2f7a387b32 soc: st: Migrate stm32l5 series to new hw model
519752efcd boards: xenvm: doc: Remove reference to deleted file
06263dd717 boards: xenvm: Unset HEAP_MEM_POOL_SIZE in gicv3 variant
66b0df5526 boards: qemu_cortex_a53: Fix Kconfig warnings in SMP
variant
fa07bd9419 boards: mps3: Fix non-secure variant
8f6f0726dd boards: Move xenvm under xen
7b155a7031 boards: Raspberry Pi vendor fix
804697afa5 boards: Move 96b_aerocore to 96boards
d2f001e320 boards: x86: acrn: move and convert to HWMv2
ec7f7b3c30 tests: kernel: qemu_x86: adjust to the HWMv2
89dfcddc7e boards: x86: qemu_x86_tiny@768: change to board variant
eb724eb6a7 boards: x86: qemu_x86: optimize default HWMv2
configurations
6f1043cde6 boards: x86: qemu_x86: move and convert to HWMv2
cab924cbfb soc: x86: ia32: move and convert to HWMv2
237fdff918 soc: x86: lakemont: move and convert to HWMv2
03042b7704 boards: move 96b_carbon to 96boards folder
767b94414e boards: rename vendor seeed to seeed_studio
07fa3a3d79 boards: Convert olimex_lora_stm32wl_devkit to HWM v2
ba01d3beca boards: Convert nucleo_wl55jc to HWM v2
7ce84f4041 boards: Convert lora_e5_mini to HWM v2
b988bae576 boards: Convert lora_e5_dev_board to HWM v2
6fbf39c726 soc: v2: stm32: Migrate STM32WL series
4a41878442 soc: st: stm32g4: add missing include
1e79ba15f6 boards: Convert weact_stm32g431_core to HWM v2
ffdcb60185 boards: Convert nucleo_g474re to HWM v2
d6acb08d3e boards: Convert nucleo_g431rb to HWM v2
90e592ffd1 boards: Convert b_g474e_dpow1 to HWM v2
eb8a7e3441 soc: st: stm32: Migrate STM32G4 series
ada469f237 tests: Update board names for hwmv2
0342433187 boards: arm: npcx9m6f_evb: Convert to v2
c10248d964 boards: arm: npcx7m6fb_evb: Convert to v2
21ddc5e6a6 boards: arm: npcx4m8f_evb: Convert to v2
5500f3ef21 soc: npcx*: Port to HWMv2
e7baf09ede soc: m48x: Port to HWMv2
5bae4a6480 boards: arm: numaker_pfm_m467: Convert to v2
3b0bd70c8c soc: m46x: Port to HWMv2
d52eab9e83 boards: Convert stm32g081b_eval to HWM v2
6f2835cb11 boards: Convert stm32g071b_disco to HWM v2
ca36d331d2 boards: Convert stm32g0316_disco to HWM v2
662cc4e09b boards: Convert nucleo_g0b1re to HWM v2
dd9bc29769 boards: Convert nucleo_g071rb to HWM v2
353da23ffb boards: Convert nucleo_g070rb to HWM v2
acc932b424 boards: Convert nucleo_g031k8 to HWM v2
cea9b140fd boards: Convert google_twinkie_v2 to HWM v2
52e025943a soc: st: stm32: Migrate STM32G0 series
1c7347686a ci: update check_compliance to not create duplicate lines
in Kconfig
9debd98799 hwmv2: boards: up_squared_pro_700: Add missed intel_adl
changes
adab07c42f boards: Convert msp_exp432p401r_launchxl to HWM v2
642aacdcdf soc: ti_simplelink: Add missing SoC
48637066d3 boards: Fix file paths in documentation
e983bc2a23 samples/tests: Fix mps3 board name
61e0f32716 boards: Convert stm32f3_seco_d23 to HWM v2
a1688ff641 boards: Convert stm32f3_disco to HWM v2
35fb228599 boards: Convert stm32373c_eval to HWM v2
10e5d1122b boards: Convert nucleo_f334r8 to HWM v2
c319cb19f0 boards: Convert nucleo_f303re to HWM v2
11725ccac1 boards: Convert nucleo_f303k8 to HWM v2
400f7f6a4f boards: Convert nucleo_f302r8 to HWM v2
8d84861390 soc: v2: stm32: Migrate STM32F3 series
85b9eee7e8 boards: arm: kv260_r5: Convert to v2
dafbd638e4 boards: arm: mercury_xu: Convert to v2
3ecd12f415 boards: arm: qemu_cortex_r5: Convert to v2
5db2390e9d soc: xilinx_zyncmp: Port to HWMv2
9ba8195cdc boards: arm: qemu_cortex_a9: Convert to v2
8e94b85361 boards: arm: zybo: Convert to v2
c970127fc2 soc: xilinx_zynq7000: Port to HWMv2
394c75373c boards: arm: ast1030_evb: Convert to v2
f2a1cc8714 soc: ast10x0: Port to HWMv2
28f3f25945 boards: arm: cc3235sf_launchxl: Convert to v2
c3e480f740 boards: arm: cc3220sf_launchxl: Convert to v2
fd5847123f boards: arm: beagleconnect_freedom: Convert to v2
76ba9a0587 boards: arm: cc1352p1_launchxl: Convert to v2
719baa8850 boards: arm: cc1352r1_launchxl: Convert to v2
5060a61ae1 boards: arm: cc1352r_sensortag: Convert to v2
99584be1c5 boards: arm: cc26x2r1_launchxl: Convert to v2
2dc8933942 soc: ti_simplelink: Port to HWMv2
a5b004663b scripts/utils/board_v1_to_v2.py: couple of fixes
77c2c333e5 boards: move 96b_stm32_sensor_mez to 96boards
c14ff98650 boards: stm32f411e_disco: delete obsolete file
bcdc268ccf boards: Convert stm32mp157c_dk2 to HWM v2
0c8ba92e1f boards: Convert 96b_avenger96 to HWM v2
b54fe33077 soc: v2: stm32: Migrate STM32MP1 series
2ba3639b2a boards: Convert nucleo_c031c6 to HWM v2
dbc5ed79f5 soc: st: stm32: Migrate STM32C0 series
ce6d493aa3 boards: Convert stm32l1_disco to HWM v2
a28086a9ca boards: Convert nucleo_l152re to HWM v2
1b2a511d06 boards: Convert 96b_wistrio to HWM v2
ce281f09ab soc: v2: stm32: Migrate STM32L1 series
cdb5364fd7 boards: Convert stm32f769i_disco to HWM v2
768f173dcb boards: Convert stm32f7508_dk to HWM v2
21bbbbd9cb boards: Convert stm32f746g_disco to HWM v2
bab4265693 boards: Convert stm32f723e_disco to HWM v2
58f8fe82ba boards: Convert nucleo_f767zi to HWM v2
37e9084070 boards: Convert nucleo_f756zg to HWM v2
d467e7053a boards: Convert nucleo_f746zg to HWM v2
5f2808d7cc boards: Convert nucleo_f722ze to HWM v2
bbb73e7550 soc: st: Migrate stm32f7 series to new hw model
e9094afc4d soc: st: stm32: stm32f4: change SOC_STM32F405XG to
SOC_STM32F405XX
a1712cdd53 boards: Convert stm32f4_disco to HWM v2
5be404b365 boards: Convert stm32f469i_disco to HWM v2
baaa697ab2 boards: Convert stm32f429i_disc1 to HWM v2
69ecab3c90 boards: Convert stm32f412g_disco to HWM v2
2a572e3fb0 boards: Convert stm32f411e_disco to HWM v2
ecfbf42757 boards: Convert stm32f401_mini to HWM v2
e0191d03bb boards: Convert steval_fcu001v1 to HWM v2
4454648976 boards: Convert segger_trb_stm32f407 to HWM v2
f0ad6ee6b8 boards: Convert olimex_stm32_p405 to HWM v2
1f5e228ec8 boards: Convert olimex_stm32_h407 to HWM v2
834bdb615e boards: Convert olimex_stm32_h405 to HWM v2
8f27fa8de2 boards: Convert olimex_stm32_e407 to HWM v2
f8633a9038 boards: Convert nucleo_f446ze to HWM v2
07e0bd2c07 boards: Convert nucleo_f446re to HWM v2
24d7f625dc boards: Convert nucleo_f429zi to HWM v2
157a8cde53 boards: Convert nucleo_f413zh to HWM v2
4ec99c31b0 boards: Convert nucleo_f412zg to HWM v2
a21546140a boards: Convert nucleo_f411re to HWM v2
43f01ab6de boards: Convert nucleo_f410rb to HWM v2
60c16bcb8b boards: Convert nucleo_f401re to HWM v2
2db228d730 boards: Convert mikroe_mini_m4_for_stm32 to HWM v2
73fc26225c boards: Convert mikroe_clicker_2 to HWM v2
6b62d90114 boards: Convert google_dragonclaw to HWM v2
fa845af309 boards: Convert blackpill_f411ce to HWM v2
5c8c3c3be0 boards: Convert blackpill_f401ce to HWM v2
3c02db1290 boards: Convert blackpill_f401cc to HWM v2
7eeb723cb7 boards: Convert black_f407zg_pro to HWM v2
4f9461d068 boards: Convert black_f407ve to HWM v2
a821de8532 boards: Convert az3166_iotdevkit to HWM v2
ba580c7236 boards: Convert adi_sdp_k1 to HWM v2
eb272ddf19 boards: Convert adafruit_feather_stm32f405 to HWM v2
58ed121c3a boards: Convert 96b_stm32_sensor_mez to HWM v2
b0d70959d3 boards: Convert 96b_neonkey to HWM v2
b1088baadc boards: Convert 96b_carbon to HWM v2
18d867b0a9 boards: Convert 96b_argonkey to HWM v2
ee6ede7119 boards: Convert 96b_aerocore2 to HWM v2
b48e70ead9 soc: v2: stm32: Migrate STM32F4 series
14d2b955da cmake: convert path to CMake style before writing Kconfig
files
9c4ac6a202 boards: posix: bsim: Update paths
14b57f56d7 tests: drivers: gpio: gpio_ite_it8xxx2_v2: Temp fix
f3b173be18 scripts: board_v1_to_v2: Update following move to
boards_legacy
05b50f6691 cmake: CMake soc dir variable improvements for HWMv2
a188e01a12 hwmv2: move all ported boards and socs to their final
location
22c53e97b5 hwmv2: move all non-ported legacy boards and socs to
legacy folders
53f3b181b0 soc: ti_k3: Port to HWMv2
9f19a2075a soc: rk3568: Port to HWMv2
b8928b1628 soc: rk3399: Port to HWMv2
cda3a74868 boards: arm64: qemu_kvm_arm64: Convert to v2
70d704bd20 soc: x86: atom: move and convert to HWMv2
4789e1068e boards: x86: intel_rpl: move and convert raptor_lake
boards to HWMv2
384307e3dc soc: x86: raptor_lake: move and convert to HWMv2
ed025df674 boards: x86: intel_ehl: move and convert elkhart_lake
boards to HWMv2
994b6e1731 soc: x86: elkhart_lake: move and convert to HWMv2
73b30a04cf boards: x86: up_squared_pro_7000: move and convert to
HWMv2
83b133c207 boards: x86: intel_adl: move and convert alder_lake
boards to HWMv2
847a12f1e4 soc: alder_lake: move and convert to HWMv2
67f4c8d2a1 samples: up_squared: adjust gpio_counter to HWMv2
5326b5bfc0 boards: x86: up_squared: move and convert to HWMv2
cfd5e691b4 soc: apollo_lake: move and convert to HWMv2
ac9c235741 boards: xtensa: qemu_xtensa: Convert to v2
f198c3a761 ci: update to osource for soc/Kconfig.defconfig files
e438e6cad4 ci: add SOC_SERIES_ as false positive in
check_compliance.py
95e34da7c1 soc: v2: Convert st_stm32 to st/stm32
313717df76 soc: mps3: Fix missing family
392c3969ed boards: arm: am62x_m4: Convert to v2
8f245d764d tests: Update board names for hwmv2
8f71bb7b4f boards: arm64: khadas_edgev: Convert to v2
e27d23aad0 soc: rk3399: Port to HWMv2
80823b860e boards: arm64: roc_rk3568_pc: Convert to v2
72e4483dec soc: rk3568: Port to HWMv2
bed94669e3 boards: arm64: phycore_am62x_a53: Convert to v2
c01af5a7b8 soc: ti_k3: Port to HWMv2
1e563b4ca3 boards: arm64: xenvm: Convert to v2
76e484adae soc: xenvm: Port to HWMv2
34412f7fe2 boards: arm64: rpi_4b: Convert to v2
9be50e2ca9 soc: bcm2711: Port to HWMv2
bbbed12c2f boards: arm64: qemu_kvm_arm64: Convert to v2
4f5ec7ff8f soc: qemu_virt_arm64: Port to HWMv2
d8d1b9f200 boards: arm64: qemu_cortex_a53: Convert to v2
30bd34b31e soc: qemu_cortex_a53: Port to HWMv2
c20d0dcbb6 boards: arm64: fvp_baser_aemv8r: Convert to v2
02ed6af463 boards: arm64: fvp_base_revc_2xaemv8a: Convert to v2
1b175003a4 soc: fvp_aemv8*: Port to HWMv2
de231b911d boards: v2: Clean up obsolete comments
aa9597f6d9 boards: Convert waveshare_open103z to HWM v2
9644828c81 boards: Convert stm32vl_disco to HWM v2
86ab2bd430 boards: Convert stm32_min_dev to HWM v2
d88d3ddcc4 boards: Convert stm32f103_mini to HWM v2
0ccc0204e1 boards: Convert stm3210c_eval to HWM v2
dd9972d782 boards: Convert olimex_stm32_h103 to HWM v2
a2c2e1406d boards: Convert olimexino_stm32 to HWM v2
2d9c62e118 boards: Convert nucleo_f103rb to HWM v2
e8ba99dc59 soc: v2: stm32: Migrate STM32F1 series
9a93916604 tests: Update board names for hwmv2
9c4d94844d boards: arm: bcm958401m2: Convert to v2
feaf4ffba1 boards: arm: bcm958402m2: Convert to v2
87f0827121 soc: bcm_vk: Port to HWMv2
4526be24a5 boards: arm: quick_feather: Convert to v2
cd921d2b97 boards: arm: qomu: Convert to v2
b3c04051fc soc: quicklogic_eos_s3: Port to HWMv2
a73a9e7533 boards: v2: Clean up obsolete comments
8d87bcc167 boards: Convert stm32f0_disco to HWM v2
1933585785 boards: Convert stm32f072_eval to HWM v2
6f9fe5429d boards: Convert stm32f072b_disco to HWM v2
9dc78e4025 boards: Convert stm32f030_demo to HWM v2
35113e8923 boards: Convert nucleo_f091rc to HWM v2
b276aee9a4 boards: Convert nucleo_f070rb to HWM v2
795f8d611b boards: Convert nucleo_f042k6 to HWM v2
2d82646443 boards: Convert nucleo_f031k6 to HWM v2
959786f12d boards: Convert nucleo_f030r8 to HWM v2
81670db2e9 boards: Convert legend to HWM v2
8980430aad boards: Convert google_kukui to HWM v2
ac020f66e0 dts: stm32f0: fix few warnings
5140e4551a boards: v2: doc: Add vendors
77d640e0c9 soc: v2: stm32: Migrate STM32F0 series
0131e1c159 soc: v2: Add st_stm32 structure and common folder
36b63787a7 boards: v2: Add documentation index for converted boards
ae02fc5047 boards: sparc: qemu_leon3: Convert to v2
f38f7bb223 boards: sparc: gr716a: Convert to v2
d3cca3580e soc: gr716a: Port to HWMv2
6a8a0c1647 boards: sparc: generic_leon3: Convert to v2
faf22185ce soc: leon3: Port to HWMv2
e94762ecdc tests: Update board names for hwmv2
9afcc27e05 boards: xtensa: qemu_xtensa: Convert to v2
3e4a17018f soc: dc233c: Port to HWMv2
9188fdcd78 boards: xtensa: xt-sim: Convert to v2
fcaa41cb5d soc: xtensa_sample_controller: Port to HWMv2
dbc413f7f7 scripts: board_v1_to_v2: Fix CONFIG_SOC_SERIES_ exclusion
6be3d4bc80 kconfig: remove Kconfig BOARD_RPI_PICO_W safe guard.
f4442fa698 boards: v2: Add documentation index for converted boards
ec5fbd67f7 boards: nios2: qemu_nios2: Convert to v2
d3ef220460 soc: nios2-qemu: Port to HWMv2
a223f284b5 boards: nios2: altera_max10: Convert to v2
c381edcb73 soc: nios2f-zephyr: Port to HWMv2
97401c7d2a boards: mips: qemu_malta: Convert to v2
e7a3243a24 soc: qemu_malta: Port to HWMv2
bec82c690d boards: v2: Add documentation index for converted boards
94f6f9b636 boards: arm: w5500_evb_pico: Convert to v2
209235ab6e boards: arm: sparkfun_pro_micro_rp2040: Convert to v2
e5b1885907 boards: arm: adafruit_qt_py_rp2040: Convert to v2
4c750818f9 boards: arm: adafruit_kb2040: Convert to v2
8d3896caa4 boards: arm: rpi_pico: Convert to v2
42cff42c42 soc: rpi_pico: Port to HWMv2
c2df4ca9cb scripts: improve yaml schema and board.yml validation for
revisions
3970f90f71 cmake: clear BOARD_CACHE when invalid board identifier is
given
3a70ee9ccd cmake: improve board revision handling
3cda715fae scripts: board_v1_to_v2: Don't add select
CONFIG_SOC_SERIES_FOO
dc56a543f3 scripts: board_v1_to_v2: Add License + copyright
87147f88c4 cmake: prefer cache BOARD_IDENTIFIER over extracting from
BOARD
65f5dc5b8c cmake: fail when board identifier is applied in legacy hw
model
7db2b6efd8 cmake: cache BOARD_IDENTIFIER to preserve it between
CMake invocations
85dddac5a2 scripts: using extend in list_boards for variant list
6ae5c4e7fd scripts: utils: add board v1->v2 conversion utility
ef834a12d0 maintainers: update Renesas RZT2M path
3ab7830625 boards: renesas: add documentation entry
a0c2ca0491 boards: arm: add documentation entry
27ff3654b7 boards: gigadevice: add documentation entry
6e02f43c0a maintainers: update GD32 paths
1bfcf1d974 boards: gd32l233r_eval: convert to HWMv2
6e621ee43f boards: gd32f470i_eval: convert to HWMv2
219b149768 boards: gd32f450z_eval: convert to HWMv2
91c52b0d39 boards: gd32f450v_start: convert to HWMv2
f0e0a973f6 boards: gd32f407v_start: convert to HWMv2
6f592b64c9 boards: gd32f403z_eval: convert to HWMv2
4bcb4b2ac8 boards: gd32f350r_eval: convert to HWMv2
fdc7ed6eb0 boards: gd32e507z_eval: convert to HWMv2
770376250d boards: gd32e507v_start: convert to HWMv2
a6d8b92e86 boards: gd32e103v_eval: convert to HWMv2
a5f8e5daa1 boards: gd32a503v_eval: convert to HWMv2
5ee799cc5f boards: gd32f450i_eval: convert to HWMv2
8aa8ce4ac8 soc: gigadevice: port to HWMv2
4e203c14c7 cmake: enhanced board entry file handling
312265ee04 scripts: make SoC field mandatory in board.yml
c12ae3bcbc boards: update Renesas rzt2m board.yml to contain SoC
information
c5321c1dbe cmake: make SoC optional for boards containing a single
SoC
bcc06c60ae scripts: support SoC list output for boards
db9e46010c twister: update testcase.yaml and sample.yaml to
mps3/an547 identifier
a988adee7d boards: update arm mps3 an547 board to HWMv2 scheme
7dc2c9db0c soc: use HWMv2 for arm mps3 SoC
c506675b7c boards: update Renesas Starter Kit+ for RZ/T2M board to
HWMv2 scheme
3abb792073 soc: use HWMv2 for renesas_rzt2m SoC
4f52bc646e cmake: support hw model v2 in arch/Kconfig tree
a712b5005b scripts: extend kconfig compliance to verify board / SoC
scheme v2
baa55141a1 twister: update twister testplan.py to handle HWMv2
boards
1f026f70eb boards: extend list_boards.py and update boards CMake
module
bd854a3af8 cmake: introduce arch and soc cmake modules for hw model
v2
c9edefa8fd arch: add existing archs to archs.yml for HWMv2 support
61bbfb5ba2 scripts: introduce list_hardware.py for listing of
architectures and SoCs
a4d1980c35 build: board/ soc: introduce hw model v2 scheme
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
Signed-off-by: David Leach <david.leach@nxp.com>
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This commit is contained in:
Torsten Rasmussen
Anas Nashif
parent
418b0a1e65
commit
8dc3f85622
13315 changed files with 159282 additions and 157416 deletions
9
soc/nxp/imx/CMakeLists.txt
Normal file
9
soc/nxp/imx/CMakeLists.txt
Normal file
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@ -0,0 +1,9 @@
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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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add_subdirectory(${SOC_SERIES})
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zephyr_include_directories(.)
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zephyr_include_directories(${SOC_SERIES})
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zephyr_include_directories(${SOC_SERIES}/include)
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13
soc/nxp/imx/Kconfig
Normal file
13
soc/nxp/imx/Kconfig
Normal file
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@ -0,0 +1,13 @@
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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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config SOC_FAMILY_NXP_IMX
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select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
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if SOC_FAMILY_NXP_IMX
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# Source series Kconfig files first, so SOCs
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# can override the defaults given here
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rsource "*/Kconfig"
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endif # SOC_FAMILY_NXP_IMX
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10
soc/nxp/imx/Kconfig.defconfig
Normal file
10
soc/nxp/imx/Kconfig.defconfig
Normal file
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@ -0,0 +1,10 @@
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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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if SOC_FAMILY_NXP_IMX
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# Source series Kconfig files first, so SoCs
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# can override the defaults given here
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rsource "*/Kconfig.defconfig"
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|
||||
endif # SOC_FAMILY_NXP_IMX
|
||||
10
soc/nxp/imx/Kconfig.soc
Normal file
10
soc/nxp/imx/Kconfig.soc
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
# Copyright 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_FAMILY_NXP_IMX
|
||||
bool
|
||||
|
||||
config SOC_FAMILY
|
||||
default "nxp_imx" if SOC_FAMILY_NXP_IMX
|
||||
|
||||
rsource "*/Kconfig.soc"
|
||||
14
soc/nxp/imx/imx6sx/CMakeLists.txt
Normal file
14
soc/nxp/imx/imx6sx/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
#
|
||||
# Copyright 2018,2024 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
zephyr_sources(
|
||||
soc.c
|
||||
soc_clk_freq.c
|
||||
)
|
||||
|
||||
zephyr_include_directories(.)
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
|
||||
18
soc/nxp/imx/imx6sx/Kconfig
Normal file
18
soc/nxp/imx/imx6sx/Kconfig
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
# Copyright 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_IMX6SX
|
||||
select ARM
|
||||
select CPU_CORTEX_M4
|
||||
select CPU_CORTEX_M_HAS_DWT
|
||||
select HAS_IMX_HAL
|
||||
select CPU_HAS_FPU
|
||||
select CPU_HAS_ARM_MPU
|
||||
select CLOCK_CONTROL
|
||||
|
||||
config SOC_MCIMX6X_M4
|
||||
select HAS_IMX_HAL
|
||||
select HAS_IMX_GPIO
|
||||
select HAS_IMX_EPIT
|
||||
select HAS_IMX_I2C
|
||||
select HAS_IMX_IOMUXC
|
||||
18
soc/nxp/imx/imx6sx/Kconfig.defconfig
Normal file
18
soc/nxp/imx/imx6sx/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
# i.MX 6SoloX core series
|
||||
|
||||
# Copyright 2018,2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_IMX6SX
|
||||
|
||||
config NUM_IRQS
|
||||
# must be >= the highest interrupt number used
|
||||
default 128
|
||||
|
||||
config PINCTRL_IMX
|
||||
default y if HAS_IMX_IOMUXC
|
||||
depends on PINCTRL
|
||||
|
||||
rsource "Kconfig.defconfig.*"
|
||||
|
||||
endif # SOC_SERIES_IMX6SX
|
||||
11
soc/nxp/imx/imx6sx/Kconfig.defconfig.mcimx6x_m4
Normal file
11
soc/nxp/imx/imx6sx/Kconfig.defconfig.mcimx6x_m4
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
# i.MX 6SoloX
|
||||
|
||||
# Copyright 2018,2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_MCIMX6X_M4
|
||||
|
||||
config FPU
|
||||
default y
|
||||
|
||||
endif # SOC_MCIMX6X_M4
|
||||
83
soc/nxp/imx/imx6sx/Kconfig.soc
Normal file
83
soc/nxp/imx/imx6sx/Kconfig.soc
Normal file
|
|
@ -0,0 +1,83 @@
|
|||
# i.MX 6SoloX core series
|
||||
|
||||
# Copyright 2018,2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
config SOC_SERIES_IMX6SX
|
||||
bool
|
||||
select SOC_FAMILY_NXP_IMX
|
||||
|
||||
config SOC_MCIMX6X
|
||||
bool
|
||||
select SOC_SERIES_IMX6SX
|
||||
|
||||
config SOC_MCIMX6X_M4
|
||||
select SOC_MCIMX6X
|
||||
bool
|
||||
help
|
||||
NXP iMX6 SoloX M4 core
|
||||
|
||||
config SOC_SERIES
|
||||
default "imx6sx" if SOC_SERIES_IMX6SX
|
||||
|
||||
config SOC
|
||||
default "mcimx6x" if SOC_MCIMX6X
|
||||
|
||||
config SOC_PART_NUMBER_MCIMX6X1EVK10AB
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MCIMX6X1EVK10AC
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MCIMX6X3EVK10AB
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MCIMX6X3EVK10AC
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MCIMX6X1EVO10AB
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MCIMX6X1EVO10AC
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MCIMX6X3EVO10AB
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MCIMX6X3EVO10AC
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MCIMX6X2EVN10AB
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MCIMX6X2EVN10AC
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MCIMX6X3EVN10AB
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MCIMX6X3EVN10AC
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MCIMX6X4EVM10AB
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MCIMX6X4EVM10AC
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER
|
||||
default "MCIMX6X1EVK10AB" if SOC_PART_NUMBER_MCIMX6X1EVK10AB
|
||||
default "MCIMX6X1EVK10AC" if SOC_PART_NUMBER_MCIMX6X1EVK10AC
|
||||
default "MCIMX6X3EVK10AB" if SOC_PART_NUMBER_MCIMX6X3EVK10AB
|
||||
default "MCIMX6X3EVK10AC" if SOC_PART_NUMBER_MCIMX6X3EVK10AC
|
||||
default "MCIMX6X1EVO10AB" if SOC_PART_NUMBER_MCIMX6X1EVO10AB
|
||||
default "MCIMX6X1EVO10AC" if SOC_PART_NUMBER_MCIMX6X1EVO10AC
|
||||
default "MCIMX6X3EVO10AB" if SOC_PART_NUMBER_MCIMX6X3EVO10AB
|
||||
default "MCIMX6X3EVO10AC" if SOC_PART_NUMBER_MCIMX6X3EVO10AC
|
||||
default "MCIMX6X2EVN10AB" if SOC_PART_NUMBER_MCIMX6X2EVN10AB
|
||||
default "MCIMX6X2EVN10AC" if SOC_PART_NUMBER_MCIMX6X2EVN10AC
|
||||
default "MCIMX6X3EVN10AB" if SOC_PART_NUMBER_MCIMX6X3EVN10AB
|
||||
default "MCIMX6X3EVN10AC" if SOC_PART_NUMBER_MCIMX6X3EVN10AC
|
||||
default "MCIMX6X4EVM10AB" if SOC_PART_NUMBER_MCIMX6X4EVM10AB
|
||||
default "MCIMX6X4EVM10AC" if SOC_PART_NUMBER_MCIMX6X4EVM10AC
|
||||
94
soc/nxp/imx/imx6sx/pinctrl_soc.h
Normal file
94
soc/nxp/imx/imx6sx/pinctrl_soc.h
Normal file
|
|
@ -0,0 +1,94 @@
|
|||
/*
|
||||
* Copyright (c) 2022, NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_ARM_NXP_IMX_MCIMX6X_PINCTRL_SOC_H_
|
||||
#define ZEPHYR_SOC_ARM_NXP_IMX_MCIMX6X_PINCTRL_SOC_H_
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/types.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) ((x) & 0xF)
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((x) & 0x1) << 4)
|
||||
#define IOMUXC_SELECT_INPUT_DAISY(x) ((x) & 0x7)
|
||||
|
||||
#define MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT 16
|
||||
#define MCUX_IMX_BIAS_PULL_DOWN_SHIFT 14
|
||||
#define MCUX_IMX_BIAS_PULL_UP_SHIFT 14
|
||||
#define MCUX_IMX_BIAS_BUS_HOLD_SHIFT 13
|
||||
#define MCUX_IMX_PULL_ENABLE_SHIFT 12
|
||||
#define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT 11
|
||||
#define MCUX_IMX_SPEED_SHIFT 6
|
||||
#define MCUX_IMX_DRIVE_STRENGTH_SHIFT 3
|
||||
#define MCUX_IMX_SLEW_RATE_SHIFT 0
|
||||
#define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
|
||||
#define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1)
|
||||
|
||||
#define Z_PINCTRL_MCUX_IMX_PINCFG_INIT(node_id) \
|
||||
((DT_PROP(node_id, input_schmitt_enable) << MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT) | \
|
||||
IF_ENABLED(DT_PROP(node_id, bias_pull_up), (DT_ENUM_IDX(node_id, bias_pull_up_value) \
|
||||
<< MCUX_IMX_BIAS_PULL_UP_SHIFT) |) \
|
||||
IF_ENABLED(DT_PROP(node_id, bias_pull_down), (DT_ENUM_IDX(node_id, bias_pull_down_value)\
|
||||
<< MCUX_IMX_BIAS_PULL_DOWN_SHIFT) |) \
|
||||
((DT_PROP(node_id, bias_pull_down) | DT_PROP(node_id, bias_pull_up)) \
|
||||
<< MCUX_IMX_BIAS_BUS_HOLD_SHIFT) | \
|
||||
((!DT_PROP(node_id, bias_disable)) << MCUX_IMX_PULL_ENABLE_SHIFT) | \
|
||||
(DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) | \
|
||||
(DT_ENUM_IDX(node_id, nxp_speed) << MCUX_IMX_SPEED_SHIFT) | \
|
||||
(DT_ENUM_IDX(node_id, drive_strength) << MCUX_IMX_DRIVE_STRENGTH_SHIFT) | \
|
||||
(DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \
|
||||
(DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT))
|
||||
|
||||
|
||||
/* This struct must be present. It is used by the mcux gpio driver */
|
||||
struct pinctrl_soc_pinmux {
|
||||
uint32_t mux_register; /*!< IOMUXC SW_PAD_MUX register */
|
||||
uint32_t config_register; /*!< IOMUXC SW_PAD_CTL register */
|
||||
uint32_t input_register; /*!< IOMUXC SELECT_INPUT DAISY register */
|
||||
uint8_t mux_mode: 4; /*!< Mux value for SW_PAD_MUX register */
|
||||
uint32_t input_daisy:4; /*!< Mux value for SELECT_INPUT_DAISY register */
|
||||
};
|
||||
|
||||
struct pinctrl_soc_pin {
|
||||
struct pinctrl_soc_pinmux pinmux;
|
||||
uint32_t pin_ctrl_flags; /*!< value to write to IOMUXC_SW_PAD_CTL register */
|
||||
};
|
||||
|
||||
typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
|
||||
|
||||
/* This definition must be present. It is used by the mcux gpio driver */
|
||||
#define MCUX_IMX_PINMUX(node_id) \
|
||||
{ \
|
||||
.mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \
|
||||
.config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \
|
||||
.input_register = DT_PROP_BY_IDX(node_id, pinmux, 2), \
|
||||
.mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1), \
|
||||
.input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3), \
|
||||
}
|
||||
|
||||
#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \
|
||||
MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
|
||||
|
||||
#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \
|
||||
{ \
|
||||
.pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
|
||||
.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PINCFG_INIT(group_id), \
|
||||
},
|
||||
|
||||
|
||||
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
|
||||
DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)}; \
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ZEPHYR_SOC_ARM_NXP_IMX_MCIMX6X_PINCTRL_SOC_H_ */
|
||||
305
soc/nxp/imx/imx6sx/soc.c
Normal file
305
soc/nxp/imx/imx6sx/soc.c
Normal file
|
|
@ -0,0 +1,305 @@
|
|||
/*
|
||||
* Copyright (c) 2018, NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/init.h>
|
||||
#include <zephyr/sys/barrier.h>
|
||||
#include <soc.h>
|
||||
#include <zephyr/dt-bindings/rdc/imx_rdc.h>
|
||||
#include "wdog_imx.h"
|
||||
|
||||
#include <cmsis_core.h>
|
||||
|
||||
/* Initialize Resource Domain Controller. */
|
||||
static void SOC_RdcInit(void)
|
||||
{
|
||||
/* Move M4 core to the configured RDC domain */
|
||||
RDC_SetDomainID(RDC, rdcMdaM4, M4_DOMAIN_ID, false);
|
||||
|
||||
/* Set access to WDOG3 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapWdog3,
|
||||
RDC_DOMAIN_PERM(M4_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
|
||||
false, false);
|
||||
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay)
|
||||
/* Set access to UART_1 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapUart1, RDC_DT_VAL(uart1), false, false);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay)
|
||||
/* Set access to UART_2 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapUart2, RDC_DT_VAL(uart2), false, false);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart3), okay)
|
||||
/* Set access to UART_3 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapUart3, RDC_DT_VAL(uart3), false, false);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart4), okay)
|
||||
/* Set access to UART_4 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapUart4, RDC_DT_VAL(uart4), false, false);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart5), okay)
|
||||
/* Set access to UART_5 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapUart5, RDC_DT_VAL(uart5), false, false);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart6), okay)
|
||||
/* Set access to UART_6 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapUart6, RDC_DT_VAL(uart6), false, false);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
|
||||
/* Set access to GPIO_1 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapGpio1, RDC_DT_VAL(gpio1), false, false);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay)
|
||||
/* Set access to GPIO_2 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapGpio2, RDC_DT_VAL(gpio2), false, false);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio3), okay)
|
||||
/* Set access to GPIO_3 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapGpio3, RDC_DT_VAL(gpio3), false, false);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio4), okay)
|
||||
/* Set access to GPIO_4 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapGpio4, RDC_DT_VAL(gpio4), false, false);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio5), okay)
|
||||
/* Set access to GPIO_5 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapGpio5, RDC_DT_VAL(gpio5), false, false);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio6), okay)
|
||||
/* Set access to GPIO_6 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapGpio6, RDC_DT_VAL(gpio6), false, false);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio7), okay)
|
||||
/* Set access to GPIO_7 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapGpio7, RDC_DT_VAL(gpio7), false, false);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IPM_IMX
|
||||
/* Set access to MU B for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapMuB, RDC_DT_VAL(mub), false, false);
|
||||
#endif /* CONFIG_IPM_IMX */
|
||||
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(epit1), okay)
|
||||
/* Set access to EPIT_1 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapEpit1, RDC_DT_VAL(epit1), false, false);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(epit2), okay)
|
||||
/* Set access to EPIT_2 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapEpit2, RDC_DT_VAL(epit2), false, false);
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c1), okay)
|
||||
/* Set access to I2C-1 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapI2c1, RDC_DT_VAL(i2c1), false, false);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c2), okay)
|
||||
/* Set access to I2C-2 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapI2c2, RDC_DT_VAL(i2c2), false, false);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c3), okay)
|
||||
/* Set access to I2C-3 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapI2c3, RDC_DT_VAL(i2c3), false, false);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c4), okay)
|
||||
/* Set access to I2C-4 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapI2c4, RDC_DT_VAL(i2c4), false, false);
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm1), okay)
|
||||
/* Set access to PWM-1 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapPwm1, RDC_DT_VAL(pwm1), false, false);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm2), okay)
|
||||
/* Set access to PWM-2 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapPwm2, RDC_DT_VAL(pwm2), false, false);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm3), okay)
|
||||
/* Set access to PWM-3 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapPwm3, RDC_DT_VAL(pwm3), false, false);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm4), okay)
|
||||
/* Set access to PWM-4 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapPwm4, RDC_DT_VAL(pwm4), false, false);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm5), okay)
|
||||
/* Set access to PWM-5 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapPwm5, RDC_DT_VAL(pwm5), false, false);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm6), okay)
|
||||
/* Set access to PWM-6 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapPwm6, RDC_DT_VAL(pwm6), false, false);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm7), okay)
|
||||
/* Set access to PWM-7 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapPwm7, RDC_DT_VAL(pwm7), false, false);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm8), okay)
|
||||
/* Set access to PWM-8 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapPwm8, RDC_DT_VAL(pwm8), false, false);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(adc1), okay)
|
||||
/* Set access to ADC-1 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapAdc1, RDC_DT_VAL(adc1), false, false);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(adc2), okay)
|
||||
/* Set access to ADC-2 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapAdc2, RDC_DT_VAL(adc2), false, false);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Initialize cache. */
|
||||
static void SOC_CacheInit(void)
|
||||
{
|
||||
/* Enable System Bus Cache */
|
||||
/* set command to invalidate all ways and write GO bit
|
||||
* to initiate command
|
||||
*/
|
||||
LMEM_PSCCR = LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK;
|
||||
LMEM_PSCCR |= LMEM_PSCCR_GO_MASK;
|
||||
/* Wait until the command completes */
|
||||
while (LMEM_PSCCR & LMEM_PSCCR_GO_MASK)
|
||||
;
|
||||
/* Enable system bus cache, enable write buffer */
|
||||
LMEM_PSCCR = (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK);
|
||||
barrier_isync_fence_full();
|
||||
|
||||
/* Enable Code Bus Cache */
|
||||
/* set command to invalidate all ways and write GO bit
|
||||
* to initiate command
|
||||
*/
|
||||
LMEM_PCCCR = LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK;
|
||||
LMEM_PCCCR |= LMEM_PCCCR_GO_MASK;
|
||||
/* Wait until the command completes */
|
||||
while (LMEM_PCCCR & LMEM_PCCCR_GO_MASK)
|
||||
;
|
||||
/* Enable code bus cache, enable write buffer */
|
||||
LMEM_PCCCR = (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK);
|
||||
barrier_isync_fence_full();
|
||||
barrier_dsync_fence_full();
|
||||
}
|
||||
|
||||
/* Initialize clock. */
|
||||
static void SOC_ClockInit(void)
|
||||
{
|
||||
/* OSC/PLL is already initialized by Cortex-A9 core */
|
||||
|
||||
/* Enable IP bridge and IO mux clock */
|
||||
CCM_ControlGate(CCM, ccmCcgrGateIomuxIptClkIo, ccmClockNeededAll);
|
||||
CCM_ControlGate(CCM, ccmCcgrGateIpmux1Clk, ccmClockNeededAll);
|
||||
CCM_ControlGate(CCM, ccmCcgrGateIpmux2Clk, ccmClockNeededAll);
|
||||
CCM_ControlGate(CCM, ccmCcgrGateIpmux3Clk, ccmClockNeededAll);
|
||||
|
||||
#ifdef CONFIG_UART_IMX
|
||||
/* Set UART clock is derived from OSC clock (24M) */
|
||||
CCM_SetRootMux(CCM, ccmRootUartClkSel, ccmRootmuxUartClkOsc24m);
|
||||
|
||||
/* Configure UART divider */
|
||||
CCM_SetRootDivider(CCM, ccmRootUartClkPodf, 0);
|
||||
|
||||
/* Enable UART clock */
|
||||
CCM_ControlGate(CCM, ccmCcgrGateUartClk, ccmClockNeededAll);
|
||||
CCM_ControlGate(CCM, ccmCcgrGateUartSerialClk, ccmClockNeededAll);
|
||||
#endif /* CONFIG_UART_IMX */
|
||||
|
||||
#ifdef CONFIG_COUNTER_IMX_EPIT
|
||||
/* Select EPIT clock is derived from OSC (24M) */
|
||||
CCM_SetRootMux(CCM, ccmRootPerclkClkSel, ccmRootmuxPerclkClkOsc24m);
|
||||
|
||||
/* Configure EPIT divider */
|
||||
CCM_SetRootDivider(CCM, ccmRootPerclkPodf, 0);
|
||||
|
||||
/* Enable EPIT clocks */
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(epit1), okay)
|
||||
CCM_ControlGate(CCM, ccmCcgrGateEpit1Clk, ccmClockNeededAll);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(epit2), okay)
|
||||
CCM_ControlGate(CCM, ccmCcgrGateEpit2Clk, ccmClockNeededAll);
|
||||
#endif
|
||||
#endif /* CONFIG_COUNTER_IMX_EPIT */
|
||||
|
||||
#ifdef CONFIG_I2C_IMX
|
||||
/* Select I2C clock is derived from OSC (24M) */
|
||||
CCM_SetRootMux(CCM, ccmRootPerclkClkSel, ccmRootmuxPerclkClkOsc24m);
|
||||
|
||||
/* Set relevant divider = 1. */
|
||||
CCM_SetRootDivider(CCM, ccmRootPerclkPodf, 0);
|
||||
|
||||
/* Enable I2C clock */
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c1), okay)
|
||||
CCM_ControlGate(CCM, ccmCcgrGateI2c1Serialclk, ccmClockNeededAll);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c2), okay)
|
||||
CCM_ControlGate(CCM, ccmCcgrGateI2c2Serialclk, ccmClockNeededAll);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c3), okay)
|
||||
CCM_ControlGate(CCM, ccmCcgrGateI2c3Serialclk, ccmClockNeededAll);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c4), okay)
|
||||
CCM_ControlGate(CCM, ccmCcgrGateI2c4Serialclk, ccmClockNeededAll);
|
||||
#endif
|
||||
#endif /* CONFIG_I2C_IMX */
|
||||
|
||||
#ifdef CONFIG_PWM_IMX
|
||||
/* Select PWM clock is derived from OSC (24M) */
|
||||
CCM_SetRootMux(CCM, ccmRootPerclkClkSel, ccmRootmuxPerclkClkOsc24m);
|
||||
|
||||
/* Set relevant divider = 1. */
|
||||
CCM_SetRootDivider(CCM, ccmRootPerclkPodf, 0);
|
||||
|
||||
/* Enable PWM clock */
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm1), okay)
|
||||
CCM_ControlGate(CCM, ccmCcgrGatePwm1Clk, ccmClockNeededAll);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm2), okay)
|
||||
CCM_ControlGate(CCM, ccmCcgrGatePwm2Clk, ccmClockNeededAll);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm3), okay)
|
||||
CCM_ControlGate(CCM, ccmCcgrGatePwm3Clk, ccmClockNeededAll);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm4), okay)
|
||||
CCM_ControlGate(CCM, ccmCcgrGatePwm4Clk, ccmClockNeededAll);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm5), okay)
|
||||
CCM_ControlGate(CCM, ccmCcgrGatePwm5Clk, ccmClockNeededAll);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm6), okay)
|
||||
CCM_ControlGate(CCM, ccmCcgrGatePwm6Clk, ccmClockNeededAll);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm7), okay)
|
||||
CCM_ControlGate(CCM, ccmCcgrGatePwm7Clk, ccmClockNeededAll);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm8), okay)
|
||||
CCM_ControlGate(CCM, ccmCcgrGatePwm8Clk, ccmClockNeededAll);
|
||||
#endif
|
||||
#endif /* CONFIG_PWM_IMX */
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief Perform basic hardware initialization
|
||||
*
|
||||
* Initialize the interrupt controller device drivers.
|
||||
* Also initialize the counter device driver, if required.
|
||||
*
|
||||
* @return 0
|
||||
*/
|
||||
static int mcimx6x_m4_init(void)
|
||||
{
|
||||
/* Configure RDC */
|
||||
SOC_RdcInit();
|
||||
|
||||
/* Disable WDOG3 powerdown */
|
||||
WDOG_DisablePowerdown(WDOG3);
|
||||
|
||||
/* Initialize Cache */
|
||||
SOC_CacheInit();
|
||||
|
||||
/* Initialize clock */
|
||||
SOC_ClockInit();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(mcimx6x_m4_init, PRE_KERNEL_1, 0);
|
||||
20
soc/nxp/imx/imx6sx/soc.h
Normal file
20
soc/nxp/imx/imx6sx/soc.h
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
/*
|
||||
* Copyright (c) 2018, NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _SOC__H_
|
||||
#define _SOC__H_
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#include "rdc.h"
|
||||
#include "rdc_defs_imx6sx.h"
|
||||
#include "ccm_imx6sx.h"
|
||||
#include "clock_freq.h"
|
||||
#include "soc_clk_freq.h"
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif /* _SOC__H_ */
|
||||
79
soc/nxp/imx/imx6sx/soc_clk_freq.c
Normal file
79
soc/nxp/imx/imx6sx/soc_clk_freq.c
Normal file
|
|
@ -0,0 +1,79 @@
|
|||
/*
|
||||
* Copyright (c) 2021, Antonio Tessarolo
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <ccm_imx6sx.h>
|
||||
#include <ccm_analog_imx6sx.h>
|
||||
#include "soc_clk_freq.h"
|
||||
|
||||
#ifdef CONFIG_PWM_IMX
|
||||
|
||||
uint32_t get_pwm_clock_freq(PWM_Type *base)
|
||||
{
|
||||
uint32_t root;
|
||||
uint32_t hz;
|
||||
uint32_t divPerclkPodf, divIpgPodf, divAhbPodf, divPeriphClk2Podf;
|
||||
|
||||
/* Different instance has the same clock root, it's different from i.mx7d. */
|
||||
/* Get the clock root according to the mux node of clock tree. */
|
||||
if (CCM_GetRootMux(CCM, ccmRootPerclkClkSel) ==
|
||||
ccmRootmuxPerclkClkOsc24m) {
|
||||
root = ccmRootmuxPerclkClkOsc24m;
|
||||
hz = 24000000;
|
||||
divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf);
|
||||
divIpgPodf = 0;
|
||||
divAhbPodf = 0;
|
||||
divPeriphClk2Podf = 0;
|
||||
} else if (CCM_GetRootMux(CCM, ccmRootPeriphClkSel) ==
|
||||
ccmRootmuxPeriphClkPrePeriphClkSel) {
|
||||
root = CCM_GetRootMux(CCM, ccmRootPrePeriphClkSel);
|
||||
/* Here do not show all the clock root source,
|
||||
* if user use other clock root source, such as PLL2_PFD2, please
|
||||
* add it as follows according to the clock tree of CCM in reference manual.
|
||||
*/
|
||||
switch (root) {
|
||||
case ccmRootmuxPrePeriphClkPll2:
|
||||
hz = CCM_ANALOG_GetPllFreq(CCM_ANALOG, ccmAnalogPllSysControl);
|
||||
divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf);
|
||||
divIpgPodf = CCM_GetRootDivider(CCM, ccmRootIpgPodf);
|
||||
divAhbPodf = CCM_GetRootDivider(CCM, ccmRootAhbPodf);
|
||||
divPeriphClk2Podf = 0;
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
} else if (CCM_GetRootMux(CCM, ccmRootPeriphClk2Sel) ==
|
||||
ccmRootmuxPeriphClk2OSC24m) {
|
||||
root = ccmRootmuxPeriphClk2OSC24m;
|
||||
hz = 24000000;
|
||||
divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf);
|
||||
divIpgPodf = CCM_GetRootDivider(CCM, ccmRootIpgPodf);
|
||||
divAhbPodf = CCM_GetRootDivider(CCM, ccmRootAhbPodf);
|
||||
divPeriphClk2Podf = CCM_GetRootDivider(CCM, ccmRootPeriphClk2Podf);
|
||||
} else {
|
||||
root = CCM_GetRootMux(CCM, ccmRootPll3SwClkSel);
|
||||
/* Here do not show all the clock root source,
|
||||
* if user use other clock root source, such as PLL3_BYP, please
|
||||
* add it as follows according to the clock tree of CCM in reference manual.
|
||||
*/
|
||||
switch (root) {
|
||||
case ccmRootmuxPll3SwClkPll3:
|
||||
hz = CCM_ANALOG_GetPllFreq(CCM_ANALOG, ccmAnalogPllUsb1Control);
|
||||
divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf);
|
||||
divIpgPodf = CCM_GetRootDivider(CCM, ccmRootIpgPodf);
|
||||
divAhbPodf = CCM_GetRootDivider(CCM, ccmRootAhbPodf);
|
||||
divPeriphClk2Podf =
|
||||
CCM_GetRootDivider(CCM, ccmRootPeriphClk2Podf);
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
return hz / (divPerclkPodf + 1) / (divIpgPodf + 1) /
|
||||
(divAhbPodf + 1) / (divPeriphClk2Podf + 1);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_PWM_IMX */
|
||||
30
soc/nxp/imx/imx6sx/soc_clk_freq.h
Normal file
30
soc/nxp/imx/imx6sx/soc_clk_freq.h
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* Copyright (c) 2021, Antonio Tessarolo
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __SOC_CLOCK_FREQ_H__
|
||||
#define __SOC_CLOCK_FREQ_H__
|
||||
|
||||
#include "device_imx.h"
|
||||
#include <zephyr/types.h>
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PWM_IMX
|
||||
/*!
|
||||
* @brief Get clock frequency applies to the PWM module
|
||||
*
|
||||
* @param base PWM base pointer.
|
||||
* @return clock frequency (in HZ) applies to the PWM module
|
||||
*/
|
||||
uint32_t get_pwm_clock_freq(PWM_Type *base);
|
||||
#endif /* CONFIG_PWM_IMX */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
#endif /* __SOC_CLOCK_FREQ_H__ */
|
||||
14
soc/nxp/imx/imx7d/CMakeLists.txt
Normal file
14
soc/nxp/imx/imx7d/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
#
|
||||
# Copyright 2017,2024 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
zephyr_sources(
|
||||
soc.c
|
||||
soc_clk_freq.c
|
||||
)
|
||||
|
||||
zephyr_include_directories(.)
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
|
||||
16
soc/nxp/imx/imx7d/Kconfig
Normal file
16
soc/nxp/imx/imx7d/Kconfig
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
# Copyright 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_IMX7D
|
||||
select ARM
|
||||
select CPU_CORTEX_M4
|
||||
select CPU_CORTEX_M_HAS_DWT
|
||||
select CLOCK_CONTROL
|
||||
select CPU_HAS_FPU
|
||||
select CPU_HAS_ARM_MPU
|
||||
|
||||
config SOC_MCIMX7D_M4
|
||||
select HAS_IMX_HAL
|
||||
select HAS_IMX_GPIO
|
||||
select HAS_IMX_I2C
|
||||
select HAS_IMX_IOMUXC
|
||||
18
soc/nxp/imx/imx7d/Kconfig.defconfig
Normal file
18
soc/nxp/imx/imx7d/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
# iMX7 core series
|
||||
|
||||
# Copyright 2017,2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_IMX7D
|
||||
|
||||
config NUM_IRQS
|
||||
# must be >= the highest interrupt number used
|
||||
default 127
|
||||
|
||||
config PINCTRL_IMX
|
||||
default y if HAS_IMX_IOMUXC
|
||||
depends on PINCTRL
|
||||
|
||||
rsource "Kconfig.defconfig.*"
|
||||
|
||||
endif # SOC_SERIES_IMX7D
|
||||
14
soc/nxp/imx/imx7d/Kconfig.defconfig.mcimx7d_m4
Normal file
14
soc/nxp/imx/imx7d/Kconfig.defconfig.mcimx7d_m4
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
# iMX7 M4 core series
|
||||
|
||||
# Copyright 2017,2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_MCIMX7D_M4
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default 200000000
|
||||
|
||||
config GPIO
|
||||
default y
|
||||
|
||||
endif # SOC_MCIMX7D_M4
|
||||
40
soc/nxp/imx/imx7d/Kconfig.soc
Normal file
40
soc/nxp/imx/imx7d/Kconfig.soc
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
# iMX7D core series
|
||||
|
||||
# Copyright 2017,2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_IMX7D
|
||||
bool
|
||||
select SOC_FAMILY_NXP_IMX
|
||||
help
|
||||
Enable support for iMX7D MCU series
|
||||
|
||||
config SOC_MCIMX7D
|
||||
bool
|
||||
select SOC_SERIES_IMX7D
|
||||
|
||||
config SOC_MCIMX7D_M4
|
||||
bool
|
||||
select SOC_MCIMX7D
|
||||
help
|
||||
NXP iMX7 Dual M4 Core
|
||||
|
||||
config SOC_SERIES
|
||||
default "imx7d" if SOC_SERIES_IMX7D
|
||||
|
||||
config SOC
|
||||
default "mcimx7d" if SOC_MCIMX7D
|
||||
|
||||
config SOC_PART_NUMBER_MCIMX7D7DVM10SC
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MCIMX7D5EVM10SC
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MCIMX7S3DVK08SA
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER
|
||||
default "MCIMX7D7DVM10SC" if SOC_PART_NUMBER_MCIMX7D7DVM10SC
|
||||
default "MCIMX7D5EVM10SC" if SOC_PART_NUMBER_MCIMX7D5EVM10SC
|
||||
default "MCIMX7S3DVK08SA" if SOC_PART_NUMBER_MCIMX7S3DVK08SA
|
||||
98
soc/nxp/imx/imx7d/pinctrl_soc.h
Normal file
98
soc/nxp/imx/imx7d/pinctrl_soc.h
Normal file
|
|
@ -0,0 +1,98 @@
|
|||
/*
|
||||
* Copyright (c) 2022, NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_ARM_NXP_IMX_MCIMX6X_PINCTRL_SOC_H_
|
||||
#define ZEPHYR_SOC_ARM_NXP_IMX_MCIMX6X_PINCTRL_SOC_H_
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/types.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) ((x) & 0xF)
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((x) & 0x1) << 4)
|
||||
#define IOMUXC_SELECT_INPUT_DAISY(x) ((x) & 0x7)
|
||||
|
||||
#define MCUX_IMX_BIAS_PULL_UP_SHIFT 5
|
||||
#define MCUX_IMX_PULL_ENABLE_SHIFT 4
|
||||
#define MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT 3
|
||||
#define MCUX_IMX_SLEW_RATE_SHIFT 2
|
||||
#define MCUX_IMX_DRIVE_STRENGTH_SHIFT 0
|
||||
#define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
|
||||
#define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1)
|
||||
|
||||
#define Z_PINCTRL_MCUX_IMX_PINCFG_INIT(node_id) \
|
||||
((DT_PROP(node_id, input_schmitt_enable) << MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT) | \
|
||||
IF_ENABLED(DT_PROP(node_id, bias_pull_up), (DT_ENUM_IDX(node_id, bias_pull_up_value) \
|
||||
<< MCUX_IMX_BIAS_PULL_UP_SHIFT) |) \
|
||||
((DT_PROP(node_id, bias_pull_down) | DT_PROP(node_id, bias_pull_up)) \
|
||||
<< MCUX_IMX_PULL_ENABLE_SHIFT) | \
|
||||
(DT_ENUM_IDX(node_id, drive_strength) << MCUX_IMX_DRIVE_STRENGTH_SHIFT) | \
|
||||
(DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \
|
||||
(DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT))
|
||||
|
||||
|
||||
#define Z_PINCTRL_MCUX_IMX_LPSR_PINCFG_INIT(node_id) \
|
||||
(IF_ENABLED(DT_PROP(node_id, bias_pull_up), (DT_ENUM_IDX(node_id, bias_pull_up_value) \
|
||||
<< MCUX_IMX_BIAS_PULL_UP_SHIFT) |) \
|
||||
IF_ENABLED(DT_PROP(node_id, bias_pull_down), (DT_ENUM_IDX(node_id, bias_pull_down_value)\
|
||||
<< MCUX_IMX_BIAS_PULL_DOWN_SHIFT) |) \
|
||||
((DT_PROP(node_id, bias_pull_down) | DT_PROP(node_id, bias_pull_up)) \
|
||||
<< MCUX_IMX_PULL_ENABLE_SHIFT) | \
|
||||
(DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT))
|
||||
|
||||
|
||||
/* This struct must be present. It is used by the mcux gpio driver */
|
||||
struct pinctrl_soc_pinmux {
|
||||
uint32_t mux_register; /*!< IOMUXC SW_PAD_MUX register */
|
||||
uint32_t config_register; /*!< IOMUXC SW_PAD_CTL register */
|
||||
uint32_t input_register; /*!< IOMUXC SELECT_INPUT DAISY register */
|
||||
uint8_t mux_mode: 4; /*!< Mux value for SW_PAD_MUX register */
|
||||
uint32_t input_daisy:4; /*!< Mux value for SELECT_INPUT_DAISY register */
|
||||
};
|
||||
|
||||
struct pinctrl_soc_pin {
|
||||
struct pinctrl_soc_pinmux pinmux;
|
||||
uint32_t pin_ctrl_flags; /*!< value to write to IOMUXC_SW_PAD_CTL register */
|
||||
};
|
||||
|
||||
typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
|
||||
|
||||
/* This definition must be present. It is used by the mcux gpio driver */
|
||||
#define MCUX_IMX_PINMUX(node_id) \
|
||||
{ \
|
||||
.mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \
|
||||
.config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \
|
||||
.input_register = DT_PROP_BY_IDX(node_id, pinmux, 2), \
|
||||
.mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1), \
|
||||
.input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3), \
|
||||
}
|
||||
|
||||
#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \
|
||||
MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
|
||||
|
||||
#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \
|
||||
{ \
|
||||
.pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
|
||||
.pin_ctrl_flags = COND_CODE_0( \
|
||||
DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_lpsr), \
|
||||
(Z_PINCTRL_MCUX_IMX_PINCFG_INIT(group_id)), \
|
||||
(Z_PINCTRL_MCUX_IMX_LPSR_PINCFG_INIT(group_id))), \
|
||||
},
|
||||
|
||||
|
||||
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
|
||||
DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)}; \
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ZEPHYR_SOC_ARM_NXP_IMX_MCIMX6X_PINCTRL_SOC_H_ */
|
||||
257
soc/nxp/imx/imx7d/soc.c
Normal file
257
soc/nxp/imx/imx7d/soc.c
Normal file
|
|
@ -0,0 +1,257 @@
|
|||
/*
|
||||
* Copyright (c) 2017, NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/init.h>
|
||||
#include <soc.h>
|
||||
#include <zephyr/dt-bindings/rdc/imx_rdc.h>
|
||||
#include <zephyr/devicetree.h>
|
||||
#include "wdog_imx.h"
|
||||
|
||||
/* Initialize clock. */
|
||||
void SOC_ClockInit(void)
|
||||
{
|
||||
/* OSC/PLL is already initialized by Cortex-A7 (u-boot) */
|
||||
|
||||
/*
|
||||
* Disable WDOG3
|
||||
* Note : The WDOG clock Root is shared by all the 4 WDOGs,
|
||||
* so Zephyr code should avoid closing it
|
||||
*/
|
||||
CCM_UpdateRoot(CCM, ccmRootWdog, ccmRootmuxWdogOsc24m, 0, 0);
|
||||
CCM_EnableRoot(CCM, ccmRootWdog);
|
||||
CCM_ControlGate(CCM, ccmCcgrGateWdog3, ccmClockNeededRun);
|
||||
|
||||
RDC_SetPdapAccess(RDC, rdcPdapWdog3,
|
||||
RDC_DOMAIN_PERM(M4_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
|
||||
false, false);
|
||||
|
||||
WDOG_DisablePowerdown(WDOG3);
|
||||
|
||||
CCM_ControlGate(CCM, ccmCcgrGateWdog3, ccmClockNotNeeded);
|
||||
|
||||
/* We need system PLL Div2 to run M4 core */
|
||||
CCM_ControlGate(CCM, ccmPllGateSys, ccmClockNeededRun);
|
||||
CCM_ControlGate(CCM, ccmPllGateSysDiv2, ccmClockNeededRun);
|
||||
|
||||
/* Enable clock gate for IP bridge and IO mux */
|
||||
CCM_ControlGate(CCM, ccmCcgrGateIpmux1, ccmClockNeededRun);
|
||||
CCM_ControlGate(CCM, ccmCcgrGateIpmux2, ccmClockNeededRun);
|
||||
CCM_ControlGate(CCM, ccmCcgrGateIpmux3, ccmClockNeededRun);
|
||||
CCM_ControlGate(CCM, ccmCcgrGateIomux, ccmClockNeededRun);
|
||||
CCM_ControlGate(CCM, ccmCcgrGateIomuxLpsr, ccmClockNeededRun);
|
||||
|
||||
/* Enable clock gate for RDC */
|
||||
CCM_ControlGate(CCM, ccmCcgrGateRdc, ccmClockNeededRun);
|
||||
}
|
||||
|
||||
void SOC_RdcInit(void)
|
||||
{
|
||||
/* Move M4 core to specific RDC domain */
|
||||
RDC_SetDomainID(RDC, rdcMdaM4, M4_DOMAIN_ID, false);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_GPIO_IMX
|
||||
static void nxp_mcimx7_gpio_config(void)
|
||||
{
|
||||
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
|
||||
RDC_SetPdapAccess(RDC, rdcPdapGpio1, RDC_DT_VAL(gpio1), false, false);
|
||||
/* Enable gpio clock gate */
|
||||
CCM_ControlGate(CCM, ccmCcgrGateGpio1, ccmClockNeededRunWait);
|
||||
#endif
|
||||
|
||||
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay)
|
||||
RDC_SetPdapAccess(RDC, rdcPdapGpio2, RDC_DT_VAL(gpio2), false, false);
|
||||
/* Enable gpio clock gate */
|
||||
CCM_ControlGate(CCM, ccmCcgrGateGpio2, ccmClockNeededRunWait);
|
||||
#endif
|
||||
|
||||
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio7), okay)
|
||||
RDC_SetPdapAccess(RDC, rdcPdapGpio7, RDC_DT_VAL(gpio7), false, false);
|
||||
/* Enable gpio clock gate */
|
||||
CCM_ControlGate(CCM, ccmCcgrGateGpio7, ccmClockNeededRunWait);
|
||||
#endif
|
||||
|
||||
}
|
||||
#endif /* CONFIG_GPIO_IMX */
|
||||
|
||||
#ifdef CONFIG_UART_IMX
|
||||
static void nxp_mcimx7_uart_config(void)
|
||||
{
|
||||
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay)
|
||||
/* We need to grasp board uart exclusively */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapUart2, RDC_DT_VAL(uart2), false, false);
|
||||
/* Select clock derived from OSC clock(24M) */
|
||||
CCM_UpdateRoot(CCM, ccmRootUart2, ccmRootmuxUartOsc24m, 0, 0);
|
||||
/* Enable uart clock */
|
||||
CCM_EnableRoot(CCM, ccmRootUart2);
|
||||
/*
|
||||
* IC Limitation
|
||||
* M4 stop will cause A7 UART lose functionality
|
||||
* So we need UART clock all the time
|
||||
*/
|
||||
CCM_ControlGate(CCM, ccmCcgrGateUart2, ccmClockNeededAll);
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart6), okay)
|
||||
/* We need to grasp board uart exclusively */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapUart6, RDC_DT_VAL(uart6), false, false);
|
||||
/* Select clock derived from OSC clock(24M) */
|
||||
CCM_UpdateRoot(CCM, ccmRootUart6, ccmRootmuxUartOsc24m, 0, 0);
|
||||
/* Enable uart clock */
|
||||
CCM_EnableRoot(CCM, ccmRootUart6);
|
||||
/*
|
||||
* IC Limitation
|
||||
* M4 stop will cause A7 UART lose functionality
|
||||
* So we need UART clock all the time
|
||||
*/
|
||||
CCM_ControlGate(CCM, ccmCcgrGateUart6, ccmClockNeededAll);
|
||||
#endif
|
||||
}
|
||||
#endif /* CONFIG_UART_IMX */
|
||||
|
||||
|
||||
#ifdef CONFIG_I2C_IMX
|
||||
static void nxp_mcimx7_i2c_config(void)
|
||||
{
|
||||
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c1), okay)
|
||||
/* In this example, we need to grasp board I2C exclusively */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapI2c1, RDC_DT_VAL(i2c1), false, false);
|
||||
/* Select I2C clock derived from OSC clock(24M) */
|
||||
CCM_UpdateRoot(CCM, ccmRootI2c1, ccmRootmuxI2cOsc24m, 0, 0);
|
||||
/* Enable I2C clock */
|
||||
CCM_EnableRoot(CCM, ccmRootI2c1);
|
||||
CCM_ControlGate(CCM, ccmCcgrGateI2c1, ccmClockNeededRunWait);
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c2), okay)
|
||||
/* In this example, we need to grasp board I2C exclusively */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapI2c2, RDC_DT_VAL(i2c2), false, false);
|
||||
/* Select I2C clock derived from OSC clock(24M) */
|
||||
CCM_UpdateRoot(CCM, ccmRootI2c2, ccmRootmuxI2cOsc24m, 0, 0);
|
||||
/* Enable I2C clock */
|
||||
CCM_EnableRoot(CCM, ccmRootI2c2);
|
||||
CCM_ControlGate(CCM, ccmCcgrGateI2c2, ccmClockNeededRunWait);
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c3), okay)
|
||||
/* In this example, we need to grasp board I2C exclusively */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapI2c3, RDC_DT_VAL(i2c3), false, false);
|
||||
/* Select I2C clock derived from OSC clock(24M) */
|
||||
CCM_UpdateRoot(CCM, ccmRootI2c3, ccmRootmuxI2cOsc24m, 0, 0);
|
||||
/* Enable I2C clock */
|
||||
CCM_EnableRoot(CCM, ccmRootI2c3);
|
||||
CCM_ControlGate(CCM, ccmCcgrGateI2c3, ccmClockNeededRunWait);
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c4), okay)
|
||||
/* In this example, we need to grasp board I2C exclusively */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapI2c4, RDC_DT_VAL(i2c4), false, false);
|
||||
/* Select I2C clock derived from OSC clock(24M) */
|
||||
CCM_UpdateRoot(CCM, ccmRootI2c4, ccmRootmuxI2cOsc24m, 0, 0);
|
||||
/* Enable I2C clock */
|
||||
CCM_EnableRoot(CCM, ccmRootI2c4);
|
||||
CCM_ControlGate(CCM, ccmCcgrGateI2c4, ccmClockNeededRunWait);
|
||||
#endif
|
||||
|
||||
}
|
||||
#endif /* CONFIG_I2C_IMX */
|
||||
|
||||
#ifdef CONFIG_PWM_IMX
|
||||
static void nxp_mcimx7_pwm_config(void)
|
||||
{
|
||||
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm1), okay)
|
||||
/* We need to grasp board pwm exclusively */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapPwm1, RDC_DT_VAL(pwm1), false, false);
|
||||
/* Select clock derived from OSC clock(24M) */
|
||||
CCM_UpdateRoot(CCM, ccmRootPwm1, ccmRootmuxPwmOsc24m, 0, 0);
|
||||
/* Enable pwm clock */
|
||||
CCM_EnableRoot(CCM, ccmRootPwm1);
|
||||
CCM_ControlGate(CCM, ccmCcgrGatePwm1, ccmClockNeededAll);
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm2), okay)
|
||||
/* We need to grasp board pwm exclusively */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapPwm2, RDC_DT_VAL(pwm2), false, false);
|
||||
/* Select clock derived from OSC clock(24M) */
|
||||
CCM_UpdateRoot(CCM, ccmRootPwm2, ccmRootmuxPwmOsc24m, 0, 0);
|
||||
/* Enable pwm clock */
|
||||
CCM_EnableRoot(CCM, ccmRootPwm2);
|
||||
CCM_ControlGate(CCM, ccmCcgrGatePwm2, ccmClockNeededAll);
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm3), okay)
|
||||
/* We need to grasp board pwm exclusively */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapPwm3, RDC_DT_VAL(pwm3), false, false);
|
||||
/* Select clock derived from OSC clock(24M) */
|
||||
CCM_UpdateRoot(CCM, ccmRootPwm3, ccmRootmuxPwmOsc24m, 0, 0);
|
||||
/* Enable pwm clock */
|
||||
CCM_EnableRoot(CCM, ccmRootPwm3);
|
||||
CCM_ControlGate(CCM, ccmCcgrGatePwm3, ccmClockNeededAll);
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm4), okay)
|
||||
/* We need to grasp board pwm exclusively */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapPwm4, RDC_DT_VAL(pwm4), false, false);
|
||||
/* Select clock derived from OSC clock(24M) */
|
||||
CCM_UpdateRoot(CCM, ccmRootPwm4, ccmRootmuxPwmOsc24m, 0, 0);
|
||||
/* Enable pwm clock */
|
||||
CCM_EnableRoot(CCM, ccmRootPwm4);
|
||||
CCM_ControlGate(CCM, ccmCcgrGatePwm4, ccmClockNeededAll);
|
||||
#endif
|
||||
|
||||
}
|
||||
#endif /* CONFIG_PWM_IMX */
|
||||
|
||||
#ifdef CONFIG_IPM_IMX
|
||||
static void nxp_mcimx7_mu_config(void)
|
||||
{
|
||||
/* Set access to MU B for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapMuB, RDC_DT_VAL(mub), false, false);
|
||||
|
||||
/* Enable clock gate for MU*/
|
||||
CCM_ControlGate(CCM, ccmCcgrGateMu, ccmClockNeededRun);
|
||||
}
|
||||
#endif /* CONFIG_IPM_IMX */
|
||||
|
||||
static int nxp_mcimx7_init(void)
|
||||
{
|
||||
|
||||
/* SoC specific RDC settings */
|
||||
SOC_RdcInit();
|
||||
|
||||
/* BoC specific clock settings */
|
||||
SOC_ClockInit();
|
||||
|
||||
#ifdef CONFIG_GPIO_IMX
|
||||
nxp_mcimx7_gpio_config();
|
||||
#endif /* CONFIG_GPIO_IMX */
|
||||
|
||||
#ifdef CONFIG_UART_IMX
|
||||
nxp_mcimx7_uart_config();
|
||||
#endif /* CONFIG_UART_IMX */
|
||||
|
||||
#ifdef CONFIG_I2C_IMX
|
||||
nxp_mcimx7_i2c_config();
|
||||
#endif /* CONFIG_I2C_IMX */
|
||||
|
||||
#ifdef CONFIG_PWM_IMX
|
||||
nxp_mcimx7_pwm_config();
|
||||
#endif /* CONFIG_PWM_IMX */
|
||||
|
||||
#ifdef CONFIG_IPM_IMX
|
||||
nxp_mcimx7_mu_config();
|
||||
#endif /* CONFIG_IPM_IMX */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(nxp_mcimx7_init, PRE_KERNEL_1, 0);
|
||||
20
soc/nxp/imx/imx7d/soc.h
Normal file
20
soc/nxp/imx/imx7d/soc.h
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
/*
|
||||
* Copyright (c) 2017, NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _SOC__H_
|
||||
#define _SOC__H_
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#include "rdc.h"
|
||||
#include "rdc_defs_imx7d.h"
|
||||
#include "ccm_imx7d.h"
|
||||
#include "clock_freq.h"
|
||||
#include "soc_clk_freq.h"
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif /* _SOC__H_ */
|
||||
52
soc/nxp/imx/imx7d/soc_clk_freq.c
Normal file
52
soc/nxp/imx/imx7d/soc_clk_freq.c
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Diego Sueiro
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <ccm_imx7d.h>
|
||||
#include <ccm_analog_imx7d.h>
|
||||
#include "soc_clk_freq.h"
|
||||
|
||||
#ifdef CONFIG_PWM_IMX
|
||||
uint32_t get_pwm_clock_freq(PWM_Type *base)
|
||||
{
|
||||
uint32_t root;
|
||||
uint32_t hz;
|
||||
uint32_t pre, post;
|
||||
|
||||
switch ((uint32_t)base) {
|
||||
case PWM1_BASE:
|
||||
root = CCM_GetRootMux(CCM, ccmRootPwm1);
|
||||
CCM_GetRootDivider(CCM, ccmRootPwm1, &pre, &post);
|
||||
break;
|
||||
case PWM2_BASE:
|
||||
root = CCM_GetRootMux(CCM, ccmRootPwm2);
|
||||
CCM_GetRootDivider(CCM, ccmRootPwm2, &pre, &post);
|
||||
break;
|
||||
case PWM3_BASE:
|
||||
root = CCM_GetRootMux(CCM, ccmRootPwm3);
|
||||
CCM_GetRootDivider(CCM, ccmRootPwm3, &pre, &post);
|
||||
break;
|
||||
case PWM4_BASE:
|
||||
root = CCM_GetRootMux(CCM, ccmRootPwm4);
|
||||
CCM_GetRootDivider(CCM, ccmRootPwm4, &pre, &post);
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
switch (root) {
|
||||
case ccmRootmuxPwmOsc24m:
|
||||
hz = 24000000U;
|
||||
break;
|
||||
case ccmRootmuxPwmSysPllDiv4:
|
||||
hz = CCM_ANALOG_GetSysPllFreq(CCM_ANALOG) >> 2;
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
return hz / (pre + 1) / (post + 1);
|
||||
}
|
||||
#endif /* CONFIG_PWM_IMX */
|
||||
58
soc/nxp/imx/imx7d/soc_clk_freq.h
Normal file
58
soc/nxp/imx/imx7d/soc_clk_freq.h
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Diego Sueiro
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __SOC_CLOCK_FREQ_H__
|
||||
#define __SOC_CLOCK_FREQ_H__
|
||||
|
||||
#include "device_imx.h"
|
||||
#include <zephyr/types.h>
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PWM_IMX
|
||||
/*!
|
||||
* @brief Get clock frequency applies to the PWM module
|
||||
*
|
||||
* @param base PWM base pointer.
|
||||
* @return clock frequency (in HZ) applies to the PWM module
|
||||
*/
|
||||
uint32_t get_pwm_clock_freq(PWM_Type *base);
|
||||
#endif /* CONFIG_PWM_IMX */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @brief Root control names for root clock setting. */
|
||||
enum _ccm_root_control_extra {
|
||||
ccmRootPwm1 = (uint32_t)(&CCM_TARGET_ROOT106),
|
||||
ccmRootPwm2 = (uint32_t)(&CCM_TARGET_ROOT107),
|
||||
ccmRootPwm3 = (uint32_t)(&CCM_TARGET_ROOT108),
|
||||
ccmRootPwm4 = (uint32_t)(&CCM_TARGET_ROOT109),
|
||||
};
|
||||
|
||||
/*! @brief Clock source enumeration for PWM peripheral. */
|
||||
enum _ccm_rootmux_pwm {
|
||||
ccmRootmuxPwmOsc24m = 0U,
|
||||
ccmRootmuxPwmEnetPllDiv10 = 1U,
|
||||
ccmRootmuxPwmSysPllDiv4 = 2U,
|
||||
ccmRootmuxPwmEnetPllDiv25 = 3U,
|
||||
ccmRootmuxPwmAudioPll = 4U,
|
||||
ccmRootmuxPwmExtClk2 = 5U,
|
||||
ccmRootmuxPwmRef1m = 6U,
|
||||
ccmRootmuxPwmVideoPll = 7U,
|
||||
};
|
||||
|
||||
/*! @brief CCM CCGR gate control. */
|
||||
enum _ccm_ccgr_gate_extra {
|
||||
ccmCcgrGatePwm1 = (uint32_t)(&CCM_CCGR132),
|
||||
ccmCcgrGatePwm2 = (uint32_t)(&CCM_CCGR133),
|
||||
ccmCcgrGatePwm3 = (uint32_t)(&CCM_CCGR134),
|
||||
ccmCcgrGatePwm4 = (uint32_t)(&CCM_CCGR135),
|
||||
};
|
||||
#endif /* __SOC_CLOCK_FREQ_H__ */
|
||||
27
soc/nxp/imx/imx8/CMakeLists.txt
Normal file
27
soc/nxp/imx/imx8/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
# Copyright 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if(CONFIG_SOC_MIMX8QM_ADSP)
|
||||
zephyr_include_directories(adsp)
|
||||
add_subdirectory(adsp)
|
||||
|
||||
zephyr_sources(
|
||||
adsp/pinctrl_soc.h
|
||||
)
|
||||
|
||||
# west sign
|
||||
|
||||
# See detailed comments in soc/intel/intel_adsp/common/CMakeLists.txt
|
||||
add_custom_target(zephyr.ri ALL
|
||||
DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri
|
||||
)
|
||||
|
||||
add_custom_command(
|
||||
OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri
|
||||
COMMENT "west sign --if-tool-available --tool rimage ..."
|
||||
COMMAND west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS}
|
||||
DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}
|
||||
)
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/adsp/linker.ld CACHE INTERNAL "")
|
||||
endif()
|
||||
15
soc/nxp/imx/imx8/Kconfig
Normal file
15
soc/nxp/imx/imx8/Kconfig
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
# Copyright 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_MIMX8QM_ADSP
|
||||
select XTENSA
|
||||
select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
|
||||
select XTENSA_RESET_VECTOR
|
||||
select XTENSA_USE_CORE_CRT1
|
||||
select ATOMIC_OPERATIONS_BUILTIN
|
||||
select GEN_ISR_TABLES
|
||||
select XTENSA_SMALL_VECTOR_TABLE_ENTRY
|
||||
select HAS_MCUX
|
||||
|
||||
config MCUX_CORE_SUFFIX
|
||||
default "_dsp" if SOC_MIMX8QM_ADSP
|
||||
45
soc/nxp/imx/imx8/Kconfig.defconfig
Normal file
45
soc/nxp/imx/imx8/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
# Copyright 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_IMX8
|
||||
|
||||
if SOC_MIMX8QM_ADSP
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default 666000000
|
||||
|
||||
config SYS_CLOCK_TICKS_PER_SEC
|
||||
default 50000
|
||||
|
||||
config DCACHE_LINE_SIZE
|
||||
default 128
|
||||
|
||||
config GEN_IRQ_VECTOR_TABLE
|
||||
default n
|
||||
|
||||
config CACHE_MANAGEMENT
|
||||
default y
|
||||
|
||||
config SMP
|
||||
default n
|
||||
|
||||
config XTENSA_TIMER
|
||||
default y
|
||||
|
||||
config KERNEL_ENTRY
|
||||
default "__start"
|
||||
|
||||
config MULTI_LEVEL_INTERRUPTS
|
||||
default n
|
||||
|
||||
config 2ND_LEVEL_INTERRUPTS
|
||||
default n
|
||||
|
||||
# To prevent test uses TEST_LOGGING_MINIMAL
|
||||
config TEST_LOGGING_DEFAULTS
|
||||
default n
|
||||
depends on TEST
|
||||
|
||||
endif # SOC_MIMX8QM_ADSP
|
||||
|
||||
endif # SOC_SERIES_IMX8
|
||||
32
soc/nxp/imx/imx8/Kconfig.soc
Normal file
32
soc/nxp/imx/imx8/Kconfig.soc
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
# Copyright 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_IMX8
|
||||
bool
|
||||
select SOC_FAMILY_NXP_IMX
|
||||
|
||||
config SOC_SERIES
|
||||
default "imx8" if SOC_SERIES_IMX8
|
||||
|
||||
config SOC_MIMX8QM
|
||||
bool
|
||||
select SOC_SERIES_IMX8
|
||||
|
||||
config SOC
|
||||
default "mimx8qm6" if SOC_MIMX8QM
|
||||
|
||||
config SOC_MIMX8QM_ADSP
|
||||
bool
|
||||
select SOC_MIMX8QM
|
||||
help
|
||||
Enable support for NXP i.MX 8QM Audio DSP
|
||||
|
||||
config SOC_TOOLCHAIN_NAME
|
||||
string
|
||||
default "nxp_imx_adsp" if SOC_MIMX8QM_ADSP
|
||||
|
||||
config SOC_PART_NUMBER_MIMX8QM6AVUFF
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER
|
||||
default "MIMX8QM6AVUFF" if SOC_PART_NUMBER_MIMX8QM6AVUFF
|
||||
6
soc/nxp/imx/imx8/adsp/CMakeLists.txt
Normal file
6
soc/nxp/imx/imx8/adsp/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
# NXP SoC family CMake file
|
||||
#
|
||||
# Copyright (c) 2021, 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_include_directories(include)
|
||||
177
soc/nxp/imx/imx8/adsp/_soc_inthandlers.h
Normal file
177
soc/nxp/imx/imx8/adsp/_soc_inthandlers.h
Normal file
|
|
@ -0,0 +1,177 @@
|
|||
/*
|
||||
* Copyright (c) 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
/*
|
||||
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*
|
||||
* Functions here are designed to produce efficient code to
|
||||
* search an Xtensa bitmask of interrupts, inspecting only those bits
|
||||
* declared to be associated with a given interrupt level. Each
|
||||
* dispatcher will handle exactly one flagged interrupt, in numerical
|
||||
* order (low bits first) and will return a mask of that bit that can
|
||||
* then be cleared by the calling code. Unrecognized bits for the
|
||||
* level will invoke an error handler.
|
||||
*/
|
||||
|
||||
#include <xtensa/config/core-isa.h>
|
||||
#include <zephyr/sys/util.h>
|
||||
#include <zephyr/sw_isr_table.h>
|
||||
|
||||
#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 5
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
|
||||
static inline int _xtensa_handle_one_int1(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (mask & BIT(8)) {
|
||||
mask = BIT(8);
|
||||
irq = 8;
|
||||
goto handle_irq;
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int2(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
int i = 0;
|
||||
|
||||
mask &= XCHAL_INTLEVEL2_MASK;
|
||||
for (i = 0; i <= 31; i++)
|
||||
if (mask & BIT(i)) {
|
||||
mask = BIT(i);
|
||||
irq = i;
|
||||
goto handle_irq;
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int3(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (mask & BIT(1)) {
|
||||
mask = BIT(1);
|
||||
irq = 1;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(3)) {
|
||||
mask = BIT(3);
|
||||
irq = 3;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(31)) {
|
||||
mask = BIT(31);
|
||||
irq = 31;
|
||||
goto handle_irq;
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int5(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (mask & BIT(0)) {
|
||||
mask = BIT(0);
|
||||
irq = 0;
|
||||
goto handle_irq;
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int0(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int4(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int6(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int7(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
12
soc/nxp/imx/imx8/adsp/include/adsp/cache.h
Normal file
12
soc/nxp/imx/imx8/adsp/include/adsp/cache.h
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __COMMON_ADSP_CACHE_H__
|
||||
#define __COMMON_ADSP_CACHE_H__
|
||||
|
||||
#include <xtensa/hal.h>
|
||||
|
||||
#endif
|
||||
41
soc/nxp/imx/imx8/adsp/include/adsp/io.h
Normal file
41
soc/nxp/imx/imx8/adsp/include/adsp/io.h
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* Copyright (c) 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __INCLUDE_IO__
|
||||
#define __INCLUDE_IO__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <soc/memory.h>
|
||||
#include <zephyr/sys/sys_io.h>
|
||||
#include <zephyr/arch/common/sys_io.h>
|
||||
|
||||
static inline uint32_t io_reg_read(uint32_t reg)
|
||||
{
|
||||
return sys_read32(reg);
|
||||
}
|
||||
|
||||
static inline void io_reg_write(uint32_t reg, uint32_t val)
|
||||
{
|
||||
sys_write32(val, reg);
|
||||
}
|
||||
|
||||
static inline void io_reg_update_bits(uint32_t reg, uint32_t mask,
|
||||
uint32_t value)
|
||||
{
|
||||
io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask));
|
||||
}
|
||||
|
||||
static inline uint16_t io_reg_read16(uint32_t reg)
|
||||
{
|
||||
return sys_read16(reg);
|
||||
}
|
||||
|
||||
static inline void io_reg_write16(uint32_t reg, uint16_t val)
|
||||
{
|
||||
sys_write16(val, reg);
|
||||
}
|
||||
|
||||
#endif
|
||||
33
soc/nxp/imx/imx8/adsp/include/soc.h
Normal file
33
soc/nxp/imx/imx8/adsp/include/soc.h
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* Copyright (c) 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <zephyr/sys/sys_io.h>
|
||||
|
||||
#include <adsp/cache.h>
|
||||
|
||||
#ifndef __INC_IMX_SOC_H
|
||||
#define __INC_IMX_SOC_H
|
||||
|
||||
/* Macros related to interrupt handling */
|
||||
#define XTENSA_IRQ_NUM_SHIFT 0
|
||||
#define XTENSA_IRQ_NUM_MASK 0xff
|
||||
|
||||
/*
|
||||
* IRQs are mapped on levels. 2nd, 3rd and 4th level are left as 0x00.
|
||||
*
|
||||
* 1. Peripheral Register bit offset.
|
||||
*/
|
||||
#define XTENSA_IRQ_NUMBER(_irq) \
|
||||
((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK)
|
||||
|
||||
extern void z_soc_irq_enable(uint32_t irq);
|
||||
extern void z_soc_irq_disable(uint32_t irq);
|
||||
extern int z_soc_irq_is_enabled(unsigned int irq);
|
||||
|
||||
#endif /* __INC_IMX_SOC_H */
|
||||
517
soc/nxp/imx/imx8/adsp/linker.ld
Normal file
517
soc/nxp/imx/imx8/adsp/linker.ld
Normal file
|
|
@ -0,0 +1,517 @@
|
|||
/*
|
||||
* Copyright (c) 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Linker command/script file
|
||||
*
|
||||
* Linker script for the NXP i.MX8 platform
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(xtensa)
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <xtensa/config/core-isa.h>
|
||||
#include <memory.h>
|
||||
#include <zephyr/linker/sections.h>
|
||||
|
||||
#include <zephyr/linker/linker-defs.h>
|
||||
#include <zephyr/linker/linker-tool.h>
|
||||
|
||||
PROVIDE(__memctl_default = 0x00000000);
|
||||
PROVIDE(_MemErrorHandler = 0x00000000);
|
||||
|
||||
#define RAMABLE_REGION sdram0 :sdram0_phdr
|
||||
#define ROMABLE_REGION sdram0 :sdram0_phdr
|
||||
|
||||
MEMORY
|
||||
{
|
||||
vector_reset_text :
|
||||
org = XCHAL_RESET_VECTOR0_PADDR_IRAM,
|
||||
len = MEM_RESET_TEXT_SIZE
|
||||
vector_reset_lit :
|
||||
org = XCHAL_RESET_VECTOR0_PADDR_IRAM + MEM_RESET_TEXT_SIZE,
|
||||
len = MEM_RESET_LIT_SIZE
|
||||
vector_base_text :
|
||||
org = XCHAL_VECBASE_RESET_PADDR_IRAM,
|
||||
len = MEM_VECBASE_LIT_SIZE
|
||||
vector_int2_lit :
|
||||
org = XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_int2_text :
|
||||
org = XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_int3_lit :
|
||||
org = XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_int3_text :
|
||||
org = XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_int4_lit :
|
||||
org = XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_int4_text :
|
||||
org = XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_int5_lit :
|
||||
org = XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_int5_text :
|
||||
org = XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_kernel_lit :
|
||||
org = XCHAL_KERNEL_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_kernel_text :
|
||||
org = XCHAL_KERNEL_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_user_lit :
|
||||
org = XCHAL_USER_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_user_text :
|
||||
org = XCHAL_USER_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_double_lit :
|
||||
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_double_text :
|
||||
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
iram_text_start :
|
||||
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE,
|
||||
len = (IRAM_BASE + IRAM_SIZE) - (XCHAL_DOUBLEEXC_VECTOR_PADDR + MEM_VECT_TEXT_SIZE)
|
||||
sdram0 :
|
||||
org = SDRAM0_BASE,
|
||||
len = SDRAM0_SIZE
|
||||
sdram1 :
|
||||
org = SDRAM1_BASE + SOF_MAILBOX_SIZE,
|
||||
len = SDRAM1_SIZE - SOF_MAILBOX_SIZE
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
IDT_LIST :
|
||||
org = IDT_BASE,
|
||||
len = IDT_SIZE
|
||||
#endif
|
||||
|
||||
static_uuid_entries_seg (!ari) :
|
||||
org = UUID_ENTRY_ELF_BASE,
|
||||
len = UUID_ENTRY_ELF_SIZE
|
||||
static_log_entries_seg (!ari) :
|
||||
org = LOG_ENTRY_ELF_BASE,
|
||||
len = LOG_ENTRY_ELF_SIZE
|
||||
fw_metadata_seg (!ari) :
|
||||
org = EXT_MANIFEST_ELF_BASE,
|
||||
len = EXT_MANIFEST_ELF_SIZE
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
vector_reset_text_phdr PT_LOAD;
|
||||
vector_reset_lit_phdr PT_LOAD;
|
||||
vector_base_text_phdr PT_LOAD;
|
||||
vector_base_lit_phdr PT_LOAD;
|
||||
vector_int2_text_phdr PT_LOAD;
|
||||
vector_int2_lit_phdr PT_LOAD;
|
||||
vector_int3_text_phdr PT_LOAD;
|
||||
vector_int3_lit_phdr PT_LOAD;
|
||||
vector_int4_text_phdr PT_LOAD;
|
||||
vector_int4_lit_phdr PT_LOAD;
|
||||
vector_int5_text_phdr PT_LOAD;
|
||||
vector_int5_lit_phdr PT_LOAD;
|
||||
vector_kernel_text_phdr PT_LOAD;
|
||||
vector_kernel_lit_phdr PT_LOAD;
|
||||
vector_user_text_phdr PT_LOAD;
|
||||
vector_user_lit_phdr PT_LOAD;
|
||||
vector_double_text_phdr PT_LOAD;
|
||||
vector_double_lit_phdr PT_LOAD;
|
||||
iram_text_start_phdr PT_LOAD;
|
||||
sdram0_phdr PT_LOAD;
|
||||
sdram1_phdr PT_LOAD;
|
||||
static_uuid_entries_phdr PT_NOTE;
|
||||
static_log_entries_phdr PT_NOTE;
|
||||
metadata_entries_phdr PT_NOTE;
|
||||
}
|
||||
|
||||
_rom_store_table = 0;
|
||||
|
||||
PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR);
|
||||
|
||||
ENTRY(CONFIG_KERNEL_ENTRY)
|
||||
|
||||
/* Various memory-map dependent cache attribute settings: */
|
||||
_memmap_cacheattr_wb_base = 0x44024000;
|
||||
_memmap_cacheattr_wt_base = 0x11021000;
|
||||
_memmap_cacheattr_bp_base = 0x22022000;
|
||||
_memmap_cacheattr_unused_mask = 0x00F00FFF;
|
||||
_memmap_cacheattr_wb_trapnull = 0x4422422F;
|
||||
_memmap_cacheattr_wba_trapnull = 0x4422422F;
|
||||
_memmap_cacheattr_wbna_trapnull = 0x25222222;
|
||||
_memmap_cacheattr_wt_trapnull = 0x1122122F;
|
||||
_memmap_cacheattr_bp_trapnull = 0x2222222F;
|
||||
_memmap_cacheattr_wb_strict = 0x44F24FFF;
|
||||
_memmap_cacheattr_wt_strict = 0x11F21FFF;
|
||||
_memmap_cacheattr_bp_strict = 0x22F22FFF;
|
||||
_memmap_cacheattr_wb_allvalid = 0x44224222;
|
||||
_memmap_cacheattr_wt_allvalid = 0x11221222;
|
||||
_memmap_cacheattr_bp_allvalid = 0x22222222;
|
||||
/*
|
||||
* Every 512M in 4GB space has dedicate cache attribute.
|
||||
* 1: write through
|
||||
* 2: cache bypass
|
||||
* 4: write back
|
||||
* F: invalid access
|
||||
*/
|
||||
_memmap_cacheattr_imx8_wt_allvalid = 0x22212222;
|
||||
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_imx8_wt_allvalid);
|
||||
|
||||
_EXT_MAN_ALIGN_ = 16;
|
||||
EXTERN(ext_man_fw_ver)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
#include <zephyr/linker/rel-sections.ld>
|
||||
.ResetVector.text : ALIGN(4)
|
||||
{
|
||||
_ResetVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.ResetVector.text))
|
||||
_ResetVector_text_end = ABSOLUTE(.);
|
||||
} >vector_reset_text :vector_reset_text_phdr
|
||||
|
||||
.ResetVector.literal : ALIGN(4)
|
||||
{
|
||||
_ResetVector_literal_start = ABSOLUTE(.);
|
||||
*(.ResetVector.literal)
|
||||
_ResetVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_reset_lit :vector_reset_lit_phdr
|
||||
|
||||
.WindowVectors.text : ALIGN(4)
|
||||
{
|
||||
_WindowVectors_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.WindowVectors.text))
|
||||
_WindowVectors_text_end = ABSOLUTE(.);
|
||||
} >vector_base_text :vector_base_text_phdr
|
||||
|
||||
.Level2InterruptVector.literal : ALIGN(4)
|
||||
{
|
||||
_Level2InterruptVector_literal_start = ABSOLUTE(.);
|
||||
*(.Level2InterruptVector.literal)
|
||||
_Level2InterruptVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_int2_lit :vector_int2_lit_phdr
|
||||
|
||||
.Level2InterruptVector.text : ALIGN(4)
|
||||
{
|
||||
_Level2InterruptVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.Level2InterruptVector.text))
|
||||
_Level2InterruptVector_text_end = ABSOLUTE(.);
|
||||
} >vector_int2_text :vector_int2_text_phdr
|
||||
|
||||
.Level3InterruptVector.literal : ALIGN(4)
|
||||
{
|
||||
_Level3InterruptVector_literal_start = ABSOLUTE(.);
|
||||
*(.Level3InterruptVector.literal)
|
||||
_Level3InterruptVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_int3_lit :vector_int3_lit_phdr
|
||||
|
||||
.Level3InterruptVector.text : ALIGN(4)
|
||||
{
|
||||
_Level3InterruptVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.Level3InterruptVector.text))
|
||||
_Level3InterruptVector_text_end = ABSOLUTE(.);
|
||||
} >vector_int3_text :vector_int3_text_phdr
|
||||
|
||||
.DebugExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_DebugExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.DebugExceptionVector.literal)
|
||||
_DebugExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_int4_lit :vector_int4_lit_phdr
|
||||
|
||||
.DebugExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_DebugExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.DebugExceptionVector.text))
|
||||
_DebugExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_int4_text :vector_int4_text_phdr
|
||||
|
||||
.NMIExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_NMIExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.NMIExceptionVector.literal)
|
||||
_NMIExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_int5_lit :vector_int5_lit_phdr
|
||||
|
||||
.NMIExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_NMIExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.NMIExceptionVector.text))
|
||||
_NMIExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_int5_text :vector_int5_text_phdr
|
||||
|
||||
.KernelExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_KernelExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.KernelExceptionVector.literal)
|
||||
_KernelExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_kernel_lit :vector_kernel_lit_phdr
|
||||
|
||||
.KernelExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_KernelExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.KernelExceptionVector.text))
|
||||
_KernelExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_kernel_text :vector_kernel_text_phdr
|
||||
|
||||
.UserExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_UserExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.UserExceptionVector.literal)
|
||||
_UserExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_user_lit :vector_user_lit_phdr
|
||||
|
||||
.UserExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_UserExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.UserExceptionVector.text))
|
||||
_UserExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_user_text :vector_user_text_phdr
|
||||
|
||||
.DoubleExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_DoubleExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.DoubleExceptionVector.literal)
|
||||
_DoubleExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_double_lit :vector_double_lit_phdr
|
||||
|
||||
.DoubleExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_DoubleExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.DoubleExceptionVector.text))
|
||||
_DoubleExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_double_text :vector_double_text_phdr
|
||||
|
||||
.iram.text : ALIGN(4)
|
||||
{
|
||||
_stext = .;
|
||||
_iram_text_start = ABSOLUTE(.);
|
||||
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
|
||||
_iram_text_end = ABSOLUTE(.);
|
||||
} >iram_text_start :iram_text_start_phdr
|
||||
|
||||
.rodata : ALIGN(4)
|
||||
{
|
||||
__rodata_region_start = ABSOLUTE(.);
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
|
||||
KEEP (*(.xt_except_table))
|
||||
KEEP (*(.gcc_except_table .gcc_except_table.*))
|
||||
*(.gnu.linkonce.e.*)
|
||||
*(.gnu.version_r)
|
||||
KEEP (*(.eh_frame))
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc)
|
||||
*(.gnu.linkonce.h.*)
|
||||
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc_end)
|
||||
*(.dynamic)
|
||||
*(.gnu.version_d)
|
||||
. = ALIGN(4);
|
||||
_bss_table_start = ABSOLUTE(.);
|
||||
LONG(_bss_start)
|
||||
LONG(_bss_end)
|
||||
_bss_table_end = ABSOLUTE(.);
|
||||
__rodata_region_end = ABSOLUTE(.);
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
.module_init : ALIGN(4)
|
||||
{
|
||||
_module_init_start = ABSOLUTE(.);
|
||||
*(*.initcall)
|
||||
_module_init_end = ABSOLUTE(.);
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
.text : ALIGN(4)
|
||||
{
|
||||
_stext = .;
|
||||
__text_region_start = ABSOLUTE(.);
|
||||
KEEP (*(.ResetVector.text))
|
||||
*(.ResetVector.literal)
|
||||
*(.entry.text)
|
||||
*(.init.literal)
|
||||
KEEP(*(.init))
|
||||
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||||
*(.fini.literal)
|
||||
KEEP(*(.fini))
|
||||
*(.gnu.version)
|
||||
__text_region_end = ABSOLUTE(.);
|
||||
_etext = .;
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
#include <zephyr/linker/common-rom.ld>
|
||||
|
||||
.fw_ready : ALIGN(4)
|
||||
{
|
||||
KEEP(*(".fw_ready"));
|
||||
KEEP (*(.fw_ready_metadata))
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
.noinit : ALIGN(4)
|
||||
{
|
||||
*(.noinit)
|
||||
*(.noinit.*)
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
.data : ALIGN(4)
|
||||
{
|
||||
__data_start = ABSOLUTE(.);
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
KEEP(*(.gnu.linkonce.d.*personality*))
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
KEEP(*(.jcr))
|
||||
_trace_ctx_start = ABSOLUTE(.);
|
||||
*(.trace_ctx)
|
||||
_trace_ctx_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
*(.gna_model)
|
||||
__data_end = ABSOLUTE(.);
|
||||
. = ALIGN(4096);
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
.lit4 : ALIGN(4)
|
||||
{
|
||||
_lit4_start = ABSOLUTE(.);
|
||||
*(*.lit4)
|
||||
*(.lit4.*)
|
||||
*(.gnu.linkonce.lit4.*)
|
||||
_lit4_end = ABSOLUTE(.);
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
#include <zephyr/linker/common-ram.ld>
|
||||
|
||||
.bss (NOLOAD) : ALIGN(8)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_bss_start = ABSOLUTE(.);
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN (8);
|
||||
_bss_end = ABSOLUTE(.);
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
.heap_mem (NOLOAD) : ALIGN(8)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_heap_mem_start = ABSOLUTE(.);
|
||||
*(*.heap_mem)
|
||||
_heap_mem_end = ABSOLUTE(.);
|
||||
} >sdram1 :sdram1_phdr
|
||||
|
||||
/* stack */
|
||||
_end = ALIGN (8);
|
||||
PROVIDE(end = ALIGN (8));
|
||||
|
||||
__stack = SDRAM1_BASE + SDRAM1_SIZE;
|
||||
.comment 0 : { *(.comment) }
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
.debug_ranges 0 : { *(.debug_ranges) }
|
||||
.xtensa.info 0 : { *(.xtensa.info) }
|
||||
.xt.insn 0 :
|
||||
{
|
||||
KEEP (*(.xt.insn))
|
||||
KEEP (*(.gnu.linkonce.x.*))
|
||||
}
|
||||
.xt.prop 0 :
|
||||
{
|
||||
KEEP (*(.xt.prop))
|
||||
KEEP (*(.xt.prop.*))
|
||||
KEEP (*(.gnu.linkonce.prop.*))
|
||||
}
|
||||
.xt.lit 0 :
|
||||
{
|
||||
KEEP (*(.xt.lit))
|
||||
KEEP (*(.xt.lit.*))
|
||||
KEEP (*(.gnu.linkonce.p.*))
|
||||
}
|
||||
.xt.profile_range 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_range))
|
||||
KEEP (*(.gnu.linkonce.profile_range.*))
|
||||
}
|
||||
.xt.profile_ranges 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_ranges))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
|
||||
}
|
||||
.xt.profile_files 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_files))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_files.*))
|
||||
}
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
#include <zephyr/linker/intlist.ld>
|
||||
#endif
|
||||
|
||||
.static_uuid_entries (COPY) : ALIGN(1024)
|
||||
{
|
||||
*(*.static_uuids)
|
||||
} > static_uuid_entries_seg :static_uuid_entries_phdr
|
||||
|
||||
.static_log_entries (COPY) : ALIGN(1024)
|
||||
{
|
||||
*(*.static_log*)
|
||||
} > static_log_entries_seg :static_log_entries_phdr
|
||||
|
||||
.fw_metadata (COPY) : ALIGN(1024)
|
||||
{
|
||||
KEEP (*(.fw_metadata))
|
||||
. = ALIGN(_EXT_MAN_ALIGN_);
|
||||
} >fw_metadata_seg :metadata_entries_phdr
|
||||
}
|
||||
162
soc/nxp/imx/imx8/adsp/memory.h
Normal file
162
soc/nxp/imx/imx8/adsp/memory.h
Normal file
|
|
@ -0,0 +1,162 @@
|
|||
/*
|
||||
* Copyright (c) 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_NXP_ADSP_MEMORY_H_
|
||||
#define ZEPHYR_SOC_NXP_ADSP_MEMORY_H_
|
||||
|
||||
#define IRAM_RESERVE_HEADER_SPACE 0x400
|
||||
|
||||
#define IRAM_BASE 0x596f8000
|
||||
#define IRAM_SIZE 0x800
|
||||
|
||||
#define SDRAM0_BASE 0x92400000
|
||||
#define SDRAM0_SIZE 0x800000
|
||||
|
||||
#define SDRAM1_BASE 0x92C00000
|
||||
#define SDRAM1_SIZE 0x800000
|
||||
|
||||
/* The reset vector address in SRAM and its size */
|
||||
#define MEM_RESET_TEXT_SIZE 0x2e0
|
||||
#define MEM_RESET_LIT_SIZE 0x120
|
||||
|
||||
/* This is the base address of all the vectors defined in IRAM */
|
||||
#define XCHAL_VECBASE_RESET_PADDR_IRAM \
|
||||
(IRAM_BASE + IRAM_RESERVE_HEADER_SPACE)
|
||||
|
||||
#define MEM_VECBASE_LIT_SIZE 0x178
|
||||
|
||||
/*
|
||||
* EXCEPTIONS and VECTORS
|
||||
*/
|
||||
#define XCHAL_RESET_VECTOR0_PADDR_IRAM 0x596F8000
|
||||
|
||||
/* Vector and literal sizes */
|
||||
#define MEM_VECT_LIT_SIZE 0x4
|
||||
#define MEM_VECT_TEXT_SIZE 0x1C
|
||||
#define MEM_VECT_SIZE (MEM_VECT_TEXT_SIZE +\
|
||||
MEM_VECT_LIT_SIZE)
|
||||
|
||||
/* The addresses of the vectors.
|
||||
* Only the mem_error vector continues to point to its ROM address.
|
||||
*/
|
||||
#define XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x17C)
|
||||
|
||||
#define XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x19C)
|
||||
|
||||
#define XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1BC)
|
||||
|
||||
#define XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1DC)
|
||||
|
||||
#define XCHAL_KERNEL_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1FC)
|
||||
|
||||
#define XCHAL_USER_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x21C)
|
||||
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x23C)
|
||||
|
||||
/* Location for the intList section which is later used to construct the
|
||||
* Interrupt Descriptor Table (IDT). This is a bogus address as this
|
||||
* section will be stripped off in the final image.
|
||||
*/
|
||||
#define IDT_BASE (IRAM_BASE + IRAM_SIZE)
|
||||
|
||||
/* size of the Interrupt Descriptor Table (IDT) */
|
||||
#define IDT_SIZE 0x2000
|
||||
|
||||
/* physical DSP addresses */
|
||||
#define IRAM_BASE 0x596f8000
|
||||
#define IRAM_SIZE 0x800
|
||||
|
||||
#define DRAM0_BASE 0x596e8000
|
||||
#define DRAM0_SIZE 0x8000
|
||||
|
||||
#define DRAM1_BASE 0x596f0000
|
||||
#define DRAM1_SIZE 0x8000
|
||||
|
||||
#define SDRAM0_BASE 0x92400000
|
||||
#define SDRAM0_SIZE 0x800000
|
||||
|
||||
#define SDRAM1_BASE 0x92C00000
|
||||
#define SDRAM1_SIZE 0x800000
|
||||
|
||||
#define XSHAL_MU13_SIDEB_BYPASS_PADDR 0x5D310000
|
||||
#define MU_BASE XSHAL_MU13_SIDEB_BYPASS_PADDR
|
||||
|
||||
#define EDMA0_BASE 0x59200000
|
||||
#define EDMA0_SIZE 0x10000
|
||||
|
||||
#define ESAI_BASE 0x59010000
|
||||
#define ESAI_SIZE 0x00010000
|
||||
|
||||
#define SAI_1_BASE 0x59050000
|
||||
#define SAI_1_SIZE 0x00010000
|
||||
|
||||
#define UUID_ENTRY_ELF_BASE 0x1FFFA000
|
||||
#define UUID_ENTRY_ELF_SIZE 0x6000
|
||||
|
||||
#define LOG_ENTRY_ELF_BASE 0x20000000
|
||||
#define LOG_ENTRY_ELF_SIZE 0x2000000
|
||||
|
||||
#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
|
||||
#define EXT_MANIFEST_ELF_SIZE 0x2000000
|
||||
|
||||
/*
|
||||
* The Heap and Stack on i.MX8 are organized like this :-
|
||||
*
|
||||
* +--------------------------------------------------------------------------+
|
||||
* | Offset | Region | Size |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | SDRAM_BASE | RO Data | SOF_DATA_SIZE |
|
||||
* | | Data | |
|
||||
* | | BSS | |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | HEAP_SYSTEM_BASE | System Heap | HEAP_SYSTEM_SIZE |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | HEAP_RUNTIME_BASE | Runtime Heap | HEAP_RUNTIME_SIZE |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | HEAP_BUFFER_BASE | Module Buffers | HEAP_BUFFER_SIZE |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | SOF_STACK_END | Stack | SOF_STACK_SIZE |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | SOF_STACK_BASE | | |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
*/
|
||||
|
||||
#define SRAM_OUTBOX_BASE SDRAM1_BASE
|
||||
#define SRAM_OUTBOX_SIZE 0x1000
|
||||
#define SRAM_OUTBOX_OFFSET 0
|
||||
|
||||
#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE)
|
||||
#define SRAM_INBOX_SIZE 0x1000
|
||||
#define SRAM_INBOX_OFFSET SRAM_OUTBOX_SIZE
|
||||
|
||||
#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
|
||||
#define SRAM_DEBUG_SIZE 0x800
|
||||
#define SRAM_DEBUG_OFFSET (SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE)
|
||||
|
||||
#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
|
||||
#define SRAM_EXCEPT_SIZE 0x800
|
||||
#define SRAM_EXCEPT_OFFSET (SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE)
|
||||
|
||||
#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
|
||||
#define SRAM_STREAM_SIZE 0x1000
|
||||
#define SRAM_STREAM_OFFSET (SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE)
|
||||
|
||||
#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
|
||||
#define SRAM_TRACE_SIZE 0x1000
|
||||
#define SRAM_TRACE_OFFSET (SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE)
|
||||
|
||||
#define SOF_MAILBOX_SIZE (SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE \
|
||||
+ SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE \
|
||||
+ SRAM_STREAM_SIZE + SRAM_TRACE_SIZE)
|
||||
|
||||
#endif /* ZEPHYR_SOC_NXP_ADSP_MEMORY_H_ */
|
||||
41
soc/nxp/imx/imx8/adsp/pinctrl_soc.h
Normal file
41
soc/nxp/imx/imx8/adsp/pinctrl_soc.h
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* Copyright 2023 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_XTENSA_NXP_ADSP_IMX8_PINCTRL_SOC_H_
|
||||
#define ZEPHYR_SOC_XTENSA_NXP_ADSP_IMX8_PINCTRL_SOC_H_
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/types.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct pinctrl_soc_pinmux {
|
||||
uint32_t pad;
|
||||
uint32_t mux;
|
||||
};
|
||||
|
||||
typedef struct pinctrl_soc_pinmux pinctrl_soc_pin_t;
|
||||
|
||||
#define IMX8_PINMUX(n) \
|
||||
{ \
|
||||
.pad = DT_PROP_BY_IDX(n, pinmux, 0), \
|
||||
.mux = DT_PROP_BY_IDX(n, pinmux, 1), \
|
||||
},
|
||||
|
||||
#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx)\
|
||||
IMX8_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
|
||||
|
||||
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||
{ DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
|
||||
DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_PINMUX) };
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ZEPHYR_SOC_XTENSA_NXP_ADSP_IMX8_PINCTRL_SOC_H_ */
|
||||
52
soc/nxp/imx/imx8m/CMakeLists.txt
Normal file
52
soc/nxp/imx/imx8m/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
# Copyright 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if(CONFIG_SOC_MIMX8MP_ADSP)
|
||||
zephyr_include_directories(adsp)
|
||||
add_subdirectory(adsp)
|
||||
|
||||
zephyr_sources(
|
||||
adsp/pinctrl_soc.h
|
||||
)
|
||||
|
||||
# west sign
|
||||
|
||||
# See detailed comments in soc/intel/intel_adsp/common/CMakeLists.txt
|
||||
add_custom_target(zephyr.ri ALL
|
||||
DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri
|
||||
)
|
||||
|
||||
add_custom_command(
|
||||
OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri
|
||||
COMMENT "west sign --if-tool-available --tool rimage ..."
|
||||
COMMAND west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS}
|
||||
DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}
|
||||
)
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/adsp/linker.ld CACHE INTERNAL "")
|
||||
endif()
|
||||
|
||||
if(CONFIG_SOC_MIMX8ML8_A53 OR CONFIG_SOC_MIMX8MM6_A53 OR CONFIG_SOC_MIMX8MN6_A53)
|
||||
zephyr_include_directories(.)
|
||||
zephyr_include_directories(a53)
|
||||
|
||||
zephyr_sources(
|
||||
a53/pinctrl_soc.h
|
||||
)
|
||||
|
||||
zephyr_sources_ifdef(CONFIG_ARM_MMU a53/mmu_regions.c)
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "")
|
||||
endif()
|
||||
|
||||
if(CONFIG_SOC_MIMX8MM6_M4)
|
||||
add_subdirectory(m4_mini)
|
||||
endif()
|
||||
|
||||
if(CONFIG_SOC_MIMX8MQ6_M4)
|
||||
add_subdirectory(m4_quad)
|
||||
endif()
|
||||
|
||||
if(CONFIG_SOC_MIMX8MP_M7)
|
||||
add_subdirectory(m7)
|
||||
endif()
|
||||
98
soc/nxp/imx/imx8m/Kconfig
Normal file
98
soc/nxp/imx/imx8m/Kconfig
Normal file
|
|
@ -0,0 +1,98 @@
|
|||
# Copyright 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_MIMX8MM6_A53
|
||||
select ARM64
|
||||
select CPU_CORTEX_A53
|
||||
select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS
|
||||
select HAS_MCUX if CLOCK_CONTROL
|
||||
select HAS_MCUX_CCM if CLOCK_CONTROL
|
||||
select HAS_MCUX_IOMUXC if PINCTRL
|
||||
|
||||
config SOC_MIMX8MM6_M4
|
||||
select ARM
|
||||
select CPU_CORTEX_M4
|
||||
select CPU_HAS_FPU
|
||||
select CPU_HAS_ARM_MPU
|
||||
select HAS_MCUX
|
||||
select HAS_MCUX_CCM
|
||||
select HAS_MCUX_RDC
|
||||
select HAS_MCUX_IGPIO
|
||||
select HAS_MCUX_IOMUXC
|
||||
|
||||
config SOC_MIMX8ML8_A53
|
||||
select ARM64
|
||||
select CPU_CORTEX_A53
|
||||
select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS
|
||||
select HAS_MCUX if CLOCK_CONTROL
|
||||
select HAS_MCUX_CCM if CLOCK_CONTROL
|
||||
select HAS_MCUX_IOMUXC if PINCTRL
|
||||
|
||||
config SOC_MIMX8MN6_A53
|
||||
select ARM64
|
||||
select CPU_CORTEX_A53
|
||||
select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS
|
||||
select HAS_MCUX if CLOCK_CONTROL
|
||||
select HAS_MCUX_CCM if CLOCK_CONTROL
|
||||
select HAS_MCUX_IOMUXC if PINCTRL
|
||||
|
||||
config SOC_MIMX8MP_ADSP
|
||||
select XTENSA
|
||||
select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
|
||||
select XTENSA_RESET_VECTOR
|
||||
select XTENSA_USE_CORE_CRT1
|
||||
select ATOMIC_OPERATIONS_BUILTIN
|
||||
select GEN_ISR_TABLES
|
||||
select XTENSA_SMALL_VECTOR_TABLE_ENTRY
|
||||
select HAS_MCUX if CLOCK_CONTROL
|
||||
select HAS_MCUX_CCM if CLOCK_CONTROL
|
||||
select HAS_MCUX_IOMUXC if PINCTRL
|
||||
select PINCTRL_IMX if HAS_MCUX_IOMUXC
|
||||
|
||||
config SOC_MIMX8MP_M7
|
||||
select ARM
|
||||
select CPU_CORTEX_M7
|
||||
select CPU_HAS_FPU
|
||||
select CPU_HAS_ICACHE
|
||||
select CPU_HAS_DCACHE
|
||||
select INIT_VIDEO_PLL
|
||||
select HAS_MCUX
|
||||
select HAS_MCUX_CCM
|
||||
select HAS_MCUX_RDC
|
||||
select CPU_HAS_ARM_MPU
|
||||
select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
|
||||
select ARM_MPU
|
||||
select HAS_MCUX_IGPIO
|
||||
select HAS_MCUX_IOMUXC
|
||||
|
||||
config SOC_MIMX8MQ6_M4
|
||||
select ARM
|
||||
select CPU_CORTEX_M4
|
||||
select CPU_HAS_FPU
|
||||
select CPU_HAS_ARM_MPU
|
||||
select HAS_MCUX
|
||||
select HAS_MCUX_CCM
|
||||
select HAS_MCUX_RDC
|
||||
select HAS_MCUX_IOMUXC
|
||||
|
||||
config MCUX_CORE_SUFFIX
|
||||
default "_ca53" if SOC_MIMX8MM6_A53 || SOC_MIMX8MN6_A53 || SOC_MIMX8ML8_A53
|
||||
default "_dsp" if SOC_MIMX8MP_ADSP
|
||||
|
||||
if SOC_MIMX8MP_M7
|
||||
|
||||
choice CODE_LOCATION
|
||||
prompt "Code location selection"
|
||||
|
||||
config CODE_ITCM
|
||||
bool "Link code into internal instruction tightly coupled memory (ITCM)"
|
||||
|
||||
config CODE_DDR
|
||||
bool "Link code into DDR memory"
|
||||
|
||||
endchoice
|
||||
|
||||
config INIT_VIDEO_PLL
|
||||
bool "Initialize Video PLL"
|
||||
|
||||
endif # SOC_MIMX8MP_M7
|
||||
8
soc/nxp/imx/imx8m/Kconfig.defconfig
Normal file
8
soc/nxp/imx/imx8m/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
# Copyright 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_IMX8M
|
||||
|
||||
rsource "Kconfig.defconfig.*"
|
||||
|
||||
endif # SOC_SERIES_IMX8M
|
||||
53
soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8.m7
Normal file
53
soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8.m7
Normal file
|
|
@ -0,0 +1,53 @@
|
|||
# MIMX8ML8 SoC defconfig
|
||||
|
||||
# Copyright (c) 2021, Laird Connectivity
|
||||
# Copyright 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_MIMX8MP_M7
|
||||
|
||||
config SOC
|
||||
string
|
||||
default "mimx8ml8"
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
int
|
||||
default 800000000
|
||||
|
||||
config GPIO
|
||||
default y
|
||||
|
||||
config IPM_IMX
|
||||
default y
|
||||
depends on IPM
|
||||
|
||||
if CODE_ITCM
|
||||
|
||||
config FLASH_SIZE
|
||||
default $(dt_node_reg_size_int,/soc/itcm@0,0,K)
|
||||
|
||||
config FLASH_BASE_ADDRESS
|
||||
default $(dt_node_reg_addr_hex,/soc/itcm@0)
|
||||
|
||||
endif # CODE_ITCM
|
||||
|
||||
if CODE_DDR
|
||||
|
||||
config FLASH_SIZE
|
||||
default $(dt_node_reg_size_int,/soc/code@80000000,0,K)
|
||||
|
||||
config FLASH_BASE_ADDRESS
|
||||
default $(dt_node_reg_addr_hex,/soc/code@80000000)
|
||||
|
||||
endif # CODE_DDR
|
||||
|
||||
config NUM_IRQS
|
||||
int
|
||||
# must be >= the highest interrupt number used
|
||||
default 159
|
||||
|
||||
config PINCTRL_IMX
|
||||
default y if HAS_MCUX_IOMUXC
|
||||
depends on PINCTRL
|
||||
|
||||
endif # SOC_MIMX8MP_M7
|
||||
48
soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8_adsp
Normal file
48
soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8_adsp
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
# Copyright 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_IMX8M
|
||||
|
||||
if SOC_MIMX8MP_ADSP
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default 800000000
|
||||
|
||||
config SYS_CLOCK_TICKS_PER_SEC
|
||||
default 50000
|
||||
|
||||
config DCACHE_LINE_SIZE
|
||||
default 128
|
||||
|
||||
config GEN_IRQ_VECTOR_TABLE
|
||||
default n
|
||||
|
||||
config CACHE_MANAGEMENT
|
||||
default y
|
||||
|
||||
config SMP
|
||||
default n
|
||||
|
||||
config XTENSA_TIMER
|
||||
default y
|
||||
|
||||
config KERNEL_ENTRY
|
||||
default "__start"
|
||||
|
||||
config MULTI_LEVEL_INTERRUPTS
|
||||
default n
|
||||
|
||||
config 2ND_LEVEL_INTERRUPTS
|
||||
default n
|
||||
|
||||
config DYNAMIC_INTERRUPTS
|
||||
default y
|
||||
|
||||
# To prevent test uses TEST_LOGGING_MINIMAL
|
||||
config TEST_LOGGING_DEFAULTS
|
||||
default n
|
||||
depends on TEST
|
||||
|
||||
endif # SOC_MIMX8MP_ADSP
|
||||
|
||||
endif # SOC_SERIES_IMX8M
|
||||
27
soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm.a53
Normal file
27
soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm.a53
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
# Copyright 2020-2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_MIMX8MM6_A53
|
||||
|
||||
# Workaround for not being able to have commas in macro arguments
|
||||
DT_CHOSEN_Z_FLASH := zephyr,flash
|
||||
|
||||
config FLASH_SIZE
|
||||
default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
|
||||
|
||||
config FLASH_BASE_ADDRESS
|
||||
default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
|
||||
|
||||
config NUM_IRQS
|
||||
int
|
||||
default 240
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
int
|
||||
default 8000000
|
||||
|
||||
config PINCTRL_IMX
|
||||
default y if HAS_MCUX_IOMUXC
|
||||
depends on PINCTRL
|
||||
|
||||
endif
|
||||
26
soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm.m4
Normal file
26
soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm.m4
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
# MIMX8MM6 M4 SoC defconfig
|
||||
|
||||
# Copyright (c) 2020, Manivannan Sadhasivam <mani@kernel.org>
|
||||
# Copyright 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_MIMX8MM6_M4
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
int
|
||||
default 400000000
|
||||
|
||||
config IPM_IMX
|
||||
default y
|
||||
depends on IPM
|
||||
|
||||
config NUM_IRQS
|
||||
int
|
||||
# must be >= the highest interrupt number used
|
||||
default 127
|
||||
|
||||
config PINCTRL_IMX
|
||||
default y if HAS_MCUX_IOMUXC
|
||||
depends on PINCTRL
|
||||
|
||||
endif # SOC_MIMX8MM6_M4
|
||||
27
soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mn.a53
Normal file
27
soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mn.a53
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
# Copyright 2022-2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_MIMX8MN6_A53
|
||||
|
||||
# Workaround for not being able to have commas in macro arguments
|
||||
DT_CHOSEN_Z_FLASH := zephyr,flash
|
||||
|
||||
config FLASH_SIZE
|
||||
default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
|
||||
|
||||
config FLASH_BASE_ADDRESS
|
||||
default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
|
||||
|
||||
config NUM_IRQS
|
||||
int
|
||||
default 240
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
int
|
||||
default 8000000
|
||||
|
||||
config PINCTRL_IMX
|
||||
default y if HAS_MCUX_IOMUXC
|
||||
depends on PINCTRL
|
||||
|
||||
endif
|
||||
27
soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mp.a53
Normal file
27
soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mp.a53
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
# Copyright 2021-2023 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_MIMX8ML8_A53
|
||||
|
||||
# Workaround for not being able to have commas in macro arguments
|
||||
DT_CHOSEN_Z_FLASH := zephyr,flash
|
||||
|
||||
config FLASH_SIZE
|
||||
default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
|
||||
|
||||
config FLASH_BASE_ADDRESS
|
||||
default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
|
||||
|
||||
config NUM_IRQS
|
||||
int
|
||||
default 240
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
int
|
||||
default 8000000
|
||||
|
||||
config PINCTRL_IMX
|
||||
default y if HAS_MCUX_IOMUXC
|
||||
depends on PINCTRL
|
||||
|
||||
endif
|
||||
22
soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mq.m4
Normal file
22
soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mq.m4
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
# MIMX8MQ6 M4 SoC defconfig
|
||||
|
||||
# Copyright (c) 2021, Kwon Tae-young <tykwon@m2i.co.kr>
|
||||
# Copyright 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_MIMX8MQ6_M4
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
int
|
||||
default 266000000
|
||||
|
||||
config PINCTRL_IMX
|
||||
default y if HAS_MCUX_IOMUXC
|
||||
depends on PINCTRL
|
||||
|
||||
config NUM_IRQS
|
||||
int
|
||||
# must be >= the highest interrupt number used
|
||||
default 127
|
||||
|
||||
endif # SOC_MIMX8MQ6_M4
|
||||
115
soc/nxp/imx/imx8m/Kconfig.soc
Normal file
115
soc/nxp/imx/imx8m/Kconfig.soc
Normal file
|
|
@ -0,0 +1,115 @@
|
|||
# Copyright 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_IMX8M
|
||||
bool
|
||||
select SOC_FAMILY_NXP_IMX
|
||||
|
||||
config SOC_SERIES
|
||||
default "imx8m" if SOC_SERIES_IMX8M
|
||||
|
||||
config SOC_MIMX8MP
|
||||
bool
|
||||
select SOC_SERIES_IMX8M
|
||||
|
||||
config SOC_MIMX8MM6
|
||||
bool
|
||||
select SOC_SERIES_IMX8M
|
||||
|
||||
config SOC_MIMX8MM6_A53
|
||||
bool
|
||||
select SOC_MIMX8MM6
|
||||
help
|
||||
NXP i.MX8MM A53
|
||||
|
||||
config SOC_MIMX8MM6_M4
|
||||
bool
|
||||
select SOC_MIMX8MM6
|
||||
help
|
||||
NXP i.MX8MM M4
|
||||
|
||||
config SOC_MIMX8MP
|
||||
bool
|
||||
select SOC_SERIES_IMX8M
|
||||
|
||||
config SOC_MIMX8ML8_A53
|
||||
bool
|
||||
select SOC_MIMX8MP
|
||||
help
|
||||
NXP i.MX8MP A53
|
||||
|
||||
config SOC_MIMX8MP_ADSP
|
||||
bool
|
||||
select SOC_MIMX8MP
|
||||
help
|
||||
Enable support for NXP i.MX 8MPLUS Audio DSP
|
||||
|
||||
config SOC_MIMX8MP_M7
|
||||
bool
|
||||
select SOC_MIMX8MP
|
||||
help
|
||||
Enable support for NXP i.MX 8MPLUS M7 MCU
|
||||
|
||||
config SOC_MIMX8MQ6
|
||||
bool
|
||||
select SOC_SERIES_IMX8M
|
||||
|
||||
config SOC_MIMX8MQ6_M4
|
||||
bool
|
||||
select SOC_MIMX8MQ6
|
||||
help
|
||||
Enable support for NXP i.MX 8M Quad M4 MCU
|
||||
|
||||
config SOC_TOOLCHAIN_NAME
|
||||
string
|
||||
default "nxp_imx8m_adsp" if SOC_MIMX8MP_ADSP
|
||||
|
||||
config SOC_MIMX8MN6
|
||||
bool
|
||||
select SOC_SERIES_IMX8M
|
||||
|
||||
config SOC_MIMX8MN6_A53
|
||||
bool
|
||||
select SOC_MIMX8MN6
|
||||
help
|
||||
NXP i.MX8MN A53
|
||||
|
||||
config SOC
|
||||
default "mimx8mm6" if SOC_MIMX8MM6
|
||||
default "mimx8mn6" if SOC_MIMX8MN6
|
||||
default "mimx8ml8" if SOC_MIMX8MP
|
||||
default "mimx8mq6" if SOC_MIMX8MQ6
|
||||
|
||||
config SOC_PART_NUMBER_MIMX8ML8DVNLZ
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MIMX8MM6DVTLZ
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MIMX8MM6CVTKZ
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MIMX8MN6DVTJZ
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MIMX8MN6DUCJZ
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MIMX8MN6CVTIZ
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MIMX8MN6CUCIZ
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MIMX8MQ6DVAJZ
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER
|
||||
default "MIMX8ML8DVNLZ" if SOC_PART_NUMBER_MIMX8ML8DVNLZ
|
||||
default "MIMX8MM6DVTLZ" if SOC_PART_NUMBER_MIMX8MM6DVTLZ
|
||||
default "MIMX8MM6CVTKZ" if SOC_PART_NUMBER_MIMX8MM6CVTKZ
|
||||
default "MIMX8MN6DVTJZ" if SOC_PART_NUMBER_MIMX8MN6DVTJZ
|
||||
default "MIMX8MN6DUCJZ" if SOC_PART_NUMBER_MIMX8MN6DUCJZ
|
||||
default "MIMX8MN6CVTIZ" if SOC_PART_NUMBER_MIMX8MN6CVTIZ
|
||||
default "MIMX8MN6CUCIZ" if SOC_PART_NUMBER_MIMX8MN6CUCIZ
|
||||
default "MIMX8MQ6DVAJZ" if SOC_PART_NUMBER_MIMX8MQ6DVAJZ
|
||||
45
soc/nxp/imx/imx8m/a53/mmu_regions.c
Normal file
45
soc/nxp/imx/imx8m/a53/mmu_regions.c
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* Copyright 2020-2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/arch/arm64/arm_mmu.h>
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/sys/util.h>
|
||||
|
||||
static const struct arm_mmu_region mmu_regions[] = {
|
||||
|
||||
MMU_REGION_FLAT_ENTRY("GIC",
|
||||
DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
|
||||
DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0),
|
||||
MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
|
||||
|
||||
MMU_REGION_FLAT_ENTRY("GIC",
|
||||
DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1),
|
||||
DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1),
|
||||
MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
|
||||
|
||||
MMU_REGION_FLAT_ENTRY("CCM",
|
||||
DT_REG_ADDR(DT_NODELABEL(ccm)),
|
||||
DT_REG_SIZE(DT_NODELABEL(ccm)),
|
||||
MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
|
||||
|
||||
MMU_REGION_FLAT_ENTRY("ANA_PLL",
|
||||
DT_REG_ADDR(DT_NODELABEL(ana_pll)),
|
||||
DT_REG_SIZE(DT_NODELABEL(ana_pll)),
|
||||
MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
|
||||
|
||||
MMU_REGION_FLAT_ENTRY("IOMUXC",
|
||||
DT_REG_ADDR(DT_NODELABEL(iomuxc)),
|
||||
DT_REG_SIZE(DT_NODELABEL(iomuxc)),
|
||||
MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
|
||||
|
||||
MMU_REGION_DT_COMPAT_FOREACH_FLAT_ENTRY(nxp_imx_iuart,
|
||||
(MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS))
|
||||
};
|
||||
|
||||
const struct arm_mmu_config mmu_config = {
|
||||
.num_regions = ARRAY_SIZE(mmu_regions),
|
||||
.mmu_regions = mmu_regions,
|
||||
};
|
||||
83
soc/nxp/imx/imx8m/a53/pinctrl_soc.h
Normal file
83
soc/nxp/imx/imx8m/a53/pinctrl_soc.h
Normal file
|
|
@ -0,0 +1,83 @@
|
|||
/*
|
||||
* Copyright (c) 2022, NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_ARM64_NXP_IMX8M_PINCTRL_SOC_H_
|
||||
#define ZEPHYR_SOC_ARM64_NXP_IMX8M_PINCTRL_SOC_H_
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/types.h>
|
||||
#include "fsl_common.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT
|
||||
#define MCUX_IMX_BIAS_PULL_UP_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT
|
||||
#define MCUX_IMX_BIAS_PULL_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_PE_SHIFT
|
||||
#define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT
|
||||
#define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT
|
||||
#define MCUX_IMX_DRIVE_STRENGTH_SHIFT IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT
|
||||
#define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
|
||||
#define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1)
|
||||
|
||||
#define Z_PINCTRL_MCUX_IMX_PINCFG_INIT(node_id) \
|
||||
((DT_PROP(node_id, input_schmitt_enable) << MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT) | \
|
||||
(DT_PROP(node_id, bias_pull_up) << MCUX_IMX_BIAS_PULL_UP_SHIFT) | \
|
||||
((DT_PROP(node_id, bias_pull_up) | DT_PROP(node_id, bias_pull_down)) \
|
||||
<< MCUX_IMX_BIAS_PULL_ENABLE_SHIFT) | \
|
||||
(DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) | \
|
||||
(DT_ENUM_IDX(node_id, drive_strength) << MCUX_IMX_DRIVE_STRENGTH_SHIFT) | \
|
||||
(DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \
|
||||
(DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT))
|
||||
|
||||
|
||||
/* This struct must be present. It is used by the mcux gpio driver */
|
||||
struct pinctrl_soc_pinmux {
|
||||
uint32_t mux_register; /*!< IOMUXC SW_PAD_MUX register */
|
||||
uint32_t config_register; /*!< IOMUXC SW_PAD_CTL register */
|
||||
uint32_t input_register; /*!< IOMUXC SELECT_INPUT DAISY register */
|
||||
uint8_t mux_mode: 4; /*!< Mux value for SW_PAD_MUX register */
|
||||
uint32_t input_daisy:4; /*!< Mux value for SELECT_INPUT_DAISY register */
|
||||
};
|
||||
|
||||
struct pinctrl_soc_pin {
|
||||
struct pinctrl_soc_pinmux pinmux;
|
||||
uint32_t pin_ctrl_flags; /*!< value to write to IOMUXC_SW_PAD_CTL register */
|
||||
};
|
||||
|
||||
typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
|
||||
|
||||
/* This definition must be present. It is used by the mcux gpio driver */
|
||||
#define MCUX_IMX_PINMUX(node_id) \
|
||||
{ \
|
||||
.mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \
|
||||
.config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \
|
||||
.input_register = DT_PROP_BY_IDX(node_id, pinmux, 2), \
|
||||
.mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1), \
|
||||
.input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3), \
|
||||
}
|
||||
|
||||
#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \
|
||||
MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
|
||||
|
||||
#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \
|
||||
{ \
|
||||
.pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
|
||||
.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PINCFG_INIT(group_id), \
|
||||
},
|
||||
|
||||
|
||||
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
|
||||
DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)}; \
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ZEPHYR_SOC_ARM64_NXP_IMX8M_PINCTRL_SOC_H_ */
|
||||
6
soc/nxp/imx/imx8m/adsp/CMakeLists.txt
Normal file
6
soc/nxp/imx/imx8m/adsp/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
# NXP SoC family CMake file
|
||||
#
|
||||
# Copyright (c) 2021, 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_include_directories(include)
|
||||
177
soc/nxp/imx/imx8m/adsp/_soc_inthandlers.h
Normal file
177
soc/nxp/imx/imx8m/adsp/_soc_inthandlers.h
Normal file
|
|
@ -0,0 +1,177 @@
|
|||
/*
|
||||
* Copyright (c) 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
/*
|
||||
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*
|
||||
* Functions here are designed to produce efficient code to
|
||||
* search an Xtensa bitmask of interrupts, inspecting only those bits
|
||||
* declared to be associated with a given interrupt level. Each
|
||||
* dispatcher will handle exactly one flagged interrupt, in numerical
|
||||
* order (low bits first) and will return a mask of that bit that can
|
||||
* then be cleared by the calling code. Unrecognized bits for the
|
||||
* level will invoke an error handler.
|
||||
*/
|
||||
|
||||
#include <xtensa/config/core-isa.h>
|
||||
#include <zephyr/sys/util.h>
|
||||
#include <zephyr/sw_isr_table.h>
|
||||
|
||||
#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 5
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
|
||||
static inline int _xtensa_handle_one_int1(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (mask & BIT(8)) {
|
||||
mask = BIT(8);
|
||||
irq = 8;
|
||||
goto handle_irq;
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int2(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
int i = 0;
|
||||
|
||||
mask &= XCHAL_INTLEVEL2_MASK;
|
||||
for (i = 0; i <= 31; i++)
|
||||
if (mask & BIT(i)) {
|
||||
mask = BIT(i);
|
||||
irq = i;
|
||||
goto handle_irq;
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int3(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (mask & BIT(1)) {
|
||||
mask = BIT(1);
|
||||
irq = 1;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(3)) {
|
||||
mask = BIT(3);
|
||||
irq = 3;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(31)) {
|
||||
mask = BIT(31);
|
||||
irq = 31;
|
||||
goto handle_irq;
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int5(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (mask & BIT(0)) {
|
||||
mask = BIT(0);
|
||||
irq = 0;
|
||||
goto handle_irq;
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int0(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int4(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int6(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int7(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
12
soc/nxp/imx/imx8m/adsp/include/adsp/cache.h
Normal file
12
soc/nxp/imx/imx8m/adsp/include/adsp/cache.h
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __COMMON_ADSP_CACHE_H__
|
||||
#define __COMMON_ADSP_CACHE_H__
|
||||
|
||||
#include <xtensa/hal.h>
|
||||
|
||||
#endif
|
||||
41
soc/nxp/imx/imx8m/adsp/include/adsp/io.h
Normal file
41
soc/nxp/imx/imx8m/adsp/include/adsp/io.h
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* Copyright (c) 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __INCLUDE_IO__
|
||||
#define __INCLUDE_IO__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <soc/memory.h>
|
||||
#include <zephyr/sys/sys_io.h>
|
||||
#include <zephyr/arch/common/sys_io.h>
|
||||
|
||||
static inline uint32_t io_reg_read(uint32_t reg)
|
||||
{
|
||||
return sys_read32(reg);
|
||||
}
|
||||
|
||||
static inline void io_reg_write(uint32_t reg, uint32_t val)
|
||||
{
|
||||
sys_write32(val, reg);
|
||||
}
|
||||
|
||||
static inline void io_reg_update_bits(uint32_t reg, uint32_t mask,
|
||||
uint32_t value)
|
||||
{
|
||||
io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask));
|
||||
}
|
||||
|
||||
static inline uint16_t io_reg_read16(uint32_t reg)
|
||||
{
|
||||
return sys_read16(reg);
|
||||
}
|
||||
|
||||
static inline void io_reg_write16(uint32_t reg, uint16_t val)
|
||||
{
|
||||
sys_write16(val, reg);
|
||||
}
|
||||
|
||||
#endif
|
||||
33
soc/nxp/imx/imx8m/adsp/include/soc.h
Normal file
33
soc/nxp/imx/imx8m/adsp/include/soc.h
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* Copyright (c) 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <zephyr/sys/sys_io.h>
|
||||
|
||||
#include <adsp/cache.h>
|
||||
|
||||
#ifndef __INC_IMX_SOC_H
|
||||
#define __INC_IMX_SOC_H
|
||||
|
||||
/* Macros related to interrupt handling */
|
||||
#define XTENSA_IRQ_NUM_SHIFT 0
|
||||
#define XTENSA_IRQ_NUM_MASK 0xff
|
||||
|
||||
/*
|
||||
* IRQs are mapped on levels. 2nd, 3rd and 4th level are left as 0x00.
|
||||
*
|
||||
* 1. Peripheral Register bit offset.
|
||||
*/
|
||||
#define XTENSA_IRQ_NUMBER(_irq) \
|
||||
((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK)
|
||||
|
||||
extern void z_soc_irq_enable(uint32_t irq);
|
||||
extern void z_soc_irq_disable(uint32_t irq);
|
||||
extern int z_soc_irq_is_enabled(unsigned int irq);
|
||||
|
||||
#endif /* __INC_IMX_SOC_H */
|
||||
532
soc/nxp/imx/imx8m/adsp/linker.ld
Normal file
532
soc/nxp/imx/imx8m/adsp/linker.ld
Normal file
|
|
@ -0,0 +1,532 @@
|
|||
/*
|
||||
* Copyright 2021, 2023 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Linker command/script file
|
||||
*
|
||||
* Linker script for the NXP i.MX8M platform
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(xtensa)
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <xtensa/config/core-isa.h>
|
||||
#include <memory.h>
|
||||
#include <zephyr/linker/sections.h>
|
||||
|
||||
#include <zephyr/linker/linker-defs.h>
|
||||
#include <zephyr/linker/linker-tool.h>
|
||||
|
||||
PROVIDE(__memctl_default = 0x00000000);
|
||||
PROVIDE(_MemErrorHandler = 0x00000000);
|
||||
|
||||
#define RAMABLE_REGION sdram0 :sdram0_phdr
|
||||
#define ROMABLE_REGION sdram0 :sdram0_phdr
|
||||
|
||||
MEMORY
|
||||
{
|
||||
vector_reset_text :
|
||||
org = XCHAL_RESET_VECTOR0_PADDR_IRAM,
|
||||
len = MEM_RESET_TEXT_SIZE
|
||||
vector_reset_lit :
|
||||
org = XCHAL_RESET_VECTOR0_PADDR_IRAM + MEM_RESET_TEXT_SIZE,
|
||||
len = MEM_RESET_LIT_SIZE
|
||||
vector_base_text :
|
||||
org = XCHAL_VECBASE_RESET_PADDR_IRAM,
|
||||
len = MEM_VECBASE_LIT_SIZE
|
||||
vector_int2_lit :
|
||||
org = XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_int2_text :
|
||||
org = XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_int3_lit :
|
||||
org = XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_int3_text :
|
||||
org = XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_int4_lit :
|
||||
org = XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_int4_text :
|
||||
org = XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_int5_lit :
|
||||
org = XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_int5_text :
|
||||
org = XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_kernel_lit :
|
||||
org = XCHAL_KERNEL_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_kernel_text :
|
||||
org = XCHAL_KERNEL_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_user_lit :
|
||||
org = XCHAL_USER_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_user_text :
|
||||
org = XCHAL_USER_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_double_lit :
|
||||
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_double_text :
|
||||
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
iram_text_start :
|
||||
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE,
|
||||
len = (IRAM_BASE + IRAM_SIZE) - (XCHAL_DOUBLEEXC_VECTOR_PADDR + MEM_VECT_TEXT_SIZE)
|
||||
sdram0 :
|
||||
org = SDRAM0_BASE,
|
||||
len = SDRAM0_SIZE
|
||||
sdram1 :
|
||||
org = SDRAM1_BASE + SOF_MAILBOX_SIZE,
|
||||
len = SDRAM1_SIZE - SOF_MAILBOX_SIZE
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
IDT_LIST :
|
||||
org = IDT_BASE,
|
||||
len = IDT_SIZE
|
||||
#endif
|
||||
|
||||
static_uuid_entries_seg (!ari) :
|
||||
org = UUID_ENTRY_ELF_BASE,
|
||||
len = UUID_ENTRY_ELF_SIZE
|
||||
static_log_entries_seg (!ari) :
|
||||
org = LOG_ENTRY_ELF_BASE,
|
||||
len = LOG_ENTRY_ELF_SIZE
|
||||
fw_metadata_seg (!ari) :
|
||||
org = EXT_MANIFEST_ELF_BASE,
|
||||
len = EXT_MANIFEST_ELF_SIZE
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
vector_reset_text_phdr PT_LOAD;
|
||||
vector_reset_lit_phdr PT_LOAD;
|
||||
vector_base_text_phdr PT_LOAD;
|
||||
vector_base_lit_phdr PT_LOAD;
|
||||
vector_int2_text_phdr PT_LOAD;
|
||||
vector_int2_lit_phdr PT_LOAD;
|
||||
vector_int3_text_phdr PT_LOAD;
|
||||
vector_int3_lit_phdr PT_LOAD;
|
||||
vector_int4_text_phdr PT_LOAD;
|
||||
vector_int4_lit_phdr PT_LOAD;
|
||||
vector_int5_text_phdr PT_LOAD;
|
||||
vector_int5_lit_phdr PT_LOAD;
|
||||
vector_kernel_text_phdr PT_LOAD;
|
||||
vector_kernel_lit_phdr PT_LOAD;
|
||||
vector_user_text_phdr PT_LOAD;
|
||||
vector_user_lit_phdr PT_LOAD;
|
||||
vector_double_text_phdr PT_LOAD;
|
||||
vector_double_lit_phdr PT_LOAD;
|
||||
iram_text_start_phdr PT_LOAD;
|
||||
sdram0_phdr PT_LOAD;
|
||||
sdram1_phdr PT_LOAD;
|
||||
static_uuid_entries_phdr PT_NOTE;
|
||||
static_log_entries_phdr PT_NOTE;
|
||||
metadata_entries_phdr PT_NOTE;
|
||||
}
|
||||
|
||||
_rom_store_table = 0;
|
||||
|
||||
PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR);
|
||||
|
||||
ENTRY(CONFIG_KERNEL_ENTRY)
|
||||
|
||||
/* Various memory-map dependent cache attribute settings: */
|
||||
_memmap_cacheattr_wb_base = 0x44024000;
|
||||
_memmap_cacheattr_wt_base = 0x11021000;
|
||||
_memmap_cacheattr_bp_base = 0x22022000;
|
||||
_memmap_cacheattr_unused_mask = 0x00F00FFF;
|
||||
_memmap_cacheattr_wb_trapnull = 0x4422422F;
|
||||
_memmap_cacheattr_wba_trapnull = 0x4422422F;
|
||||
_memmap_cacheattr_wbna_trapnull = 0x25222222;
|
||||
_memmap_cacheattr_wt_trapnull = 0x1122122F;
|
||||
_memmap_cacheattr_bp_trapnull = 0x2222222F;
|
||||
_memmap_cacheattr_wb_strict = 0x44F24FFF;
|
||||
_memmap_cacheattr_wt_strict = 0x11F21FFF;
|
||||
_memmap_cacheattr_bp_strict = 0x22F22FFF;
|
||||
_memmap_cacheattr_wb_allvalid = 0x44224222;
|
||||
_memmap_cacheattr_wt_allvalid = 0x11221222;
|
||||
_memmap_cacheattr_bp_allvalid = 0x22222222;
|
||||
/*
|
||||
* Every 512M in 4GB space has dedicate cache attribute.
|
||||
* 1: write through
|
||||
* 2: cache bypass
|
||||
* 4: write back
|
||||
* F: invalid access
|
||||
*/
|
||||
_memmap_cacheattr_imx8_wt_allvalid = 0x22212222;
|
||||
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_imx8_wt_allvalid);
|
||||
|
||||
_EXT_MAN_ALIGN_ = 16;
|
||||
EXTERN(ext_man_fw_ver)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
#ifdef CONFIG_OPENAMP_RSC_TABLE
|
||||
SECTION_PROLOGUE(.resource_table,, SUBALIGN(4))
|
||||
{
|
||||
KEEP(*(.resource_table*))
|
||||
} GROUP_LINK_IN(ROMABLE_REGION)
|
||||
#endif
|
||||
|
||||
#include <zephyr/linker/rel-sections.ld>
|
||||
.ResetVector.text : ALIGN(4)
|
||||
{
|
||||
_ResetVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.ResetVector.text))
|
||||
_ResetVector_text_end = ABSOLUTE(.);
|
||||
} >vector_reset_text :vector_reset_text_phdr
|
||||
|
||||
.ResetVector.literal : ALIGN(4)
|
||||
{
|
||||
_ResetVector_literal_start = ABSOLUTE(.);
|
||||
*(.ResetVector.literal)
|
||||
_ResetVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_reset_lit :vector_reset_lit_phdr
|
||||
|
||||
.WindowVectors.text : ALIGN(4)
|
||||
{
|
||||
_WindowVectors_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.WindowVectors.text))
|
||||
_WindowVectors_text_end = ABSOLUTE(.);
|
||||
} >vector_base_text :vector_base_text_phdr
|
||||
|
||||
.Level2InterruptVector.literal : ALIGN(4)
|
||||
{
|
||||
_Level2InterruptVector_literal_start = ABSOLUTE(.);
|
||||
*(.Level2InterruptVector.literal)
|
||||
_Level2InterruptVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_int2_lit :vector_int2_lit_phdr
|
||||
|
||||
.Level2InterruptVector.text : ALIGN(4)
|
||||
{
|
||||
_Level2InterruptVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.Level2InterruptVector.text))
|
||||
_Level2InterruptVector_text_end = ABSOLUTE(.);
|
||||
} >vector_int2_text :vector_int2_text_phdr
|
||||
|
||||
.Level3InterruptVector.literal : ALIGN(4)
|
||||
{
|
||||
_Level3InterruptVector_literal_start = ABSOLUTE(.);
|
||||
*(.Level3InterruptVector.literal)
|
||||
_Level3InterruptVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_int3_lit :vector_int3_lit_phdr
|
||||
|
||||
.Level3InterruptVector.text : ALIGN(4)
|
||||
{
|
||||
_Level3InterruptVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.Level3InterruptVector.text))
|
||||
_Level3InterruptVector_text_end = ABSOLUTE(.);
|
||||
} >vector_int3_text :vector_int3_text_phdr
|
||||
|
||||
.DebugExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_DebugExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.DebugExceptionVector.literal)
|
||||
_DebugExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_int4_lit :vector_int4_lit_phdr
|
||||
|
||||
.DebugExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_DebugExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.DebugExceptionVector.text))
|
||||
_DebugExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_int4_text :vector_int4_text_phdr
|
||||
|
||||
.NMIExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_NMIExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.NMIExceptionVector.literal)
|
||||
_NMIExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_int5_lit :vector_int5_lit_phdr
|
||||
|
||||
.NMIExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_NMIExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.NMIExceptionVector.text))
|
||||
_NMIExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_int5_text :vector_int5_text_phdr
|
||||
|
||||
.KernelExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_KernelExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.KernelExceptionVector.literal)
|
||||
_KernelExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_kernel_lit :vector_kernel_lit_phdr
|
||||
|
||||
.KernelExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_KernelExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.KernelExceptionVector.text))
|
||||
_KernelExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_kernel_text :vector_kernel_text_phdr
|
||||
|
||||
.UserExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_UserExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.UserExceptionVector.literal)
|
||||
_UserExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_user_lit :vector_user_lit_phdr
|
||||
|
||||
.UserExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_UserExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.UserExceptionVector.text))
|
||||
_UserExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_user_text :vector_user_text_phdr
|
||||
|
||||
.DoubleExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_DoubleExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.DoubleExceptionVector.literal)
|
||||
_DoubleExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_double_lit :vector_double_lit_phdr
|
||||
|
||||
.DoubleExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_DoubleExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.DoubleExceptionVector.text))
|
||||
_DoubleExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_double_text :vector_double_text_phdr
|
||||
|
||||
.iram.text : ALIGN(4)
|
||||
{
|
||||
_stext = .;
|
||||
_iram_text_start = ABSOLUTE(.);
|
||||
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
|
||||
_iram_text_end = ABSOLUTE(.);
|
||||
} >iram_text_start :iram_text_start_phdr
|
||||
|
||||
.rodata : ALIGN(4)
|
||||
{
|
||||
__rodata_region_start = ABSOLUTE(.);
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
|
||||
KEEP (*(.xt_except_table))
|
||||
KEEP (*(.gcc_except_table .gcc_except_table.*))
|
||||
*(.gnu.linkonce.e.*)
|
||||
*(.gnu.version_r)
|
||||
KEEP (*(.eh_frame))
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc)
|
||||
*(.gnu.linkonce.h.*)
|
||||
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc_end)
|
||||
*(.dynamic)
|
||||
*(.gnu.version_d)
|
||||
. = ALIGN(4);
|
||||
_bss_table_start = ABSOLUTE(.);
|
||||
LONG(_bss_start)
|
||||
LONG(_bss_end)
|
||||
_bss_table_end = ABSOLUTE(.);
|
||||
__rodata_region_end = ABSOLUTE(.);
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
.module_init : ALIGN(4)
|
||||
{
|
||||
_module_init_start = ABSOLUTE(.);
|
||||
*(*.initcall)
|
||||
_module_init_end = ABSOLUTE(.);
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
.text : ALIGN(4)
|
||||
{
|
||||
_stext = .;
|
||||
__text_region_start = ABSOLUTE(.);
|
||||
KEEP (*(.ResetVector.text))
|
||||
*(.ResetVector.literal)
|
||||
*(.entry.text)
|
||||
*(.init.literal)
|
||||
KEEP(*(.init))
|
||||
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||||
*(.fini.literal)
|
||||
KEEP(*(.fini))
|
||||
*(.gnu.version)
|
||||
__text_region_end = ABSOLUTE(.);
|
||||
_etext = .;
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
#include <zephyr/linker/common-rom.ld>
|
||||
|
||||
.fw_ready : ALIGN(4)
|
||||
{
|
||||
KEEP(*(".fw_ready"));
|
||||
KEEP (*(.fw_ready_metadata))
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
.noinit : ALIGN(4)
|
||||
{
|
||||
*(.noinit)
|
||||
*(.noinit.*)
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
.data : ALIGN(4)
|
||||
{
|
||||
__data_start = ABSOLUTE(.);
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
KEEP(*(.gnu.linkonce.d.*personality*))
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
KEEP(*(.jcr))
|
||||
_trace_ctx_start = ABSOLUTE(.);
|
||||
*(.trace_ctx)
|
||||
_trace_ctx_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
*(.gna_model)
|
||||
__data_end = ABSOLUTE(.);
|
||||
. = ALIGN(4096);
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
.lit4 : ALIGN(4)
|
||||
{
|
||||
_lit4_start = ABSOLUTE(.);
|
||||
*(*.lit4)
|
||||
*(.lit4.*)
|
||||
*(.gnu.linkonce.lit4.*)
|
||||
_lit4_end = ABSOLUTE(.);
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
#include <zephyr/linker/common-ram.ld>
|
||||
|
||||
/* Used for C++ build */
|
||||
.tm_clone_table : {
|
||||
*(.tm_clone_table)
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
.bss (NOLOAD) : ALIGN(8)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_bss_start = ABSOLUTE(.);
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN (8);
|
||||
_bss_end = ABSOLUTE(.);
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
.heap_mem (NOLOAD) : ALIGN(8)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_heap_mem_start = ABSOLUTE(.);
|
||||
*(*.heap_mem)
|
||||
_heap_mem_end = ABSOLUTE(.);
|
||||
} >sdram1 :sdram1_phdr
|
||||
|
||||
/* stack */
|
||||
_end = ALIGN (8);
|
||||
PROVIDE(end = ALIGN (8));
|
||||
|
||||
/* Mostly unused, though newlib likes them */
|
||||
_heap_sentry = .;
|
||||
__stack = SDRAM1_BASE + SDRAM1_SIZE;
|
||||
.comment 0 : { *(.comment) }
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
.debug_ranges 0 : { *(.debug_ranges) }
|
||||
.xtensa.info 0 : { *(.xtensa.info) }
|
||||
.xt.insn 0 :
|
||||
{
|
||||
KEEP (*(.xt.insn))
|
||||
KEEP (*(.gnu.linkonce.x.*))
|
||||
}
|
||||
.xt.prop 0 :
|
||||
{
|
||||
KEEP (*(.xt.prop))
|
||||
KEEP (*(.xt.prop.*))
|
||||
KEEP (*(.gnu.linkonce.prop.*))
|
||||
}
|
||||
.xt.lit 0 :
|
||||
{
|
||||
KEEP (*(.xt.lit))
|
||||
KEEP (*(.xt.lit.*))
|
||||
KEEP (*(.gnu.linkonce.p.*))
|
||||
}
|
||||
.xt.profile_range 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_range))
|
||||
KEEP (*(.gnu.linkonce.profile_range.*))
|
||||
}
|
||||
.xt.profile_ranges 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_ranges))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
|
||||
}
|
||||
.xt.profile_files 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_files))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_files.*))
|
||||
}
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
#include <zephyr/linker/intlist.ld>
|
||||
#endif
|
||||
|
||||
.static_uuid_entries (COPY) : ALIGN(1024)
|
||||
{
|
||||
*(*.static_uuids)
|
||||
} > static_uuid_entries_seg :static_uuid_entries_phdr
|
||||
|
||||
.static_log_entries (COPY) : ALIGN(1024)
|
||||
{
|
||||
*(*.static_log*)
|
||||
} > static_log_entries_seg :static_log_entries_phdr
|
||||
|
||||
.fw_metadata (COPY) : ALIGN(1024)
|
||||
{
|
||||
KEEP (*(.fw_metadata))
|
||||
. = ALIGN(_EXT_MAN_ALIGN_);
|
||||
} >fw_metadata_seg :metadata_entries_phdr
|
||||
|
||||
#include <snippets-sections.ld>
|
||||
}
|
||||
169
soc/nxp/imx/imx8m/adsp/memory.h
Normal file
169
soc/nxp/imx/imx8m/adsp/memory.h
Normal file
|
|
@ -0,0 +1,169 @@
|
|||
/*
|
||||
* Copyright 2021, 2023 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_NXP_ADSP_MEMORY_H_
|
||||
#define ZEPHYR_SOC_NXP_ADSP_MEMORY_H_
|
||||
|
||||
#define PLATFORM_CORE_COUNT 1
|
||||
|
||||
/** Id of master DSP core */
|
||||
#define PLATFORM_PRIMARY_CORE_ID 0
|
||||
|
||||
#define IRAM_RESERVE_HEADER_SPACE 0x400
|
||||
|
||||
#define IRAM_BASE 0x3B6F8000
|
||||
#define IRAM_SIZE 0x800
|
||||
|
||||
#define SDRAM0_BASE 0x92400000
|
||||
#define SDRAM0_SIZE 0x800000
|
||||
|
||||
#define SDRAM1_BASE 0x92C00000
|
||||
#define SDRAM1_SIZE 0x800000
|
||||
|
||||
/* The reset vector address in SRAM and its size */
|
||||
#define MEM_RESET_TEXT_SIZE 0x2E0
|
||||
#define MEM_RESET_LIT_SIZE 0x120
|
||||
|
||||
/* This is the base address of all the vectors defined in IRAM */
|
||||
#define XCHAL_VECBASE_RESET_PADDR_IRAM \
|
||||
(IRAM_BASE + IRAM_RESERVE_HEADER_SPACE)
|
||||
|
||||
#define MEM_VECBASE_LIT_SIZE 0x178
|
||||
|
||||
/*
|
||||
* EXCEPTIONS and VECTORS
|
||||
*/
|
||||
#define XCHAL_RESET_VECTOR0_PADDR_IRAM 0x3B6F8000
|
||||
|
||||
/* Vector and literal sizes */
|
||||
#define MEM_VECT_LIT_SIZE 0x4
|
||||
#define MEM_VECT_TEXT_SIZE 0x1C
|
||||
#define MEM_VECT_SIZE (MEM_VECT_TEXT_SIZE +\
|
||||
MEM_VECT_LIT_SIZE)
|
||||
|
||||
/* The addresses of the vectors.
|
||||
* Only the mem_error vector continues to point to its ROM address.
|
||||
*/
|
||||
#define XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x17C)
|
||||
|
||||
#define XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x19C)
|
||||
|
||||
#define XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1BC)
|
||||
|
||||
#define XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1DC)
|
||||
|
||||
#define XCHAL_KERNEL_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1FC)
|
||||
|
||||
#define XCHAL_USER_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x21C)
|
||||
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x23C)
|
||||
|
||||
/* Location for the intList section which is later used to construct the
|
||||
* Interrupt Descriptor Table (IDT). This is a bogus address as this
|
||||
* section will be stripped off in the final image.
|
||||
*/
|
||||
#define IDT_BASE (IRAM_BASE + IRAM_SIZE)
|
||||
|
||||
/* size of the Interrupt Descriptor Table (IDT) */
|
||||
#define IDT_SIZE 0x2000
|
||||
|
||||
/* physical DSP addresses */
|
||||
#define IRAM_BASE 0x3B6F8000
|
||||
#define IRAM_SIZE 0x800
|
||||
|
||||
#define DRAM0_BASE 0x3B6E8000
|
||||
#define DRAM0_SIZE 0x8000
|
||||
|
||||
#define DRAM1_BASE 0x3B6F0000
|
||||
#define DRAM1_SIZE 0x8000
|
||||
|
||||
#define SDRAM0_BASE 0x92400000
|
||||
#define SDRAM0_SIZE 0x800000
|
||||
|
||||
#define SDRAM1_BASE 0x92C00000
|
||||
#define SDRAM1_SIZE 0x800000
|
||||
|
||||
#define XSHAL_MU2_SIDEB_BYPASS_PADDR 0x30E70000
|
||||
#define MU_BASE XSHAL_MU2_SIDEB_BYPASS_PADDR
|
||||
|
||||
#define SDMA2_BASE 0x30E10000
|
||||
#define SDMA2_SIZE 0x10000
|
||||
|
||||
#define SDMA3_BASE 0x30E00000
|
||||
#define SDMA3_SIZE 0x10000
|
||||
|
||||
#define SAI_1_BASE 0x30C10000
|
||||
#define SAI_1_SIZE 0x00010000
|
||||
|
||||
#define SAI_3_BASE 0x30C30000
|
||||
#define SAI_3_SIZE 0x00010000
|
||||
#define UUID_ENTRY_ELF_BASE 0x1FFFA000
|
||||
#define UUID_ENTRY_ELF_SIZE 0x6000
|
||||
|
||||
#define LOG_ENTRY_ELF_BASE 0x20000000
|
||||
#define LOG_ENTRY_ELF_SIZE 0x2000000
|
||||
|
||||
#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
|
||||
#define EXT_MANIFEST_ELF_SIZE 0x2000000
|
||||
|
||||
/*
|
||||
* The Heap and Stack on i.MX8 are organized like this :-
|
||||
*
|
||||
* +--------------------------------------------------------------------------+
|
||||
* | Offset | Region | Size |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | SDRAM_BASE | RO Data | SOF_DATA_SIZE |
|
||||
* | | Data | |
|
||||
* | | BSS | |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | HEAP_SYSTEM_BASE | System Heap | HEAP_SYSTEM_SIZE |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | HEAP_RUNTIME_BASE | Runtime Heap | HEAP_RUNTIME_SIZE |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | HEAP_BUFFER_BASE | Module Buffers | HEAP_BUFFER_SIZE |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | SOF_STACK_END | Stack | SOF_STACK_SIZE |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | SOF_STACK_BASE | | |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
*/
|
||||
|
||||
#define SRAM_OUTBOX_BASE SDRAM1_BASE
|
||||
#define SRAM_OUTBOX_SIZE 0x1000
|
||||
#define SRAM_OUTBOX_OFFSET 0
|
||||
|
||||
#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE)
|
||||
#define SRAM_INBOX_SIZE 0x1000
|
||||
#define SRAM_INBOX_OFFSET SRAM_OUTBOX_SIZE
|
||||
|
||||
#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
|
||||
#define SRAM_DEBUG_SIZE 0x800
|
||||
#define SRAM_DEBUG_OFFSET (SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE)
|
||||
|
||||
#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
|
||||
#define SRAM_EXCEPT_SIZE 0x800
|
||||
#define SRAM_EXCEPT_OFFSET (SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE)
|
||||
|
||||
#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
|
||||
#define SRAM_STREAM_SIZE 0x1000
|
||||
#define SRAM_STREAM_OFFSET (SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE)
|
||||
|
||||
#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
|
||||
#define SRAM_TRACE_SIZE 0x1000
|
||||
#define SRAM_TRACE_OFFSET (SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE)
|
||||
|
||||
#define SOF_MAILBOX_SIZE (SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE \
|
||||
+ SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE \
|
||||
+ SRAM_STREAM_SIZE + SRAM_TRACE_SIZE)
|
||||
|
||||
#endif /* ZEPHYR_SOC_NXP_ADSP_MEMORY_H_ */
|
||||
83
soc/nxp/imx/imx8m/adsp/pinctrl_soc.h
Normal file
83
soc/nxp/imx/imx8m/adsp/pinctrl_soc.h
Normal file
|
|
@ -0,0 +1,83 @@
|
|||
/*
|
||||
* Copyright (c) 2023, NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_XTENSA_NXP_IMX8M_PINCTRL_SOC_H_
|
||||
#define ZEPHYR_SOC_XTENSA_NXP_IMX8M_PINCTRL_SOC_H_
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/types.h>
|
||||
#include "fsl_common.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT
|
||||
#define MCUX_IMX_BIAS_PULL_UP_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT
|
||||
#define MCUX_IMX_BIAS_PULL_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_PE_SHIFT
|
||||
#define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT
|
||||
#define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT
|
||||
#define MCUX_IMX_DRIVE_STRENGTH_SHIFT IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT
|
||||
#define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
|
||||
#define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1)
|
||||
|
||||
#define Z_PINCTRL_MCUX_IMX_PINCFG_INIT(node_id) \
|
||||
((DT_PROP(node_id, input_schmitt_enable) << MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT) | \
|
||||
(DT_PROP(node_id, bias_pull_up) << MCUX_IMX_BIAS_PULL_UP_SHIFT) | \
|
||||
((DT_PROP(node_id, bias_pull_up) | DT_PROP(node_id, bias_pull_down)) \
|
||||
<< MCUX_IMX_BIAS_PULL_ENABLE_SHIFT) | \
|
||||
(DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) | \
|
||||
(DT_ENUM_IDX(node_id, drive_strength) << MCUX_IMX_DRIVE_STRENGTH_SHIFT) | \
|
||||
(DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \
|
||||
(DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT))
|
||||
|
||||
|
||||
/* This struct must be present. It is used by the mcux gpio driver */
|
||||
struct pinctrl_soc_pinmux {
|
||||
uint32_t mux_register; /*!< IOMUXC SW_PAD_MUX register */
|
||||
uint32_t config_register; /*!< IOMUXC SW_PAD_CTL register */
|
||||
uint32_t input_register; /*!< IOMUXC SELECT_INPUT DAISY register */
|
||||
uint8_t mux_mode: 4; /*!< Mux value for SW_PAD_MUX register */
|
||||
uint32_t input_daisy:4; /*!< Mux value for SELECT_INPUT_DAISY register */
|
||||
};
|
||||
|
||||
struct pinctrl_soc_pin {
|
||||
struct pinctrl_soc_pinmux pinmux;
|
||||
uint32_t pin_ctrl_flags; /*!< value to write to IOMUXC_SW_PAD_CTL register */
|
||||
};
|
||||
|
||||
typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
|
||||
|
||||
/* This definition must be present. It is used by the mcux gpio driver */
|
||||
#define MCUX_IMX_PINMUX(node_id) \
|
||||
{ \
|
||||
.mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \
|
||||
.config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \
|
||||
.input_register = DT_PROP_BY_IDX(node_id, pinmux, 2), \
|
||||
.mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1), \
|
||||
.input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3), \
|
||||
}
|
||||
|
||||
#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \
|
||||
MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
|
||||
|
||||
#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \
|
||||
{ \
|
||||
.pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
|
||||
.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PINCFG_INIT(group_id), \
|
||||
},
|
||||
|
||||
|
||||
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
|
||||
DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)}; \
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ZEPHYR_SOC_XTENSA_NXP_IMX8M_PINCTRL_SOC_H_ */
|
||||
19
soc/nxp/imx/imx8m/m4_mini/CMakeLists.txt
Normal file
19
soc/nxp/imx/imx8m/m4_mini/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
#
|
||||
# Copyright (c) 2020, Manivannan Sadhasivam <mani@kernel.org>
|
||||
# Copyright 2024 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
zephyr_sources(
|
||||
soc.c
|
||||
)
|
||||
|
||||
zephyr_include_directories(.)
|
||||
|
||||
if(CONFIG_OPENAMP_RSC_TABLE)
|
||||
zephyr_linker_section(NAME .resource_table GROUP ROM_REGION NOINPUT)
|
||||
zephyr_linker_section_configure(SECTION .resource_table KEEP INPUT ".resource_table*")
|
||||
endif()
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")
|
||||
17
soc/nxp/imx/imx8m/m4_mini/linker.ld
Normal file
17
soc/nxp/imx/imx8m/m4_mini/linker.ld
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2020, Manivannan Sadhasivam <mani@kernel.org>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/arch/arm/cortex_m/scripts/linker.ld>
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
#ifdef CONFIG_OPENAMP_RSC_TABLE
|
||||
SECTION_PROLOGUE(.resource_table,, SUBALIGN(4))
|
||||
{
|
||||
KEEP(*(.resource_table*))
|
||||
} GROUP_LINK_IN(ROMABLE_REGION)
|
||||
#endif
|
||||
}
|
||||
83
soc/nxp/imx/imx8m/m4_mini/pinctrl_soc.h
Normal file
83
soc/nxp/imx/imx8m/m4_mini/pinctrl_soc.h
Normal file
|
|
@ -0,0 +1,83 @@
|
|||
/*
|
||||
* Copyright (c) 2022, NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_ARM_NXP_MIMX8MM6_PINCTRL_SOC_H_
|
||||
#define ZEPHYR_SOC_ARM_NXP_MIMX8MM6_PINCTRL_SOC_H_
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/types.h>
|
||||
#include "fsl_common.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT
|
||||
#define MCUX_IMX_BIAS_PULL_UP_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT
|
||||
#define MCUX_IMX_BIAS_PULL_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_PE_SHIFT
|
||||
#define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT
|
||||
#define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT
|
||||
#define MCUX_IMX_DRIVE_STRENGTH_SHIFT IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT
|
||||
#define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
|
||||
#define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1)
|
||||
|
||||
#define Z_PINCTRL_MCUX_IMX_PINCFG_INIT(node_id) \
|
||||
((DT_PROP(node_id, input_schmitt_enable) << MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT) | \
|
||||
(DT_PROP(node_id, bias_pull_up) << MCUX_IMX_BIAS_PULL_UP_SHIFT) | \
|
||||
((DT_PROP(node_id, bias_pull_up) | DT_PROP(node_id, bias_pull_down)) \
|
||||
<< MCUX_IMX_BIAS_PULL_ENABLE_SHIFT) | \
|
||||
(DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) | \
|
||||
(DT_ENUM_IDX(node_id, drive_strength) << MCUX_IMX_DRIVE_STRENGTH_SHIFT) | \
|
||||
(DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \
|
||||
(DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT))
|
||||
|
||||
|
||||
/* This struct must be present. It is used by the mcux gpio driver */
|
||||
struct pinctrl_soc_pinmux {
|
||||
uint32_t mux_register; /*!< IOMUXC SW_PAD_MUX register */
|
||||
uint32_t config_register; /*!< IOMUXC SW_PAD_CTL register */
|
||||
uint32_t input_register; /*!< IOMUXC SELECT_INPUT DAISY register */
|
||||
uint8_t mux_mode: 4; /*!< Mux value for SW_PAD_MUX register */
|
||||
uint32_t input_daisy:4; /*!< Mux value for SELECT_INPUT_DAISY register */
|
||||
};
|
||||
|
||||
struct pinctrl_soc_pin {
|
||||
struct pinctrl_soc_pinmux pinmux;
|
||||
uint32_t pin_ctrl_flags; /*!< value to write to IOMUXC_SW_PAD_CTL register */
|
||||
};
|
||||
|
||||
typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
|
||||
|
||||
/* This definition must be present. It is used by the mcux gpio driver */
|
||||
#define MCUX_IMX_PINMUX(node_id) \
|
||||
{ \
|
||||
.mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \
|
||||
.config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \
|
||||
.input_register = DT_PROP_BY_IDX(node_id, pinmux, 2), \
|
||||
.mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1), \
|
||||
.input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3), \
|
||||
}
|
||||
|
||||
#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \
|
||||
MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
|
||||
|
||||
#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \
|
||||
{ \
|
||||
.pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
|
||||
.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PINCFG_INIT(group_id), \
|
||||
},
|
||||
|
||||
|
||||
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
|
||||
DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)}; \
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ZEPHYR_SOC_ARM_NXP_MIMX8MM6_PINCTRL_SOC_H_ */
|
||||
163
soc/nxp/imx/imx8m/m4_mini/soc.c
Normal file
163
soc/nxp/imx/imx8m/m4_mini/soc.c
Normal file
|
|
@ -0,0 +1,163 @@
|
|||
/*
|
||||
* Copyright (c) 2020, Manivannan Sadhasivam <mani@kernel.org>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/device.h>
|
||||
#include <fsl_clock.h>
|
||||
#include <fsl_common.h>
|
||||
#include <fsl_rdc.h>
|
||||
#include <zephyr/init.h>
|
||||
#include <zephyr/kernel.h>
|
||||
#include <soc.h>
|
||||
|
||||
#include <zephyr/dt-bindings/rdc/imx_rdc.h>
|
||||
|
||||
/* OSC/PLL is already initialized by ROM and Cortex-A53 (u-boot) */
|
||||
static void SOC_RdcInit(void)
|
||||
{
|
||||
/* Move M4 core to specific RDC domain 1 */
|
||||
rdc_domain_assignment_t assignment = {0};
|
||||
|
||||
assignment.domainId = M4_DOMAIN_ID;
|
||||
RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
|
||||
|
||||
/*
|
||||
* The M4 core is running at domain 1, enable clock gate for
|
||||
* Iomux to run at domain 1.
|
||||
*/
|
||||
CLOCK_EnableClock(kCLOCK_Iomux);
|
||||
CLOCK_EnableClock(kCLOCK_Ipmux1);
|
||||
CLOCK_EnableClock(kCLOCK_Ipmux2);
|
||||
CLOCK_EnableClock(kCLOCK_Ipmux3);
|
||||
CLOCK_EnableClock(kCLOCK_Ipmux4);
|
||||
|
||||
CLOCK_EnableClock(kCLOCK_Qspi);
|
||||
|
||||
/*
|
||||
* The M4 core is running at domain 1, enable the PLL clock sources
|
||||
* to domain 1.
|
||||
*/
|
||||
/* Enable SysPLL1 to Domain 1 */
|
||||
CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll);
|
||||
/* Enable SysPLL2 to Domain 1 */
|
||||
CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll);
|
||||
/* Enable SysPLL3 to Domain 1 */
|
||||
CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll);
|
||||
/* Enable AudioPLL1 to Domain 1 */
|
||||
CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll);
|
||||
/* Enable AudioPLL2 to Domain 1 */
|
||||
CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll);
|
||||
/* Enable VideoPLL1 to Domain 1 */
|
||||
CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll);
|
||||
}
|
||||
|
||||
/* AUDIO PLL1 configuration */
|
||||
static const ccm_analog_frac_pll_config_t g_audioPll1Config = {
|
||||
.refSel = kANALOG_PllRefOsc24M, /* PLL reference OSC24M */
|
||||
.mainDiv = 655U,
|
||||
.dsm = 23593U,
|
||||
.preDiv = 5U,
|
||||
.postDiv = 2U, /* AUDIO PLL1 frequency = 786432000HZ */
|
||||
};
|
||||
|
||||
/* AUDIO PLL2 configuration */
|
||||
static const ccm_analog_frac_pll_config_t g_audioPll2Config = {
|
||||
.refSel = kANALOG_PllRefOsc24M, /* PLL reference OSC24M */
|
||||
.mainDiv = 301U,
|
||||
.dsm = 3670U,
|
||||
.preDiv = 5U,
|
||||
.postDiv = 1U, /* AUDIO PLL2 frequency = 722534399HZ */
|
||||
};
|
||||
|
||||
static void SOC_ClockInit(void)
|
||||
{
|
||||
/*
|
||||
* Switch AHB NOC root to 24M first in order to configure
|
||||
* the SYSTEM PLL1
|
||||
*/
|
||||
CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
|
||||
|
||||
/*
|
||||
* Switch AXI M4 root to 24M first in order to configure
|
||||
* the SYSTEM PLL2
|
||||
*/
|
||||
CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
|
||||
|
||||
/* Init AUDIO PLL1 to run at 786432000HZ */
|
||||
CLOCK_InitAudioPll1(&g_audioPll1Config);
|
||||
/* Init AUDIO PLL2 to run at 722534399HZ */
|
||||
CLOCK_InitAudioPll2(&g_audioPll2Config);
|
||||
|
||||
CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
|
||||
/* Switch cortex-m4 to SYSTEM PLL1 */
|
||||
CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1);
|
||||
|
||||
CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
|
||||
/* Switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
|
||||
CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6);
|
||||
|
||||
/* Set root clock to 800MHZ/ 2= 400MHZ */
|
||||
CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U);
|
||||
/* switch AUDIO AHB to SYSTEM PLL1 */
|
||||
CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1);
|
||||
|
||||
#if defined(CONFIG_UART_MCUX_IUART)
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay)
|
||||
/* Set UART source to SysPLL1 Div10 80MHZ */
|
||||
CLOCK_SetRootMux(kCLOCK_RootUart1, kCLOCK_UartRootmuxSysPll1Div10);
|
||||
/* Set root clock to 80MHZ/ 1= 80MHZ */
|
||||
CLOCK_SetRootDivider(kCLOCK_RootUart1, 1U, 1U);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay)
|
||||
/* Set UART source to SysPLL1 Div10 80MHZ */
|
||||
CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10);
|
||||
/* Set root clock to 80MHZ/ 1= 80MHZ */
|
||||
CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart3), okay)
|
||||
/* Set UART source to SysPLL1 Div10 80MHZ */
|
||||
CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10);
|
||||
/* Set root clock to 80MHZ/ 1= 80MHZ */
|
||||
CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart4), okay)
|
||||
/* Set UART source to SysPLL1 Div10 80MHZ */
|
||||
CLOCK_SetRootMux(kCLOCK_RootUart4, kCLOCK_UartRootmuxSysPll1Div10);
|
||||
/* Set root clock to 80MHZ/ 1= 80MHZ */
|
||||
CLOCK_SetRootDivider(kCLOCK_RootUart4, 1U, 1U);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Enable RDC clock */
|
||||
CLOCK_EnableClock(kCLOCK_Rdc);
|
||||
|
||||
/*
|
||||
* The purpose to enable the following modules clock is to make
|
||||
* sure the M4 core could work normally when A53 core
|
||||
* enters the low power state
|
||||
*/
|
||||
CLOCK_EnableClock(kCLOCK_Sim_display);
|
||||
CLOCK_EnableClock(kCLOCK_Sim_m);
|
||||
CLOCK_EnableClock(kCLOCK_Sim_main);
|
||||
CLOCK_EnableClock(kCLOCK_Sim_s);
|
||||
CLOCK_EnableClock(kCLOCK_Sim_wakeup);
|
||||
CLOCK_EnableClock(kCLOCK_Debug);
|
||||
CLOCK_EnableClock(kCLOCK_Dram);
|
||||
CLOCK_EnableClock(kCLOCK_Sec_Debug);
|
||||
}
|
||||
|
||||
static int nxp_mimx8mm6_init(void)
|
||||
{
|
||||
|
||||
/* SoC specific RDC settings */
|
||||
SOC_RdcInit();
|
||||
|
||||
/* SoC specific Clock settings */
|
||||
SOC_ClockInit();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(nxp_mimx8mm6_init, PRE_KERNEL_1, 0);
|
||||
24
soc/nxp/imx/imx8m/m4_mini/soc.h
Normal file
24
soc/nxp/imx/imx8m/m4_mini/soc.h
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* Copyright (c) 2020, Manivannan Sadhasivam <mani@kernel.org>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _SOC__H_
|
||||
#define _SOC__H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#include <fsl_device_registers.h>
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC__H_ */
|
||||
13
soc/nxp/imx/imx8m/m4_quad/CMakeLists.txt
Normal file
13
soc/nxp/imx/imx8m/m4_quad/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
#
|
||||
# Copyright (c) 2021, Kwon Tae-young <tykwon@m2i.co.kr>
|
||||
# Copyright 2024 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
zephyr_sources(
|
||||
soc.c
|
||||
)
|
||||
zephyr_include_directories(.)
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
|
||||
82
soc/nxp/imx/imx8m/m4_quad/pinctrl_soc.h
Normal file
82
soc/nxp/imx/imx8m/m4_quad/pinctrl_soc.h
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* Copyright (c) 2022, NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_ARM_NXP_MIMX8MQ6_M4_PINCTRL_SOC_H_
|
||||
#define ZEPHYR_SOC_ARM_NXP_MIMX8MQ6_M4_PINCTRL_SOC_H_
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/types.h>
|
||||
#include "fsl_common.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define MCUX_IMX_LVTTL_SHIFT IOMUXC_SW_PAD_CTL_PAD_LVTTL_SHIFT
|
||||
#define MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT
|
||||
#define MCUX_IMX_BIAS_PULL_UP_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT
|
||||
#define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT
|
||||
#define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT
|
||||
#define MCUX_IMX_DRIVE_STRENGTH_SHIFT IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT
|
||||
#define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
|
||||
#define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1)
|
||||
|
||||
#define Z_PINCTRL_MCUX_IMX_PINCFG_INIT(node_id) \
|
||||
((DT_PROP(node_id, nxp_lvttl) << MCUX_IMX_LVTTL_SHIFT) | \
|
||||
(DT_PROP(node_id, input_schmitt_enable) << MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT) | \
|
||||
(DT_PROP(node_id, bias_pull_up) << MCUX_IMX_BIAS_PULL_UP_SHIFT) | \
|
||||
(DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) | \
|
||||
(DT_ENUM_IDX(node_id, drive_strength) << MCUX_IMX_DRIVE_STRENGTH_SHIFT) | \
|
||||
(DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \
|
||||
(DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT))
|
||||
|
||||
|
||||
/* This struct must be present. It is used by the mcux gpio driver */
|
||||
struct pinctrl_soc_pinmux {
|
||||
uint32_t mux_register; /*!< IOMUXC SW_PAD_MUX register */
|
||||
uint32_t config_register; /*!< IOMUXC SW_PAD_CTL register */
|
||||
uint32_t input_register; /*!< IOMUXC SELECT_INPUT DAISY register */
|
||||
uint8_t mux_mode: 4; /*!< Mux value for SW_PAD_MUX register */
|
||||
uint32_t input_daisy:4; /*!< Mux value for SELECT_INPUT_DAISY register */
|
||||
};
|
||||
|
||||
struct pinctrl_soc_pin {
|
||||
struct pinctrl_soc_pinmux pinmux;
|
||||
uint32_t pin_ctrl_flags; /* value to write to IOMUXC_SW_PAD_CTL register */
|
||||
};
|
||||
|
||||
typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
|
||||
|
||||
/* This definition must be present. It is used by the mcux gpio driver */
|
||||
#define MCUX_IMX_PINMUX(node_id) \
|
||||
{ \
|
||||
.mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \
|
||||
.config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \
|
||||
.input_register = DT_PROP_BY_IDX(node_id, pinmux, 2), \
|
||||
.mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1), \
|
||||
.input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3), \
|
||||
}
|
||||
|
||||
#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \
|
||||
MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
|
||||
|
||||
#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \
|
||||
{ \
|
||||
.pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
|
||||
.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PINCFG_INIT(group_id), \
|
||||
},
|
||||
|
||||
|
||||
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
|
||||
DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)}; \
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ZEPHYR_SOC_ARM_NXP_MIMX8MQ6_M4_PINCTRL_SOC_H_ */
|
||||
126
soc/nxp/imx/imx8m/m4_quad/soc.c
Normal file
126
soc/nxp/imx/imx8m/m4_quad/soc.c
Normal file
|
|
@ -0,0 +1,126 @@
|
|||
/*
|
||||
* Copyright (c) 2021, Kwon Tae-young <tykwon@m2i.co.kr>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/device.h>
|
||||
#include <fsl_clock.h>
|
||||
#include <fsl_common.h>
|
||||
#include <fsl_rdc.h>
|
||||
#include <zephyr/init.h>
|
||||
#include <zephyr/kernel.h>
|
||||
#include <soc.h>
|
||||
|
||||
#include <zephyr/dt-bindings/rdc/imx_rdc.h>
|
||||
|
||||
/* OSC/PLL is already initialized by ROM and Cortex-A53 (u-boot) */
|
||||
static void SOC_RdcInit(void)
|
||||
{
|
||||
/* Move M4 core to specific RDC domain 1 */
|
||||
rdc_domain_assignment_t assignment = {0};
|
||||
|
||||
assignment.domainId = M4_DOMAIN_ID;
|
||||
RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
|
||||
|
||||
/*
|
||||
* The M4 core is running at domain 1, enable clock gate for
|
||||
* Iomux to run at domain 1.
|
||||
*/
|
||||
CLOCK_EnableClock(kCLOCK_Iomux);
|
||||
CLOCK_EnableClock(kCLOCK_Ipmux1);
|
||||
CLOCK_EnableClock(kCLOCK_Ipmux2);
|
||||
CLOCK_EnableClock(kCLOCK_Ipmux3);
|
||||
CLOCK_EnableClock(kCLOCK_Ipmux4);
|
||||
|
||||
/*
|
||||
* The M4 core is running at domain 1, enable the PLL clock sources
|
||||
* to domain 1.
|
||||
*/
|
||||
CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll);
|
||||
CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll);
|
||||
CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll);
|
||||
CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll);
|
||||
CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll);
|
||||
CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll);
|
||||
CLOCK_ControlGate(kCLOCK_VideoPll2Gate, kCLOCK_ClockNeededAll);
|
||||
}
|
||||
|
||||
static void SOC_ClockInit(void)
|
||||
{
|
||||
/*
|
||||
* Switch AHB NOC root to 25M first in order to configure
|
||||
* the SYSTEM PLL1
|
||||
*/
|
||||
CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m);
|
||||
CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
|
||||
/* Switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
|
||||
CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6);
|
||||
|
||||
/*
|
||||
* Switch AXI M4 root to 25M first in order to configure
|
||||
* the SYSTEM PLL1
|
||||
*/
|
||||
CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc25m);
|
||||
CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U);
|
||||
/* Switch cortex-m4 to SYSTEM PLL1 DIV3 */
|
||||
CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3);
|
||||
|
||||
#if defined(CONFIG_UART_MCUX_IUART)
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay)
|
||||
/* Set UART source to SysPLL1 Div10 80MHZ */
|
||||
CLOCK_SetRootMux(kCLOCK_RootUart1, kCLOCK_UartRootmuxSysPll1Div10);
|
||||
/* Set root clock to 80MHZ/ 1= 80MHZ */
|
||||
CLOCK_SetRootDivider(kCLOCK_RootUart1, 1U, 1U);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay)
|
||||
/* Set UART source to SysPLL1 Div10 80MHZ */
|
||||
CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10);
|
||||
/* Set root clock to 80MHZ/ 1= 80MHZ */
|
||||
CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart3), okay)
|
||||
/* Set UART source to SysPLL1 Div10 80MHZ */
|
||||
CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10);
|
||||
/* Set root clock to 80MHZ/ 1= 80MHZ */
|
||||
CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart4), okay)
|
||||
/* Set UART source to SysPLL1 Div10 80MHZ */
|
||||
CLOCK_SetRootMux(kCLOCK_RootUart4, kCLOCK_UartRootmuxSysPll1Div10);
|
||||
/* Set root clock to 80MHZ/ 1= 80MHZ */
|
||||
CLOCK_SetRootDivider(kCLOCK_RootUart4, 1U, 1U);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Enable RDC clock */
|
||||
CLOCK_EnableClock(kCLOCK_Rdc);
|
||||
|
||||
/*
|
||||
* The purpose to enable the following modules clock is to make
|
||||
* sure the M4 core could work normally when A53 core
|
||||
* enters the low power state
|
||||
*/
|
||||
CLOCK_EnableClock(kCLOCK_Sim_display);
|
||||
CLOCK_EnableClock(kCLOCK_Sim_m);
|
||||
CLOCK_EnableClock(kCLOCK_Sim_main);
|
||||
CLOCK_EnableClock(kCLOCK_Sim_s);
|
||||
CLOCK_EnableClock(kCLOCK_Sim_wakeup);
|
||||
CLOCK_EnableClock(kCLOCK_Debug);
|
||||
CLOCK_EnableClock(kCLOCK_Dram);
|
||||
CLOCK_EnableClock(kCLOCK_Sec_Debug);
|
||||
}
|
||||
|
||||
static int nxp_mimx8mq6_init(void)
|
||||
{
|
||||
|
||||
/* SoC specific RDC settings */
|
||||
SOC_RdcInit();
|
||||
|
||||
/* SoC specific Clock settings */
|
||||
SOC_ClockInit();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(nxp_mimx8mq6_init, PRE_KERNEL_1, 0);
|
||||
24
soc/nxp/imx/imx8m/m4_quad/soc.h
Normal file
24
soc/nxp/imx/imx8m/m4_quad/soc.h
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* Copyright (c) 2021, Kwon Tae-young <tykwon@m2i.co.kr>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _SOC__H_
|
||||
#define _SOC__H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#include <fsl_device_registers.h>
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC__H_ */
|
||||
21
soc/nxp/imx/imx8m/m7/CMakeLists.txt
Normal file
21
soc/nxp/imx/imx8m/m7/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
#
|
||||
# Copyright (c) 2021, Laird Connectivity
|
||||
# Copyright 2024 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
zephyr_include_directories(${ZEPHYR_BASE}/drivers)
|
||||
zephyr_include_directories(.)
|
||||
|
||||
zephyr_sources(
|
||||
soc.c
|
||||
mpu_regions.c
|
||||
)
|
||||
|
||||
if(CONFIG_OPENAMP_RSC_TABLE)
|
||||
zephyr_linker_section(NAME .resource_table GROUP ROM_REGION NOINPUT)
|
||||
zephyr_linker_section_configure(SECTION .resource_table KEEP INPUT ".resource_table*")
|
||||
endif()
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")
|
||||
29
soc/nxp/imx/imx8m/m7/linker.ld
Normal file
29
soc/nxp/imx/imx8m/m7/linker.ld
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* Copyright (c) 2021, Laird Connectivity
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
|
||||
MEMORY
|
||||
{
|
||||
#if defined(CONFIG_CODE_DDR)
|
||||
DDR (wx) : ORIGIN = 0x80400000, LENGTH = 0x00C00000
|
||||
#else
|
||||
DDR (wx) : ORIGIN = 0x80000000, LENGTH = 0x01000000
|
||||
#endif
|
||||
}
|
||||
|
||||
#include <zephyr/arch/arm/cortex_m/scripts/linker.ld>
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
#ifdef CONFIG_OPENAMP_RSC_TABLE
|
||||
SECTION_PROLOGUE(.resource_table,, SUBALIGN(4))
|
||||
{
|
||||
KEEP(*(.resource_table*))
|
||||
} GROUP_LINK_IN(ROMABLE_REGION)
|
||||
#endif
|
||||
}
|
||||
91
soc/nxp/imx/imx8m/m7/mpu_regions.c
Normal file
91
soc/nxp/imx/imx8m/m7/mpu_regions.c
Normal file
|
|
@ -0,0 +1,91 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Laird Connectivity
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
|
||||
|
||||
#define REGION_MASK_BASE_ADDRESS 0x00000000U
|
||||
#define REGION_ITCM_BASE_ADDRESS 0x00000000U
|
||||
#define REGION_QSPI_BASE_ADDRESS 0x08000000U
|
||||
#define REGION_DTCM_BASE_ADDRESS 0x20000000U
|
||||
#define REGION_DDR_BASE_ADDRESS 0x40000000U
|
||||
#define REGION_DDR2_BASE_ADDRESS 0x80000000U
|
||||
#if defined(CONFIG_CODE_DDR)
|
||||
#define REGION_DDR_NONCACHE_BASE_ADDRESS 0x80000000U
|
||||
#define REGION_DDR_NONCACHE_SIZE 0x00400000U
|
||||
#endif
|
||||
|
||||
static const struct arm_mpu_region mpu_regions[] = {
|
||||
/*
|
||||
* Region 0 [0x0000_0000 - 0x4000_0000]:
|
||||
* Memory with Device type, not executable, not shareable, non-cacheable.
|
||||
*/
|
||||
MPU_REGION_ENTRY("MASK", REGION_MASK_BASE_ADDRESS,
|
||||
{ ARM_MPU_RASR(1, ARM_MPU_AP_FULL,
|
||||
0, 0, 0, 1, 0, ARM_MPU_REGION_SIZE_1GB) }),
|
||||
|
||||
/*
|
||||
* Region 1 ITCM[0x0000_0000 - 0x0001_FFFF]:
|
||||
* Memory with Normal type, not shareable, non-cacheable
|
||||
*/
|
||||
MPU_REGION_ENTRY("ITCM", REGION_ITCM_BASE_ADDRESS,
|
||||
{ ARM_MPU_RASR(0, ARM_MPU_AP_FULL,
|
||||
1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_128KB) }),
|
||||
|
||||
/*
|
||||
* Region 2 QSPI[0x0800_0000 - 0x0FFF_FFFF]:
|
||||
* Memory with Normal type, not shareable, cacheable
|
||||
*/
|
||||
MPU_REGION_ENTRY("QSPI", REGION_QSPI_BASE_ADDRESS,
|
||||
{ ARM_MPU_RASR(0, ARM_MPU_AP_FULL,
|
||||
1, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128MB) }),
|
||||
|
||||
/*
|
||||
* Region 3 DTCM[0x2000_0000 - 0x2002_0000]:
|
||||
* Memory with Normal type, not shareable, non-cacheable
|
||||
*/
|
||||
MPU_REGION_ENTRY("DTCM", REGION_DTCM_BASE_ADDRESS,
|
||||
{ ARM_MPU_RASR(0, ARM_MPU_AP_FULL,
|
||||
1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_128KB) }),
|
||||
|
||||
/*
|
||||
* Region 4 DDR[0x4000_0000 - 0x8000_0000]:
|
||||
* Memory with Normal type, not shareable, non-cacheable
|
||||
*/
|
||||
MPU_REGION_ENTRY("DDR", REGION_DDR_BASE_ADDRESS,
|
||||
{ ARM_MPU_RASR(0, ARM_MPU_AP_FULL,
|
||||
1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB) }),
|
||||
|
||||
/*
|
||||
* Non-cacheable area is provided in DDR memory, the DDR region [0x80000000 ~ 0x81000000]
|
||||
* (please see the imx8mp-evk-rpmsg.dts) totally 16MB is reserved for CM7 core. You can put
|
||||
* global or static uninitialized variables in NonCacheable section(initialized variables in
|
||||
* NonCacheable.init section) to make them uncacheable. Since the base address of MPU region
|
||||
* should be multiples of region size, to make it simple, the MPU region 5 set the address
|
||||
* space 0x80000000 ~ 0xBFFFFFFF to be non-cacheable. Then MPU region 6 set the text and
|
||||
* data section to be cacheable if the program running on DDR. The cacheable area base
|
||||
* address should be multiples of its size in linker file, they can be modified per your
|
||||
* needs.
|
||||
*
|
||||
* Region 5 DDR[0x8000_0000 - 0xBFFFFFFF]:
|
||||
* Memory with Normal type, not shareable, non-cacheable
|
||||
*/
|
||||
MPU_REGION_ENTRY("DDR2", REGION_DDR2_BASE_ADDRESS,
|
||||
{ ARM_MPU_RASR(0, ARM_MPU_AP_FULL,
|
||||
1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB) }),
|
||||
|
||||
#if defined(CONFIG_CODE_DDR)
|
||||
/* If run on DDR, configure text and data section to be cacheable */
|
||||
MPU_REGION_ENTRY("DDR_NONCACHE", REGION_DDR_NONCACHE_BASE_ADDRESS,
|
||||
{ ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1,
|
||||
0, 1, 1, 0, REGION_DDR_NONCACHE_SIZE) }),
|
||||
#endif
|
||||
};
|
||||
|
||||
const struct arm_mpu_config mpu_config = {
|
||||
.num_regions = ARRAY_SIZE(mpu_regions),
|
||||
.mpu_regions = mpu_regions,
|
||||
};
|
||||
83
soc/nxp/imx/imx8m/m7/pinctrl_soc.h
Normal file
83
soc/nxp/imx/imx8m/m7/pinctrl_soc.h
Normal file
|
|
@ -0,0 +1,83 @@
|
|||
/*
|
||||
* Copyright (c) 2022, NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_ARM_NXP_MIMX8ML8_M7_PINCTRL_SOC_H_
|
||||
#define ZEPHYR_SOC_ARM_NXP_MIMX8ML8_M7_PINCTRL_SOC_H_
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/types.h>
|
||||
#include "fsl_common.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT
|
||||
#define MCUX_IMX_BIAS_PULL_UP_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT
|
||||
#define MCUX_IMX_BIAS_PULL_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_PE_SHIFT
|
||||
#define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT
|
||||
#define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT
|
||||
#define MCUX_IMX_DRIVE_STRENGTH_SHIFT IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT
|
||||
#define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
|
||||
#define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1)
|
||||
|
||||
#define Z_PINCTRL_MCUX_IMX_PINCFG_INIT(node_id) \
|
||||
((DT_PROP(node_id, input_schmitt_enable) << MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT) | \
|
||||
(DT_PROP(node_id, bias_pull_up) << MCUX_IMX_BIAS_PULL_UP_SHIFT) | \
|
||||
((DT_PROP(node_id, bias_pull_up) | DT_PROP(node_id, bias_pull_down)) \
|
||||
<< MCUX_IMX_BIAS_PULL_ENABLE_SHIFT) | \
|
||||
(DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) | \
|
||||
(DT_ENUM_IDX(node_id, drive_strength) << MCUX_IMX_DRIVE_STRENGTH_SHIFT) | \
|
||||
(DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \
|
||||
(DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT))
|
||||
|
||||
|
||||
/* This struct must be present. It is used by the mcux gpio driver */
|
||||
struct pinctrl_soc_pinmux {
|
||||
uint32_t mux_register; /*!< IOMUXC SW_PAD_MUX register */
|
||||
uint32_t config_register; /*!< IOMUXC SW_PAD_CTL register */
|
||||
uint32_t input_register; /*!< IOMUXC SELECT_INPUT DAISY register */
|
||||
uint8_t mux_mode: 4; /*!< Mux value for SW_PAD_MUX register */
|
||||
uint32_t input_daisy:4; /*!< Mux value for SELECT_INPUT_DAISY register */
|
||||
};
|
||||
|
||||
struct pinctrl_soc_pin {
|
||||
struct pinctrl_soc_pinmux pinmux;
|
||||
uint32_t pin_ctrl_flags; /*!< value to write to IOMUXC_SW_PAD_CTL register */
|
||||
};
|
||||
|
||||
typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
|
||||
|
||||
/* This definition must be present. It is used by the mcux gpio driver */
|
||||
#define MCUX_IMX_PINMUX(node_id) \
|
||||
{ \
|
||||
.mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \
|
||||
.config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \
|
||||
.input_register = DT_PROP_BY_IDX(node_id, pinmux, 2), \
|
||||
.mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1), \
|
||||
.input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3), \
|
||||
}
|
||||
|
||||
#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \
|
||||
MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
|
||||
|
||||
#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \
|
||||
{ \
|
||||
.pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
|
||||
.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PINCFG_INIT(group_id), \
|
||||
},
|
||||
|
||||
|
||||
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
|
||||
DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)}; \
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ZEPHYR_SOC_ARM_NXP_MIMX8ML8_M7_PINCTRL_SOC_H_ */
|
||||
163
soc/nxp/imx/imx8m/m7/soc.c
Normal file
163
soc/nxp/imx/imx8m/m7/soc.c
Normal file
|
|
@ -0,0 +1,163 @@
|
|||
/*
|
||||
* Copyright (c) 2021, Laird Connectivity
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/device.h>
|
||||
#include <fsl_clock.h>
|
||||
#include <fsl_common.h>
|
||||
#include <fsl_rdc.h>
|
||||
#include <zephyr/init.h>
|
||||
#include <zephyr/kernel.h>
|
||||
#include <soc.h>
|
||||
|
||||
#include <zephyr/dt-bindings/rdc/imx_rdc.h>
|
||||
|
||||
/* OSC/PLL is already initialized by ROM and Cortex-A53 (u-boot) */
|
||||
static void SOC_RdcInit(void)
|
||||
{
|
||||
/* Move M7 core to specific RDC domain 1 */
|
||||
rdc_domain_assignment_t assignment = {0};
|
||||
uint8_t domainId = 0U;
|
||||
|
||||
domainId = RDC_GetCurrentMasterDomainId(RDC);
|
||||
/* Only configure the RDC if RDC peripheral write access allowed. */
|
||||
if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U) {
|
||||
assignment.domainId = M7_DOMAIN_ID;
|
||||
RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M7, &assignment);
|
||||
}
|
||||
|
||||
/*
|
||||
* The M7 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL
|
||||
* in domain 1 in the CCM. In this way, to ensure the clock of the peripherals used by M
|
||||
* core not be affected by A core which is running at domain 0.
|
||||
*/
|
||||
CLOCK_EnableClock(kCLOCK_Iomux);
|
||||
|
||||
CLOCK_EnableClock(kCLOCK_Ipmux1);
|
||||
CLOCK_EnableClock(kCLOCK_Ipmux2);
|
||||
CLOCK_EnableClock(kCLOCK_Ipmux3);
|
||||
|
||||
#if defined(FLASH_TARGET)
|
||||
CLOCK_EnableClock(kCLOCK_Qspi);
|
||||
#endif
|
||||
|
||||
/* Enable the CCGR gate for SysPLL1 in Domain 1 */
|
||||
CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll);
|
||||
/* Enable the CCGR gate for SysPLL2 in Domain 1 */
|
||||
CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll);
|
||||
/* Enable the CCGR gate for SysPLL3 in Domain 1 */
|
||||
CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll);
|
||||
#ifdef CONFIG_INIT_VIDEO_PLL
|
||||
/* Enable the CCGR gate for VideoPLL1 in Domain 1 */
|
||||
CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
|
||||
/* SYSTEM PLL1 configuration */
|
||||
const ccm_analog_integer_pll_config_t g_sysPll1Config = {
|
||||
.refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
|
||||
.mainDiv = 400U,
|
||||
.preDiv = 3U,
|
||||
.postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
|
||||
};
|
||||
|
||||
/* SYSTEM PLL2 configuration */
|
||||
const ccm_analog_integer_pll_config_t g_sysPll2Config = {
|
||||
.refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
|
||||
.mainDiv = 250U,
|
||||
.preDiv = 3U,
|
||||
.postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
|
||||
};
|
||||
|
||||
/* SYSTEM PLL3 configuration */
|
||||
const ccm_analog_integer_pll_config_t g_sysPll3Config = {
|
||||
.refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
|
||||
.mainDiv = 300,
|
||||
.preDiv = 3U,
|
||||
.postDiv = 2U, /*!< SYSTEM PLL3 frequency = 600MHZ */
|
||||
};
|
||||
|
||||
static void SOC_ClockInit(void)
|
||||
{
|
||||
/*
|
||||
* The following steps just show how to configure the PLL clock sources using the clock
|
||||
* driver on M7 core side . Please note that the ROM has already configured the SYSTEM PLL1
|
||||
* to 800Mhz when power up the SOC, meanwhile A core would enable SYSTEM PLL1, SYSTEM PLL2
|
||||
* and SYSTEM PLL3 by U-Boot. Therefore, there is no need to configure the system PLL again
|
||||
* on M7 side, otherwise it would have a risk to make the SOC hang.
|
||||
*/
|
||||
|
||||
/* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
|
||||
CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
|
||||
|
||||
/* switch AXI M7 root to 24M first in order to configure the SYSTEM PLL2. */
|
||||
CLOCK_SetRootMux(kCLOCK_RootM7, kCLOCK_M7RootmuxOsc24M);
|
||||
|
||||
/* Set root clock to 800M */
|
||||
CLOCK_SetRootDivider(kCLOCK_RootM7, 1U, 1U);
|
||||
/* switch cortex-m7 to SYSTEM PLL1 */
|
||||
CLOCK_SetRootMux(kCLOCK_RootM7, kCLOCK_M7RootmuxSysPll1);
|
||||
|
||||
/* Set root clock freq to 133M / 1= 133MHZ */
|
||||
CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
|
||||
/* switch AHB to SYSTEM PLL1 DIV6 */
|
||||
CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6);
|
||||
|
||||
#if defined(CONFIG_UART_MCUX_IUART)
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay)
|
||||
/* Set UART source to SysPLL1 Div10 80MHZ */
|
||||
CLOCK_SetRootMux(kCLOCK_RootUart1, kCLOCK_UartRootmuxSysPll1Div10);
|
||||
/* Set root clock to 80MHZ/ 1= 80MHZ */
|
||||
CLOCK_SetRootDivider(kCLOCK_RootUart1, 1U, 1U);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay)
|
||||
/* Set UART source to SysPLL1 Div10 80MHZ */
|
||||
CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10);
|
||||
/* Set root clock to 80MHZ/ 1= 80MHZ */
|
||||
CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart3), okay)
|
||||
/* Set UART source to SysPLL1 Div10 80MHZ */
|
||||
CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10);
|
||||
/* Set root clock to 80MHZ/ 1= 80MHZ */
|
||||
CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U);
|
||||
#endif
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart4), okay)
|
||||
/* Set UART source to SysPLL1 Div10 80MHZ */
|
||||
CLOCK_SetRootMux(kCLOCK_RootUart4, kCLOCK_UartRootmuxSysPll1Div10);
|
||||
/* Set root clock to 80MHZ/ 1= 80MHZ */
|
||||
CLOCK_SetRootDivider(kCLOCK_RootUart4, 1U, 1U);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
|
||||
CLOCK_EnableClock(kCLOCK_Ocram); /* Enable Ocram clock */
|
||||
|
||||
/* The purpose to enable the following modules clock is to make sure the M7 core could work
|
||||
* normally when A53 core enters the low power status.
|
||||
*/
|
||||
CLOCK_EnableClock(kCLOCK_Sim_m);
|
||||
CLOCK_EnableClock(kCLOCK_Sim_main);
|
||||
CLOCK_EnableClock(kCLOCK_Sim_s);
|
||||
CLOCK_EnableClock(kCLOCK_Sim_wakeup);
|
||||
CLOCK_EnableClock(kCLOCK_Debug);
|
||||
CLOCK_EnableClock(kCLOCK_Dram);
|
||||
CLOCK_EnableClock(kCLOCK_Sec_Debug);
|
||||
}
|
||||
|
||||
static int nxp_mimx8ml8_init(void)
|
||||
{
|
||||
|
||||
/* SoC specific RDC settings */
|
||||
SOC_RdcInit();
|
||||
|
||||
/* SoC specific Clock settings */
|
||||
SOC_ClockInit();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(nxp_mimx8ml8_init, PRE_KERNEL_1, 0);
|
||||
25
soc/nxp/imx/imx8m/m7/soc.h
Normal file
25
soc/nxp/imx/imx8m/m7/soc.h
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Copyright (c) 2021, Laird Connectivity
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _SOC__H_
|
||||
#define _SOC__H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
|
||||
#include <fsl_device_registers.h>
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC__H_ */
|
||||
23
soc/nxp/imx/imx8ulp/CMakeLists.txt
Normal file
23
soc/nxp/imx/imx8ulp/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
# Copyright 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if(CONFIG_SOC_MIMX8ULP_ADSP)
|
||||
zephyr_include_directories(adsp)
|
||||
add_subdirectory(adsp)
|
||||
|
||||
# west sign
|
||||
|
||||
# See detailed comments in soc/intel/intel_adsp/common/CMakeLists.txt
|
||||
add_custom_target(zephyr.ri ALL
|
||||
DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri
|
||||
)
|
||||
|
||||
add_custom_command(
|
||||
OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri
|
||||
COMMENT "west sign --if-tool-available --tool rimage ..."
|
||||
COMMAND west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS}
|
||||
DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}
|
||||
)
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/adsp/linker.ld CACHE INTERNAL "")
|
||||
endif()
|
||||
11
soc/nxp/imx/imx8ulp/Kconfig
Normal file
11
soc/nxp/imx/imx8ulp/Kconfig
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
# Copyright 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_MIMX8ULP_ADSP
|
||||
select XTENSA
|
||||
select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
|
||||
select XTENSA_RESET_VECTOR
|
||||
select XTENSA_USE_CORE_CRT1
|
||||
select ATOMIC_OPERATIONS_BUILTIN
|
||||
select GEN_ISR_TABLES
|
||||
select XTENSA_SMALL_VECTOR_TABLE_ENTRY
|
||||
45
soc/nxp/imx/imx8ulp/Kconfig.defconfig
Normal file
45
soc/nxp/imx/imx8ulp/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
# Copyright 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_IMX8ULP
|
||||
|
||||
if SOC_MIMX8ULP_ADSP
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default 528000000
|
||||
|
||||
config SYS_CLOCK_TICKS_PER_SEC
|
||||
default 50000
|
||||
|
||||
config DCACHE_LINE_SIZE
|
||||
default 128
|
||||
|
||||
config GEN_IRQ_VECTOR_TABLE
|
||||
default n
|
||||
|
||||
config CACHE_MANAGEMENT
|
||||
default y
|
||||
|
||||
config SMP
|
||||
default n
|
||||
|
||||
config XTENSA_TIMER
|
||||
default y
|
||||
|
||||
config KERNEL_ENTRY
|
||||
default "__start"
|
||||
|
||||
config MULTI_LEVEL_INTERRUPTS
|
||||
default n
|
||||
|
||||
config 2ND_LEVEL_INTERRUPTS
|
||||
default n
|
||||
|
||||
# To prevent test uses TEST_LOGGING_MINIMAL
|
||||
config TEST_LOGGING_DEFAULTS
|
||||
default n
|
||||
depends on TEST
|
||||
|
||||
endif # SOC_MIMX8ULP_ADSP
|
||||
|
||||
endif # SOC_SERIES_IMX8ULP
|
||||
26
soc/nxp/imx/imx8ulp/Kconfig.soc
Normal file
26
soc/nxp/imx/imx8ulp/Kconfig.soc
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
# Copyright 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_IMX8ULP
|
||||
bool
|
||||
select SOC_FAMILY_NXP_IMX
|
||||
|
||||
config SOC_SERIES
|
||||
default "imx8ulp" if SOC_SERIES_IMX8ULP
|
||||
|
||||
config SOC_MIMX8ULP
|
||||
bool
|
||||
select SOC_SERIES_IMX8ULP
|
||||
|
||||
config SOC
|
||||
default "imx8ulp" if SOC_MIMX8ULP
|
||||
|
||||
config SOC_MIMX8ULP_ADSP
|
||||
bool
|
||||
select SOC_MIMX8ULP
|
||||
help
|
||||
Enable support for NXP i.MX 8ULP Audio DSP
|
||||
|
||||
config SOC_TOOLCHAIN_NAME
|
||||
string
|
||||
default "nxp_imx8ulp_adsp" if SOC_MIMX8ULP_ADSP
|
||||
6
soc/nxp/imx/imx8ulp/adsp/CMakeLists.txt
Normal file
6
soc/nxp/imx/imx8ulp/adsp/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
# NXP SoC family CMake file
|
||||
#
|
||||
# Copyright (c) 2021, 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_include_directories(include)
|
||||
393
soc/nxp/imx/imx8ulp/adsp/_soc_inthandlers.h
Normal file
393
soc/nxp/imx/imx8ulp/adsp/_soc_inthandlers.h
Normal file
|
|
@ -0,0 +1,393 @@
|
|||
/*
|
||||
* Copyright (c) 2023 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
/*
|
||||
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*
|
||||
* Functions here are designed to produce efficient code to
|
||||
* search an Xtensa bitmask of interrupts, inspecting only those bits
|
||||
* declared to be associated with a given interrupt level. Each
|
||||
* dispatcher will handle exactly one flagged interrupt, in numerical
|
||||
* order (low bits first) and will return a mask of that bit that can
|
||||
* then be cleared by the calling code. Unrecognized bits for the
|
||||
* level will invoke an error handler.
|
||||
*/
|
||||
|
||||
#include <xtensa/config/core-isa.h>
|
||||
#include <zephyr/sys/util.h>
|
||||
#include <zephyr/sw_isr_table.h>
|
||||
|
||||
#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 5
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT21_LEVEL) || XCHAL_INT21_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT22_LEVEL) || XCHAL_INT22_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT23_LEVEL) || XCHAL_INT23_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT24_LEVEL) || XCHAL_INT24_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT25_LEVEL) || XCHAL_INT25_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT26_LEVEL) || XCHAL_INT26_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT27_LEVEL) || XCHAL_INT27_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT28_LEVEL) || XCHAL_INT28_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT29_LEVEL) || XCHAL_INT29_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT30_LEVEL) || XCHAL_INT30_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT31_LEVEL) || XCHAL_INT31_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
|
||||
static inline int _xtensa_handle_one_int5(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (mask & BIT(0)) {
|
||||
mask = BIT(0);
|
||||
irq = 0;
|
||||
goto handle_irq;
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int2(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (mask & 0x70006) {
|
||||
if (mask & 0x6) {
|
||||
if (mask & BIT(1)) {
|
||||
mask = BIT(1);
|
||||
irq = 1;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(2)) {
|
||||
mask = BIT(2);
|
||||
irq = 2;
|
||||
goto handle_irq;
|
||||
}
|
||||
} else {
|
||||
if (mask & BIT(16)) {
|
||||
mask = BIT(16);
|
||||
irq = 16;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(17)) {
|
||||
mask = BIT(17);
|
||||
irq = 17;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(18)) {
|
||||
mask = BIT(18);
|
||||
irq = 18;
|
||||
goto handle_irq;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
if (mask & 0x180000) {
|
||||
if (mask & BIT(19)) {
|
||||
mask = BIT(19);
|
||||
irq = 19;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(20)) {
|
||||
mask = BIT(20);
|
||||
irq = 20;
|
||||
goto handle_irq;
|
||||
}
|
||||
} else {
|
||||
if (mask & BIT(21)) {
|
||||
mask = BIT(21);
|
||||
irq = 21;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(22)) {
|
||||
mask = BIT(22);
|
||||
irq = 22;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(23)) {
|
||||
mask = BIT(23);
|
||||
irq = 23;
|
||||
goto handle_irq;
|
||||
}
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int3(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (mask & 0x3000038) {
|
||||
if (mask & 0x18) {
|
||||
if (mask & BIT(3)) {
|
||||
mask = BIT(3);
|
||||
irq = 3;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(4)) {
|
||||
mask = BIT(4);
|
||||
irq = 4;
|
||||
goto handle_irq;
|
||||
}
|
||||
} else {
|
||||
if (mask & BIT(5)) {
|
||||
mask = BIT(5);
|
||||
irq = 5;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(24)) {
|
||||
mask = BIT(24);
|
||||
irq = 24;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(25)) {
|
||||
mask = BIT(25);
|
||||
irq = 25;
|
||||
goto handle_irq;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
if (mask & 0x1c000000) {
|
||||
if (mask & BIT(26)) {
|
||||
mask = BIT(26);
|
||||
irq = 26;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(27)) {
|
||||
mask = BIT(27);
|
||||
irq = 27;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(28)) {
|
||||
mask = BIT(28);
|
||||
irq = 28;
|
||||
goto handle_irq;
|
||||
}
|
||||
} else {
|
||||
if (mask & BIT(29)) {
|
||||
mask = BIT(29);
|
||||
irq = 29;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(30)) {
|
||||
mask = BIT(30);
|
||||
irq = 30;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(31)) {
|
||||
mask = BIT(31);
|
||||
irq = 31;
|
||||
goto handle_irq;
|
||||
}
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int1(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (mask & 0x7c0) {
|
||||
if (mask & 0xc0) {
|
||||
if (mask & BIT(6)) {
|
||||
mask = BIT(6);
|
||||
irq = 6;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(7)) {
|
||||
mask = BIT(7);
|
||||
irq = 7;
|
||||
goto handle_irq;
|
||||
}
|
||||
} else {
|
||||
if (mask & BIT(8)) {
|
||||
mask = BIT(8);
|
||||
irq = 8;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(9)) {
|
||||
mask = BIT(9);
|
||||
irq = 9;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(10)) {
|
||||
mask = BIT(10);
|
||||
irq = 10;
|
||||
goto handle_irq;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
if (mask & 0x1800) {
|
||||
if (mask & BIT(11)) {
|
||||
mask = BIT(11);
|
||||
irq = 11;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(12)) {
|
||||
mask = BIT(12);
|
||||
irq = 12;
|
||||
goto handle_irq;
|
||||
}
|
||||
} else {
|
||||
if (mask & BIT(13)) {
|
||||
mask = BIT(13);
|
||||
irq = 13;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(14)) {
|
||||
mask = BIT(14);
|
||||
irq = 14;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(15)) {
|
||||
mask = BIT(15);
|
||||
irq = 15;
|
||||
goto handle_irq;
|
||||
}
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int0(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int _xtensa_handle_one_int4(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int _xtensa_handle_one_int6(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int _xtensa_handle_one_int7(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int _xtensa_handle_one_int8(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int _xtensa_handle_one_int9(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int _xtensa_handle_one_int10(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int _xtensa_handle_one_int11(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int _xtensa_handle_one_int12(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int _xtensa_handle_one_int13(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int _xtensa_handle_one_int14(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int _xtensa_handle_one_int15(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
12
soc/nxp/imx/imx8ulp/adsp/include/adsp/cache.h
Normal file
12
soc/nxp/imx/imx8ulp/adsp/include/adsp/cache.h
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __COMMON_ADSP_CACHE_H__
|
||||
#define __COMMON_ADSP_CACHE_H__
|
||||
|
||||
#include <xtensa/hal.h>
|
||||
|
||||
#endif
|
||||
41
soc/nxp/imx/imx8ulp/adsp/include/adsp/io.h
Normal file
41
soc/nxp/imx/imx8ulp/adsp/include/adsp/io.h
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* Copyright (c) 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __INCLUDE_IO__
|
||||
#define __INCLUDE_IO__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <soc/memory.h>
|
||||
#include <zephyr/sys/sys_io.h>
|
||||
#include <zephyr/arch/common/sys_io.h>
|
||||
|
||||
static inline uint32_t io_reg_read(uint32_t reg)
|
||||
{
|
||||
return sys_read32(reg);
|
||||
}
|
||||
|
||||
static inline void io_reg_write(uint32_t reg, uint32_t val)
|
||||
{
|
||||
sys_write32(val, reg);
|
||||
}
|
||||
|
||||
static inline void io_reg_update_bits(uint32_t reg, uint32_t mask,
|
||||
uint32_t value)
|
||||
{
|
||||
io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask));
|
||||
}
|
||||
|
||||
static inline uint16_t io_reg_read16(uint32_t reg)
|
||||
{
|
||||
return sys_read16(reg);
|
||||
}
|
||||
|
||||
static inline void io_reg_write16(uint32_t reg, uint16_t val)
|
||||
{
|
||||
sys_write16(val, reg);
|
||||
}
|
||||
|
||||
#endif
|
||||
33
soc/nxp/imx/imx8ulp/adsp/include/soc.h
Normal file
33
soc/nxp/imx/imx8ulp/adsp/include/soc.h
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* Copyright (c) 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <zephyr/sys/sys_io.h>
|
||||
|
||||
#include <adsp/cache.h>
|
||||
|
||||
#ifndef __INC_IMX_SOC_H
|
||||
#define __INC_IMX_SOC_H
|
||||
|
||||
/* Macros related to interrupt handling */
|
||||
#define XTENSA_IRQ_NUM_SHIFT 0
|
||||
#define XTENSA_IRQ_NUM_MASK 0xff
|
||||
|
||||
/*
|
||||
* IRQs are mapped on levels. 2nd, 3rd and 4th level are left as 0x00.
|
||||
*
|
||||
* 1. Peripheral Register bit offset.
|
||||
*/
|
||||
#define XTENSA_IRQ_NUMBER(_irq) \
|
||||
((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK)
|
||||
|
||||
extern void z_soc_irq_enable(uint32_t irq);
|
||||
extern void z_soc_irq_disable(uint32_t irq);
|
||||
extern int z_soc_irq_is_enabled(unsigned int irq);
|
||||
|
||||
#endif /* __INC_IMX_SOC_H */
|
||||
517
soc/nxp/imx/imx8ulp/adsp/linker.ld
Normal file
517
soc/nxp/imx/imx8ulp/adsp/linker.ld
Normal file
|
|
@ -0,0 +1,517 @@
|
|||
/*
|
||||
* Copyright (c) 2023 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Linker command/script file
|
||||
*
|
||||
* Linker script for the NXP i.MX8ULP platform
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(xtensa)
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <xtensa/config/core-isa.h>
|
||||
#include <memory.h>
|
||||
#include <zephyr/linker/sections.h>
|
||||
|
||||
#include <zephyr/linker/linker-defs.h>
|
||||
#include <zephyr/linker/linker-tool.h>
|
||||
|
||||
PROVIDE(__memctl_default = 0x00000000);
|
||||
PROVIDE(_MemErrorHandler = 0x00000000);
|
||||
|
||||
#define RAMABLE_REGION sdram0 :sdram0_phdr
|
||||
#define ROMABLE_REGION sdram0 :sdram0_phdr
|
||||
|
||||
MEMORY
|
||||
{
|
||||
vector_reset_text :
|
||||
org = XCHAL_RESET_VECTOR0_PADDR_IRAM,
|
||||
len = MEM_RESET_TEXT_SIZE
|
||||
vector_reset_lit :
|
||||
org = XCHAL_RESET_VECTOR0_PADDR_IRAM + MEM_RESET_TEXT_SIZE,
|
||||
len = MEM_RESET_LIT_SIZE
|
||||
vector_base_text :
|
||||
org = XCHAL_VECBASE_RESET_PADDR_IRAM,
|
||||
len = MEM_VECBASE_LIT_SIZE
|
||||
vector_int2_lit :
|
||||
org = XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_int2_text :
|
||||
org = XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_int3_lit :
|
||||
org = XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_int3_text :
|
||||
org = XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_int4_lit :
|
||||
org = XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_int4_text :
|
||||
org = XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_int5_lit :
|
||||
org = XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_int5_text :
|
||||
org = XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_kernel_lit :
|
||||
org = XCHAL_KERNEL_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_kernel_text :
|
||||
org = XCHAL_KERNEL_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_user_lit :
|
||||
org = XCHAL_USER_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_user_text :
|
||||
org = XCHAL_USER_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_double_lit :
|
||||
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_double_text :
|
||||
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
iram_text_start :
|
||||
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE,
|
||||
len = (IRAM_BASE + IRAM_SIZE) - (XCHAL_DOUBLEEXC_VECTOR_PADDR + MEM_VECT_TEXT_SIZE)
|
||||
sdram0 :
|
||||
org = SDRAM0_BASE,
|
||||
len = SDRAM0_SIZE
|
||||
sdram1 :
|
||||
org = SDRAM1_BASE + SOF_MAILBOX_SIZE,
|
||||
len = SDRAM1_SIZE - SOF_MAILBOX_SIZE
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
IDT_LIST :
|
||||
org = IDT_BASE,
|
||||
len = IDT_SIZE
|
||||
#endif
|
||||
|
||||
static_uuid_entries_seg (!ari) :
|
||||
org = UUID_ENTRY_ELF_BASE,
|
||||
len = UUID_ENTRY_ELF_SIZE
|
||||
static_log_entries_seg (!ari) :
|
||||
org = LOG_ENTRY_ELF_BASE,
|
||||
len = LOG_ENTRY_ELF_SIZE
|
||||
fw_metadata_seg (!ari) :
|
||||
org = EXT_MANIFEST_ELF_BASE,
|
||||
len = EXT_MANIFEST_ELF_SIZE
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
vector_reset_text_phdr PT_LOAD;
|
||||
vector_reset_lit_phdr PT_LOAD;
|
||||
vector_base_text_phdr PT_LOAD;
|
||||
vector_base_lit_phdr PT_LOAD;
|
||||
vector_int2_text_phdr PT_LOAD;
|
||||
vector_int2_lit_phdr PT_LOAD;
|
||||
vector_int3_text_phdr PT_LOAD;
|
||||
vector_int3_lit_phdr PT_LOAD;
|
||||
vector_int4_text_phdr PT_LOAD;
|
||||
vector_int4_lit_phdr PT_LOAD;
|
||||
vector_int5_text_phdr PT_LOAD;
|
||||
vector_int5_lit_phdr PT_LOAD;
|
||||
vector_kernel_text_phdr PT_LOAD;
|
||||
vector_kernel_lit_phdr PT_LOAD;
|
||||
vector_user_text_phdr PT_LOAD;
|
||||
vector_user_lit_phdr PT_LOAD;
|
||||
vector_double_text_phdr PT_LOAD;
|
||||
vector_double_lit_phdr PT_LOAD;
|
||||
iram_text_start_phdr PT_LOAD;
|
||||
sdram0_phdr PT_LOAD;
|
||||
sdram1_phdr PT_LOAD;
|
||||
static_uuid_entries_phdr PT_NOTE;
|
||||
static_log_entries_phdr PT_NOTE;
|
||||
metadata_entries_phdr PT_NOTE;
|
||||
}
|
||||
|
||||
_rom_store_table = 0;
|
||||
|
||||
PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR);
|
||||
|
||||
ENTRY(CONFIG_KERNEL_ENTRY)
|
||||
|
||||
/* Various memory-map dependent cache attribute settings: */
|
||||
_memmap_cacheattr_wb_base = 0x44024000;
|
||||
_memmap_cacheattr_wt_base = 0x11021000;
|
||||
_memmap_cacheattr_bp_base = 0x22022000;
|
||||
_memmap_cacheattr_unused_mask = 0x00F00FFF;
|
||||
_memmap_cacheattr_wb_trapnull = 0x4422422F;
|
||||
_memmap_cacheattr_wba_trapnull = 0x4422422F;
|
||||
_memmap_cacheattr_wbna_trapnull = 0x25222222;
|
||||
_memmap_cacheattr_wt_trapnull = 0x1122122F;
|
||||
_memmap_cacheattr_bp_trapnull = 0x2222222F;
|
||||
_memmap_cacheattr_wb_strict = 0x44F24FFF;
|
||||
_memmap_cacheattr_wt_strict = 0x11F21FFF;
|
||||
_memmap_cacheattr_bp_strict = 0x22F22FFF;
|
||||
_memmap_cacheattr_wb_allvalid = 0x44224222;
|
||||
_memmap_cacheattr_wt_allvalid = 0x11221222;
|
||||
_memmap_cacheattr_bp_allvalid = 0x22222222;
|
||||
/*
|
||||
* Every 512M in 4GB space has dedicate cache attribute.
|
||||
* 1: write through
|
||||
* 2: cache bypass
|
||||
* 4: write back
|
||||
* F: invalid access
|
||||
*/
|
||||
_memmap_cacheattr_imx8_wt_allvalid = 0x222222221;
|
||||
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_imx8_wt_allvalid);
|
||||
|
||||
_EXT_MAN_ALIGN_ = 16;
|
||||
EXTERN(ext_man_fw_ver)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
#include <zephyr/linker/rel-sections.ld>
|
||||
.ResetVector.text : ALIGN(4)
|
||||
{
|
||||
_ResetVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.ResetVector.text))
|
||||
_ResetVector_text_end = ABSOLUTE(.);
|
||||
} >vector_reset_text :vector_reset_text_phdr
|
||||
|
||||
.ResetVector.literal : ALIGN(4)
|
||||
{
|
||||
_ResetVector_literal_start = ABSOLUTE(.);
|
||||
*(.ResetVector.literal)
|
||||
_ResetVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_reset_lit :vector_reset_lit_phdr
|
||||
|
||||
.WindowVectors.text : ALIGN(4)
|
||||
{
|
||||
_WindowVectors_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.WindowVectors.text))
|
||||
_WindowVectors_text_end = ABSOLUTE(.);
|
||||
} >vector_base_text :vector_base_text_phdr
|
||||
|
||||
.Level2InterruptVector.literal : ALIGN(4)
|
||||
{
|
||||
_Level2InterruptVector_literal_start = ABSOLUTE(.);
|
||||
*(.Level2InterruptVector.literal)
|
||||
_Level2InterruptVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_int2_lit :vector_int2_lit_phdr
|
||||
|
||||
.Level2InterruptVector.text : ALIGN(4)
|
||||
{
|
||||
_Level2InterruptVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.Level2InterruptVector.text))
|
||||
_Level2InterruptVector_text_end = ABSOLUTE(.);
|
||||
} >vector_int2_text :vector_int2_text_phdr
|
||||
|
||||
.Level3InterruptVector.literal : ALIGN(4)
|
||||
{
|
||||
_Level3InterruptVector_literal_start = ABSOLUTE(.);
|
||||
*(.Level3InterruptVector.literal)
|
||||
_Level3InterruptVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_int3_lit :vector_int3_lit_phdr
|
||||
|
||||
.Level3InterruptVector.text : ALIGN(4)
|
||||
{
|
||||
_Level3InterruptVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.Level3InterruptVector.text))
|
||||
_Level3InterruptVector_text_end = ABSOLUTE(.);
|
||||
} >vector_int3_text :vector_int3_text_phdr
|
||||
|
||||
.DebugExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_DebugExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.DebugExceptionVector.literal)
|
||||
_DebugExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_int4_lit :vector_int4_lit_phdr
|
||||
|
||||
.DebugExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_DebugExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.DebugExceptionVector.text))
|
||||
_DebugExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_int4_text :vector_int4_text_phdr
|
||||
|
||||
.NMIExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_NMIExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.NMIExceptionVector.literal)
|
||||
_NMIExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_int5_lit :vector_int5_lit_phdr
|
||||
|
||||
.NMIExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_NMIExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.NMIExceptionVector.text))
|
||||
_NMIExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_int5_text :vector_int5_text_phdr
|
||||
|
||||
.KernelExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_KernelExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.KernelExceptionVector.literal)
|
||||
_KernelExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_kernel_lit :vector_kernel_lit_phdr
|
||||
|
||||
.KernelExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_KernelExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.KernelExceptionVector.text))
|
||||
_KernelExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_kernel_text :vector_kernel_text_phdr
|
||||
|
||||
.UserExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_UserExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.UserExceptionVector.literal)
|
||||
_UserExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_user_lit :vector_user_lit_phdr
|
||||
|
||||
.UserExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_UserExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.UserExceptionVector.text))
|
||||
_UserExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_user_text :vector_user_text_phdr
|
||||
|
||||
.DoubleExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_DoubleExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.DoubleExceptionVector.literal)
|
||||
_DoubleExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_double_lit :vector_double_lit_phdr
|
||||
|
||||
.DoubleExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_DoubleExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.DoubleExceptionVector.text))
|
||||
_DoubleExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_double_text :vector_double_text_phdr
|
||||
|
||||
.iram.text : ALIGN(4)
|
||||
{
|
||||
_stext = .;
|
||||
_iram_text_start = ABSOLUTE(.);
|
||||
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
|
||||
_iram_text_end = ABSOLUTE(.);
|
||||
} >iram_text_start :iram_text_start_phdr
|
||||
|
||||
.rodata : ALIGN(4)
|
||||
{
|
||||
__rodata_region_start = ABSOLUTE(.);
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
|
||||
KEEP (*(.xt_except_table))
|
||||
KEEP (*(.gcc_except_table .gcc_except_table.*))
|
||||
*(.gnu.linkonce.e.*)
|
||||
*(.gnu.version_r)
|
||||
KEEP (*(.eh_frame))
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc)
|
||||
*(.gnu.linkonce.h.*)
|
||||
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc_end)
|
||||
*(.dynamic)
|
||||
*(.gnu.version_d)
|
||||
. = ALIGN(4);
|
||||
_bss_table_start = ABSOLUTE(.);
|
||||
LONG(_bss_start)
|
||||
LONG(_bss_end)
|
||||
_bss_table_end = ABSOLUTE(.);
|
||||
__rodata_region_end = ABSOLUTE(.);
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
.module_init : ALIGN(4)
|
||||
{
|
||||
_module_init_start = ABSOLUTE(.);
|
||||
*(*.initcall)
|
||||
_module_init_end = ABSOLUTE(.);
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
.text : ALIGN(4)
|
||||
{
|
||||
_stext = .;
|
||||
_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.ResetVector.text))
|
||||
*(.ResetVector.literal)
|
||||
*(.entry.text)
|
||||
*(.init.literal)
|
||||
KEEP(*(.init))
|
||||
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||||
*(.fini.literal)
|
||||
KEEP(*(.fini))
|
||||
*(.gnu.version)
|
||||
_text_end = ABSOLUTE(.);
|
||||
_etext = .;
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
#include <zephyr/linker/common-rom.ld>
|
||||
|
||||
.fw_ready : ALIGN(4)
|
||||
{
|
||||
KEEP(*(".fw_ready"));
|
||||
KEEP (*(.fw_ready_metadata))
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
.noinit : ALIGN(4)
|
||||
{
|
||||
*(.noinit)
|
||||
*(.noinit.*)
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
.data : ALIGN(4)
|
||||
{
|
||||
__data_start = ABSOLUTE(.);
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
KEEP(*(.gnu.linkonce.d.*personality*))
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
KEEP(*(.jcr))
|
||||
_trace_ctx_start = ABSOLUTE(.);
|
||||
*(.trace_ctx)
|
||||
_trace_ctx_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
*(.gna_model)
|
||||
__data_end = ABSOLUTE(.);
|
||||
. = ALIGN(4096);
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
.lit4 : ALIGN(4)
|
||||
{
|
||||
_lit4_start = ABSOLUTE(.);
|
||||
*(*.lit4)
|
||||
*(.lit4.*)
|
||||
*(.gnu.linkonce.lit4.*)
|
||||
_lit4_end = ABSOLUTE(.);
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
#include <zephyr/linker/common-ram.ld>
|
||||
|
||||
.bss (NOLOAD) : ALIGN(8)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_bss_start = ABSOLUTE(.);
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN (8);
|
||||
_bss_end = ABSOLUTE(.);
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
.heap_mem (NOLOAD) : ALIGN(8)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_heap_mem_start = ABSOLUTE(.);
|
||||
*(*.heap_mem)
|
||||
_heap_mem_end = ABSOLUTE(.);
|
||||
} >sdram1 :sdram1_phdr
|
||||
|
||||
/* stack */
|
||||
_end = ALIGN (8);
|
||||
PROVIDE(end = ALIGN (8));
|
||||
|
||||
__stack = SDRAM1_BASE + SDRAM1_SIZE;
|
||||
.comment 0 : { *(.comment) }
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
.debug_ranges 0 : { *(.debug_ranges) }
|
||||
.xtensa.info 0 : { *(.xtensa.info) }
|
||||
.xt.insn 0 :
|
||||
{
|
||||
KEEP (*(.xt.insn))
|
||||
KEEP (*(.gnu.linkonce.x.*))
|
||||
}
|
||||
.xt.prop 0 :
|
||||
{
|
||||
KEEP (*(.xt.prop))
|
||||
KEEP (*(.xt.prop.*))
|
||||
KEEP (*(.gnu.linkonce.prop.*))
|
||||
}
|
||||
.xt.lit 0 :
|
||||
{
|
||||
KEEP (*(.xt.lit))
|
||||
KEEP (*(.xt.lit.*))
|
||||
KEEP (*(.gnu.linkonce.p.*))
|
||||
}
|
||||
.xt.profile_range 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_range))
|
||||
KEEP (*(.gnu.linkonce.profile_range.*))
|
||||
}
|
||||
.xt.profile_ranges 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_ranges))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
|
||||
}
|
||||
.xt.profile_files 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_files))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_files.*))
|
||||
}
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
#include <zephyr/linker/intlist.ld>
|
||||
#endif
|
||||
|
||||
.static_uuid_entries (COPY) : ALIGN(1024)
|
||||
{
|
||||
*(*.static_uuids)
|
||||
} > static_uuid_entries_seg :static_uuid_entries_phdr
|
||||
|
||||
.static_log_entries (COPY) : ALIGN(1024)
|
||||
{
|
||||
*(*.static_log*)
|
||||
} > static_log_entries_seg :static_log_entries_phdr
|
||||
|
||||
.fw_metadata (COPY) : ALIGN(1024)
|
||||
{
|
||||
KEEP (*(.fw_metadata))
|
||||
. = ALIGN(_EXT_MAN_ALIGN_);
|
||||
} >fw_metadata_seg :metadata_entries_phdr
|
||||
}
|
||||
159
soc/nxp/imx/imx8ulp/adsp/memory.h
Normal file
159
soc/nxp/imx/imx8ulp/adsp/memory.h
Normal file
|
|
@ -0,0 +1,159 @@
|
|||
/*
|
||||
* Copyright (c) 2023 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef ZEPHYR_SOC_NXP_ADSP_MEMORY_H_
|
||||
#define ZEPHYR_SOC_NXP_ADSP_MEMORY_H_
|
||||
|
||||
#define IRAM_RESERVE_HEADER_SPACE 0x400
|
||||
|
||||
#define IRAM_BASE 0x21170000
|
||||
#define IRAM_SIZE 0x10000
|
||||
|
||||
#define SDRAM0_BASE 0x1a000000
|
||||
#define SDRAM0_SIZE 0x800000
|
||||
|
||||
#define SDRAM1_BASE 0x1a800000
|
||||
#define SDRAM1_SIZE 0x800000
|
||||
|
||||
/* The reset vector address in SRAM and its size */
|
||||
#define MEM_RESET_TEXT_SIZE 0x2e0
|
||||
#define MEM_RESET_LIT_SIZE 0x120
|
||||
|
||||
/* This is the base address of all the vectors defined in IRAM */
|
||||
#define XCHAL_VECBASE_RESET_PADDR_IRAM \
|
||||
(IRAM_BASE + IRAM_RESERVE_HEADER_SPACE)
|
||||
|
||||
#define MEM_VECBASE_LIT_SIZE 0x178
|
||||
|
||||
/*
|
||||
* EXCEPTIONS and VECTORS
|
||||
*/
|
||||
#define XCHAL_RESET_VECTOR0_PADDR_IRAM 0x21170000
|
||||
|
||||
/* Vector and literal sizes */
|
||||
#define MEM_VECT_LIT_SIZE 0x4
|
||||
#define MEM_VECT_TEXT_SIZE 0x1C
|
||||
#define MEM_VECT_SIZE (MEM_VECT_TEXT_SIZE +\
|
||||
MEM_VECT_LIT_SIZE)
|
||||
|
||||
/* The addresses of the vectors.
|
||||
* Only the mem_error vector continues to point to its ROM address.
|
||||
*/
|
||||
#define XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x17C)
|
||||
|
||||
#define XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x19C)
|
||||
|
||||
#define XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1BC)
|
||||
|
||||
#define XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1DC)
|
||||
|
||||
#define XCHAL_KERNEL_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1FC)
|
||||
|
||||
#define XCHAL_USER_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x21C)
|
||||
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x23C)
|
||||
|
||||
/* Location for the intList section which is later used to construct the
|
||||
* Interrupt Descriptor Table (IDT). This is a bogus address as this
|
||||
* section will be stripped off in the final image.
|
||||
*/
|
||||
#define IDT_BASE (IRAM_BASE + IRAM_SIZE)
|
||||
|
||||
/* size of the Interrupt Descriptor Table (IDT) */
|
||||
#define IDT_SIZE 0x2000
|
||||
|
||||
/* physical DSP addresses */
|
||||
#define IRAM_BASE 0x21170000
|
||||
#define IRAM_SIZE 0x10000
|
||||
|
||||
#define DRAM0_BASE 0x21180000
|
||||
#define DRAM0_SIZE 0x10000
|
||||
|
||||
#define SDRAM0_BASE 0x1a000000
|
||||
#define SDRAM0_SIZE 0x800000
|
||||
|
||||
#define SDRAM1_BASE 0x1a800000
|
||||
#define SDRAM1_SIZE 0x800000
|
||||
|
||||
#define XSHAL_MU13_SIDEB_BYPASS_PADDR 0x2DA20000
|
||||
#define MU_BASE XSHAL_MU13_SIDEB_BYPASS_PADDR
|
||||
|
||||
#define EDMA2_BASE 0x2D810000
|
||||
#define EDMA2_SIZE 0x10000
|
||||
|
||||
#define SAI_5_BASE 0x29890000
|
||||
#define SAI_5_SIZE 0x00010000
|
||||
#define SAI_6_BASE 0x2DA90000
|
||||
#define SAI_6_SIZE 0x00010000
|
||||
#define SAI_7_BASE 0x2DAA0000
|
||||
#define SAI_7_SIZE 0x00010000
|
||||
|
||||
#define UUID_ENTRY_ELF_BASE 0x1FFFA000
|
||||
#define UUID_ENTRY_ELF_SIZE 0x6000
|
||||
|
||||
#define LOG_ENTRY_ELF_BASE 0x20000000
|
||||
#define LOG_ENTRY_ELF_SIZE 0x2000000
|
||||
|
||||
#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
|
||||
#define EXT_MANIFEST_ELF_SIZE 0x2000000
|
||||
|
||||
/*
|
||||
* The Heap and Stack on i.MX8 are organized like this :-
|
||||
*
|
||||
* +--------------------------------------------------------------------------+
|
||||
* | Offset | Region | Size |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | SDRAM_BASE | RO Data | SOF_DATA_SIZE |
|
||||
* | | Data | |
|
||||
* | | BSS | |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | HEAP_SYSTEM_BASE | System Heap | HEAP_SYSTEM_SIZE |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | HEAP_RUNTIME_BASE | Runtime Heap | HEAP_RUNTIME_SIZE |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | HEAP_BUFFER_BASE | Module Buffers | HEAP_BUFFER_SIZE |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | SOF_STACK_END | Stack | SOF_STACK_SIZE |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | SOF_STACK_BASE | | |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
*/
|
||||
|
||||
#define SRAM_OUTBOX_BASE SDRAM1_BASE
|
||||
#define SRAM_OUTBOX_SIZE 0x1000
|
||||
#define SRAM_OUTBOX_OFFSET 0
|
||||
|
||||
#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE)
|
||||
#define SRAM_INBOX_SIZE 0x1000
|
||||
#define SRAM_INBOX_OFFSET SRAM_OUTBOX_SIZE
|
||||
|
||||
#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
|
||||
#define SRAM_DEBUG_SIZE 0x2800
|
||||
#define SRAM_DEBUG_OFFSET (SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE)
|
||||
|
||||
#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
|
||||
#define SRAM_EXCEPT_SIZE 0x800
|
||||
#define SRAM_EXCEPT_OFFSET (SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE)
|
||||
|
||||
#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
|
||||
#define SRAM_STREAM_SIZE 0x1000
|
||||
#define SRAM_STREAM_OFFSET (SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE)
|
||||
|
||||
#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
|
||||
#define SRAM_TRACE_SIZE 0x1000
|
||||
#define SRAM_TRACE_OFFSET (SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE)
|
||||
|
||||
#define SOF_MAILBOX_SIZE (SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE \
|
||||
+ SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE \
|
||||
+ SRAM_STREAM_SIZE + SRAM_TRACE_SIZE)
|
||||
|
||||
#endif /* ZEPHYR_SOC_NXP_ADSP_MEMORY_H_ */
|
||||
27
soc/nxp/imx/imx8x/CMakeLists.txt
Normal file
27
soc/nxp/imx/imx8x/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
# Copyright 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if(CONFIG_SOC_MIMX8QXP_ADSP)
|
||||
zephyr_include_directories(adsp)
|
||||
add_subdirectory(adsp)
|
||||
|
||||
zephyr_sources(
|
||||
adsp/pinctrl_soc.h
|
||||
)
|
||||
|
||||
# west sign
|
||||
|
||||
# See detailed comments in soc/intel/intel_adsp/common/CMakeLists.txt
|
||||
add_custom_target(zephyr.ri ALL
|
||||
DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri
|
||||
)
|
||||
|
||||
add_custom_command(
|
||||
OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri
|
||||
COMMENT "west sign --if-tool-available --tool rimage ..."
|
||||
COMMAND west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS}
|
||||
DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}
|
||||
)
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/adsp/linker.ld CACHE INTERNAL "")
|
||||
endif()
|
||||
15
soc/nxp/imx/imx8x/Kconfig
Normal file
15
soc/nxp/imx/imx8x/Kconfig
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
# Copyright 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_MIMX8QXP_ADSP
|
||||
select XTENSA
|
||||
select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
|
||||
select XTENSA_RESET_VECTOR
|
||||
select XTENSA_USE_CORE_CRT1
|
||||
select ATOMIC_OPERATIONS_BUILTIN
|
||||
select GEN_ISR_TABLES
|
||||
select XTENSA_SMALL_VECTOR_TABLE_ENTRY
|
||||
select HAS_MCUX
|
||||
|
||||
config MCUX_CORE_SUFFIX
|
||||
default "_dsp" if SOC_MIMX8QXP_ADSP
|
||||
45
soc/nxp/imx/imx8x/Kconfig.defconfig
Normal file
45
soc/nxp/imx/imx8x/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
# Copyright 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_IMX8X
|
||||
|
||||
if SOC_MIMX8QXP_ADSP
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default 640000000
|
||||
|
||||
config SYS_CLOCK_TICKS_PER_SEC
|
||||
default 50000
|
||||
|
||||
config DCACHE_LINE_SIZE
|
||||
default 128
|
||||
|
||||
config GEN_IRQ_VECTOR_TABLE
|
||||
default n
|
||||
|
||||
config CACHE_MANAGEMENT
|
||||
default y
|
||||
|
||||
config SMP
|
||||
default n
|
||||
|
||||
config XTENSA_TIMER
|
||||
default y
|
||||
|
||||
config KERNEL_ENTRY
|
||||
default "__start"
|
||||
|
||||
config MULTI_LEVEL_INTERRUPTS
|
||||
default n
|
||||
|
||||
config 2ND_LEVEL_INTERRUPTS
|
||||
default n
|
||||
|
||||
# To prevent test uses TEST_LOGGING_MINIMAL
|
||||
config TEST_LOGGING_DEFAULTS
|
||||
default n
|
||||
depends on TEST
|
||||
|
||||
endif # SOC_MIMX8QXP_ADSP
|
||||
|
||||
endif # SOC_SERIES_IMX8X
|
||||
36
soc/nxp/imx/imx8x/Kconfig.soc
Normal file
36
soc/nxp/imx/imx8x/Kconfig.soc
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
# Copyright 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_IMX8X
|
||||
bool
|
||||
select SOC_FAMILY_NXP_IMX
|
||||
|
||||
config SOC_SERIES
|
||||
default "imx8x" if SOC_SERIES_IMX8X
|
||||
|
||||
config SOC_MIMX8QXP
|
||||
bool
|
||||
select SOC_SERIES_IMX8X
|
||||
|
||||
config SOC
|
||||
default "mimx8qx6" if SOC_MIMX8QXP
|
||||
|
||||
config SOC_MIMX8QXP_ADSP
|
||||
bool
|
||||
select SOC_MIMX8QXP
|
||||
help
|
||||
Enable support for NXP i.MX 8QXP Audio DSP
|
||||
|
||||
config SOC_TOOLCHAIN_NAME
|
||||
string
|
||||
default "nxp_imx_adsp" if SOC_MIMX8QXP_ADSP
|
||||
|
||||
config SOC_PART_NUMBER_MIMX8QX6AVLFZ
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MIMX8QX6CVLDZ
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER
|
||||
default "MIMX8QX6AVLFZ" if SOC_PART_NUMBER_MIMX8QX6AVLFZ
|
||||
default "MIMX8QX6CVLDZ" if SOC_PART_NUMBER_MIMX8QX6CVLDZ
|
||||
6
soc/nxp/imx/imx8x/adsp/CMakeLists.txt
Normal file
6
soc/nxp/imx/imx8x/adsp/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
# NXP SoC family CMake file
|
||||
#
|
||||
# Copyright (c) 2021, 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_include_directories(include)
|
||||
177
soc/nxp/imx/imx8x/adsp/_soc_inthandlers.h
Normal file
177
soc/nxp/imx/imx8x/adsp/_soc_inthandlers.h
Normal file
|
|
@ -0,0 +1,177 @@
|
|||
/*
|
||||
* Copyright (c) 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
/*
|
||||
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*
|
||||
* Functions here are designed to produce efficient code to
|
||||
* search an Xtensa bitmask of interrupts, inspecting only those bits
|
||||
* declared to be associated with a given interrupt level. Each
|
||||
* dispatcher will handle exactly one flagged interrupt, in numerical
|
||||
* order (low bits first) and will return a mask of that bit that can
|
||||
* then be cleared by the calling code. Unrecognized bits for the
|
||||
* level will invoke an error handler.
|
||||
*/
|
||||
|
||||
#include <xtensa/config/core-isa.h>
|
||||
#include <zephyr/sys/util.h>
|
||||
#include <zephyr/sw_isr_table.h>
|
||||
|
||||
#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 5
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
|
||||
static inline int _xtensa_handle_one_int1(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (mask & BIT(8)) {
|
||||
mask = BIT(8);
|
||||
irq = 8;
|
||||
goto handle_irq;
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int2(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
int i = 0;
|
||||
|
||||
mask &= XCHAL_INTLEVEL2_MASK;
|
||||
for (i = 0; i <= 31; i++)
|
||||
if (mask & BIT(i)) {
|
||||
mask = BIT(i);
|
||||
irq = i;
|
||||
goto handle_irq;
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int3(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (mask & BIT(1)) {
|
||||
mask = BIT(1);
|
||||
irq = 1;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(3)) {
|
||||
mask = BIT(3);
|
||||
irq = 3;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(31)) {
|
||||
mask = BIT(31);
|
||||
irq = 31;
|
||||
goto handle_irq;
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int5(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (mask & BIT(0)) {
|
||||
mask = BIT(0);
|
||||
irq = 0;
|
||||
goto handle_irq;
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int0(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int4(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int6(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int7(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
12
soc/nxp/imx/imx8x/adsp/include/adsp/cache.h
Normal file
12
soc/nxp/imx/imx8x/adsp/include/adsp/cache.h
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __COMMON_ADSP_CACHE_H__
|
||||
#define __COMMON_ADSP_CACHE_H__
|
||||
|
||||
#include <xtensa/hal.h>
|
||||
|
||||
#endif
|
||||
41
soc/nxp/imx/imx8x/adsp/include/adsp/io.h
Normal file
41
soc/nxp/imx/imx8x/adsp/include/adsp/io.h
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* Copyright (c) 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __INCLUDE_IO__
|
||||
#define __INCLUDE_IO__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <soc/memory.h>
|
||||
#include <zephyr/sys/sys_io.h>
|
||||
#include <zephyr/arch/common/sys_io.h>
|
||||
|
||||
static inline uint32_t io_reg_read(uint32_t reg)
|
||||
{
|
||||
return sys_read32(reg);
|
||||
}
|
||||
|
||||
static inline void io_reg_write(uint32_t reg, uint32_t val)
|
||||
{
|
||||
sys_write32(val, reg);
|
||||
}
|
||||
|
||||
static inline void io_reg_update_bits(uint32_t reg, uint32_t mask,
|
||||
uint32_t value)
|
||||
{
|
||||
io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask));
|
||||
}
|
||||
|
||||
static inline uint16_t io_reg_read16(uint32_t reg)
|
||||
{
|
||||
return sys_read16(reg);
|
||||
}
|
||||
|
||||
static inline void io_reg_write16(uint32_t reg, uint16_t val)
|
||||
{
|
||||
sys_write16(val, reg);
|
||||
}
|
||||
|
||||
#endif
|
||||
33
soc/nxp/imx/imx8x/adsp/include/soc.h
Normal file
33
soc/nxp/imx/imx8x/adsp/include/soc.h
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* Copyright (c) 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <zephyr/sys/sys_io.h>
|
||||
|
||||
#include <adsp/cache.h>
|
||||
|
||||
#ifndef __INC_IMX_SOC_H
|
||||
#define __INC_IMX_SOC_H
|
||||
|
||||
/* Macros related to interrupt handling */
|
||||
#define XTENSA_IRQ_NUM_SHIFT 0
|
||||
#define XTENSA_IRQ_NUM_MASK 0xff
|
||||
|
||||
/*
|
||||
* IRQs are mapped on levels. 2nd, 3rd and 4th level are left as 0x00.
|
||||
*
|
||||
* 1. Peripheral Register bit offset.
|
||||
*/
|
||||
#define XTENSA_IRQ_NUMBER(_irq) \
|
||||
((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK)
|
||||
|
||||
extern void z_soc_irq_enable(uint32_t irq);
|
||||
extern void z_soc_irq_disable(uint32_t irq);
|
||||
extern int z_soc_irq_is_enabled(unsigned int irq);
|
||||
|
||||
#endif /* __INC_IMX_SOC_H */
|
||||
517
soc/nxp/imx/imx8x/adsp/linker.ld
Normal file
517
soc/nxp/imx/imx8x/adsp/linker.ld
Normal file
|
|
@ -0,0 +1,517 @@
|
|||
/*
|
||||
* Copyright (c) 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Linker command/script file
|
||||
*
|
||||
* Linker script for the NXP i.MX8 platform
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(xtensa)
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <xtensa/config/core-isa.h>
|
||||
#include <memory.h>
|
||||
#include <zephyr/linker/sections.h>
|
||||
|
||||
#include <zephyr/linker/linker-defs.h>
|
||||
#include <zephyr/linker/linker-tool.h>
|
||||
|
||||
PROVIDE(__memctl_default = 0x00000000);
|
||||
PROVIDE(_MemErrorHandler = 0x00000000);
|
||||
|
||||
#define RAMABLE_REGION sdram0 :sdram0_phdr
|
||||
#define ROMABLE_REGION sdram0 :sdram0_phdr
|
||||
|
||||
MEMORY
|
||||
{
|
||||
vector_reset_text :
|
||||
org = XCHAL_RESET_VECTOR0_PADDR_IRAM,
|
||||
len = MEM_RESET_TEXT_SIZE
|
||||
vector_reset_lit :
|
||||
org = XCHAL_RESET_VECTOR0_PADDR_IRAM + MEM_RESET_TEXT_SIZE,
|
||||
len = MEM_RESET_LIT_SIZE
|
||||
vector_base_text :
|
||||
org = XCHAL_VECBASE_RESET_PADDR_IRAM,
|
||||
len = MEM_VECBASE_LIT_SIZE
|
||||
vector_int2_lit :
|
||||
org = XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_int2_text :
|
||||
org = XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_int3_lit :
|
||||
org = XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_int3_text :
|
||||
org = XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_int4_lit :
|
||||
org = XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_int4_text :
|
||||
org = XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_int5_lit :
|
||||
org = XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_int5_text :
|
||||
org = XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_kernel_lit :
|
||||
org = XCHAL_KERNEL_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_kernel_text :
|
||||
org = XCHAL_KERNEL_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_user_lit :
|
||||
org = XCHAL_USER_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_user_text :
|
||||
org = XCHAL_USER_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
vector_double_lit :
|
||||
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||
len = MEM_VECT_LIT_SIZE
|
||||
vector_double_text :
|
||||
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM,
|
||||
len = MEM_VECT_TEXT_SIZE
|
||||
iram_text_start :
|
||||
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE,
|
||||
len = (IRAM_BASE + IRAM_SIZE) - (XCHAL_DOUBLEEXC_VECTOR_PADDR + MEM_VECT_TEXT_SIZE)
|
||||
sdram0 :
|
||||
org = SDRAM0_BASE,
|
||||
len = SDRAM0_SIZE
|
||||
sdram1 :
|
||||
org = SDRAM1_BASE + SOF_MAILBOX_SIZE,
|
||||
len = SDRAM1_SIZE - SOF_MAILBOX_SIZE
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
IDT_LIST :
|
||||
org = IDT_BASE,
|
||||
len = IDT_SIZE
|
||||
#endif
|
||||
|
||||
static_uuid_entries_seg (!ari) :
|
||||
org = UUID_ENTRY_ELF_BASE,
|
||||
len = UUID_ENTRY_ELF_SIZE
|
||||
static_log_entries_seg (!ari) :
|
||||
org = LOG_ENTRY_ELF_BASE,
|
||||
len = LOG_ENTRY_ELF_SIZE
|
||||
fw_metadata_seg (!ari) :
|
||||
org = EXT_MANIFEST_ELF_BASE,
|
||||
len = EXT_MANIFEST_ELF_SIZE
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
vector_reset_text_phdr PT_LOAD;
|
||||
vector_reset_lit_phdr PT_LOAD;
|
||||
vector_base_text_phdr PT_LOAD;
|
||||
vector_base_lit_phdr PT_LOAD;
|
||||
vector_int2_text_phdr PT_LOAD;
|
||||
vector_int2_lit_phdr PT_LOAD;
|
||||
vector_int3_text_phdr PT_LOAD;
|
||||
vector_int3_lit_phdr PT_LOAD;
|
||||
vector_int4_text_phdr PT_LOAD;
|
||||
vector_int4_lit_phdr PT_LOAD;
|
||||
vector_int5_text_phdr PT_LOAD;
|
||||
vector_int5_lit_phdr PT_LOAD;
|
||||
vector_kernel_text_phdr PT_LOAD;
|
||||
vector_kernel_lit_phdr PT_LOAD;
|
||||
vector_user_text_phdr PT_LOAD;
|
||||
vector_user_lit_phdr PT_LOAD;
|
||||
vector_double_text_phdr PT_LOAD;
|
||||
vector_double_lit_phdr PT_LOAD;
|
||||
iram_text_start_phdr PT_LOAD;
|
||||
sdram0_phdr PT_LOAD;
|
||||
sdram1_phdr PT_LOAD;
|
||||
static_uuid_entries_phdr PT_NOTE;
|
||||
static_log_entries_phdr PT_NOTE;
|
||||
metadata_entries_phdr PT_NOTE;
|
||||
}
|
||||
|
||||
_rom_store_table = 0;
|
||||
|
||||
PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR);
|
||||
|
||||
ENTRY(CONFIG_KERNEL_ENTRY)
|
||||
|
||||
/* Various memory-map dependent cache attribute settings: */
|
||||
_memmap_cacheattr_wb_base = 0x44024000;
|
||||
_memmap_cacheattr_wt_base = 0x11021000;
|
||||
_memmap_cacheattr_bp_base = 0x22022000;
|
||||
_memmap_cacheattr_unused_mask = 0x00F00FFF;
|
||||
_memmap_cacheattr_wb_trapnull = 0x4422422F;
|
||||
_memmap_cacheattr_wba_trapnull = 0x4422422F;
|
||||
_memmap_cacheattr_wbna_trapnull = 0x25222222;
|
||||
_memmap_cacheattr_wt_trapnull = 0x1122122F;
|
||||
_memmap_cacheattr_bp_trapnull = 0x2222222F;
|
||||
_memmap_cacheattr_wb_strict = 0x44F24FFF;
|
||||
_memmap_cacheattr_wt_strict = 0x11F21FFF;
|
||||
_memmap_cacheattr_bp_strict = 0x22F22FFF;
|
||||
_memmap_cacheattr_wb_allvalid = 0x44224222;
|
||||
_memmap_cacheattr_wt_allvalid = 0x11221222;
|
||||
_memmap_cacheattr_bp_allvalid = 0x22222222;
|
||||
/*
|
||||
* Every 512M in 4GB space has dedicate cache attribute.
|
||||
* 1: write through
|
||||
* 2: cache bypass
|
||||
* 4: write back
|
||||
* F: invalid access
|
||||
*/
|
||||
_memmap_cacheattr_imx8_wt_allvalid = 0x22212222;
|
||||
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_imx8_wt_allvalid);
|
||||
|
||||
_EXT_MAN_ALIGN_ = 16;
|
||||
EXTERN(ext_man_fw_ver)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
#include <zephyr/linker/rel-sections.ld>
|
||||
.ResetVector.text : ALIGN(4)
|
||||
{
|
||||
_ResetVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.ResetVector.text))
|
||||
_ResetVector_text_end = ABSOLUTE(.);
|
||||
} >vector_reset_text :vector_reset_text_phdr
|
||||
|
||||
.ResetVector.literal : ALIGN(4)
|
||||
{
|
||||
_ResetVector_literal_start = ABSOLUTE(.);
|
||||
*(.ResetVector.literal)
|
||||
_ResetVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_reset_lit :vector_reset_lit_phdr
|
||||
|
||||
.WindowVectors.text : ALIGN(4)
|
||||
{
|
||||
_WindowVectors_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.WindowVectors.text))
|
||||
_WindowVectors_text_end = ABSOLUTE(.);
|
||||
} >vector_base_text :vector_base_text_phdr
|
||||
|
||||
.Level2InterruptVector.literal : ALIGN(4)
|
||||
{
|
||||
_Level2InterruptVector_literal_start = ABSOLUTE(.);
|
||||
*(.Level2InterruptVector.literal)
|
||||
_Level2InterruptVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_int2_lit :vector_int2_lit_phdr
|
||||
|
||||
.Level2InterruptVector.text : ALIGN(4)
|
||||
{
|
||||
_Level2InterruptVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.Level2InterruptVector.text))
|
||||
_Level2InterruptVector_text_end = ABSOLUTE(.);
|
||||
} >vector_int2_text :vector_int2_text_phdr
|
||||
|
||||
.Level3InterruptVector.literal : ALIGN(4)
|
||||
{
|
||||
_Level3InterruptVector_literal_start = ABSOLUTE(.);
|
||||
*(.Level3InterruptVector.literal)
|
||||
_Level3InterruptVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_int3_lit :vector_int3_lit_phdr
|
||||
|
||||
.Level3InterruptVector.text : ALIGN(4)
|
||||
{
|
||||
_Level3InterruptVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.Level3InterruptVector.text))
|
||||
_Level3InterruptVector_text_end = ABSOLUTE(.);
|
||||
} >vector_int3_text :vector_int3_text_phdr
|
||||
|
||||
.DebugExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_DebugExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.DebugExceptionVector.literal)
|
||||
_DebugExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_int4_lit :vector_int4_lit_phdr
|
||||
|
||||
.DebugExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_DebugExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.DebugExceptionVector.text))
|
||||
_DebugExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_int4_text :vector_int4_text_phdr
|
||||
|
||||
.NMIExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_NMIExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.NMIExceptionVector.literal)
|
||||
_NMIExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_int5_lit :vector_int5_lit_phdr
|
||||
|
||||
.NMIExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_NMIExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.NMIExceptionVector.text))
|
||||
_NMIExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_int5_text :vector_int5_text_phdr
|
||||
|
||||
.KernelExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_KernelExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.KernelExceptionVector.literal)
|
||||
_KernelExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_kernel_lit :vector_kernel_lit_phdr
|
||||
|
||||
.KernelExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_KernelExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.KernelExceptionVector.text))
|
||||
_KernelExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_kernel_text :vector_kernel_text_phdr
|
||||
|
||||
.UserExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_UserExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.UserExceptionVector.literal)
|
||||
_UserExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_user_lit :vector_user_lit_phdr
|
||||
|
||||
.UserExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_UserExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.UserExceptionVector.text))
|
||||
_UserExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_user_text :vector_user_text_phdr
|
||||
|
||||
.DoubleExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_DoubleExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.DoubleExceptionVector.literal)
|
||||
_DoubleExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_double_lit :vector_double_lit_phdr
|
||||
|
||||
.DoubleExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_DoubleExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.DoubleExceptionVector.text))
|
||||
_DoubleExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_double_text :vector_double_text_phdr
|
||||
|
||||
.iram.text : ALIGN(4)
|
||||
{
|
||||
_stext = .;
|
||||
_iram_text_start = ABSOLUTE(.);
|
||||
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
|
||||
_iram_text_end = ABSOLUTE(.);
|
||||
} >iram_text_start :iram_text_start_phdr
|
||||
|
||||
.rodata : ALIGN(4)
|
||||
{
|
||||
__rodata_region_start = ABSOLUTE(.);
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
|
||||
KEEP (*(.xt_except_table))
|
||||
KEEP (*(.gcc_except_table .gcc_except_table.*))
|
||||
*(.gnu.linkonce.e.*)
|
||||
*(.gnu.version_r)
|
||||
KEEP (*(.eh_frame))
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc)
|
||||
*(.gnu.linkonce.h.*)
|
||||
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc_end)
|
||||
*(.dynamic)
|
||||
*(.gnu.version_d)
|
||||
. = ALIGN(4);
|
||||
_bss_table_start = ABSOLUTE(.);
|
||||
LONG(_bss_start)
|
||||
LONG(_bss_end)
|
||||
_bss_table_end = ABSOLUTE(.);
|
||||
__rodata_region_end = ABSOLUTE(.);
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
.module_init : ALIGN(4)
|
||||
{
|
||||
_module_init_start = ABSOLUTE(.);
|
||||
*(*.initcall)
|
||||
_module_init_end = ABSOLUTE(.);
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
.text : ALIGN(4)
|
||||
{
|
||||
_stext = .;
|
||||
__text_region_start = ABSOLUTE(.);
|
||||
KEEP (*(.ResetVector.text))
|
||||
*(.ResetVector.literal)
|
||||
*(.entry.text)
|
||||
*(.init.literal)
|
||||
KEEP(*(.init))
|
||||
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||||
*(.fini.literal)
|
||||
KEEP(*(.fini))
|
||||
*(.gnu.version)
|
||||
__text_region_end = ABSOLUTE(.);
|
||||
_etext = .;
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
#include <zephyr/linker/common-rom.ld>
|
||||
|
||||
.fw_ready : ALIGN(4)
|
||||
{
|
||||
KEEP(*(".fw_ready"));
|
||||
KEEP (*(.fw_ready_metadata))
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
.noinit : ALIGN(4)
|
||||
{
|
||||
*(.noinit)
|
||||
*(.noinit.*)
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
.data : ALIGN(4)
|
||||
{
|
||||
__data_start = ABSOLUTE(.);
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
KEEP(*(.gnu.linkonce.d.*personality*))
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
KEEP(*(.jcr))
|
||||
_trace_ctx_start = ABSOLUTE(.);
|
||||
*(.trace_ctx)
|
||||
_trace_ctx_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
*(.gna_model)
|
||||
__data_end = ABSOLUTE(.);
|
||||
. = ALIGN(4096);
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
.lit4 : ALIGN(4)
|
||||
{
|
||||
_lit4_start = ABSOLUTE(.);
|
||||
*(*.lit4)
|
||||
*(.lit4.*)
|
||||
*(.gnu.linkonce.lit4.*)
|
||||
_lit4_end = ABSOLUTE(.);
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
#include <zephyr/linker/common-ram.ld>
|
||||
|
||||
.bss (NOLOAD) : ALIGN(8)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_bss_start = ABSOLUTE(.);
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN (8);
|
||||
_bss_end = ABSOLUTE(.);
|
||||
} >sdram0 :sdram0_phdr
|
||||
|
||||
.heap_mem (NOLOAD) : ALIGN(8)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_heap_mem_start = ABSOLUTE(.);
|
||||
*(*.heap_mem)
|
||||
_heap_mem_end = ABSOLUTE(.);
|
||||
} >sdram1 :sdram1_phdr
|
||||
|
||||
/* stack */
|
||||
_end = ALIGN (8);
|
||||
PROVIDE(end = ALIGN (8));
|
||||
|
||||
__stack = SDRAM1_BASE + SDRAM1_SIZE;
|
||||
.comment 0 : { *(.comment) }
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
.debug_ranges 0 : { *(.debug_ranges) }
|
||||
.xtensa.info 0 : { *(.xtensa.info) }
|
||||
.xt.insn 0 :
|
||||
{
|
||||
KEEP (*(.xt.insn))
|
||||
KEEP (*(.gnu.linkonce.x.*))
|
||||
}
|
||||
.xt.prop 0 :
|
||||
{
|
||||
KEEP (*(.xt.prop))
|
||||
KEEP (*(.xt.prop.*))
|
||||
KEEP (*(.gnu.linkonce.prop.*))
|
||||
}
|
||||
.xt.lit 0 :
|
||||
{
|
||||
KEEP (*(.xt.lit))
|
||||
KEEP (*(.xt.lit.*))
|
||||
KEEP (*(.gnu.linkonce.p.*))
|
||||
}
|
||||
.xt.profile_range 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_range))
|
||||
KEEP (*(.gnu.linkonce.profile_range.*))
|
||||
}
|
||||
.xt.profile_ranges 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_ranges))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
|
||||
}
|
||||
.xt.profile_files 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_files))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_files.*))
|
||||
}
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
#include <zephyr/linker/intlist.ld>
|
||||
#endif
|
||||
|
||||
.static_uuid_entries (COPY) : ALIGN(1024)
|
||||
{
|
||||
*(*.static_uuids)
|
||||
} > static_uuid_entries_seg :static_uuid_entries_phdr
|
||||
|
||||
.static_log_entries (COPY) : ALIGN(1024)
|
||||
{
|
||||
*(*.static_log*)
|
||||
} > static_log_entries_seg :static_log_entries_phdr
|
||||
|
||||
.fw_metadata (COPY) : ALIGN(1024)
|
||||
{
|
||||
KEEP (*(.fw_metadata))
|
||||
. = ALIGN(_EXT_MAN_ALIGN_);
|
||||
} >fw_metadata_seg :metadata_entries_phdr
|
||||
}
|
||||
162
soc/nxp/imx/imx8x/adsp/memory.h
Normal file
162
soc/nxp/imx/imx8x/adsp/memory.h
Normal file
|
|
@ -0,0 +1,162 @@
|
|||
/*
|
||||
* Copyright (c) 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_NXP_ADSP_MEMORY_H_
|
||||
#define ZEPHYR_SOC_NXP_ADSP_MEMORY_H_
|
||||
|
||||
#define IRAM_RESERVE_HEADER_SPACE 0x400
|
||||
|
||||
#define IRAM_BASE 0x596f8000
|
||||
#define IRAM_SIZE 0x800
|
||||
|
||||
#define SDRAM0_BASE 0x92400000
|
||||
#define SDRAM0_SIZE 0x800000
|
||||
|
||||
#define SDRAM1_BASE 0x92C00000
|
||||
#define SDRAM1_SIZE 0x800000
|
||||
|
||||
/* The reset vector address in SRAM and its size */
|
||||
#define MEM_RESET_TEXT_SIZE 0x2e0
|
||||
#define MEM_RESET_LIT_SIZE 0x120
|
||||
|
||||
/* This is the base address of all the vectors defined in IRAM */
|
||||
#define XCHAL_VECBASE_RESET_PADDR_IRAM \
|
||||
(IRAM_BASE + IRAM_RESERVE_HEADER_SPACE)
|
||||
|
||||
#define MEM_VECBASE_LIT_SIZE 0x178
|
||||
|
||||
/*
|
||||
* EXCEPTIONS and VECTORS
|
||||
*/
|
||||
#define XCHAL_RESET_VECTOR0_PADDR_IRAM 0x596F8000
|
||||
|
||||
/* Vector and literal sizes */
|
||||
#define MEM_VECT_LIT_SIZE 0x4
|
||||
#define MEM_VECT_TEXT_SIZE 0x1C
|
||||
#define MEM_VECT_SIZE (MEM_VECT_TEXT_SIZE +\
|
||||
MEM_VECT_LIT_SIZE)
|
||||
|
||||
/* The addresses of the vectors.
|
||||
* Only the mem_error vector continues to point to its ROM address.
|
||||
*/
|
||||
#define XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x17C)
|
||||
|
||||
#define XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x19C)
|
||||
|
||||
#define XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1BC)
|
||||
|
||||
#define XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1DC)
|
||||
|
||||
#define XCHAL_KERNEL_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1FC)
|
||||
|
||||
#define XCHAL_USER_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x21C)
|
||||
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM \
|
||||
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x23C)
|
||||
|
||||
/* Location for the intList section which is later used to construct the
|
||||
* Interrupt Descriptor Table (IDT). This is a bogus address as this
|
||||
* section will be stripped off in the final image.
|
||||
*/
|
||||
#define IDT_BASE (IRAM_BASE + IRAM_SIZE)
|
||||
|
||||
/* size of the Interrupt Descriptor Table (IDT) */
|
||||
#define IDT_SIZE 0x2000
|
||||
|
||||
/* physical DSP addresses */
|
||||
#define IRAM_BASE 0x596f8000
|
||||
#define IRAM_SIZE 0x800
|
||||
|
||||
#define DRAM0_BASE 0x596e8000
|
||||
#define DRAM0_SIZE 0x8000
|
||||
|
||||
#define DRAM1_BASE 0x596f0000
|
||||
#define DRAM1_SIZE 0x8000
|
||||
|
||||
#define SDRAM0_BASE 0x92400000
|
||||
#define SDRAM0_SIZE 0x800000
|
||||
|
||||
#define SDRAM1_BASE 0x92C00000
|
||||
#define SDRAM1_SIZE 0x800000
|
||||
|
||||
#define XSHAL_MU13_SIDEB_BYPASS_PADDR 0x5D310000
|
||||
#define MU_BASE XSHAL_MU13_SIDEB_BYPASS_PADDR
|
||||
|
||||
#define EDMA0_BASE 0x59200000
|
||||
#define EDMA0_SIZE 0x10000
|
||||
|
||||
#define ESAI_BASE 0x59010000
|
||||
#define ESAI_SIZE 0x00010000
|
||||
|
||||
#define SAI_1_BASE 0x59050000
|
||||
#define SAI_1_SIZE 0x00010000
|
||||
|
||||
#define UUID_ENTRY_ELF_BASE 0x1FFFA000
|
||||
#define UUID_ENTRY_ELF_SIZE 0x6000
|
||||
|
||||
#define LOG_ENTRY_ELF_BASE 0x20000000
|
||||
#define LOG_ENTRY_ELF_SIZE 0x2000000
|
||||
|
||||
#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
|
||||
#define EXT_MANIFEST_ELF_SIZE 0x2000000
|
||||
|
||||
/*
|
||||
* The Heap and Stack on i.MX8 are organized like this :-
|
||||
*
|
||||
* +--------------------------------------------------------------------------+
|
||||
* | Offset | Region | Size |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | SDRAM_BASE | RO Data | SOF_DATA_SIZE |
|
||||
* | | Data | |
|
||||
* | | BSS | |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | HEAP_SYSTEM_BASE | System Heap | HEAP_SYSTEM_SIZE |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | HEAP_RUNTIME_BASE | Runtime Heap | HEAP_RUNTIME_SIZE |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | HEAP_BUFFER_BASE | Module Buffers | HEAP_BUFFER_SIZE |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | SOF_STACK_END | Stack | SOF_STACK_SIZE |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | SOF_STACK_BASE | | |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
*/
|
||||
|
||||
#define SRAM_OUTBOX_BASE SDRAM1_BASE
|
||||
#define SRAM_OUTBOX_SIZE 0x1000
|
||||
#define SRAM_OUTBOX_OFFSET 0
|
||||
|
||||
#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE)
|
||||
#define SRAM_INBOX_SIZE 0x1000
|
||||
#define SRAM_INBOX_OFFSET SRAM_OUTBOX_SIZE
|
||||
|
||||
#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
|
||||
#define SRAM_DEBUG_SIZE 0x800
|
||||
#define SRAM_DEBUG_OFFSET (SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE)
|
||||
|
||||
#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
|
||||
#define SRAM_EXCEPT_SIZE 0x800
|
||||
#define SRAM_EXCEPT_OFFSET (SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE)
|
||||
|
||||
#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
|
||||
#define SRAM_STREAM_SIZE 0x1000
|
||||
#define SRAM_STREAM_OFFSET (SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE)
|
||||
|
||||
#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
|
||||
#define SRAM_TRACE_SIZE 0x1000
|
||||
#define SRAM_TRACE_OFFSET (SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE)
|
||||
|
||||
#define SOF_MAILBOX_SIZE (SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE \
|
||||
+ SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE \
|
||||
+ SRAM_STREAM_SIZE + SRAM_TRACE_SIZE)
|
||||
|
||||
#endif /* ZEPHYR_SOC_NXP_ADSP_MEMORY_H_ */
|
||||
41
soc/nxp/imx/imx8x/adsp/pinctrl_soc.h
Normal file
41
soc/nxp/imx/imx8x/adsp/pinctrl_soc.h
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* Copyright 2023 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_XTENSA_NXP_ADSP_IMX8_PINCTRL_SOC_H_
|
||||
#define ZEPHYR_SOC_XTENSA_NXP_ADSP_IMX8_PINCTRL_SOC_H_
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/types.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct pinctrl_soc_pinmux {
|
||||
uint32_t pad;
|
||||
uint32_t mux;
|
||||
};
|
||||
|
||||
typedef struct pinctrl_soc_pinmux pinctrl_soc_pin_t;
|
||||
|
||||
#define IMX8_PINMUX(n) \
|
||||
{ \
|
||||
.pad = DT_PROP_BY_IDX(n, pinmux, 0), \
|
||||
.mux = DT_PROP_BY_IDX(n, pinmux, 1), \
|
||||
},
|
||||
|
||||
#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx)\
|
||||
IMX8_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
|
||||
|
||||
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||
{ DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
|
||||
DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_PINMUX) };
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ZEPHYR_SOC_XTENSA_NXP_ADSP_IMX8_PINCTRL_SOC_H_ */
|
||||
10
soc/nxp/imx/imx9/CMakeLists.txt
Normal file
10
soc/nxp/imx/imx9/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if(CONFIG_SOC_MIMX9352_A55)
|
||||
zephyr_include_directories(.)
|
||||
zephyr_include_directories(a55)
|
||||
|
||||
zephyr_sources_ifdef(CONFIG_ARM_MMU a55/mmu_regions.c)
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/a55/linker.ld CACHE INTERNAL "")
|
||||
endif()
|
||||
13
soc/nxp/imx/imx9/Kconfig
Normal file
13
soc/nxp/imx/imx9/Kconfig
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
# Copyright 2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_MIMX9352_A55
|
||||
select ARM64
|
||||
select CPU_CORTEX_A55
|
||||
select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS
|
||||
select HAS_MCUX if CLOCK_CONTROL
|
||||
select HAS_MCUX_CCM_REV2 if CLOCK_CONTROL
|
||||
select HAS_MCUX_IOMUXC if PINCTRL
|
||||
|
||||
config MCUX_CORE_SUFFIX
|
||||
default "_ca55" if SOC_MIMX9352_A55
|
||||
8
soc/nxp/imx/imx9/Kconfig.defconfig
Normal file
8
soc/nxp/imx/imx9/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
# Copyright 2022,2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_IMX9
|
||||
|
||||
rsource "Kconfig.defconfig.*"
|
||||
|
||||
endif # SOC_SERIES_IMX9
|
||||
27
soc/nxp/imx/imx9/Kconfig.defconfig.mimx93.a55
Normal file
27
soc/nxp/imx/imx9/Kconfig.defconfig.mimx93.a55
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
# Copyright 2022-2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_MIMX9352_A55
|
||||
|
||||
# Workaround for not being able to have commas in macro arguments
|
||||
DT_CHOSEN_Z_FLASH := zephyr,flash
|
||||
|
||||
config FLASH_SIZE
|
||||
default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
|
||||
|
||||
config FLASH_BASE_ADDRESS
|
||||
default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
|
||||
|
||||
config NUM_IRQS
|
||||
int
|
||||
default 240
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
int
|
||||
default 24000000
|
||||
|
||||
config PINCTRL_IMX
|
||||
default y if HAS_MCUX_IOMUXC
|
||||
depends on PINCTRL
|
||||
|
||||
endif
|
||||
32
soc/nxp/imx/imx9/Kconfig.soc
Normal file
32
soc/nxp/imx/imx9/Kconfig.soc
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
# Copyright 2022,2024 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_IMX9
|
||||
bool
|
||||
select SOC_FAMILY_NXP_IMX
|
||||
|
||||
config SOC_MIMX9352
|
||||
bool
|
||||
select SOC_SERIES_IMX9
|
||||
|
||||
config SOC_MIMX9352_A55
|
||||
bool
|
||||
select SOC_MIMX9352
|
||||
help
|
||||
NXP i.MX93 A55
|
||||
|
||||
config SOC_PART_NUMBER_MIMX9352CVUXK
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MIMX9352DVUXM
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER
|
||||
default "MIMX9352CVUXK" if SOC_PART_NUMBER_MIMX9352CVUXK
|
||||
default "MIMX9352DVUXM" if SOC_PART_NUMBER_MIMX9352DVUXM
|
||||
|
||||
config SOC
|
||||
default "mimx9352" if SOC_MIMX9352
|
||||
|
||||
config SOC_SERIES
|
||||
default "imx9" if SOC_SERIES_IMX9
|
||||
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