hwmv2: Introduce Hardware model version 2 and convert devices
This is a squash of the ``collab-hwm`` branch which converts all
in-tree boards to hardware model version 2 including build system
changes, board updates and soc conversions.
This squash is a combination of the following commits:
ca214745a1 soc: Remove soc_legacy folder and move ARM Kconfig
f12cb0979f scripts: ci: check_compliance: remove HWMv1 checks
1807bcf4d4 boards: mimx8mq_evk: port to HWMv2
3ec2299c62 soc: nxp: port imx8mq SOC to HWMv2
8ea02f4e63 boards: verdin_imx8mp: convert to HVMv2
f2eb7652ce boards: phyboard_pollux: move to HVMv2
ab509a5ee0 boards: nxp: mimx8mp_evk: port M7 core to HWMv2
06ad037f99 soc: nxp: imx8mp: port M7 core to HWMv2
3f9e706859 boards: mimx8mm_phyboard: convert to HVMv2
204372d264 boards: imx8mm_evk: port CM4 core to HWMv2
f82c961a46 soc: nxp: imx8mm: port iMX8MM M4 core to HVMv2
6987b2e305 boards: pico_pi: convert to HVMv2
84484e6707 boards: warp7: convert to HWMv2
ae443d1e3c boards: meerkat96: port to HWMv2
e3629c64e6 boards: colibri_imx7d: port to HWMv2
fc835d893d soc: nxp: convert iMX7 Dual core to HWMv2
29ef2f23eb boards: udoo_neo_full: convert to HWMv2
fd49b1749e soc: nxp: convert iMX6 SoloX core to HWMv2
1e59b7a3fd soc: nxp: imxrt11xx: only set
CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION for M7
69bb0eb258 hwmv2: MAINTAINERS: Fix NXP maintainer yaml
1c4458890f boards: firefly: roc_rk3568_pc: Fix SMP configuration
651a4370ad boards: Fix variants and revisions
196cfda66d tests/samples: Drop default revision identifiers
6ec6b1d75a boards: Drop revision from twister identifiers for
default revisions
b774cdd59f scripts: utils: board_v1_to_v2: drop board_legacy prefix
7aa36e6640 boards: riscv: esp32c3_luatos_core: make usb variant
fe25709a9c twister: add unit_testing soc and board
f88f211b4e scripts: ci: check_compliance: improve the "not sorted"
command
b21a455dfb bluetooth: controller: Fix openisa checks
fdc76c48a7 workflow: compliance: Add rename limit
14ecafc67d dts: bindings: vendor-prefixes: Sort entries
dbc366c3c7 soc: nxp: lpc: Move wrong configurations
8e02c08f96 maintainers: Fix invalid paths
b1b85e2495 boards: up: Fix spaces
58cc4013b3 maintainers: Fix xen path
66ce5c0b09 boards/soc: Add missing copyright headers
bb47243254 boards: qemu: x86: Remove pointless file
2e816a8a3a samples: tests: update esp32-based board naming
9aeab17139 samples: tests: remove platform_exclude of esp32 boards
a4fe97b9de boards: shields: m5stack_core2_ext: update board name
615fcab94a samples: ipm_esp32: fix board labels and skip testing
7752f69b7f boards: legacy: remove index entry for xtensa/riscv
boards.
3eba827956 MAINTAINERS: update Espressif entries
914362bbd5 boards: xtensa: yd_esp32: Convert to v2
a62278fd23 boards: xtensa: xiao_esp32s3: Convert to v2
b6a11ccec4 boards: xtensa: olimex_esp32_evb: Convert to v2
c1067c16d2 boards: xtensa: odroid_go: Convert to v2
b8340b0109 boards: xtensa: m5stickc_plus: Convert to v2
9d81e417be boards: xtensa: m5stack_stamps3: Convert to v2
c296672720 boards: xtensa: m5stack_core2: Convert to v2
fada12aa9d boards: xtensa: m5stack_atoms3_lite: Convert to v2
fe37ebac1e boards: xtensa: m5stack_atoms3: Convert to v2
d32828fe6a boards: xtensa: kincony_kc868_a32: Convert to v2
5afba7855b boards: xtensa: heltec_wireless_stick_lite_v3: Convert to
v2
ca48c17723 boards: xtensa: heltec_wifi_lora32_v2: Convert to v2
db1fd4d229 boards: xtensa: esp32s3_luatos_core: Convert to v2
a78b2552eb boards: xtensa: esp32s3_devkitm: Convert to v2
cc96061d96 boards: xtensa: esp32s2_saola: Convert to v2
ed854e05d1 boards: xtensa: esp32s2_lolin_mini: Convert to v2
4fa1ae8110 boards: xtensa: esp32s2_franzininho: Convert to v2
5543040a18 boards: xtensa: esp_wrover_kit: Convert to v2
2335ae79b3 boards: xtensa: esp32_ethernet_kit: Convert to v2
f910b7ad4f boards: xtensa: esp32_devkitc_wrover: Convert to v2
32104db555 boards: xtensa: esp32_devkitc_wroom: Convert to v2
e23a41200d boards: riscv: icev_wireless: Convert to v2
3c670e4e53 boards: riscv: xiao_esp32c3: Convert to v2
fc7c6a060b boards: riscv: stamp_c3: Convert to v2
22c2edb89c boards: riscv: esp32c3_luatos_core: Convert to v2
0a96dcb778 boards: riscv: esp32c3_devkitm: Convert to v2
be1ee1c446 vendors: update vendors lists
5e6c62137f soc: espressif_esp32: Port to HWMv2
037a3b52a4 boards: Raspberry Pi pico pwm led adjustment
7277cae6fa samples: blinky_pwm: enable pwm_leds in rpi_pico overlay
da3e49d34e boards: nxp: update selection of
FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
bc8424dd3b soc: nxp: imxrt: move FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
to SOC level
041cb52939 soc: brcm: bcm_vk: Rename to bcnvk
576b43a95c soc: Fix SOC_FAMILY name mismatches
e8f3e6494d hwmv2: boards: intel: adsp: Fix runner after paths
renamed
550399e927 boards: weact: stm32g431_core: Add wrongly deleted file
back
08708c909e tests: drivers: flash: Renamed missed board rename
06dac41e68 hwmv2: Convert Seagate Faze board to hwmv2
dd8f842b40 hwmv2: nxp: update MAINTAINER paths for hwmv2
b4d1c04978 hwmv2: lpc: updated overlay and conf files in samples and
tests
067c69089e boards: nxp: convert lpcxpresso55s69 to hwmv2
097205b40a hwmv2: Global fix of lpc54114_m4 overlay and conf files
d8cfa6fb29 boards: nxp: convert lpcxpresso54114 to hwmv2
c29ed228c6 boards: nxp: convert lpcxpresso55s36 to hwmv2
88cfd3d6ac boards: nxp: convert lpcxpresso55s28 to hwmv2
ad30c940ee boards: nxp: convert lpcxpresso55s16 to hwmv2
9e5a10ec80 boards: nxp: convert lpcxpresso55s06 to hwmv2
5650c83268 boards: nxp: convert lpcxpresso51u68 to hwmv2
82cf44be45 boards: nxp: convert lpcxpresso11u68 to hwmv2
1a9c405a6f soc: nxp: convert LPC SOC family to hardware model V2
f2b536d253 boards: intel: doc: hwmv2: Fix some renamed paths
5ee6058710 samples/tests: Use board revisions
b76687602f boards: Add yaml files for boards missing revisions
32ae4918d0 boards: nordic: Fix board names
cc1dabca65 MAINTAINERS: Update for renamed folders
a37ddce659 soc: xilinx: Rename to xlnx
a1393a07f6 soc: xenvm: Rename to xen
813ed00f67 soc: raspberry_pi: Rename to raspberrypi
71317d6798 soc: cadence: Rename to cdns
8cb0c51ec6 soc: broadcom: Rename to brcm
2b9db15c69 soc: andes: Rename to andestech
0101216ce1 soc: altera: Rename to altr
4b4c3ca65d boards: wurth_elektronik: Rename to we
cdc3ef499f boards: ublox: Rename to u-blox
cabdd4ad05 boards: space_cubics: Rename to sc
4b5bd7ae8a boards: seeed_studio: Rename to seeed
a992785ceb boards: raspberry_pi: Rename to raspberrypi
3c1cdc20fe boards: laird_connect: Rename to lairdconnect
291c7cde2b boards: cadence: Rename to cdns
95db897526 boards: broadcom: Rename to brcm
0a47b94879 boards: beagleboard: Change to beagle
9f9f221c24 boards: andes: Rename to andestech
e7869ca38a boards: altera: Rename to altr
bf2fb5eca3 various: Change SOC_FAMILY_NRF to SOC_FAMILY_NORDIC_NRF
e25730ba56 modules: tf-m: Rename from nordic_nrf to nordic
9e3466606a boards: nordic_nrf: Rename to nordic
09a398dcc8 soc: nordic_nrf: Rename to nordic
cb8ffc74f8 boards: renode: Add documentation index
2291ff4b55 boards: arm: riscv32_virtual: Convert to v2
484b7f1996 soc: riscv_renode_virtual: Port to HWMv2
cc5c2fb0c7 soc: raspberry_pi: Fix SOC_SERIES and SOC mismatch
59cb580513 soc: arm: designstart: Fix SOC_SERIES and SOC mismatch
aa9e0de7af samples: Fix invalid links
a1480cf1cf maintainers: Fix paths
0d719e004b boards: Update documentation links
eb5c3e6f79 boards: wurth_elektronik: Drop duplicate prefix
a34a3640b7 boards: waveshare: Drop duplicate prefix
cf50e950e7 boards: weact: Drop duplicate prefix
737cfb548f boards: sparkfun: Drop duplicate prefix
505494c97a boards: segger: Drop duplicate prefix
4eaf69f37a boards: ruuvi: Drop duplicate prefix
a1335caeae boards: ronoth: Drop duplicate prefix
a9f7f30bf6 boards: raytac: Drop duplicate prefix
80db4c81b3 boards: qemu: Drop duplicate prefix
433d7e9976 boards: particle: Drop duplicate prefix
4ea79d19e7 boards: olimex: Drop duplicate prefix
fd4ae6f6a8 boards: mikroe: Drop duplicate prefix
36080549bd boards: khados: Drop duplicate prefix
169bf8ae1d boards: intel: Drop duplicate prefix
25f04d5222 boards: holyiot: Drop duplicate prefix
11c2af0de8 boards: google: Drop duplicate prefix
d5128f4016 boards: ebyte: Drop duplicate prefix
44fbc68cad boards: dragino: Drop duplicate prefix
f7fe431b44 boards: contextual_electronics: Drop duplicate prefix
9094fea63b boards: circuit_dojo: Drop duplicate prefix
b632acc1fc boards: blue_clover: Drop duplicate prefix
1a3316ebdc boards: bbc: Drop duplicate prefix
71c0344f8c boards: arduino: Drop duplicate prefix
f0176fc25f boards: altera: Drop duplicate prefix
36b920ed0f boards: adi: Drop duplicate prefix
22520368d9 boards: adafruit: Drop duplicate prefix
296acfb2bc boards: actinius: Drop duplicate prefix
55063380b7 boards: 96boards: Drop duplicate prefix
1f93394b55 boards: nxp: convert mimxrt595_evk to hardware model v2
e7a4fd2ec1 soc: nxp: rt5xx: convert RT5xx SOC to HWMv2
01942f1d11 twister: normalize platform name when storing files/data
477c8b84dd twister: tests: test with slashes in platform names
64e3e816c4 soc: Add include guards
3a7aa2fa49 gitignore: update the compliance file list
84e1c17ad9 scripts: ci: check_compliance: add a check for board yml
file
a90f53ad57 boards: sync up the vendor tags and vendor-list
af9aa65299 dts: vendor-prefixes: add keep-sorted markers
50f0bf05a3 dts: vendor-prefixes: sort the vendor list
a10b614aa4 dts: vendor-prefixes: ensure all prefixes are lowercase
5abe735e93 manifest: update SOF sha for NXP HWMv2
9ab8f64ca9 modules: rename SOC_FAMILY_IMX
483ff8dd4d modules: mcux: remove SOC_FAMILY_NXP_ADSP
f113dd5342 samples: update board name
39b31287d9 boards: nxp: Convert i.MX ADSP boards to hardware model
v2
1511e356a2 soc: nxp: Port i.MX ADSP family to hardware model v2
c91e25ab47 soc: mec: rename all mec1501x reference to mec15xx
1c231fd939 hwmv2: boards: Convert IMXRT boards
417cff1e60 hwmv2: soc: Port IMXRT family to HWMV2
28d4e41b1b hwmv2: clean up arm64 soc and board empty directory
2b520f83cb hwmv2: port NXP SoC LS1046A to V2
bf7899c645 hwmv2: port nxp_ls1046ardb board to V2
33f7b61866 samples/tests: Rename numaker boards
8f20ea6e93 boards: nuvoton: numaker_pfm: Split into 2 boards
7cf4ff43a1 drivers: pinctrl: imx: align with hwm v2
c68e1fea4e drivers: clock_control: ccm_rev2: align with hwm v2
update
3b49014a0f hwmv2: move imx8mn EVK board to V2
14f344eeab hwmv2: move imx8mp EVK board to V2
40f3f8f22d hwmv2: move imx8mm EVK board to V2
10bf79ea51 hwmv2: move imx8m soc for a-core to V2
8727d5ca80 hwmv2: move imx93 EVK board to V2
c81ef01563 hwmv2: move imx93 soc to V2
5836c1b699 modules: mcux: introduce CONFIG_MCUX_CORE_SUFFIX
338f6f2bf1 doc: update board porting guide to match new hardware
model
9639a1b5dc soc: silabs: drop useless defconfigs
981807444e soc: silabs: introduce SOC_GECKO_SDID
5d07e82485 soc: silabs: SOC_FAMILY_* replace SOC_GECKO_SERIES*
2fd081ac86 soc: silabs: align comments with soc tree
66d425f571 soc: silabs: split in families
5bd38f47a9 arch: arch: kconfig: Fix wrong placement of endmenu
00c6ef25be tests/samples: Rename overlay files for renamed boards
0c639b8378 boards: Fix bools and selections
c2ef907d1d drivers: flash: it8xxx2: Add missing Kconfigs
553de2ebc9 soc: ite: ec: it8xxx2: Fix SOC_SERIES being in wrong file
b8ec0080c2 boards: Documentation link fixes
eb7025e50f tests: Update board names for hwmv2
10ef3d4bd2 boards: silab: Add documentation index file
ba9fdaa1d6 boards: arm: efr32_radio: Convert to v2
86c8d4a0ca boards: arm: efm32pg_stk3402a: Convert to v2
575ac5cafb manifest: Update hal_silabs
87b2907304 boards: arm: efr32_thunderboard: Convert to v2
14b30055ab boards: arm: efr32mg_sltb004a: Convert to v2
0012bfc15d boards: arm: efr32xg24_dk2601b: Convert to v2
f526225ead boards: arm: efm32wg_stk3800: Convert to v2
19e7df29df boards: arm: efm32pg_stk3401a: Convert to v2
0bd7d963d6 boards: arm: efm32hg_slstk3400a: Convert to v2
795a90f9bf boards: arm: efm32gg_stk3701a: Convert to v2
43d5540be7 boards: arm: efm32gg_slwstk6121a: Convert to v2
065148d856 boards: arm: efm32gg_sltb009a: Convert to v2
1dc9a8aa17 soc: silabs_exx32: Port to HWMv2
763571e878 tests: Expand names
dae301b8a3 boards: xen: xenvm: Expand name
19e60eef36 boards: qemu: qemu_cortex_a53: Expand names
a0a7c30f28 soc: intel: intel_adsp: Fix issues
df9a4223fe scripts: ci: introduce soc name check in check_compliance
ed401abaff soc: emsdsp: align SoC name defined in soc.yml to Kconfig
SOC setting
fc78e5eaa4 MAINTAINERS: update RISC-V arch area paths
4e586958ff boards: convert QEMU RISC-V 64 bit board to Zephyr HWMv2
f4c31a2b86 boards: convert QEMU RV32E board to Zephyr HWMv2
5b2ffc652b boards: convert QEMU RISC-V 32 bit board to Zephyr HWMv2
5db061a4c6 soc/riscv: convert the QEMU virt RISCV-32 SoC to HWMv2
6547845e9d boards: convert SparkFun RED-V Things Plus to Zephyr
HWMv2
95a1f96399 boards: convert SiFive HiFive Unmatched to Zephyr HWMv2
e563eb0a62 soc/sifive/sifive_freedom: add SiFive Freedom FU740 SoC
8914bc58b6 boards: convert SiFive HiFive Unleashed to Zephyr HWMv2
7e8de1e781 soc/sifive/sifive_freedom: add SiFive Freedom U540 SoC
bfcc2ed18f boards: convert SiFive HiFive1 Rev. B to Zephyr HWMv2
330fc38f9f boards: convert SiFive HiFive1 to Zephyr HWMv2
b9e06f4c38 soc/sifive/sifive_freedom: add SiFive Freedom E310 SoC
4b90b30b9d scripts: west_commands: completion: Add hwmv2 complete to
fish
0f6842e2fa scripts: west_commands: completion: Add hwmv2 complete to
zsh
b2af1e1737 scripts: west: list_boards: Fix hwmv2 output
686a4b78b8 scripts: west_commands: completion: Add hwmv2 complete to
bash
396b6bb856 soc: nxp: fix typo in SoC name
765299c627 soc: broadcom: align SoC names defined in soc.yml to
Kconfig SOC setting
7efd46eb41 soc: arm: align SoC names defined in soc.yml to Kconfig
SOC setting
505cbc5c42 soc: mec: align SoC names defined in soc.yml to Kconfig
SOC setting
951a140701 soc: ti: define SOC name in Kconfig
a795d28810 snippets: Initial HWMv2 support
f9a957e6f6 boards: nordic: nrf9160dk: Fix missing nrf52840 config
df994e7ee8 soc: xilinx: zync7000: Remove xilinx from soc series name
8dfabd56ca soc: cypress: Add protection guard to file
447b951593 tests: kernel: tickless: Remove old board name
bad5dfa71f boards: nordic: nrf5340dk: Fix board names
ad2e863f39 soc: atmel: Use new family prefix
3f08e714b2 soc: intel_adsp: hwmv2: Align SOC_SERIES_INTEL_ACE name
and value
6734597a76 soc: intel_adsp_cavs: hwmv2: Align SOC_SERIES name and
value
2908af0bcc boards: nrf51dk/dongle: change SoC to nRF51822
d1ceb29fca soc: align CONFIG_SOC values to match soc.yml names
4768ccaf70 tests: drivers: gpio: gpio_api_1pin: exclude hifive1
ebdb0879ad boards: nxp: s32z2xxdc2: convert to hwmv2
ae82580d08 boards: nxp: mr_canhubk3: convert to hwmv2
c5f0defbae boards: nxp: ucans32k1sic: convert to hwmv2
1e46cabce6 soc: nxp: convert NXP S32 family to hwmv2
f2f85133f2 soc: stm32: Rename series path
86642f4e78 soc: stm32: Rename Kconfig SOC_SERIES symbols
c61e807896 soc: stm32: Cleanup Kconfig.defconfig files
ca46c8abc9 tests: Fix board names
fbfed5f48f maintainers: Update synopsys entries
8cd8b1cc47 boards: synopsys: Add documentation index
6f6cc57a04 boards: arc: hsdk4xd: Convert to v2
c4c14a54ca soc: snps_arc_hsdk4xd: Port to HWMv2
06c2054e5c boards: arc: iotdk: Convert to v2
ff0e0fce1b soc: snps_arc_iot: Port to HWMv2
334264c46a boards: arc: emsdp: Convert to v2
8b947a0e91 soc: snps_emsdp: Port to HWMv2
990417bbde tests: Update board names for hwmv2
e12719154a boards: arc: em_starterkit: Convert to v2
437a430fbe soc: snps_emsk: Port to HWMv2
f93387f968 boards: arc: hsdk: Convert to v2
1cf2498b13 soc: snps_arc_hsdk: Port to HWMv2
47abe81256 boards: arc: nsim: Convert to v2
1e33786dc4 soc: snps_nsim: Port to HWMv2
7f081914db boards: arc: qemu_arc: Convert to v2
bc97349dbd soc: snps_qemu: Port to HWMv2
a9902ff58e boards: Use zephyr_file for file links
126e1a4e72 boards: Fix invalid documentation links
899f0257c3 boards: stm32wb: Restore missing .defconfig files
790c10b1ee soc: x86/atom: imply mmu, do not select it
faee62088d boards: x86: remove qemu_x86_tiny_768
c34d186a57 x86: atom: remove soc.h with unused content
1be3a9e9d3 x86: remove legacy ia32, use atom instead
60e6b400f9 boards: qemu: move qemu_x86 -> x86
c4fbac27e8 boards: infineon: Add documentation index
b4dd29a9c4 maintainers: Update paths for hwmv2
380f5fdb2b boards: cypress: Add documentation index
9de981be05 boards: arm: xmc47_relax_kit: Convert to v2
6394e8a348 boards: arm: xmc45_relax_kit: Convert to v2
04dbf17e19 soc: xmc_4xxx: Port to HWMv2
c9731f1bce boards: arm: cy8cproto_063_ble: Convert to v2
53d41869d1 boards: arm: cy8cproto_062_4343w: Convert to v2
46c4f01427 boards: arm: cy8ckit_062s4: Convert to v2
d285e19cf2 boards: arm: cy8ckit_062_wifi_bt: Convert to v2
2bebd7298c boards: arm: cy8ckit_062_ble: Convert to v2
af243274c2 soc: psoc6 and psoc_6: Port to HWMv2
105a2bae84 cmake: modules: boards: Fix board deprecation for HWMv2
dca54e000a cmake: modules: boards: Enhance board aliases for HWMv2
fc314e8e3f cmake: modules: boards: Fix BOARD_ALIAS
9a7c2ce6d5 soc: gaisler: Move Kconfig file
1ac56d0501 soc: soc_legacy: mips: Remove out file
c054381a7a boards: adjust few boards/ paths
4d93b8d9fd boards: convert all microchip MEC boards to hwmv2
ab2fcb1245 soc: convert microchip_mec to hwmv2
ead4b57a7b soc: arm64: intel_socfpga: hwmv2: Rename SoCs
d4c143d306 MAINTAINERS: intel_socfpga: Adjust to HWMv2 move
70a66ac03a boards: arm64: intel_socfpga: Move boards to
subdirectories
8a85c07799 boards: arm64: intel_socfpga_agilex5_socdk: move to HWMv2
8c253a99fc boards: arm64: intel_socfpga_agilex_socdk: move to HWMv2
ab883b8019 soc: arm64: intel_socfpga: Move and convert to HWMv2
7c8b7a153b soc: arm: intel_socfpga_std: Rename with HWMv2
8dc2b911f6 soc: board: intel_socfpga_std: Align names to 'Cyclone V'
402366117a soc: arm: intel_socfpga_std: Align board subdirectory
f0a8d12745 boards: arm: cyclonev_socdk: Move to HWMv2
2271f17a86 soc: arm: intel_socfpga_std: Move and convert to HWMv2
841c2a9d99 boards: riscv: beaglev_fire: Convert to v2
3b314531ab boards: riscv: mpfs_icicle: Convert to v2
d4ea2bf70b boards: riscv: m2gl025_miv: Convert to v2
5256e9fcc3 soc: microchip_miv: Port to HWMv2
18e5cf1d51 maintainers: Update path for hwmv2
eab8628f98 boards: arm: qemu_cortex_m3: Convert to v2
1532f2fee1 soc: ti_lm3s6965: Port to HWMv2
430ca6a475 maintainers: Update ambiq paths
a9b9b41b91 boards: ambiq: Add index
db0271ecbb boards: arm: apollo4p_blue_kxr_evb: Convert to v2
957e2b2061 boards: arm: apollo4p_evb: Convert to v2
5a90a44454 soc: ambiq: Port to HWMv2
a20c113fbd boards: nxp: convert ip_k66f to hwmv2
34e3852a54 boards: nxp: convert usb_kw24d512 to hwmv2
20ad604de6 boards: nxp: convert twr_kv58f220m to hwmv2
2e2a7b7656 boards: nxp: twr_ke18f: convert to hwmv2
f7dcc2eb5e boards: nxp: convert rddrone_fmuk66 to hwmv2
b58e90a2e9 boards: nxp: convert hexiwear to hwmv2
aae6e9e454 boards: nxp: frdm_kw41z: convert to hwmv2
1d3baac2d6 boards: nxp: convert frdm_kl25z to hwmv2
3b1d21483f boards: nxp: frdm_k82f: port to hwmv2
6046e6ded9 boards: nxp: port frdm_k64f to hwmv2
0a7bf9fd79 boards: nxp: port frdm_k22f to hwmv2
dce697c823 boards: nxp: add toctree placeholder
666a353409 soc: nxp: kinetis: convert kinetis SOC family to hardware
model V2
89f0a6034b maintainers: Update paths for renesas boards/socs
004bd43c48 tests/samples/snippets: Update board names for hwmv2
a6d756923d boards: arm and arm64: rcar_h3ulcb: Convert to v2
3801216b8d boards: arm64: rcar_salvator_xs_m3: Convert to v2
b7cc30aaea boards: arm: rcar_h3_salvatorx_cr7: Convert to v2
866427ea29 boards: arm: arduino_uno_r4: Convert to v2
2689b3f0ee soc: ra: Port to HWMv2
e7ebc727c8 boards: arm: da1469x_dk_pro: Convert to v2
903265b2bb boards: arm: da14695_dk_usb: Convert to v2
529a78ed51 soc: smartbond: Port to HWMv2
97cf636ae0 boards: arm: rcar_spider_cr52: Convert to v2
6d0c53f3a1 soc: rcar: Port to HWMv2
44e0aa0668 soc: renesas: rzt2m: Move folder structure for more SoCs
85238fc205 boards: misc: Fixed STM32 based boards doc links
dffc08af56 boards: riscv: niosv_m: move and convert to HWMv2
545093abe4 boards: riscv: niosv_g: move and convert to HWMv2
ecfa192f1b soc: riscv: intel_niosv: move and convert to HWMv2
fd1e8cdc30 hwmv2: sof: intel_adsp: submanifest provisional link
8bf067e625 doc: boards: intel_adsp: Re-order pages
4833275ccd MAINTAINERS: intel_adsp: Adjust to HWMv2 move
b9a70e5ea2 soc: intel_adsp: tools: pylint compliance workaround
18c70cc4bf hwmv2: tests: boards: intel_adsp: Adjust board names
ca52baf9de hwmv2: boards: intel_adsp: Overhaul board configurations
d1b3bcce64 soc: boards: xtensa: intel_adsp_ace: Rename with HWMv2
f362a8ae2c doc: soc: boards: intel_adsp_cavs25: Rename with HWMv2
51dee5da92 tests: samples: boards: intel_adsp_cavs25: Rename with
HWMv2
e66c35e0d0 boards: xtensa: intel_adsp_cavs25: Rename board with
HWMv2
d1491a4810 soc: boards: xtensa: intel_adsp_cavs25: Rename with HWMv2
fa0fca79c4 scripts: west: runners: intel_adsp: Adjust path to HWMv2
acd18bfaf7 boards: xtensa: intel_adsp_ace20_lnl: move and convert to
HWMv2
546c94b958 boards: xtensa: intel_adsp_ace15_mtpm: move and convert
to HWMv2
8aab718c3e boards: xtensa: intel_adsp_cavs25_tgph: change to board
variant
30f17424a4 boards: xtensa: intel_adsp_cavs25: move and convert to
HWMv2
35a97cb524 soc: xtensa: intel_adsp: HWMv2 workaround for SOF config
fdc20fdff6 soc: xtensa: intel_adsp: move and convert to HWMv2
22dc2b6391 cmake: improved board handling for revisions
2f1e33a2e6 cmake: improve arch error message for invalid arch
selection
c47c37d3db sample: basic: blinky_pwm: Exclude rpi_pico w variant
7a788b9a18 boards: raspberry_pi: rpi_pico: Use full name for w
variant
7046b92d41 tests: atmel_sam: adc: Fix sam4e_xpro adc build
253ee9638c tests: atmel_sam0: Update platform name
ccb4c63324 samples: atmel_sam0: Update platform name
2d4acf9230 boards: arduino_nano_33_iot: Convert to HWMv2
a60d28969a boards: arduino_mkrzero: Convert to HWMv2
0409e51d3f boards: arduino_zero: Convert to HWMv2
1b2528df1b boards: wio_terminal: Convert to HWMv2
af1096e7ca boards: ev11l78a: Convert to HWMv2
0b1db9c53d boards: adafruit_trinket_m0: Convert to HWMv2
e9874671e2 boards: adafruit_itsybitsy_m4_express: Convert to HWMv2
ba6c014071 boards: adafruit_grand_central_m4_express: Convert to
HWMv2
33ad4a51ca boards: adafruit_feather_m0_lora: Convert to HWMv2
9812f3d54e boards: adafruit_feather_m0_basic_proto: Convert to HWMv2
c76b1fbeca boards: serpente: Convert to HWMv2
649789e433 boards: seeeduino_xiao: Convert to HWMv2
6b3bdb7364 boards: same54_xpro: Convert to HWMv2
93dda5ee4b boards: samr34_xpro: Convert to HWMv2
e48e1f5d5b boards: samc21n_xpro: Convert to HWMv2
f11cf73df1 boards: saml21_xpro: Convert to HWMv2
ac73ed6dcd boards: samd20_xpro: Convert to HWMv2
0fdbe3552e boards: samd21_xpro: Convert to HWMv2
854cff3905 boards: samr21_xpro: Convert to HWMv2
a87ea5bc0a soc: atmel: sam0: Port to HWMv2
706e5d27cd boards: riscv: neorv32: Convert to v2
d1edcdd088 soc: neorv32: Port to HWMv2
0f7add89ca boards: native_sim/posix: Add 64bit versions as variants
b6edad8d68 soc: soc_legacy: remove the arm/st_stm32 folder
c58e0822a6 boards: Convert nucleo_f207zg to HWM v2
b987093a80 soc: v2: stm32: Migrate STM32F2 series
2096fd4652 samples: bluetooth: hci_uart: Fix wrongly converted board
names
830f9c5a82 MAINTAINERS: Update Atmel entries
527cd9d8cd CODEOWNERS: Update Atmel entries
83af7d0c1c samples: atmel_sam: Update platform name
fd9b84d457 tests: atmel_sam: Update platform name
3c72fe863c boards: arduino_due: Convert to HWMv2
37dfacbf9e boards: RoboKit1: Convert to HWMv2
1108d7b0ed boards: sam_v71_xult: Convert to HWMv2
bed44a5c28 boards: sam_e70_xplained: Convert to HWMv2
40448c5a9f boards: sam4s_xplained: Convert to HWMv2
31273692c0 boards: sam4l_ek: Convert to HWMv2
35b5d33ef0 boards: sam4e_xpro: Convert to HWMv2
3b84b9910a soc: atmel: Port SAM family to HWMv2
da00d0e7b9 boards: Convert nucleo_wba55cg to HWM v2
fb2103f89e boards: Convert nucleo_wba52cg to HWM v2
1f9a533fbc soc: st: stm32: Migrate STM32WBA series
3f92f65b28 boards: fix documentation for alientek and blues boards
7646b74aaf boards: stm32l4: doc: add zephyr_file to defconfig path
fea54ddcd9 boards: Convert adi_eval_adin2111ebz to HWM v2
d47f1878b1 boards: Convert adi_eval_adin1110ebz to HWM v2
ae42be236b boards: Convert swan_r5 to HWM v2
83bd1a9ecc boards: Convert stm32l4r9i_disco to HWM v2
39c26f09ed boards: Convert stm32l496g_disco to HWM v2
29d03c970b boards: Convert stm32l476g_disco to HWM v2
74acec315c boards: Convert sensortile_box to HWM v2
fee6d8676e boards: Convert pandora_stm32l475 to HWM v2
008b5d9392 boards: Convert nucleo_l4r5zi to HWM v2
24e357d623 boards: Convert nucleo_l4a6zg to HWM v2
2c5f9dcce0 boards: Convert nucleo_l496zg to HWM v2
4da061646f boards: Convert nucleo_l476rg to HWM v2
15956a69b8 tests: drivers: flash: stm32: update platform name
80324f7707 boards: Convert nucleo_l452re_p to HWM v2
9893e0d111 boards: Convert nucleo_l452re to HWM v2
46f92b227b boards: Convert nucleo_l433rc_p to HWM v2
ed5d1bb4cd boards: Convert nucleo_l432kc to HWM v2
325f95ec20 boards: Convert nucleo_l412rb_p to HWM v2
d055676307 boards: Convert disco_l475_iot1 to HWM v2
c7a415d92c boards: Convert b_l4s5i_iot01a to HWM v2
d15144f582 soc: st: stm32: Migrate STM32L4 series
a63ff71bcb boards: nrf_bsim: Add new nrf5340 board definitions
b53c6f412c boards: nrf_bsim: Remove redundant option setting
83eb4fc069 MAINTAINERS: intel_ish: Adjust to HWMv2 move
715685b19f boards: x86: intel_ish: move and convert intel_ish boards
to HWMv2
5b9ef94106 soc: x86: intel_ish: move and convert to HWMv2
12b297707a boards: Convert stm32wb5mmg to HWM v2
cdcea932bc boards: Convert stm32wb5mm_dk to HWM v2
0a3ae2b223 boards: Convert nucleo_wb55rg to HWM v2
20b4ce17d5 soc: st: stm32: Migrate STM32WB series
47c65400d6 soc: st: stm32: fix stm32l0 family
59ec56f9e6 boards: Convert stm32h573i_dk to HWM v2
dc5977dbba boards: Convert nucleo_h563zi to HWM v2
a6e4928543 soc: st: stm32: Migrate STM32H5 series
99f248e048 soc: stm32u5: Fix references after conversion to hw
modelv2
15f16834e6 boards: Convert stm32u5a9j_dk to HWM v2
c1ee449ef1 boards: Convert sensortile_box_pro to HWM v2
db4deddf9d boards: Convert nucleo_u5a5zj_q to HWM v2
2fd3ed43d2 boards: Convert nucleo_u575zi_q to HWM v2
902fceb173 boards: Convert b_u585i_iot02a to HWM v2
d716ca1a10 soc: st: Migrate stm32u5 series to new hw model
b7abc89428 hwmv2: boards: x86: doc: Adjust common docs to new
locations
69b334f54b MAINTAINERS: Change paths to native and nrf*bsim boards
614611a528 boards: nrf*_bsim: Convert to HW model v2
5821b9ec2e board: native_sim/posix: Convert to hwmv2
04cbad174e soc: native: Convert to HWMv2
24ca0febfc boards: nrf_bsim: Fix path to pinctrl_soc.h
9a32559a2d cmake: FindHostTools: Fix for hwmv2 for host based
targets
c4b11e0251 boards: longan_nano: port to HWMv2
97edd05be3 boards: gd32vf103c_starter: port to HWMv2
9cf624c410 boards: gd32vf103v_eval: port to HWMv2
b40bf25e5e soc: gd_gd32: reorganize folders
71600d7e95 soc: gd_gd32: move pinctrl_soc.h content back to soc
folder
2bd84a1bc5 soc: gd_gd32: port gd32vf103 series to HWMv2
9dc342143b boards: doc: fix a bunch of broken reference
10392d693d doc: boards: split out shields
b2def8ed3a boards: acrn: fix title
bf7d3efe78 boards: riscv: tlsr9518adk80d: Convert to v2
c579770e1d soc: telink_tlsr: Port to HWMv2
9131540109 soc: stm32h7: Couple of tests fixes following migration
2efcefc089 boards: Convert stm32h7b3i_dk to HWM v2
d9b295a85b boards: Convert stm32h750b_dk to HWM v2
a2f56bdcd5 boards: Convert stm32h747i_disco to HWM v2
00314155df boards: Convert stm32h735g_disco to HWM v2
b08819dff7 boards: Convert nucleo_h7a3zi_q to HWM v2
56456c16e5 boards: Convert nucleo_h753zi to HWM v2
91f9198dc4 boards: Convert nucleo_h745zi_q to HWM v2
96f1bafbf9 boards: Convert nucleo_h743zi to HWM v2
b290f25baa boards: Convert nucleo_h723zg to HWM v2
9fbe6bf191 boards: Convert fk7b0m1_vbt6 to HWM v2
44bcfe57c7 boards: Convert arduino_portenta_h7 to HWM v2
4c86af7eae boards: Convert arduino_opta_m4 to HWM v2
b4f852f738 boards: Convert arduino_giga_r1 to HWM v2
bac9789264 soc: st: Migrate stm32h7 series to new hw model
a954e1722d boards: stm32l0: Cleanup board _defconfig files after
migration
7e8515b241 boards: Convert ronoth_lodev to HWM v2
25246c21ef boards: Convert nucleo_l073rz to HWM v2
09396eb2e6 boards: Convert nucleo_l053r8 to HWM v2
70c004fd83 boards: Convert nucleo_l031k6 to HWM v2
e3daa98e79 boards: Convert nucleo_l011k4 to HWM v2
a2de60c6da boards: Convert dragino_nbsn95 to HWM v2
e877ce9cec boards: Convert dragino_lsn50 to HWM v2
2b50218c23 boards: Convert b_l072z_lrwan1 to HWM v2
4a65f55916 soc: st: Migrate stm32l0 series to new hw model
cc6e6be01f boards: fix few leftover ITE board references
a837303268 soc: stm32: Protect Kconfig symbols by SOC_FAMILY_STM32
88e5959f17 hwm2: Fix unit_testing: it is also a legacy board by now
95e06e8663 cmake: Fix uses of old SOC path
d517d3cc24 soc: set linker script for ra4m1
68f9aeddab soc: ite: add SOC_SERIES_ITE_IT8XXX2 guards around ITE
options
ccf4f48f01 boards: convert ite boards to hwmv2
4a6e286a3b soc: convert ite_ec to hwmv2
12e375f826 doc: handle arch / soc / board docs in new hardware model
b4db917de9 boards: Add documentation index files
d6e0d27efe samples: bluetooth: hci_uart: Fix wrong named files
bc16a7a727 tests: Update board names for hwmv2
2834883843 boards: riscv: rv32m1_vega: Convert to v2
9c68231ba9 soc: openisa_rv32m1: Port to HWMv2
986e9619fd soc: starfive_jh71xx: Port to HWMv2
e82932e787 boards: riscv: litex_vexriscv: Convert to v2
cb9339f88f soc: litex_vexriscv: Port to HWMv2
1cd4c34654 boards: riscv: opentitan_earlgrey: Convert to v2
92eadf06b8 soc: opentitan: Port to HWMv2
a8659e170b boards: riscv: titanium_ti60_f225: Convert to v2
359133d725 soc: efinix_sapphire: Port to HWMv2
6d466429ed soc: soc_legacy: riscv: litex_vexriscv: Add updated paths
a1ff441eb3 boards: riscv: adp_xc7k_ae350: Convert to v2
ef82a8255c soc: ae350: Port to HWMv2
282204758a samples: boards: stm32: ccm: fix include path
8ca9341195 samples: basic: threads: fix broken reference
8a947f446d boards: nrf52840dk: fix rst syntax
324cb41153 boards: nordic_nrf: fix broken references
963c74df1c boards: intel_(ish|adl|ehl|rpl), up_squared: fix include
paths
8d518ce504 boards: legacy: drop empty folders
0fef0cef5b boards: mps2: fix table formatting
e52ccc244f boards: add HWMv2 board index
c7426eca5e boards: arm: add legacy tag
1eba9d8a8f boards: acrn: create vendor folder
8d92edc727 tests: kernel: Adjust qemu_x86_tiny_768 configuration
HWMv2
75117d1b2d scripts: ensure posix path is used with --cmakeformat
0b0384b56a maintainers: update paths after HWMv2 changes
c1b77b223d boards: arm: pan1783: Convert to v2
91a077b2ab boards: posix: nrf_bsim: Update paths
413b6c2a40 cmake: modules: configuration_files: Add board identifier
overlay file
4f572ba24f treewide: Update board names for hwmv2
cb348c7edf boards: arm: nrf54l15pdk_nrf54l15: Convert to v2
811ad90566 boards: arm: nrf54h20pdk_nrf54h20: Convert to v2
d44ef90cf8 soc: nordic_nrf: Migrate nRF54H/nRF54L to v2 and fix nrf
c860f205de boards: arm: nrf9151dk_nrf9151: Convert to v2
fba98a1763 soc: nordic_nrf: Migrate nRF9151 to v2
5c156a2d35 boards: arm: 96b_carbon_nrf51: Convert to v2
cfc47a3a4b boards: arm: nrf9161dk_nrf9161: Convert to v2
37129b4e44 boards: arm: nrf9131ek_nrf9131: Convert to v2
a923beba5d boards: arm: bl5340_dvk: Convert to v2
d242b2703b boards: arm: raytac_mdbt53v_db_40_nrf5340: Convert to v2
9c80d4e644 boards: arm: raytac_mdbt53_db_40: Convert to v2
28268c4938 boards: arm: nrf5340_audio_dk_nrf5340: Convert to v2
33ad2b5bc6 boards: arm: thingy53_nrf5340: Convert to v2
40daa94f2d boards: arm: nrf9160_innblue22: Convert to v2
2b0dbb9d51 boards: arm: nrf9160_innblue21: Convert to v2
ee6f7697ac boards: arm: sparkfun_thing_plus_nrf9160: Convert to v2
594e4bad6b boards: arm: circuitdojo_feather_nrf9160: Convert to v2
a5803ba099 boards: arm: actinius_icarus: Convert to v2
db8c275456 boards: arm: actinius_icarus_bee: Convert to v2
30177cf53d boards: arm: actinius_icarus_som: Convert to v2
486504cf24 boards: arm: actinius_icarus_som_dk: Convert to v2
dd0672a64c boards: arm: nrf9160dk_*: Convert to v2
c1565b3d14 boards: arm: xiao_ble: Convert to v2
6dd2723314 boards: arm: qemu_cortex_m0: Convert to v2
ee1ce24a42 boards: arm: bbc_microbit: Convert to v2
1952d559f2 boards: arm: rm1xx_dvk: Convert to v2
9e12c3d8bd boards: arm: nrf51dongle_nrf51422: Convert to v2
0ffbc1da33 boards: arm: nrf51_blenano: Convert to v2
be52dfb7b6 boards: arm: nrf51_vbluno51: Convert to v2
4c29d1827f boards: arm: nrf51_ble400: Convert to v2
5b4a9556fd boards: arm: raytac_mdbt53_db_40_nrf5340: Fix typo
69e5d87a15 boards: arm: contextualelectronics_abc: Convert to v2
5e4ace1bbe boards: arm: degu_evk: Convert to v2
2762460a64 boards: arm: pan1781_evb: Convert to v2
fdc3913e76 boards: arm: ubx_evkninab1_nrf52832: Convert to v2
9c9c3a09a1 boards: arm: holyiot_yj16019: Convert to v2
109edc296f boards: arm: blueclover_plt_demo_v2_nrf52832: Convert to
v2
7bfcdbbe8f boards: arm: decawave_dwm1001_dev: Convert to v2
0fbb543983 boards: arm: acn52832: Convert to v2
073e0f8080 boards: arm: we_proteus2ev_nrf52832: Convert to v2
197a19f396 boards: arm: ebyte_e73_tbb_nrf52832: Convert to v2
1616fc8ae5 boards: arm: nrf52_vbluno52: Convert to v2
5622077738 boards: arm: nrf52_sparkfun: Convert to v2
a6289516e4 boards: arm: 96b_nitrogen: Convert to v2
439d836883 boards: arm: nrf52_blenano2: Convert to v2
16e65f09c4 boards: arm: arduino_nicla_sense_me: Convert to v2
862efd5a21 boards: arm: thingy52_nrf52832: Convert to v2
dede0f6cd3 boards: arm: nrf52_adafruit_feather: Convert to v2
91e864ea29 boards: arm: nrf52832_mdk: Convert to v2
47ec3e416b boards: arm: ruuvi_ruuvitag: Convert to v2
52f797a227 boards: arm: pinetime_devkit0: Convert to v2
433db339f9 boards: arm: ubx_evkannab1_nrf52832: Convert to v2
a646d3f2d5 boards: arm: ubx_bmd300eval_nrf52832: Convert to v2
d0d434bf86 cmake: print identifier instead of variant
c3f5ed8157 boards: arm: we_proteus3ev_nrf52840: Convert to v2
eecff8ee7a boards: arm: nrf52840_mdk_usb_dongle: Convert to v2
34507614f6 boards: arm: nrf52840_mdk: Convert to v2
f02b56cb96 boards: arm: nrf52840_blip: Convert to v2
600c55c92a boards: arm: nrf52840_papyr: Convert to v2
f294bfc5e4 boards: arm: reel_board: Convert to v2
882524d2a0 boards: arm: nrf21540dk_nrf52840: Convert to v2
4bce0e9b39 boards: arm: nrf52840dongle_nrf52840: Convert to v2
d0229c771f boards: arm: particle_argon: Convert to v2
23a0570e64 boards: arm: particle_boron: Convert to v2
b6d3e1764f boards: arm: particle_xenon: Convert to v2
499f3e7902 boards: arm: rak5010_nrf52840: Convert to v2
9ae6b1804d boards: arm: rak4631_nrf52840: Convert to v2
fe2c90da5c boards: arm: pinnacle_100_dvk: Convert to v2
3d4d46698c boards: arm: ubx_evkninab3_nrf52840: Convert to v2
b1afbf0158 boards: arm: ubx_bmd380eval_nrf52840: Convert to v2
9f9897c872 boards: arm: ubx_bmd345eval_nrf52840: Convert to v2
f7fb2030c7 boards: arm: ubx_bmd340eval_nrf52840: Convert to v2
7186432662 boards: arm: raytac_mdbt50q_db_40_nrf52840: Convert to v2
32c4bdc0c4 boards: arm: pan1780_evb: Convert to v2
7b64c638a8 boards: arm: pan1770_evb: Convert to v2
156ee8ad8a boards: arm: mg100: Convert to v2
3d33dadeb0 boards: arm: arduino_nano_33_ble: Convert to v2
4fee7371d2 boards: arm: adafruit_itsybitsy_nrf52840: Convert to v2
ad37a0c222 boards: arm: adafruit_feather_nrf52840: Convert to v2
cf85b7169f boards: arm: bt510: Convert to v2
44b67ac430 boards: arm: bt610: Convert to v2
7dbb65d371 boards: arm: ubx_evkninab4_nrf52833: Convert to v2
5e79cb957d boards: arm: raytac_mdbt50q_db_33_nrf52833: Convert to v2
12bd83a218 boards: arm: pan1782_evb: Convert to v2
1a135ec352 boards: arm: bbc_microbit_v2: Convert to v2
4dbe97e5ea boards: arm: nrf52833dk: Convert to v2
d632b90043 boards: arm: ubx_bmd360eval_nrf52811: Convert to v2
cc1a30f24b boards: arm: we_ophelia1ev_nrf52805: Convert to v2
df0df9000b boards: arm: ubx_bmd330eval_nrf52810: Convert to v2
d2c7972a9a boards: arm: nrf52dk: Convert to v2
202c2bf447 boards: arm: bl654_sensor_board: Convert to v2
c3e36f2042 boards: arm: bl654_usb: Convert to v2
b9dd58aea1 boards: arm: bl654_dvk: Convert to v2
0e1898b093 boards: arm: bl653_dvk: Convert to v2
286f4a7524 boards: arm: bl652_dvk: Convert to v2
d1709cdb37 boards: update nRF51dk board to board scheme v2.
8f040cff2c boards: Update nrf5340dk_nrf5340 to HWMv2 scheme
8c90fae8e0 boards: update nRF52840dk_nrf52840/nrf52811 board to
board scheme v2.
c828dcc60e boards: common: openocd-nrf5: Add HWMv2 support
c79f1b0d94 kconfig: soc: adopt Nordic SoC series to support hw model
v2 scheme
3584b30fc1 tests: Update board names for hwmv2
94024d940e boards: arm: arty_a7: Convert to v2
8053c3a8df boards: arm: scobc_module1: Convert to v2
d5473b76fe soc: designstart: Port to HWMv2
f5792b05e7 boards: arm: fvp_baser_aemv8r_aarch32: Convert to v2
ff202daa8e soc: fvp_aemv8r_aarch32: Port to HWMv2
e66cbc2945 boards: arm: v2m_musca_s1: Convert to v2
33b47b2edb boards: arm: v2m_musca_b1: Convert to v2
baeebd31d2 soc: musca: Port to HWMv2
73b257a3f9 boards: arm: v2m_beetle: Convert to v2
85de0888ec soc: beetle: Port to HWMv2
867960a891 manifest: Update modules
6ca677ed3a boards: arm: mps2: Convert to v2
bcf4ad19d4 twister: build_dir: convert / to _ to support hwmv2
0ac386683f soc: Kconfig.v2: Add SOC_PART_NUMBER
9242c3c78f soc: stm32: soc.yml: reorder series
248d17f160 boards: stm32: cleanup
0a67265e99 boards: stm32: fix for boards with revisions
f8d44317ee soc: stm32l5: Rename overlays for nucleo_l552ze_q ns
target.
400343d17e soc: stm32: Set default on USE_DT_CODE_PARTITION
d783ef549a soc: stm32l5: Update stm32l5 non secure targets in
various places
643aeac552 boards: Convert stm32l562e_dk to HWM v2
e601d64344 boards: Convert nucleo_l552ze_q to HWM v2
2f7a387b32 soc: st: Migrate stm32l5 series to new hw model
519752efcd boards: xenvm: doc: Remove reference to deleted file
06263dd717 boards: xenvm: Unset HEAP_MEM_POOL_SIZE in gicv3 variant
66b0df5526 boards: qemu_cortex_a53: Fix Kconfig warnings in SMP
variant
fa07bd9419 boards: mps3: Fix non-secure variant
8f6f0726dd boards: Move xenvm under xen
7b155a7031 boards: Raspberry Pi vendor fix
804697afa5 boards: Move 96b_aerocore to 96boards
d2f001e320 boards: x86: acrn: move and convert to HWMv2
ec7f7b3c30 tests: kernel: qemu_x86: adjust to the HWMv2
89dfcddc7e boards: x86: qemu_x86_tiny@768: change to board variant
eb724eb6a7 boards: x86: qemu_x86: optimize default HWMv2
configurations
6f1043cde6 boards: x86: qemu_x86: move and convert to HWMv2
cab924cbfb soc: x86: ia32: move and convert to HWMv2
237fdff918 soc: x86: lakemont: move and convert to HWMv2
03042b7704 boards: move 96b_carbon to 96boards folder
767b94414e boards: rename vendor seeed to seeed_studio
07fa3a3d79 boards: Convert olimex_lora_stm32wl_devkit to HWM v2
ba01d3beca boards: Convert nucleo_wl55jc to HWM v2
7ce84f4041 boards: Convert lora_e5_mini to HWM v2
b988bae576 boards: Convert lora_e5_dev_board to HWM v2
6fbf39c726 soc: v2: stm32: Migrate STM32WL series
4a41878442 soc: st: stm32g4: add missing include
1e79ba15f6 boards: Convert weact_stm32g431_core to HWM v2
ffdcb60185 boards: Convert nucleo_g474re to HWM v2
d6acb08d3e boards: Convert nucleo_g431rb to HWM v2
90e592ffd1 boards: Convert b_g474e_dpow1 to HWM v2
eb8a7e3441 soc: st: stm32: Migrate STM32G4 series
ada469f237 tests: Update board names for hwmv2
0342433187 boards: arm: npcx9m6f_evb: Convert to v2
c10248d964 boards: arm: npcx7m6fb_evb: Convert to v2
21ddc5e6a6 boards: arm: npcx4m8f_evb: Convert to v2
5500f3ef21 soc: npcx*: Port to HWMv2
e7baf09ede soc: m48x: Port to HWMv2
5bae4a6480 boards: arm: numaker_pfm_m467: Convert to v2
3b0bd70c8c soc: m46x: Port to HWMv2
d52eab9e83 boards: Convert stm32g081b_eval to HWM v2
6f2835cb11 boards: Convert stm32g071b_disco to HWM v2
ca36d331d2 boards: Convert stm32g0316_disco to HWM v2
662cc4e09b boards: Convert nucleo_g0b1re to HWM v2
dd9bc29769 boards: Convert nucleo_g071rb to HWM v2
353da23ffb boards: Convert nucleo_g070rb to HWM v2
acc932b424 boards: Convert nucleo_g031k8 to HWM v2
cea9b140fd boards: Convert google_twinkie_v2 to HWM v2
52e025943a soc: st: stm32: Migrate STM32G0 series
1c7347686a ci: update check_compliance to not create duplicate lines
in Kconfig
9debd98799 hwmv2: boards: up_squared_pro_700: Add missed intel_adl
changes
adab07c42f boards: Convert msp_exp432p401r_launchxl to HWM v2
642aacdcdf soc: ti_simplelink: Add missing SoC
48637066d3 boards: Fix file paths in documentation
e983bc2a23 samples/tests: Fix mps3 board name
61e0f32716 boards: Convert stm32f3_seco_d23 to HWM v2
a1688ff641 boards: Convert stm32f3_disco to HWM v2
35fb228599 boards: Convert stm32373c_eval to HWM v2
10e5d1122b boards: Convert nucleo_f334r8 to HWM v2
c319cb19f0 boards: Convert nucleo_f303re to HWM v2
11725ccac1 boards: Convert nucleo_f303k8 to HWM v2
400f7f6a4f boards: Convert nucleo_f302r8 to HWM v2
8d84861390 soc: v2: stm32: Migrate STM32F3 series
85b9eee7e8 boards: arm: kv260_r5: Convert to v2
dafbd638e4 boards: arm: mercury_xu: Convert to v2
3ecd12f415 boards: arm: qemu_cortex_r5: Convert to v2
5db2390e9d soc: xilinx_zyncmp: Port to HWMv2
9ba8195cdc boards: arm: qemu_cortex_a9: Convert to v2
8e94b85361 boards: arm: zybo: Convert to v2
c970127fc2 soc: xilinx_zynq7000: Port to HWMv2
394c75373c boards: arm: ast1030_evb: Convert to v2
f2a1cc8714 soc: ast10x0: Port to HWMv2
28f3f25945 boards: arm: cc3235sf_launchxl: Convert to v2
c3e480f740 boards: arm: cc3220sf_launchxl: Convert to v2
fd5847123f boards: arm: beagleconnect_freedom: Convert to v2
76ba9a0587 boards: arm: cc1352p1_launchxl: Convert to v2
719baa8850 boards: arm: cc1352r1_launchxl: Convert to v2
5060a61ae1 boards: arm: cc1352r_sensortag: Convert to v2
99584be1c5 boards: arm: cc26x2r1_launchxl: Convert to v2
2dc8933942 soc: ti_simplelink: Port to HWMv2
a5b004663b scripts/utils/board_v1_to_v2.py: couple of fixes
77c2c333e5 boards: move 96b_stm32_sensor_mez to 96boards
c14ff98650 boards: stm32f411e_disco: delete obsolete file
bcdc268ccf boards: Convert stm32mp157c_dk2 to HWM v2
0c8ba92e1f boards: Convert 96b_avenger96 to HWM v2
b54fe33077 soc: v2: stm32: Migrate STM32MP1 series
2ba3639b2a boards: Convert nucleo_c031c6 to HWM v2
dbc5ed79f5 soc: st: stm32: Migrate STM32C0 series
ce6d493aa3 boards: Convert stm32l1_disco to HWM v2
a28086a9ca boards: Convert nucleo_l152re to HWM v2
1b2a511d06 boards: Convert 96b_wistrio to HWM v2
ce281f09ab soc: v2: stm32: Migrate STM32L1 series
cdb5364fd7 boards: Convert stm32f769i_disco to HWM v2
768f173dcb boards: Convert stm32f7508_dk to HWM v2
21bbbbd9cb boards: Convert stm32f746g_disco to HWM v2
bab4265693 boards: Convert stm32f723e_disco to HWM v2
58f8fe82ba boards: Convert nucleo_f767zi to HWM v2
37e9084070 boards: Convert nucleo_f756zg to HWM v2
d467e7053a boards: Convert nucleo_f746zg to HWM v2
5f2808d7cc boards: Convert nucleo_f722ze to HWM v2
bbb73e7550 soc: st: Migrate stm32f7 series to new hw model
e9094afc4d soc: st: stm32: stm32f4: change SOC_STM32F405XG to
SOC_STM32F405XX
a1712cdd53 boards: Convert stm32f4_disco to HWM v2
5be404b365 boards: Convert stm32f469i_disco to HWM v2
baaa697ab2 boards: Convert stm32f429i_disc1 to HWM v2
69ecab3c90 boards: Convert stm32f412g_disco to HWM v2
2a572e3fb0 boards: Convert stm32f411e_disco to HWM v2
ecfbf42757 boards: Convert stm32f401_mini to HWM v2
e0191d03bb boards: Convert steval_fcu001v1 to HWM v2
4454648976 boards: Convert segger_trb_stm32f407 to HWM v2
f0ad6ee6b8 boards: Convert olimex_stm32_p405 to HWM v2
1f5e228ec8 boards: Convert olimex_stm32_h407 to HWM v2
834bdb615e boards: Convert olimex_stm32_h405 to HWM v2
8f27fa8de2 boards: Convert olimex_stm32_e407 to HWM v2
f8633a9038 boards: Convert nucleo_f446ze to HWM v2
07e0bd2c07 boards: Convert nucleo_f446re to HWM v2
24d7f625dc boards: Convert nucleo_f429zi to HWM v2
157a8cde53 boards: Convert nucleo_f413zh to HWM v2
4ec99c31b0 boards: Convert nucleo_f412zg to HWM v2
a21546140a boards: Convert nucleo_f411re to HWM v2
43f01ab6de boards: Convert nucleo_f410rb to HWM v2
60c16bcb8b boards: Convert nucleo_f401re to HWM v2
2db228d730 boards: Convert mikroe_mini_m4_for_stm32 to HWM v2
73fc26225c boards: Convert mikroe_clicker_2 to HWM v2
6b62d90114 boards: Convert google_dragonclaw to HWM v2
fa845af309 boards: Convert blackpill_f411ce to HWM v2
5c8c3c3be0 boards: Convert blackpill_f401ce to HWM v2
3c02db1290 boards: Convert blackpill_f401cc to HWM v2
7eeb723cb7 boards: Convert black_f407zg_pro to HWM v2
4f9461d068 boards: Convert black_f407ve to HWM v2
a821de8532 boards: Convert az3166_iotdevkit to HWM v2
ba580c7236 boards: Convert adi_sdp_k1 to HWM v2
eb272ddf19 boards: Convert adafruit_feather_stm32f405 to HWM v2
58ed121c3a boards: Convert 96b_stm32_sensor_mez to HWM v2
b0d70959d3 boards: Convert 96b_neonkey to HWM v2
b1088baadc boards: Convert 96b_carbon to HWM v2
18d867b0a9 boards: Convert 96b_argonkey to HWM v2
ee6ede7119 boards: Convert 96b_aerocore2 to HWM v2
b48e70ead9 soc: v2: stm32: Migrate STM32F4 series
14d2b955da cmake: convert path to CMake style before writing Kconfig
files
9c4ac6a202 boards: posix: bsim: Update paths
14b57f56d7 tests: drivers: gpio: gpio_ite_it8xxx2_v2: Temp fix
f3b173be18 scripts: board_v1_to_v2: Update following move to
boards_legacy
05b50f6691 cmake: CMake soc dir variable improvements for HWMv2
a188e01a12 hwmv2: move all ported boards and socs to their final
location
22c53e97b5 hwmv2: move all non-ported legacy boards and socs to
legacy folders
53f3b181b0 soc: ti_k3: Port to HWMv2
9f19a2075a soc: rk3568: Port to HWMv2
b8928b1628 soc: rk3399: Port to HWMv2
cda3a74868 boards: arm64: qemu_kvm_arm64: Convert to v2
70d704bd20 soc: x86: atom: move and convert to HWMv2
4789e1068e boards: x86: intel_rpl: move and convert raptor_lake
boards to HWMv2
384307e3dc soc: x86: raptor_lake: move and convert to HWMv2
ed025df674 boards: x86: intel_ehl: move and convert elkhart_lake
boards to HWMv2
994b6e1731 soc: x86: elkhart_lake: move and convert to HWMv2
73b30a04cf boards: x86: up_squared_pro_7000: move and convert to
HWMv2
83b133c207 boards: x86: intel_adl: move and convert alder_lake
boards to HWMv2
847a12f1e4 soc: alder_lake: move and convert to HWMv2
67f4c8d2a1 samples: up_squared: adjust gpio_counter to HWMv2
5326b5bfc0 boards: x86: up_squared: move and convert to HWMv2
cfd5e691b4 soc: apollo_lake: move and convert to HWMv2
ac9c235741 boards: xtensa: qemu_xtensa: Convert to v2
f198c3a761 ci: update to osource for soc/Kconfig.defconfig files
e438e6cad4 ci: add SOC_SERIES_ as false positive in
check_compliance.py
95e34da7c1 soc: v2: Convert st_stm32 to st/stm32
313717df76 soc: mps3: Fix missing family
392c3969ed boards: arm: am62x_m4: Convert to v2
8f245d764d tests: Update board names for hwmv2
8f71bb7b4f boards: arm64: khadas_edgev: Convert to v2
e27d23aad0 soc: rk3399: Port to HWMv2
80823b860e boards: arm64: roc_rk3568_pc: Convert to v2
72e4483dec soc: rk3568: Port to HWMv2
bed94669e3 boards: arm64: phycore_am62x_a53: Convert to v2
c01af5a7b8 soc: ti_k3: Port to HWMv2
1e563b4ca3 boards: arm64: xenvm: Convert to v2
76e484adae soc: xenvm: Port to HWMv2
34412f7fe2 boards: arm64: rpi_4b: Convert to v2
9be50e2ca9 soc: bcm2711: Port to HWMv2
bbbed12c2f boards: arm64: qemu_kvm_arm64: Convert to v2
4f5ec7ff8f soc: qemu_virt_arm64: Port to HWMv2
d8d1b9f200 boards: arm64: qemu_cortex_a53: Convert to v2
30bd34b31e soc: qemu_cortex_a53: Port to HWMv2
c20d0dcbb6 boards: arm64: fvp_baser_aemv8r: Convert to v2
02ed6af463 boards: arm64: fvp_base_revc_2xaemv8a: Convert to v2
1b175003a4 soc: fvp_aemv8*: Port to HWMv2
de231b911d boards: v2: Clean up obsolete comments
aa9597f6d9 boards: Convert waveshare_open103z to HWM v2
9644828c81 boards: Convert stm32vl_disco to HWM v2
86ab2bd430 boards: Convert stm32_min_dev to HWM v2
d88d3ddcc4 boards: Convert stm32f103_mini to HWM v2
0ccc0204e1 boards: Convert stm3210c_eval to HWM v2
dd9972d782 boards: Convert olimex_stm32_h103 to HWM v2
a2c2e1406d boards: Convert olimexino_stm32 to HWM v2
2d9c62e118 boards: Convert nucleo_f103rb to HWM v2
e8ba99dc59 soc: v2: stm32: Migrate STM32F1 series
9a93916604 tests: Update board names for hwmv2
9c4d94844d boards: arm: bcm958401m2: Convert to v2
feaf4ffba1 boards: arm: bcm958402m2: Convert to v2
87f0827121 soc: bcm_vk: Port to HWMv2
4526be24a5 boards: arm: quick_feather: Convert to v2
cd921d2b97 boards: arm: qomu: Convert to v2
b3c04051fc soc: quicklogic_eos_s3: Port to HWMv2
a73a9e7533 boards: v2: Clean up obsolete comments
8d87bcc167 boards: Convert stm32f0_disco to HWM v2
1933585785 boards: Convert stm32f072_eval to HWM v2
6f9fe5429d boards: Convert stm32f072b_disco to HWM v2
9dc78e4025 boards: Convert stm32f030_demo to HWM v2
35113e8923 boards: Convert nucleo_f091rc to HWM v2
b276aee9a4 boards: Convert nucleo_f070rb to HWM v2
795f8d611b boards: Convert nucleo_f042k6 to HWM v2
2d82646443 boards: Convert nucleo_f031k6 to HWM v2
959786f12d boards: Convert nucleo_f030r8 to HWM v2
81670db2e9 boards: Convert legend to HWM v2
8980430aad boards: Convert google_kukui to HWM v2
ac020f66e0 dts: stm32f0: fix few warnings
5140e4551a boards: v2: doc: Add vendors
77d640e0c9 soc: v2: stm32: Migrate STM32F0 series
0131e1c159 soc: v2: Add st_stm32 structure and common folder
36b63787a7 boards: v2: Add documentation index for converted boards
ae02fc5047 boards: sparc: qemu_leon3: Convert to v2
f38f7bb223 boards: sparc: gr716a: Convert to v2
d3cca3580e soc: gr716a: Port to HWMv2
6a8a0c1647 boards: sparc: generic_leon3: Convert to v2
faf22185ce soc: leon3: Port to HWMv2
e94762ecdc tests: Update board names for hwmv2
9afcc27e05 boards: xtensa: qemu_xtensa: Convert to v2
3e4a17018f soc: dc233c: Port to HWMv2
9188fdcd78 boards: xtensa: xt-sim: Convert to v2
fcaa41cb5d soc: xtensa_sample_controller: Port to HWMv2
dbc413f7f7 scripts: board_v1_to_v2: Fix CONFIG_SOC_SERIES_ exclusion
6be3d4bc80 kconfig: remove Kconfig BOARD_RPI_PICO_W safe guard.
f4442fa698 boards: v2: Add documentation index for converted boards
ec5fbd67f7 boards: nios2: qemu_nios2: Convert to v2
d3ef220460 soc: nios2-qemu: Port to HWMv2
a223f284b5 boards: nios2: altera_max10: Convert to v2
c381edcb73 soc: nios2f-zephyr: Port to HWMv2
97401c7d2a boards: mips: qemu_malta: Convert to v2
e7a3243a24 soc: qemu_malta: Port to HWMv2
bec82c690d boards: v2: Add documentation index for converted boards
94f6f9b636 boards: arm: w5500_evb_pico: Convert to v2
209235ab6e boards: arm: sparkfun_pro_micro_rp2040: Convert to v2
e5b1885907 boards: arm: adafruit_qt_py_rp2040: Convert to v2
4c750818f9 boards: arm: adafruit_kb2040: Convert to v2
8d3896caa4 boards: arm: rpi_pico: Convert to v2
42cff42c42 soc: rpi_pico: Port to HWMv2
c2df4ca9cb scripts: improve yaml schema and board.yml validation for
revisions
3970f90f71 cmake: clear BOARD_CACHE when invalid board identifier is
given
3a70ee9ccd cmake: improve board revision handling
3cda715fae scripts: board_v1_to_v2: Don't add select
CONFIG_SOC_SERIES_FOO
dc56a543f3 scripts: board_v1_to_v2: Add License + copyright
87147f88c4 cmake: prefer cache BOARD_IDENTIFIER over extracting from
BOARD
65f5dc5b8c cmake: fail when board identifier is applied in legacy hw
model
7db2b6efd8 cmake: cache BOARD_IDENTIFIER to preserve it between
CMake invocations
85dddac5a2 scripts: using extend in list_boards for variant list
6ae5c4e7fd scripts: utils: add board v1->v2 conversion utility
ef834a12d0 maintainers: update Renesas RZT2M path
3ab7830625 boards: renesas: add documentation entry
a0c2ca0491 boards: arm: add documentation entry
27ff3654b7 boards: gigadevice: add documentation entry
6e02f43c0a maintainers: update GD32 paths
1bfcf1d974 boards: gd32l233r_eval: convert to HWMv2
6e621ee43f boards: gd32f470i_eval: convert to HWMv2
219b149768 boards: gd32f450z_eval: convert to HWMv2
91c52b0d39 boards: gd32f450v_start: convert to HWMv2
f0e0a973f6 boards: gd32f407v_start: convert to HWMv2
6f592b64c9 boards: gd32f403z_eval: convert to HWMv2
4bcb4b2ac8 boards: gd32f350r_eval: convert to HWMv2
fdc7ed6eb0 boards: gd32e507z_eval: convert to HWMv2
770376250d boards: gd32e507v_start: convert to HWMv2
a6d8b92e86 boards: gd32e103v_eval: convert to HWMv2
a5f8e5daa1 boards: gd32a503v_eval: convert to HWMv2
5ee799cc5f boards: gd32f450i_eval: convert to HWMv2
8aa8ce4ac8 soc: gigadevice: port to HWMv2
4e203c14c7 cmake: enhanced board entry file handling
312265ee04 scripts: make SoC field mandatory in board.yml
c12ae3bcbc boards: update Renesas rzt2m board.yml to contain SoC
information
c5321c1dbe cmake: make SoC optional for boards containing a single
SoC
bcc06c60ae scripts: support SoC list output for boards
db9e46010c twister: update testcase.yaml and sample.yaml to
mps3/an547 identifier
a988adee7d boards: update arm mps3 an547 board to HWMv2 scheme
7dc2c9db0c soc: use HWMv2 for arm mps3 SoC
c506675b7c boards: update Renesas Starter Kit+ for RZ/T2M board to
HWMv2 scheme
3abb792073 soc: use HWMv2 for renesas_rzt2m SoC
4f52bc646e cmake: support hw model v2 in arch/Kconfig tree
a712b5005b scripts: extend kconfig compliance to verify board / SoC
scheme v2
baa55141a1 twister: update twister testplan.py to handle HWMv2
boards
1f026f70eb boards: extend list_boards.py and update boards CMake
module
bd854a3af8 cmake: introduce arch and soc cmake modules for hw model
v2
c9edefa8fd arch: add existing archs to archs.yml for HWMv2 support
61bbfb5ba2 scripts: introduce list_hardware.py for listing of
architectures and SoCs
a4d1980c35 build: board/ soc: introduce hw model v2 scheme
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
Signed-off-by: David Leach <david.leach@nxp.com>
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This commit is contained in:
Torsten Rasmussen
Anas Nashif
parent
418b0a1e65
commit
8dc3f85622
13315 changed files with 159282 additions and 157416 deletions
38
soc/nordic/CMakeLists.txt
Normal file
38
soc/nordic/CMakeLists.txt
Normal file
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@ -0,0 +1,38 @@
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# SPDX-License-Identifier: Apache-2.0
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zephyr_library()
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if(CONFIG_ARM)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "SoC Linker script")
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zephyr_library_sources(
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validate_base_addresses.c
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validate_enabled_instances.c
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)
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endif()
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if(CONFIG_SOC_HAS_TIMING_FUNCTIONS AND NOT CONFIG_BOARD_HAS_TIMING_FUNCTIONS)
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if(CONFIG_TIMING_FUNCTIONS)
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# Use nRF-specific timing calculations only if DWT is not present
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if(NOT CONFIG_CORTEX_M_DWT)
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zephyr_library_sources(timing.c)
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endif()
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endif()
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endif()
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if(CONFIG_BUILD_WITH_TFM)
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set_property(TARGET zephyr_property_target
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APPEND PROPERTY TFM_CMAKE_OPTIONS -DHAL_NORDIC_PATH=${ZEPHYR_HAL_NORDIC_MODULE_DIR}
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)
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set_property(TARGET zephyr_property_target
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APPEND PROPERTY TFM_CMAKE_OPTIONS -DZEPHYR_BASE=${ZEPHYR_BASE}
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)
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set_property(TARGET zephyr_property_target
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APPEND PROPERTY TFM_CMAKE_OPTIONS -DNRF_NS_STORAGE=${CONFIG_TFM_NRF_NS_STORAGE}
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)
|
||||
endif()
|
||||
|
||||
add_subdirectory(${SOC_SERIES})
|
||||
add_subdirectory(common)
|
||||
174
soc/nordic/Kconfig
Normal file
174
soc/nordic/Kconfig
Normal file
|
|
@ -0,0 +1,174 @@
|
|||
# Nordic Semiconductor nRFx MCU line
|
||||
|
||||
# Copyright (c) 2016-2018 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# This file is contains Zephyr build system Kconfig references and is not
|
||||
# re-usable outside the Zephyr tree.
|
||||
|
||||
config SOC_FAMILY_NORDIC_NRF
|
||||
select SOC_COMPATIBLE_NRF
|
||||
select PLATFORM_SPECIFIC_INIT if ARM
|
||||
|
||||
if SOC_FAMILY_NORDIC_NRF
|
||||
|
||||
rsource "common/Kconfig.peripherals"
|
||||
rsource "*/Kconfig"
|
||||
|
||||
config NRF_SOC_SECURE_SUPPORTED
|
||||
def_bool !TRUSTED_EXECUTION_NONSECURE || (BUILD_WITH_TFM && TFM_PARTITION_PLATFORM)
|
||||
depends on !SOC_SERIES_NRF54HX
|
||||
help
|
||||
Hidden function to indicate that that the soc_secure functions are
|
||||
available.
|
||||
The functions are always available when not in non-secure.
|
||||
For non-secure the functions must redirect to secure services exposed
|
||||
by the secure firmware.
|
||||
|
||||
config BUILD_WITH_TFM
|
||||
default y if TRUSTED_EXECUTION_NONSECURE
|
||||
help
|
||||
By default, if we build for a Non-Secure version of the board,
|
||||
enable building with TF-M as the Secure Execution Environment.
|
||||
|
||||
if BUILD_WITH_TFM
|
||||
|
||||
config TFM_FLASH_MERGED_BINARY
|
||||
default y
|
||||
help
|
||||
By default, if we build with TF-M, instruct build system to
|
||||
flash the combined TF-M (Secure) & Zephyr (Non Secure) image
|
||||
|
||||
config TFM_LOG_LEVEL_SILENCE
|
||||
default y if !$(dt_nodelabel_has_prop,uart1,pinctrl-names)
|
||||
help
|
||||
Disable TF-M secure output if the uart1 node has not assigned GPIO
|
||||
pins using pinctrl.
|
||||
|
||||
config TFM_NRF_NS_STORAGE
|
||||
bool "TF-M non-secure storage partition"
|
||||
default y
|
||||
|
||||
endif # BUILD_WITH_TFM
|
||||
|
||||
|
||||
config NRF_MPU_FLASH_REGION_SIZE
|
||||
hex
|
||||
default 0x1000
|
||||
depends on HAS_HW_NRF_MPU
|
||||
help
|
||||
FLASH region size for the NRF_MPU peripheral.
|
||||
|
||||
config NRF_BPROT_FLASH_REGION_SIZE
|
||||
hex
|
||||
default $(dt_node_int_prop_hex,$(DT_CHOSEN_ZEPHYR_FLASH),erase-block-size)
|
||||
depends on HAS_HW_NRF_BPROT
|
||||
help
|
||||
FLASH region size for the NRF_BPROT peripheral (nRF52).
|
||||
|
||||
config NRF_ACL_FLASH_REGION_SIZE
|
||||
hex
|
||||
default $(dt_node_int_prop_hex,$(DT_CHOSEN_ZEPHYR_FLASH),erase-block-size)
|
||||
depends on HAS_HW_NRF_ACL
|
||||
help
|
||||
FLASH region size for the NRF_ACL peripheral.
|
||||
|
||||
config NFCT_PINS_AS_GPIOS
|
||||
bool "[DEPRECATED] NFCT pins as GPIOs"
|
||||
depends on $(dt_has_compat,$(DT_COMPAT_NORDIC_NRF_NFCT))
|
||||
select DEPRECATED
|
||||
help
|
||||
Two pins are usually reserved for NFC in SoCs that implement the
|
||||
NFCT peripheral. This option switches them to normal GPIO mode.
|
||||
HW enabling happens once in the device lifetime, during the first
|
||||
system startup. Disabling this option will not switch back these
|
||||
pins to NFCT mode. Doing this requires UICR erase prior to
|
||||
flashing device using the image which has this option disabled.
|
||||
|
||||
NFC pins in nRF52 series: P0.09 and P0.10
|
||||
NFC pins in nRF5340: P0.02 and P0.03
|
||||
|
||||
This option is deprecated, please use devicetree to configure NFCT
|
||||
pins as GPIOS like this:
|
||||
|
||||
&uicr {
|
||||
nfct-pins-as-gpios;
|
||||
};
|
||||
|
||||
choice NRF_APPROTECT_HANDLING
|
||||
bool "APPROTECT handling"
|
||||
depends on SOC_SERIES_NRF52X || SOC_NRF5340_CPUNET || \
|
||||
(SOC_NRF5340_CPUAPP && !TRUSTED_EXECUTION_NONSECURE) || \
|
||||
SOC_SERIES_NRF91X
|
||||
default NRF_APPROTECT_USE_UICR
|
||||
help
|
||||
Specifies how the SystemInit() function should handle the APPROTECT
|
||||
mechanism.
|
||||
|
||||
config NRF_APPROTECT_USE_UICR
|
||||
bool "Use UICR"
|
||||
help
|
||||
When this option is selected, the SystemInit() function loads the
|
||||
firmware branch state of the APPROTECT mechanism from UICR, so if
|
||||
UICR->APPROTECT is disabled, CTRLAP->APPROTECT will be disabled.
|
||||
|
||||
config NRF_APPROTECT_LOCK
|
||||
bool "Lock"
|
||||
help
|
||||
When this option is selected, the SystemInit() function locks
|
||||
the firmware branch of the APPROTECT mechanism, preventing it
|
||||
from being opened.
|
||||
|
||||
config NRF_APPROTECT_USER_HANDLING
|
||||
bool "Allow user handling"
|
||||
depends on !SOC_SERIES_NRF52X
|
||||
help
|
||||
When this option is selected, the SystemInit() function does not
|
||||
touch the APPROTECT mechanism, allowing the user code to handle it
|
||||
at later stages, for example, to implement authenticated debug.
|
||||
|
||||
endchoice
|
||||
|
||||
choice NRF_SECURE_APPROTECT_HANDLING
|
||||
bool "Secure APPROTECT handling"
|
||||
depends on (SOC_NRF5340_CPUAPP && !TRUSTED_EXECUTION_NONSECURE)
|
||||
default NRF_SECURE_APPROTECT_USE_UICR
|
||||
help
|
||||
Specifies how the SystemInit() function should handle the secure
|
||||
APPROTECT mechanism.
|
||||
|
||||
config NRF_SECURE_APPROTECT_USE_UICR
|
||||
bool "Use UICR"
|
||||
help
|
||||
When this option is selected, the SystemInit() function loads the
|
||||
firmware branch state of the secure APPROTECT mechanism from UICR,
|
||||
so if UICR->SECUREAPPROTECT is disabled, CTRLAP->SECUREAPPROTECT
|
||||
will be disabled.
|
||||
|
||||
config NRF_SECURE_APPROTECT_LOCK
|
||||
bool "Lock"
|
||||
help
|
||||
When this option is selected, the SystemInit() function locks the
|
||||
firmware branch of the secure APPROTECT mechanism, preventing it
|
||||
from being opened.
|
||||
|
||||
config NRF_SECURE_APPROTECT_USER_HANDLING
|
||||
bool "Allow user handling"
|
||||
depends on !SOC_SERIES_NRF52X
|
||||
help
|
||||
When this option is selected, the SystemInit() function does not
|
||||
touch the secure APPROTECT mechanism, allowing the user code to
|
||||
handle it at later stages, for example, to implement authenticated
|
||||
debug.
|
||||
|
||||
endchoice
|
||||
|
||||
config NRF_TRACE_PORT
|
||||
bool "nRF TPIU"
|
||||
depends on !SOC_SERIES_NRF51X
|
||||
help
|
||||
Enable this option to initialize the TPIU (Trace Port Interface
|
||||
Unit) for tracing using a hardware probe. If disabled, the trace
|
||||
pins will be used as GPIO.
|
||||
|
||||
endif # SOC_FAMILY_NORDIC_NRF
|
||||
45
soc/nordic/Kconfig.defconfig
Normal file
45
soc/nordic/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
# Nordic Semiconductor nRFx MCU line
|
||||
|
||||
# Copyright (c) 2016-2018 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_FAMILY_NORDIC_NRF
|
||||
|
||||
rsource "*/Kconfig.defconfig"
|
||||
|
||||
# If the kernel has timer support, enable clock control
|
||||
if SYS_CLOCK_EXISTS
|
||||
|
||||
config CLOCK_CONTROL
|
||||
default y if !SOC_SERIES_NRF54HX
|
||||
|
||||
endif # SYS_CLOCK_EXISTS
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default 1000000 if NRF_GRTC_TIMER
|
||||
default 32768
|
||||
|
||||
config SYS_CLOCK_TICKS_PER_SEC
|
||||
default 128 if !TICKLESS_KERNEL
|
||||
default 10000 if NRF_GRTC_TIMER
|
||||
default 32768
|
||||
|
||||
config ARCH_HAS_CUSTOM_BUSY_WAIT
|
||||
default y if ARM && !QEMU_TARGET
|
||||
|
||||
config BUILD_OUTPUT_HEX
|
||||
default y
|
||||
|
||||
if !CORTEX_M_DWT && NRF_RTC_TIMER
|
||||
config SOC_HAS_TIMING_FUNCTIONS
|
||||
default y
|
||||
endif
|
||||
|
||||
config GPIO
|
||||
default y
|
||||
depends on SPI
|
||||
|
||||
config UART_USE_RUNTIME_CONFIGURE
|
||||
default n
|
||||
|
||||
endif # SOC_FAMILY_NORDIC_NRF
|
||||
59
soc/nordic/Kconfig.soc
Normal file
59
soc/nordic/Kconfig.soc
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
# Copyright (c) 2022 Nordic Semiconductor ASA
|
||||
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# This file contains Zephyr hw module v2 Kconfig description for
|
||||
# Nordic Semiconductor SoCs.
|
||||
# The hw model v2 is generic and contains no Kconfig references outside its own
|
||||
# tree structure and is therefore reusable in Kconfig trees outside a Zephyr build.
|
||||
|
||||
config SOC_SERIES
|
||||
default "nrf51" if SOC_SERIES_NRF51X
|
||||
default "nrf52" if SOC_SERIES_NRF52X
|
||||
default "nrf53" if SOC_SERIES_NRF53X
|
||||
default "nrf54h" if SOC_SERIES_NRF54HX
|
||||
default "nrf54l" if SOC_SERIES_NRF54LX
|
||||
default "nrf91" if SOC_SERIES_NRF91X
|
||||
|
||||
config SOC_FAMILY_NORDIC_NRF
|
||||
bool
|
||||
|
||||
config SOC_FAMILY
|
||||
default "nordic_nrf" if SOC_FAMILY_NORDIC_NRF
|
||||
|
||||
config SOC_SERIES_NRF51X
|
||||
bool
|
||||
help
|
||||
Enable support for NRF51 MCU series
|
||||
|
||||
config SOC_SERIES_NRF52X
|
||||
bool
|
||||
select SOC_FAMILY_NORDIC_NRF
|
||||
help
|
||||
Enable support for NRF52 MCU series
|
||||
|
||||
config SOC_SERIES_NRF53X
|
||||
bool
|
||||
select SOC_FAMILY_NORDIC_NRF
|
||||
help
|
||||
Enable support for NRF53 MCU series
|
||||
|
||||
config SOC_SERIES_NRF54HX
|
||||
bool
|
||||
select SOC_FAMILY_NORDIC_NRF
|
||||
help
|
||||
Nordic Semiconductor nRF54H series MCU
|
||||
|
||||
config SOC_SERIES_NRF54LX
|
||||
bool
|
||||
select SOC_FAMILY_NORDIC_NRF
|
||||
help
|
||||
Nordic Semiconductor nRF54L series MCU
|
||||
|
||||
config SOC_SERIES_NRF91X
|
||||
bool
|
||||
select SOC_FAMILY_NORDIC_NRF
|
||||
help
|
||||
Enable support for NRF91 MCU series
|
||||
|
||||
rsource "*/Kconfig.soc"
|
||||
19
soc/nordic/common/CMakeLists.txt
Normal file
19
soc/nordic/common/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
# Copyright (c) 2021 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
add_subdirectory_ifdef(CONFIG_RISCV_CORE_NORDIC_VPR vpr)
|
||||
|
||||
if(CONFIG_ARM AND CONFIG_SOC_FAMILY_NORDIC_NRF)
|
||||
zephyr_library_sources(soc_nrf_common.S)
|
||||
endif()
|
||||
|
||||
zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c)
|
||||
|
||||
zephyr_include_directories(.)
|
||||
|
||||
if(CONFIG_TFM_PARTITION_PLATFORM)
|
||||
zephyr_library_sources(soc_secure.c)
|
||||
zephyr_library_include_directories(
|
||||
$<TARGET_PROPERTY:tfm,TFM_BINARY_DIR>/api_ns/interface/include
|
||||
)
|
||||
endif()
|
||||
4
soc/nordic/common/Kconfig
Normal file
4
soc/nordic/common/Kconfig
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
# Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
rsource "vpr/Kconfig"
|
||||
8
soc/nordic/common/Kconfig.defconfig
Normal file
8
soc/nordic/common/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
# Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if RISCV_CORE_NORDIC_VPR
|
||||
|
||||
rsource "vpr/Kconfig.defconfig"
|
||||
|
||||
endif # RISCV_CORE_NORDIC_VPR
|
||||
547
soc/nordic/common/Kconfig.peripherals
Normal file
547
soc/nordic/common/Kconfig.peripherals
Normal file
|
|
@ -0,0 +1,547 @@
|
|||
# Nordic Semiconductor nRFx MCU peripherals list.
|
||||
|
||||
# Copyright (c) 2018 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config HAS_HW_NRF_ACL
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_ACL))
|
||||
|
||||
config HAS_HW_NRF_ADC
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_ADC))
|
||||
|
||||
config HAS_HW_NRF_BPROT
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_BPROT))
|
||||
|
||||
config HAS_HW_NRF_CC310
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_ARM_CRYPTOCELL_310))
|
||||
|
||||
config HAS_HW_NRF_CC312
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_ARM_CRYPTOCELL_312))
|
||||
|
||||
config HAS_HW_NRF_CCM
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_CCM))
|
||||
|
||||
config HAS_HW_NRF_CCM_LFLEN_8BIT
|
||||
def_bool $(dt_nodelabel_bool_prop,ccm,length-field-length-8-bits)
|
||||
|
||||
config HAS_HW_NRF_CCM_HEADERMASK
|
||||
def_bool $(dt_nodelabel_bool_prop,ccm,headermask-supported)
|
||||
|
||||
config HAS_HW_NRF_CLOCK
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_CLOCK))
|
||||
|
||||
config HAS_HW_NRF_COMP
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_COMP))
|
||||
|
||||
config HAS_HW_NRF_CTRLAP
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_CTRLAPPERI))
|
||||
|
||||
config HAS_HW_NRF_DCNF
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_DCNF))
|
||||
|
||||
config HAS_HW_NRF_DPPIC
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_DPPIC))
|
||||
|
||||
config HAS_HW_NRF_ECB
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_ECB))
|
||||
|
||||
config HAS_HW_NRF_EGU0
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,egu0,$(DT_COMPAT_NORDIC_NRF_EGU))
|
||||
|
||||
config HAS_HW_NRF_EGU1
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,egu1,$(DT_COMPAT_NORDIC_NRF_EGU))
|
||||
|
||||
config HAS_HW_NRF_EGU2
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,egu2,$(DT_COMPAT_NORDIC_NRF_EGU))
|
||||
|
||||
config HAS_HW_NRF_EGU3
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,egu3,$(DT_COMPAT_NORDIC_NRF_EGU))
|
||||
|
||||
config HAS_HW_NRF_EGU4
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,egu4,$(DT_COMPAT_NORDIC_NRF_EGU))
|
||||
|
||||
config HAS_HW_NRF_EGU5
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,egu5,$(DT_COMPAT_NORDIC_NRF_EGU))
|
||||
|
||||
config HAS_HW_NRF_EGU020
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,egu020,$(DT_COMPAT_NORDIC_NRF_EGU))
|
||||
|
||||
config HAS_HW_NRF_GPIO0
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,gpio0,$(DT_COMPAT_NORDIC_NRF_GPIO))
|
||||
|
||||
config HAS_HW_NRF_GPIO1
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,gpio1,$(DT_COMPAT_NORDIC_NRF_GPIO))
|
||||
|
||||
config HAS_HW_NRF_GPIOTE0
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,gpiote0,$(DT_COMPAT_NORDIC_NRF_GPIOTE))
|
||||
|
||||
config HAS_HW_NRF_GPIOTE1
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,gpiote1,$(DT_COMPAT_NORDIC_NRF_GPIOTE))
|
||||
|
||||
config HAS_HW_NRF_GPIOTE20
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,gpiote20,$(DT_COMPAT_NORDIC_NRF_GPIOTE))
|
||||
|
||||
config HAS_HW_NRF_GPIOTE30
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,gpiote30,$(DT_COMPAT_NORDIC_NRF_GPIOTE))
|
||||
|
||||
config HAS_HW_NRF_GPIOTE130
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,gpiote130,$(DT_COMPAT_NORDIC_NRF_GPIOTE))
|
||||
|
||||
config HAS_HW_NRF_GPIOTE131
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,gpiote131,$(DT_COMPAT_NORDIC_NRF_GPIOTE))
|
||||
|
||||
config HAS_HW_NRF_GRTC
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GRTC))
|
||||
|
||||
config HAS_HW_NRF_I2S0
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,i2s0,$(DT_COMPAT_NORDIC_NRF_I2S))
|
||||
|
||||
config HAS_HW_NRF_I2S20
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,i2s20,$(DT_COMPAT_NORDIC_NRF_I2S))
|
||||
|
||||
config HAS_HW_NRF_IPC
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_IPC))
|
||||
|
||||
config HAS_HW_NRF_KMU
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_KMU))
|
||||
|
||||
config HAS_HW_NRF_LPCOMP
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_LPCOMP))
|
||||
|
||||
config HAS_HW_NRF_MPU
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_MPU))
|
||||
|
||||
config HAS_HW_NRF_MUTEX
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_MUTEX))
|
||||
|
||||
config HAS_HW_NRF_MWU
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_MWU))
|
||||
|
||||
config HAS_HW_NRF_NFCT
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_NFCT))
|
||||
|
||||
config HAS_HW_NRF_NVMC_PE
|
||||
def_bool $(dt_nodelabel_bool_prop,flash_controller,partial-erase)
|
||||
|
||||
config HAS_HW_NRF_OSCILLATORS
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_OSCILLATORS))
|
||||
|
||||
config HAS_HW_NRF_PDM
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_PDM))
|
||||
|
||||
config HAS_HW_NRF_POWER
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_POWER))
|
||||
|
||||
config HAS_HW_NRF_PPI
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_PPI))
|
||||
|
||||
config HAS_HW_NRF_PWM0
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,pwm0,$(DT_COMPAT_NORDIC_NRF_PWM))
|
||||
|
||||
config HAS_HW_NRF_PWM1
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,pwm1,$(DT_COMPAT_NORDIC_NRF_PWM))
|
||||
|
||||
config HAS_HW_NRF_PWM2
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,pwm2,$(DT_COMPAT_NORDIC_NRF_PWM))
|
||||
|
||||
config HAS_HW_NRF_PWM3
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,pwm3,$(DT_COMPAT_NORDIC_NRF_PWM))
|
||||
|
||||
config HAS_HW_NRF_QDEC0
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,qdec0,$(DT_COMPAT_NORDIC_NRF_QDEC))
|
||||
|
||||
config HAS_HW_NRF_QDEC1
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,qdec1,$(DT_COMPAT_NORDIC_NRF_QDEC))
|
||||
|
||||
config HAS_HW_NRF_QDEC20
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,qdec20,$(DT_COMPAT_NORDIC_NRF_QDEC))
|
||||
|
||||
config HAS_HW_NRF_QDEC21
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,qdec21,$(DT_COMPAT_NORDIC_NRF_QDEC))
|
||||
|
||||
config HAS_HW_NRF_QDEC130
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,qdec130,$(DT_COMPAT_NORDIC_NRF_QDEC))
|
||||
|
||||
config HAS_HW_NRF_QDEC131
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,qdec131,$(DT_COMPAT_NORDIC_NRF_QDEC))
|
||||
|
||||
config HAS_HW_NRF_QSPI
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_QSPI))
|
||||
|
||||
config HAS_HW_NRF_RADIO_BLE_2M
|
||||
def_bool $(dt_nodelabel_bool_prop,radio,ble-2mbps-supported)
|
||||
|
||||
config HAS_HW_NRF_RADIO_BLE_CODED
|
||||
def_bool $(dt_nodelabel_bool_prop,radio,ble-coded-phy-supported)
|
||||
|
||||
config HAS_HW_NRF_RADIO_DFE
|
||||
def_bool $(dt_nodelabel_bool_prop,radio,dfe-supported)
|
||||
|
||||
config HAS_HW_NRF_RADIO_IEEE802154
|
||||
def_bool $(dt_nodelabel_bool_prop,radio,ieee802154-supported)
|
||||
|
||||
config HAS_HW_NRF_RADIO_TX_PWR_HIGH
|
||||
def_bool $(dt_nodelabel_bool_prop,radio,tx-high-power-supported)
|
||||
|
||||
config HAS_HW_NRF_REGULATORS
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_REGULATORS))
|
||||
|
||||
config HAS_HW_NRF_RESET
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_RESET))
|
||||
|
||||
config HAS_HW_NRF_RNG
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_RNG))
|
||||
|
||||
config HAS_HW_NRF_RTC0
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,rtc0,$(DT_COMPAT_NORDIC_NRF_RTC))
|
||||
|
||||
config HAS_HW_NRF_RTC1
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,rtc1,$(DT_COMPAT_NORDIC_NRF_RTC))
|
||||
|
||||
config HAS_HW_NRF_RTC2
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,rtc2,$(DT_COMPAT_NORDIC_NRF_RTC))
|
||||
|
||||
config HAS_HW_NRF_RTC130
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,rtc130,$(DT_COMPAT_NORDIC_NRF_RTC))
|
||||
|
||||
config HAS_HW_NRF_RTC131
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,rtc131,$(DT_COMPAT_NORDIC_NRF_RTC))
|
||||
|
||||
config HAS_HW_NRF_SAADC
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_SAADC))
|
||||
|
||||
config HAS_HW_NRF_SPI0
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi0,$(DT_COMPAT_NORDIC_NRF_SPI))
|
||||
|
||||
config HAS_HW_NRF_SPI1
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi1,$(DT_COMPAT_NORDIC_NRF_SPI))
|
||||
|
||||
config HAS_HW_NRF_SPI2
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi2,$(DT_COMPAT_NORDIC_NRF_SPI))
|
||||
|
||||
config HAS_HW_NRF_SPIM0
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi0,$(DT_COMPAT_NORDIC_NRF_SPIM))
|
||||
|
||||
config HAS_HW_NRF_SPIM1
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi1,$(DT_COMPAT_NORDIC_NRF_SPIM))
|
||||
|
||||
config HAS_HW_NRF_SPIM2
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi2,$(DT_COMPAT_NORDIC_NRF_SPIM))
|
||||
|
||||
config HAS_HW_NRF_SPIM3
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi3,$(DT_COMPAT_NORDIC_NRF_SPIM))
|
||||
|
||||
config HAS_HW_NRF_SPIM4
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi4,$(DT_COMPAT_NORDIC_NRF_SPIM))
|
||||
|
||||
config HAS_HW_NRF_SPIM00
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi00,$(DT_COMPAT_NORDIC_NRF_SPIM))
|
||||
|
||||
config HAS_HW_NRF_SPIM20
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi20,$(DT_COMPAT_NORDIC_NRF_SPIM))
|
||||
|
||||
config HAS_HW_NRF_SPIM21
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi21,$(DT_COMPAT_NORDIC_NRF_SPIM))
|
||||
|
||||
config HAS_HW_NRF_SPIM22
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi22,$(DT_COMPAT_NORDIC_NRF_SPIM))
|
||||
|
||||
config HAS_HW_NRF_SPIM30
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi30,$(DT_COMPAT_NORDIC_NRF_SPIM))
|
||||
|
||||
config HAS_HW_NRF_SPIM120
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi120,$(DT_COMPAT_NORDIC_NRF_SPIM))
|
||||
|
||||
config HAS_HW_NRF_SPIM121
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi121,$(DT_COMPAT_NORDIC_NRF_SPIM))
|
||||
|
||||
config HAS_HW_NRF_SPIM130
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi130,$(DT_COMPAT_NORDIC_NRF_SPIM))
|
||||
|
||||
config HAS_HW_NRF_SPIM131
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi131,$(DT_COMPAT_NORDIC_NRF_SPIM))
|
||||
|
||||
config HAS_HW_NRF_SPIM132
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi132,$(DT_COMPAT_NORDIC_NRF_SPIM))
|
||||
|
||||
config HAS_HW_NRF_SPIM133
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi133,$(DT_COMPAT_NORDIC_NRF_SPIM))
|
||||
|
||||
config HAS_HW_NRF_SPIM134
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi134,$(DT_COMPAT_NORDIC_NRF_SPIM))
|
||||
|
||||
config HAS_HW_NRF_SPIM135
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi135,$(DT_COMPAT_NORDIC_NRF_SPIM))
|
||||
|
||||
config HAS_HW_NRF_SPIM136
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi136,$(DT_COMPAT_NORDIC_NRF_SPIM))
|
||||
|
||||
config HAS_HW_NRF_SPIM137
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi137,$(DT_COMPAT_NORDIC_NRF_SPIM))
|
||||
|
||||
config HAS_HW_NRF_SPIS0
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi0,$(DT_COMPAT_NORDIC_NRF_SPIS))
|
||||
|
||||
config HAS_HW_NRF_SPIS1
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi1,$(DT_COMPAT_NORDIC_NRF_SPIS))
|
||||
|
||||
config HAS_HW_NRF_SPIS2
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi2,$(DT_COMPAT_NORDIC_NRF_SPIS))
|
||||
|
||||
config HAS_HW_NRF_SPIS3
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,spi3,$(DT_COMPAT_NORDIC_NRF_SPIS))
|
||||
|
||||
config HAS_HW_NRF_SPU
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_SPU))
|
||||
|
||||
config HAS_HW_NRF_SWI0
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,swi0,$(DT_COMPAT_NORDIC_NRF_SWI))
|
||||
|
||||
config HAS_HW_NRF_SWI1
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,swi1,$(DT_COMPAT_NORDIC_NRF_SWI))
|
||||
|
||||
config HAS_HW_NRF_SWI2
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,swi2,$(DT_COMPAT_NORDIC_NRF_SWI))
|
||||
|
||||
config HAS_HW_NRF_SWI3
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,swi3,$(DT_COMPAT_NORDIC_NRF_SWI))
|
||||
|
||||
config HAS_HW_NRF_SWI4
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,swi4,$(DT_COMPAT_NORDIC_NRF_SWI))
|
||||
|
||||
config HAS_HW_NRF_SWI5
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,swi5,$(DT_COMPAT_NORDIC_NRF_SWI))
|
||||
|
||||
config HAS_HW_NRF_TEMP
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_TEMP))
|
||||
|
||||
config HAS_HW_NRF_TIMER0
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,timer0,$(DT_COMPAT_NORDIC_NRF_TIMER))
|
||||
|
||||
config HAS_HW_NRF_TIMER1
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,timer1,$(DT_COMPAT_NORDIC_NRF_TIMER))
|
||||
|
||||
config HAS_HW_NRF_TIMER2
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,timer2,$(DT_COMPAT_NORDIC_NRF_TIMER))
|
||||
|
||||
config HAS_HW_NRF_TIMER3
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,timer3,$(DT_COMPAT_NORDIC_NRF_TIMER))
|
||||
|
||||
config HAS_HW_NRF_TIMER4
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,timer4,$(DT_COMPAT_NORDIC_NRF_TIMER))
|
||||
|
||||
config HAS_HW_NRF_TIMER00
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,timer00,$(DT_COMPAT_NORDIC_NRF_TIMER))
|
||||
|
||||
config HAS_HW_NRF_TIMER10
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,timer10,$(DT_COMPAT_NORDIC_NRF_TIMER))
|
||||
|
||||
config HAS_HW_NRF_TIMER20
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,timer20,$(DT_COMPAT_NORDIC_NRF_TIMER))
|
||||
|
||||
config HAS_HW_NRF_TIMER21
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,timer21,$(DT_COMPAT_NORDIC_NRF_TIMER))
|
||||
|
||||
config HAS_HW_NRF_TIMER22
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,timer22,$(DT_COMPAT_NORDIC_NRF_TIMER))
|
||||
|
||||
config HAS_HW_NRF_TIMER23
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,timer23,$(DT_COMPAT_NORDIC_NRF_TIMER))
|
||||
|
||||
config HAS_HW_NRF_TIMER24
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,timer24,$(DT_COMPAT_NORDIC_NRF_TIMER))
|
||||
|
||||
config HAS_HW_NRF_TIMER020
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,timer020,$(DT_COMPAT_NORDIC_NRF_TIMER))
|
||||
|
||||
config HAS_HW_NRF_TIMER021
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,timer021,$(DT_COMPAT_NORDIC_NRF_TIMER))
|
||||
|
||||
config HAS_HW_NRF_TIMER022
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,timer022,$(DT_COMPAT_NORDIC_NRF_TIMER))
|
||||
|
||||
config HAS_HW_NRF_TIMER120
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,timer120,$(DT_COMPAT_NORDIC_NRF_TIMER))
|
||||
|
||||
config HAS_HW_NRF_TIMER121
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,timer121,$(DT_COMPAT_NORDIC_NRF_TIMER))
|
||||
|
||||
config HAS_HW_NRF_TIMER130
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,timer130,$(DT_COMPAT_NORDIC_NRF_TIMER))
|
||||
|
||||
config HAS_HW_NRF_TIMER131
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,timer131,$(DT_COMPAT_NORDIC_NRF_TIMER))
|
||||
|
||||
config HAS_HW_NRF_TIMER132
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,timer132,$(DT_COMPAT_NORDIC_NRF_TIMER))
|
||||
|
||||
config HAS_HW_NRF_TIMER133
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,timer133,$(DT_COMPAT_NORDIC_NRF_TIMER))
|
||||
|
||||
config HAS_HW_NRF_TIMER134
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,timer134,$(DT_COMPAT_NORDIC_NRF_TIMER))
|
||||
|
||||
config HAS_HW_NRF_TIMER135
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,timer135,$(DT_COMPAT_NORDIC_NRF_TIMER))
|
||||
|
||||
config HAS_HW_NRF_TIMER136
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,timer136,$(DT_COMPAT_NORDIC_NRF_TIMER))
|
||||
|
||||
config HAS_HW_NRF_TIMER137
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,timer137,$(DT_COMPAT_NORDIC_NRF_TIMER))
|
||||
|
||||
config HAS_HW_NRF_TWI0
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,i2c0,$(DT_COMPAT_NORDIC_NRF_TWI))
|
||||
|
||||
config HAS_HW_NRF_TWI1
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,i2c1,$(DT_COMPAT_NORDIC_NRF_TWI))
|
||||
|
||||
config HAS_HW_NRF_TWIM0
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,i2c0,$(DT_COMPAT_NORDIC_NRF_TWIM))
|
||||
|
||||
config HAS_HW_NRF_TWIM1
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,i2c1,$(DT_COMPAT_NORDIC_NRF_TWIM))
|
||||
|
||||
config HAS_HW_NRF_TWIM2
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,i2c2,$(DT_COMPAT_NORDIC_NRF_TWIM))
|
||||
|
||||
config HAS_HW_NRF_TWIM3
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,i2c3,$(DT_COMPAT_NORDIC_NRF_TWIM))
|
||||
|
||||
config HAS_HW_NRF_TWIM20
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,i2c20,$(DT_COMPAT_NORDIC_NRF_TWIM))
|
||||
|
||||
config HAS_HW_NRF_TWIM21
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,i2c21,$(DT_COMPAT_NORDIC_NRF_TWIM))
|
||||
|
||||
config HAS_HW_NRF_TWIM22
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,i2c22,$(DT_COMPAT_NORDIC_NRF_TWIM))
|
||||
|
||||
config HAS_HW_NRF_TWIM30
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,i2c30,$(DT_COMPAT_NORDIC_NRF_TWIM))
|
||||
|
||||
config HAS_HW_NRF_TWIM120
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,i2c120,$(DT_COMPAT_NORDIC_NRF_TWIM))
|
||||
|
||||
config HAS_HW_NRF_TWIM130
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,i2c130,$(DT_COMPAT_NORDIC_NRF_TWIM))
|
||||
|
||||
config HAS_HW_NRF_TWIM131
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,i2c131,$(DT_COMPAT_NORDIC_NRF_TWIM))
|
||||
|
||||
config HAS_HW_NRF_TWIM132
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,i2c132,$(DT_COMPAT_NORDIC_NRF_TWIM))
|
||||
|
||||
config HAS_HW_NRF_TWIM133
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,i2c133,$(DT_COMPAT_NORDIC_NRF_TWIM))
|
||||
|
||||
config HAS_HW_NRF_TWIM134
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,i2c134,$(DT_COMPAT_NORDIC_NRF_TWIM))
|
||||
|
||||
config HAS_HW_NRF_TWIM135
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,i2c135,$(DT_COMPAT_NORDIC_NRF_TWIM))
|
||||
|
||||
config HAS_HW_NRF_TWIM136
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,i2c136,$(DT_COMPAT_NORDIC_NRF_TWIM))
|
||||
|
||||
config HAS_HW_NRF_TWIM137
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,i2c137,$(DT_COMPAT_NORDIC_NRF_TWIM))
|
||||
|
||||
config HAS_HW_NRF_TWIS0
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,i2c0,$(DT_COMPAT_NORDIC_NRF_TWIS))
|
||||
|
||||
config HAS_HW_NRF_TWIS1
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,i2c1,$(DT_COMPAT_NORDIC_NRF_TWIS))
|
||||
|
||||
config HAS_HW_NRF_TWIS2
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,i2c2,$(DT_COMPAT_NORDIC_NRF_TWIS))
|
||||
|
||||
config HAS_HW_NRF_TWIS3
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,i2c3,$(DT_COMPAT_NORDIC_NRF_TWIS))
|
||||
|
||||
config HAS_HW_NRF_UART0
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,uart0,$(DT_COMPAT_NORDIC_NRF_UART))
|
||||
|
||||
config HAS_HW_NRF_UARTE0
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,uart0,$(DT_COMPAT_NORDIC_NRF_UARTE))
|
||||
|
||||
config HAS_HW_NRF_UARTE1
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,uart1,$(DT_COMPAT_NORDIC_NRF_UARTE))
|
||||
|
||||
config HAS_HW_NRF_UARTE2
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,uart2,$(DT_COMPAT_NORDIC_NRF_UARTE))
|
||||
|
||||
config HAS_HW_NRF_UARTE3
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,uart3,$(DT_COMPAT_NORDIC_NRF_UARTE))
|
||||
|
||||
config HAS_HW_NRF_UARTE00
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,uart00,$(DT_COMPAT_NORDIC_NRF_UARTE))
|
||||
|
||||
config HAS_HW_NRF_UARTE20
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,uart20,$(DT_COMPAT_NORDIC_NRF_UARTE))
|
||||
|
||||
config HAS_HW_NRF_UARTE21
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,uart21,$(DT_COMPAT_NORDIC_NRF_UARTE))
|
||||
|
||||
config HAS_HW_NRF_UARTE22
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,uart22,$(DT_COMPAT_NORDIC_NRF_UARTE))
|
||||
|
||||
config HAS_HW_NRF_UARTE30
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,uart30,$(DT_COMPAT_NORDIC_NRF_UARTE))
|
||||
|
||||
config HAS_HW_NRF_UARTE120
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,uart120,$(DT_COMPAT_NORDIC_NRF_UARTE))
|
||||
|
||||
config HAS_HW_NRF_UARTE130
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,uart130,$(DT_COMPAT_NORDIC_NRF_UARTE))
|
||||
|
||||
config HAS_HW_NRF_UARTE131
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,uart131,$(DT_COMPAT_NORDIC_NRF_UARTE))
|
||||
|
||||
config HAS_HW_NRF_UARTE132
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,uart132,$(DT_COMPAT_NORDIC_NRF_UARTE))
|
||||
|
||||
config HAS_HW_NRF_UARTE133
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,uart133,$(DT_COMPAT_NORDIC_NRF_UARTE))
|
||||
|
||||
config HAS_HW_NRF_UARTE134
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,uart134,$(DT_COMPAT_NORDIC_NRF_UARTE))
|
||||
|
||||
config HAS_HW_NRF_UARTE135
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,uart135,$(DT_COMPAT_NORDIC_NRF_UARTE))
|
||||
|
||||
config HAS_HW_NRF_UARTE136
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,uart136,$(DT_COMPAT_NORDIC_NRF_UARTE))
|
||||
|
||||
config HAS_HW_NRF_UARTE137
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,uart137,$(DT_COMPAT_NORDIC_NRF_UARTE))
|
||||
|
||||
config HAS_HW_NRF_USBD
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_USBD))
|
||||
|
||||
config HAS_HW_NRF_USBREG
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_USBREG))
|
||||
|
||||
config HAS_HW_NRF_VMC
|
||||
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_VMC))
|
||||
|
||||
config HAS_HW_NRF_WDT0
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,wdt0,$(DT_COMPAT_NORDIC_NRF_WDT))
|
||||
|
||||
config HAS_HW_NRF_WDT1
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,wdt1,$(DT_COMPAT_NORDIC_NRF_WDT))
|
||||
|
||||
config HAS_HW_NRF_WDT30
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,wdt30,$(DT_COMPAT_NORDIC_NRF_WDT))
|
||||
|
||||
config HAS_HW_NRF_WDT31
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,wdt31,$(DT_COMPAT_NORDIC_NRF_WDT))
|
||||
|
||||
config HAS_HW_NRF_WDT130
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,wdt130,$(DT_COMPAT_NORDIC_NRF_WDT))
|
||||
|
||||
config HAS_HW_NRF_WDT131
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,wdt131,$(DT_COMPAT_NORDIC_NRF_WDT))
|
||||
|
||||
config HAS_HW_NRF_WDT132
|
||||
def_bool $(dt_nodelabel_enabled_with_compat,wdt132,$(DT_COMPAT_NORDIC_NRF_WDT))
|
||||
103
soc/nordic/common/pinctrl_soc.h
Normal file
103
soc/nordic/common/pinctrl_soc.h
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* nRF SoC specific helpers for pinctrl driver
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_ARM_NORDIC_NRF_COMMON_PINCTRL_SOC_H_
|
||||
#define ZEPHYR_SOC_ARM_NORDIC_NRF_COMMON_PINCTRL_SOC_H_
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/dt-bindings/pinctrl/nrf-pinctrl.h>
|
||||
#include <zephyr/types.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @cond INTERNAL_HIDDEN */
|
||||
|
||||
/** Type for nRF pin. */
|
||||
typedef uint32_t pinctrl_soc_pin_t;
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize each pin.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param prop Property name.
|
||||
* @param idx Property entry index.
|
||||
*/
|
||||
#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
|
||||
(DT_PROP_BY_IDX(node_id, prop, idx) | \
|
||||
((NRF_PULL_DOWN * DT_PROP(node_id, bias_pull_down)) << NRF_PULL_POS) |\
|
||||
((NRF_PULL_UP * DT_PROP(node_id, bias_pull_up)) << NRF_PULL_POS) | \
|
||||
(DT_PROP(node_id, nordic_drive_mode) << NRF_DRIVE_POS) | \
|
||||
((NRF_LP_ENABLE * DT_PROP(node_id, low_power_enable)) << NRF_LP_POS) |\
|
||||
(DT_PROP(node_id, nordic_invert) << NRF_INVERT_POS) \
|
||||
),
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize state pins contained in a given property.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param prop Property name describing state pins.
|
||||
*/
|
||||
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
|
||||
DT_FOREACH_PROP_ELEM, psels, \
|
||||
Z_PINCTRL_STATE_PIN_INIT)}
|
||||
|
||||
/**
|
||||
* @brief Utility macro to obtain pin function.
|
||||
*
|
||||
* @param pincfg Pin configuration bit field.
|
||||
*/
|
||||
#define NRF_GET_FUN(pincfg) (((pincfg) >> NRF_FUN_POS) & NRF_FUN_MSK)
|
||||
|
||||
/**
|
||||
* @brief Utility macro to obtain pin inversion flag.
|
||||
*
|
||||
* @param pincfg Pin configuration bit field.
|
||||
*/
|
||||
#define NRF_GET_INVERT(pincfg) (((pincfg) >> NRF_INVERT_POS) & NRF_INVERT_MSK)
|
||||
|
||||
/**
|
||||
* @brief Utility macro to obtain pin low power flag.
|
||||
*
|
||||
* @param pincfg Pin configuration bit field.
|
||||
*/
|
||||
#define NRF_GET_LP(pincfg) (((pincfg) >> NRF_LP_POS) & NRF_LP_MSK)
|
||||
|
||||
/**
|
||||
* @brief Utility macro to obtain pin drive mode.
|
||||
*
|
||||
* @param pincfg Pin configuration bit field.
|
||||
*/
|
||||
#define NRF_GET_DRIVE(pincfg) (((pincfg) >> NRF_DRIVE_POS) & NRF_DRIVE_MSK)
|
||||
|
||||
/**
|
||||
* @brief Utility macro to obtain pin pull configuration.
|
||||
*
|
||||
* @param pincfg Pin configuration bit field.
|
||||
*/
|
||||
#define NRF_GET_PULL(pincfg) (((pincfg) >> NRF_PULL_POS) & NRF_PULL_MSK)
|
||||
|
||||
/**
|
||||
* @brief Utility macro to obtain port and pin combination.
|
||||
*
|
||||
* @param pincfg Pin configuration bit field.
|
||||
*/
|
||||
#define NRF_GET_PIN(pincfg) (((pincfg) >> NRF_PIN_POS) & NRF_PIN_MSK)
|
||||
|
||||
/** @endcond */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ZEPHYR_SOC_ARM_NORDIC_NRF_COMMON_PINCTRL_SOC_H_ */
|
||||
24
soc/nordic/common/poweroff.c
Normal file
24
soc/nordic/common/poweroff.c
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Nordic Semiconductor ASA
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/sys/poweroff.h>
|
||||
#include <zephyr/toolchain.h>
|
||||
|
||||
#if defined(CONFIG_SOC_SERIES_NRF51X) || defined(CONFIG_SOC_SERIES_NRF52X)
|
||||
#include <hal/nrf_power.h>
|
||||
#else
|
||||
#include <hal/nrf_regulators.h>
|
||||
#endif
|
||||
|
||||
void z_sys_poweroff(void)
|
||||
{
|
||||
#if defined(CONFIG_SOC_SERIES_NRF51X) || defined(CONFIG_SOC_SERIES_NRF52X)
|
||||
nrf_power_system_off(NRF_POWER);
|
||||
#else
|
||||
nrf_regulators_system_off(NRF_REGULATORS);
|
||||
#endif
|
||||
|
||||
CODE_UNREACHABLE;
|
||||
}
|
||||
34
soc/nordic/common/soc_nrf_common.S
Normal file
34
soc/nordic/common/soc_nrf_common.S
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief System/hardware module for Nordic Semiconductor nRFxx family processors
|
||||
*/
|
||||
|
||||
#include <zephyr/toolchain.h>
|
||||
#include <zephyr/linker/sections.h>
|
||||
|
||||
_ASM_FILE_PROLOGUE
|
||||
|
||||
GTEXT(SystemInit)
|
||||
GTEXT(z_arm_platform_init)
|
||||
|
||||
SECTION_FUNC(TEXT, z_arm_platform_init)
|
||||
|
||||
/* Implement z_arm_platform_init() directly in ASM,
|
||||
* and ensure no stack access is performed until
|
||||
* we jump to SystemInit().
|
||||
*/
|
||||
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
|
||||
ldr r0, =SystemInit
|
||||
bx r0
|
||||
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
|
||||
b SystemInit
|
||||
#else
|
||||
#error "Unsupported architecture"
|
||||
#endif
|
||||
/* Return occurs via SystemInit */
|
||||
241
soc/nordic/common/soc_nrf_common.h
Normal file
241
soc/nordic/common/soc_nrf_common.h
Normal file
|
|
@ -0,0 +1,241 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Nordic Semiconductor ASA
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file Common soc.h include for Nordic nRF5 SoCs.
|
||||
*/
|
||||
|
||||
#ifndef _ZEPHYR_SOC_ARM_NORDIC_NRF_SOC_NRF_COMMON_H_
|
||||
#define _ZEPHYR_SOC_ARM_NORDIC_NRF_SOC_NRF_COMMON_H_
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
#include <nrfx.h>
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/toolchain.h>
|
||||
|
||||
/**
|
||||
* @brief Get a PSEL value out of a foo-gpios or foo-pin devicetree property
|
||||
*
|
||||
* Many Nordic bindings have 'foo-pin' properties to specify a pin
|
||||
* configuration as a PSEL value directly instead of using a 'foo-gpios'
|
||||
* <&gpioX Y flags> style controller phandle + GPIO specifier.
|
||||
*
|
||||
* It would be better to use 'foo-gpios' properties instead. This type
|
||||
* of property is more in line with the recommended DT encoding for GPIOs.
|
||||
*
|
||||
* To allow for a smooth migration from 'foo-pin' to 'foo-gpios', this
|
||||
* helper macro can be used to get a PSEL value out of the devicetree
|
||||
* using whichever one of 'foo-gpios' or 'foo-pin' is in the DTS.
|
||||
*
|
||||
* Note that you can also use:
|
||||
*
|
||||
* - NRF_DT_PSEL_CHECK_*() to check the property configuration at build time
|
||||
* - NRF_DT_GPIOS_TO_PSEL() if you only have a 'foo-gpios'
|
||||
*
|
||||
* @param node_id node identifier
|
||||
* @param psel_prop lowercase-and-underscores old-style 'foo-pin' property
|
||||
* @param gpios_prop new-style 'foo-gpios' property
|
||||
* @param default_val the value returned if neither is set
|
||||
* @return PSEL register value taken from psel_prop or gpios_prop, whichever
|
||||
* is present in the DTS. If gpios_prop is present, it is converted
|
||||
* to a PSEL register value first.
|
||||
*/
|
||||
#define NRF_DT_PSEL(node_id, psel_prop, gpios_prop, default_val) \
|
||||
COND_CODE_1(DT_NODE_HAS_PROP(node_id, psel_prop), \
|
||||
(DT_PROP(node_id, psel_prop)), \
|
||||
(COND_CODE_1( \
|
||||
DT_NODE_HAS_PROP(node_id, gpios_prop), \
|
||||
(NRF_DT_GPIOS_TO_PSEL(node_id, \
|
||||
gpios_prop)), \
|
||||
(default_val))))
|
||||
|
||||
/**
|
||||
* Error out the build if the devicetree node with identifier
|
||||
* 'node_id' has both a legacy psel-style property and a gpios
|
||||
* property.
|
||||
*
|
||||
* Otherwise, do nothing.
|
||||
*
|
||||
* @param node_id node identifier
|
||||
* @param psel_prop lowercase-and-underscores PSEL style property
|
||||
* @param psel_prop_name human-readable string name of psel_prop
|
||||
* @param gpios_prop lowercase-and-underscores foo-gpios style property
|
||||
* @param gpio_prop_name human-readable string name of gpios_prop
|
||||
*/
|
||||
#define NRF_DT_PSEL_CHECK_NOT_BOTH(node_id, psel_prop, psel_prop_name, \
|
||||
gpios_prop, gpios_prop_name) \
|
||||
BUILD_ASSERT( \
|
||||
!(DT_NODE_HAS_PROP(node_id, psel_prop) && \
|
||||
DT_NODE_HAS_PROP(node_id, gpios_prop)), \
|
||||
"Devicetree node " DT_NODE_PATH(node_id) \
|
||||
" has both of the " psel_prop_name \
|
||||
" and " gpios_prop_name \
|
||||
" properties set; you must remove one. " \
|
||||
"Note: you can use /delete-property/ to delete properties.")
|
||||
|
||||
/**
|
||||
* Like NRF_DT_PSEL_CHECK_NOT_BOTH, but instead checks that exactly one
|
||||
* of the properties is set.
|
||||
*/
|
||||
#define NRF_DT_PSEL_CHECK_EXACTLY_ONE(node_id, \
|
||||
psel_prop, psel_prop_name, \
|
||||
gpios_prop, gpios_prop_name) \
|
||||
BUILD_ASSERT( \
|
||||
(DT_NODE_HAS_PROP(node_id, psel_prop) ^ \
|
||||
DT_NODE_HAS_PROP(node_id, gpios_prop)), \
|
||||
"Devicetree node " DT_NODE_PATH(node_id) \
|
||||
" must have exactly one of the " psel_prop_name \
|
||||
" and " gpios_prop_name \
|
||||
" properties set. " \
|
||||
"Note: you can use /delete-property/ to delete properties.")
|
||||
|
||||
/**
|
||||
* @brief Convert a devicetree GPIO phandle+specifier to PSEL value
|
||||
*
|
||||
* Various peripherals in nRF SoCs have pin select registers, which
|
||||
* usually have PSEL in their names. The low bits of these registers
|
||||
* generally look like this in the register map description:
|
||||
*
|
||||
* Bit number 5 4 3 2 1 0
|
||||
* ID B A A A A A
|
||||
*
|
||||
* ID Field Value Description
|
||||
* A PIN [0..31] Pin number
|
||||
* B PORT [0..1] Port number
|
||||
*
|
||||
* Examples:
|
||||
*
|
||||
* - pin P0.4 has "PSEL value" 4 (B=0 and A=4)
|
||||
* - pin P1.5 has "PSEL value" 37 (B=1 and A=5)
|
||||
*
|
||||
* This macro converts a devicetree GPIO phandle array value
|
||||
* "<&gpioX pin ...>" to a "PSEL value".
|
||||
*
|
||||
* Note: in Nordic SoC devicetrees, "gpio0" means P0, and "gpio1"
|
||||
* means P1. This is encoded in the "port" property of each GPIO node.
|
||||
*
|
||||
* Examples:
|
||||
*
|
||||
* foo: my-node {
|
||||
* tx-gpios = <&gpio0 4 ...>;
|
||||
* rx-gpios = <&gpio0 5 ...>, <&gpio1 5 ...>;
|
||||
* };
|
||||
*
|
||||
* NRF_DT_GPIOS_TO_PSEL_BY_IDX(DT_NODELABEL(foo), tx_gpios, 0) // 0 + 4 = 4
|
||||
* NRF_DT_GPIOS_TO_PSEL_BY_IDX(DT_NODELABEL(foo), rx_gpios, 1) // 32 + 5 = 37
|
||||
*/
|
||||
#define NRF_DT_GPIOS_TO_PSEL_BY_IDX(node_id, prop, idx) \
|
||||
((DT_PROP_BY_PHANDLE_IDX(node_id, prop, idx, port) << 5) | \
|
||||
(DT_GPIO_PIN_BY_IDX(node_id, prop, idx) & 0x1F))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Equivalent to NRF_DT_GPIOS_TO_PSEL_BY_IDX(node_id, prop, 0)
|
||||
*/
|
||||
#define NRF_DT_GPIOS_TO_PSEL(node_id, prop) \
|
||||
NRF_DT_GPIOS_TO_PSEL_BY_IDX(node_id, prop, 0)
|
||||
|
||||
/**
|
||||
* If the node has the property, expands to
|
||||
* NRF_DT_GPIOS_TO_PSEL(node_id, prop). The default_value argument is
|
||||
* not expanded in this case.
|
||||
*
|
||||
* Otherwise, expands to default_value.
|
||||
*/
|
||||
#define NRF_DT_GPIOS_TO_PSEL_OR(node_id, prop, default_value) \
|
||||
COND_CODE_1(DT_NODE_HAS_PROP(node_id, prop), \
|
||||
(NRF_DT_GPIOS_TO_PSEL(node_id, prop)), \
|
||||
(default_value))
|
||||
|
||||
/**
|
||||
* @brief Convert a devicetree GPIO phandle+specifier to GPIOTE instance number.
|
||||
*
|
||||
* Some of nRF SoCs may have more instances of GPIOTE.
|
||||
* To handle this, we use the "gpiote-instance" property of the GPIO node.
|
||||
*
|
||||
* This macro converts a devicetree GPIO phandle array value
|
||||
* "<&gpioX pin ...>" to a GPIOTE instance number.
|
||||
*
|
||||
* Examples:
|
||||
*
|
||||
* &gpiote0 {
|
||||
* instance = <0>;
|
||||
* };
|
||||
*
|
||||
* &gpiote20 {
|
||||
* instance = <20>;
|
||||
* };
|
||||
*
|
||||
* &gpio0 {
|
||||
* gpiote-instance = <&gpiote0>;
|
||||
* }
|
||||
*
|
||||
* &gpio1 {
|
||||
* gpiote-instance = <&gpiote20>;
|
||||
* }
|
||||
*
|
||||
* foo: my-node {
|
||||
* tx-gpios = <&gpio0 4 ...>;
|
||||
* rx-gpios = <&gpio0 5 ...>, <&gpio1 5 ...>;
|
||||
* };
|
||||
*
|
||||
* NRF_DT_GPIOTE_INST_BY_IDX(DT_NODELABEL(foo), tx_gpios, 0) // = 0
|
||||
* NRF_DT_GPIOTE_INST_BY_IDX(DT_NODELABEL(foo), rx_gpios, 1) // = 20
|
||||
*/
|
||||
#define NRF_DT_GPIOTE_INST_BY_IDX(node_id, prop, idx) \
|
||||
DT_PROP(DT_PHANDLE(DT_GPIO_CTLR_BY_IDX(node_id, prop, idx), \
|
||||
gpiote_instance), \
|
||||
instance)
|
||||
|
||||
/**
|
||||
* @brief Equivalent to NRF_DT_GPIOTE_INST_BY_IDX(node_id, prop, 0)
|
||||
*/
|
||||
#define NRF_DT_GPIOTE_INST(node_id, prop) \
|
||||
NRF_DT_GPIOTE_INST_BY_IDX(node_id, prop, 0)
|
||||
|
||||
/**
|
||||
* Error out the build if 'prop' is set on node 'node_id' and
|
||||
* DT_GPIO_CTLR(node_id, prop) is not an SoC GPIO controller,
|
||||
* i.e. a node with compatible "nordic,nrf-gpio".
|
||||
*
|
||||
* Otherwise, do nothing.
|
||||
*
|
||||
* @param node_id node identifier
|
||||
* @param prop lowercase-and-underscores PSEL style property
|
||||
* @param prop_name human-readable string name for 'prop'
|
||||
*/
|
||||
#define NRF_DT_CHECK_GPIO_CTLR_IS_SOC(node_id, prop, prop_name) \
|
||||
COND_CODE_1(DT_NODE_HAS_PROP(node_id, prop), \
|
||||
(BUILD_ASSERT(DT_NODE_HAS_COMPAT( \
|
||||
DT_GPIO_CTLR(node_id, prop), \
|
||||
nordic_nrf_gpio), \
|
||||
"Devicetree node " \
|
||||
DT_NODE_PATH(node_id) \
|
||||
" property " prop_name \
|
||||
" must refer to a GPIO controller " \
|
||||
"with compatible nordic,nrf-gpio; " \
|
||||
"got " \
|
||||
DT_NODE_PATH(DT_GPIO_CTLR(node_id, \
|
||||
prop)) \
|
||||
", which does not have this " \
|
||||
"compatible")), \
|
||||
(BUILD_ASSERT(1, \
|
||||
"NRF_DT_CHECK_GPIO_CTLR_IS_SOC: OK")))
|
||||
/* Note: allow a trailing ";" either way */
|
||||
|
||||
/**
|
||||
* Error out the build if CONFIG_PM_DEVICE=y and pinctrl-1 state (sleep) is not
|
||||
* defined.
|
||||
*
|
||||
* @param node_id node identifier
|
||||
*/
|
||||
#define NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP(node_id) \
|
||||
BUILD_ASSERT(!IS_ENABLED(CONFIG_PM_DEVICE) || \
|
||||
DT_PINCTRL_HAS_NAME(node_id, sleep), \
|
||||
DT_NODE_PATH(node_id) " defined without sleep state")
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif
|
||||
47
soc/nordic/common/soc_secure.c
Normal file
47
soc/nordic/common/soc_secure.c
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <soc_secure.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include "nrf.h"
|
||||
|
||||
#include "tfm_platform_api.h"
|
||||
#include "tfm_ioctl_api.h"
|
||||
|
||||
#if NRF_GPIO_HAS_SEL
|
||||
void soc_secure_gpio_pin_mcu_select(uint32_t pin_number, nrf_gpio_pin_sel_t mcu)
|
||||
{
|
||||
uint32_t result;
|
||||
enum tfm_platform_err_t err;
|
||||
|
||||
err = tfm_platform_gpio_pin_mcu_select(pin_number, mcu, &result);
|
||||
__ASSERT(err == TFM_PLATFORM_ERR_SUCCESS, "TFM platform error (%d)", err);
|
||||
__ASSERT(result == 0, "GPIO service error (%d)", result);
|
||||
}
|
||||
#endif /* NRF_GPIO_HAS_SEL */
|
||||
|
||||
int soc_secure_mem_read(void *dst, void *src, size_t len)
|
||||
{
|
||||
enum tfm_platform_err_t status;
|
||||
uint32_t result;
|
||||
|
||||
status = tfm_platform_mem_read(dst, (uintptr_t)src, len, &result);
|
||||
|
||||
switch (status) {
|
||||
case TFM_PLATFORM_ERR_INVALID_PARAM:
|
||||
return -EINVAL;
|
||||
case TFM_PLATFORM_ERR_NOT_SUPPORTED:
|
||||
return -ENOTSUP;
|
||||
case TFM_PLATFORM_ERR_SUCCESS:
|
||||
if (result == 0) {
|
||||
return 0;
|
||||
}
|
||||
/* Fallthrough */
|
||||
default:
|
||||
return -EPERM;
|
||||
}
|
||||
}
|
||||
71
soc/nordic/common/soc_secure.h
Normal file
71
soc/nordic/common/soc_secure.h
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
/*
|
||||
* Copyright (c) 2019 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <stdint.h>
|
||||
#include <nrf.h>
|
||||
#include <hal/nrf_gpio.h>
|
||||
#include <hal/nrf_ficr.h>
|
||||
|
||||
#if defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
|
||||
#if NRF_GPIO_HAS_SEL
|
||||
void soc_secure_gpio_pin_mcu_select(uint32_t pin_number, nrf_gpio_pin_sel_t mcu);
|
||||
#endif
|
||||
|
||||
int soc_secure_mem_read(void *dst, void *src, size_t len);
|
||||
|
||||
#if defined(CONFIG_SOC_HFXO_CAP_INTERNAL)
|
||||
static inline uint32_t soc_secure_read_xosc32mtrim(void)
|
||||
{
|
||||
uint32_t xosc32mtrim;
|
||||
int err;
|
||||
|
||||
err = soc_secure_mem_read(&xosc32mtrim,
|
||||
(void *)&NRF_FICR_S->XOSC32MTRIM,
|
||||
sizeof(xosc32mtrim));
|
||||
__ASSERT(err == 0, "Secure read error (%d)", err);
|
||||
|
||||
return xosc32mtrim;
|
||||
}
|
||||
#endif /* defined(CONFIG_SOC_HFXO_CAP_INTERNAL) */
|
||||
|
||||
static inline void soc_secure_read_deviceid(uint32_t deviceid[2])
|
||||
{
|
||||
int err;
|
||||
|
||||
err = soc_secure_mem_read(deviceid,
|
||||
(void *)&NRF_FICR_S->INFO.DEVICEID,
|
||||
2 * sizeof(uint32_t));
|
||||
__ASSERT(err == 0, "Secure read error (%d)", err);
|
||||
}
|
||||
|
||||
#else /* defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) */
|
||||
|
||||
static inline int soc_secure_mem_read(void *dst, void *src, size_t len)
|
||||
{
|
||||
(void)memcpy(dst, src, len);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if NRF_GPIO_HAS_SEL
|
||||
static inline void soc_secure_gpio_pin_mcu_select(uint32_t pin_number,
|
||||
nrf_gpio_pin_sel_t mcu)
|
||||
{
|
||||
nrf_gpio_pin_control_select(pin_number, mcu);
|
||||
}
|
||||
#endif /* NRF_GPIO_HAS_SEL */
|
||||
|
||||
#if defined(CONFIG_SOC_HFXO_CAP_INTERNAL)
|
||||
static inline uint32_t soc_secure_read_xosc32mtrim(void)
|
||||
{
|
||||
return NRF_FICR->XOSC32MTRIM;
|
||||
}
|
||||
#endif /* defined(CONFIG_SOC_HFXO_CAP_INTERNAL) */
|
||||
|
||||
static inline void soc_secure_read_deviceid(uint32_t deviceid[2])
|
||||
{
|
||||
deviceid[0] = nrf_ficr_deviceid_get(NRF_FICR, 0);
|
||||
deviceid[1] = nrf_ficr_deviceid_get(NRF_FICR, 1);
|
||||
}
|
||||
#endif /* defined CONFIG_TRUSTED_EXECUTION_NONSECURE */
|
||||
8
soc/nordic/common/vpr/CMakeLists.txt
Normal file
8
soc/nordic/common/vpr/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
# Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_include_directories(.)
|
||||
|
||||
zephyr_library_sources(soc_irq.S soc_irq.c vector.S)
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
|
||||
19
soc/nordic/common/vpr/Kconfig
Normal file
19
soc/nordic/common/vpr/Kconfig
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
# Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config RISCV_CORE_NORDIC_VPR
|
||||
bool "RISC-V Nordic VPR core"
|
||||
default y
|
||||
depends on DT_HAS_NORDIC_VPR_ENABLED
|
||||
select RISCV
|
||||
select ATOMIC_OPERATIONS_C
|
||||
select RISCV_ISA_RV32E
|
||||
select RISCV_ISA_EXT_M
|
||||
select RISCV_ISA_EXT_C
|
||||
select RISCV_ISA_EXT_ZICSR
|
||||
select RISCV_ISA_EXT_ZIFENCEI
|
||||
select RISCV_SOC_HAS_ISR_STACKING
|
||||
select RISCV_SOC_CONTEXT_SAVE
|
||||
select HAS_FLASH_LOAD_OFFSET if XIP
|
||||
help
|
||||
Enable support for the RISC-V Nordic VPR core.
|
||||
27
soc/nordic/common/vpr/Kconfig.defconfig
Normal file
27
soc/nordic/common/vpr/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
# Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
CPU_PATH := $(dt_nodelabel_path,cpu)
|
||||
CPU_ID := $(dt_node_reg_addr_int,$(CPU_PATH))
|
||||
|
||||
config RV_BOOT_HART
|
||||
default $(CPU_ID)
|
||||
|
||||
config RISCV_MCAUSE_EXCEPTION_MASK
|
||||
default 0xFFF
|
||||
|
||||
config RISCV_RESERVED_IRQ_ISR_TABLES_OFFSET
|
||||
default 16
|
||||
|
||||
config GEN_IRQ_VECTOR_TABLE
|
||||
default y
|
||||
|
||||
choice IRQ_VECTOR_TABLE_TYPE
|
||||
default IRQ_VECTOR_TABLE_JUMP_BY_ADDRESS
|
||||
endchoice
|
||||
|
||||
config ARCH_SW_ISR_TABLE_ALIGN
|
||||
default 64
|
||||
|
||||
config RISCV_ALWAYS_SWITCH_THROUGH_ECALL
|
||||
default y if MULTITHREADING
|
||||
12
soc/nordic/common/vpr/soc_context.h
Normal file
12
soc/nordic/common/vpr/soc_context.h
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (C) 2024 Nordic Semiconductor ASA
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef SOC_RISCV_NORDIC_NRF_COMMON_VPR_SOC_CONTEXT_H_
|
||||
#define SOC_RISCV_NORDIC_NRF_COMMON_VPR_SOC_CONTEXT_H_
|
||||
|
||||
#define SOC_ESF_MEMBERS unsigned long minttresh
|
||||
#define SOC_ESF_INIT 0
|
||||
|
||||
#endif /* SOC_RISCV_NORDIC_NRF_COMMON_VPR_SOC_CONTEXT_H_ */
|
||||
30
soc/nordic/common/vpr/soc_irq.S
Normal file
30
soc/nordic/common/vpr/soc_irq.S
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* Copyright (C) 2024 Nordic Semiconductor ASA
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <offsets.h>
|
||||
#include <zephyr/toolchain.h>
|
||||
|
||||
/* Exports */
|
||||
GTEXT(__soc_handle_irq)
|
||||
GTEXT(__soc_save_context)
|
||||
GTEXT(__soc_restore_context)
|
||||
|
||||
/*
|
||||
* No need to clear anything, pending bit is cleared by HW.
|
||||
*/
|
||||
SECTION_FUNC(exception.other, __soc_handle_irq)
|
||||
ret
|
||||
|
||||
SECTION_FUNC(exception.other, __soc_save_context)
|
||||
csrr t0, 0x347
|
||||
sw t0, __soc_esf_t_minttresh_OFFSET(a0)
|
||||
|
||||
ret
|
||||
|
||||
SECTION_FUNC(exception.other, __soc_restore_context)
|
||||
lw t0, __soc_esf_t_minttresh_OFFSET(a0)
|
||||
csrw 0x347, t0
|
||||
|
||||
ret
|
||||
26
soc/nordic/common/vpr/soc_irq.c
Normal file
26
soc/nordic/common/vpr/soc_irq.c
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* Copyright (C) 2024 Nordic Semiconductor ASA
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <hal/nrf_vpr_clic.h>
|
||||
|
||||
void arch_irq_enable(unsigned int irq)
|
||||
{
|
||||
nrf_vpr_clic_int_enable_set(NRF_VPRCLIC, irq, true);
|
||||
}
|
||||
|
||||
void arch_irq_disable(unsigned int irq)
|
||||
{
|
||||
nrf_vpr_clic_int_enable_set(NRF_VPRCLIC, irq, false);
|
||||
}
|
||||
|
||||
void arch_irq_priority_set(unsigned int irq, unsigned int prio)
|
||||
{
|
||||
nrf_vpr_clic_int_priority_set(NRF_VPRCLIC, irq, prio);
|
||||
}
|
||||
|
||||
int arch_irq_is_enabled(unsigned int irq)
|
||||
{
|
||||
return nrf_vpr_clic_int_enable_check(NRF_VPRCLIC, irq);
|
||||
}
|
||||
118
soc/nordic/common/vpr/soc_isr_stacking.h
Normal file
118
soc/nordic/common/vpr/soc_isr_stacking.h
Normal file
|
|
@ -0,0 +1,118 @@
|
|||
/*
|
||||
* Copyright (C) 2024 Nordic Semiconductor ASA
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef SOC_RISCV_NORDIC_NRF_COMMON_VPR_SOC_ISR_STACKING_H_
|
||||
#define SOC_RISCV_NORDIC_NRF_COMMON_VPR_SOC_ISR_STACKING_H_
|
||||
|
||||
#include <zephyr/arch/riscv/irq.h>
|
||||
|
||||
#if !defined(_ASMLANGUAGE)
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
|
||||
#define VPR_CPU DT_INST(0, nordic_vpr)
|
||||
|
||||
#if DT_PROP(VPR_CPU, nordic_bus_width) == 64
|
||||
|
||||
#define SOC_ISR_STACKING_ESF_DECLARE \
|
||||
struct __esf { \
|
||||
unsigned long s0; \
|
||||
unsigned long mstatus; \
|
||||
unsigned long tp; \
|
||||
struct soc_esf soc_context; \
|
||||
\
|
||||
unsigned long t2; \
|
||||
unsigned long ra; \
|
||||
unsigned long t0; \
|
||||
unsigned long t1; \
|
||||
unsigned long a4; \
|
||||
unsigned long a5; \
|
||||
unsigned long a2; \
|
||||
unsigned long a3; \
|
||||
unsigned long a0; \
|
||||
unsigned long a1; \
|
||||
unsigned long mepc; \
|
||||
unsigned long _mcause; \
|
||||
} __aligned(16);
|
||||
|
||||
#else /* DT_PROP(VPR_CPU, nordic_bus_width) == 32 */
|
||||
|
||||
#define SOC_ISR_STACKING_ESF_DECLARE \
|
||||
struct __esf { \
|
||||
unsigned long s0; \
|
||||
unsigned long mstatus; \
|
||||
unsigned long tp; \
|
||||
struct soc_esf soc_context; \
|
||||
\
|
||||
unsigned long ra; \
|
||||
unsigned long t2; \
|
||||
unsigned long t1; \
|
||||
unsigned long t0; \
|
||||
unsigned long a5; \
|
||||
unsigned long a4; \
|
||||
unsigned long a3; \
|
||||
unsigned long a2; \
|
||||
unsigned long a1; \
|
||||
unsigned long a0; \
|
||||
unsigned long mepc; \
|
||||
unsigned long _mcause; \
|
||||
} __aligned(16);
|
||||
|
||||
#endif /* DT_PROP(VPR_CPU, nordic_bus_width) == 64 */
|
||||
|
||||
#else /* _ASMLANGUAGE */
|
||||
|
||||
/*
|
||||
* Size of the HW managed part of the ESF:
|
||||
* sizeof(_mcause) + sizeof(_mepc)
|
||||
*/
|
||||
#define ESF_HW_SIZEOF (0x8)
|
||||
|
||||
/*
|
||||
* Size of the SW managed part of the ESF in case of exception
|
||||
*/
|
||||
#define ESF_SW_EXC_SIZEOF (__z_arch_esf_t_SIZEOF - ESF_HW_SIZEOF)
|
||||
|
||||
/*
|
||||
* Size of the SW managed part of the ESF in case of interrupt
|
||||
* sizeof(__padding) + ... + sizeof(soc_context)
|
||||
*/
|
||||
#define ESF_SW_IRQ_SIZEOF (0x10)
|
||||
|
||||
#define SOC_ISR_SW_STACKING \
|
||||
csrw mscratch, t0; \
|
||||
\
|
||||
csrr t0, mcause; \
|
||||
srli t0, t0, RISCV_MCAUSE_IRQ_POS; \
|
||||
bnez t0, stacking_is_interrupt; \
|
||||
\
|
||||
csrrw t0, mscratch, zero; \
|
||||
\
|
||||
addi sp, sp, -ESF_SW_EXC_SIZEOF; \
|
||||
DO_CALLER_SAVED(sr); \
|
||||
j stacking_keep_going; \
|
||||
\
|
||||
stacking_is_interrupt: \
|
||||
addi sp, sp, -ESF_SW_IRQ_SIZEOF; \
|
||||
\
|
||||
stacking_keep_going:
|
||||
|
||||
#define SOC_ISR_SW_UNSTACKING \
|
||||
csrr t0, mcause; \
|
||||
srli t0, t0, RISCV_MCAUSE_IRQ_POS; \
|
||||
bnez t0, unstacking_is_interrupt; \
|
||||
\
|
||||
DO_CALLER_SAVED(lr); \
|
||||
addi sp, sp, ESF_SW_EXC_SIZEOF; \
|
||||
j unstacking_keep_going; \
|
||||
\
|
||||
unstacking_is_interrupt: \
|
||||
addi sp, sp, ESF_SW_IRQ_SIZEOF; \
|
||||
\
|
||||
unstacking_keep_going:
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#endif /* SOC_RISCV_NORDIC_NRF_COMMON_VPR_SOC_ISR_STACKING_H_ */
|
||||
11
soc/nordic/common/vpr/soc_offsets.h
Normal file
11
soc/nordic/common/vpr/soc_offsets.h
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/*
|
||||
* Copyright (C) 2024 Nordic Semiconductor ASA
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef SOC_RISCV_NORDIC_NRF_COMMON_VPR_SOC_OFFSETS_H_
|
||||
#define SOC_RISCV_NORDIC_NRF_COMMON_VPR_SOC_OFFSETS_H_
|
||||
|
||||
#define GEN_SOC_OFFSET_SYMS() GEN_OFFSET_SYM(soc_esf_t, minttresh)
|
||||
|
||||
#endif /* SOC_RISCV_NORDIC_NRF_COMMON_VPR_SOC_OFFSETS_H_ */
|
||||
28
soc/nordic/common/vpr/vector.S
Normal file
28
soc/nordic/common/vpr/vector.S
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* Copyright (C) 2024 Nordic Semiconductor ASA
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/toolchain.h>
|
||||
|
||||
/* Imports */
|
||||
GTEXT(__initialize)
|
||||
|
||||
/* Exports */
|
||||
GTEXT(__start)
|
||||
|
||||
SECTION_FUNC(vectors, __start)
|
||||
/* Set mtvec.base (mtvec.mode is RO, no need to mask it). */
|
||||
la t0, _isr_wrapper
|
||||
csrw mtvec, t0
|
||||
|
||||
/* Set mtvt. */
|
||||
la t0, _irq_vector_table
|
||||
csrw 0x307, t0
|
||||
|
||||
/* Enable mstatus.mie */
|
||||
li t0, 0x1888
|
||||
csrw mstatus, t0
|
||||
|
||||
/* Call into Zephyr initialization. */
|
||||
tail __initialize
|
||||
4
soc/nordic/nrf51/CMakeLists.txt
Normal file
4
soc/nordic/nrf51/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_library_sources(soc.c)
|
||||
zephyr_include_directories(.)
|
||||
13
soc/nordic/nrf51/Kconfig
Normal file
13
soc/nordic/nrf51/Kconfig
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
# Nordic Semiconductor nRF51 MCU line
|
||||
|
||||
# Copyright (c) 2016 Linaro Limited
|
||||
# Copyright (c) 2018 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_NRF51X
|
||||
select ARM
|
||||
select CPU_CORTEX_M0
|
||||
imply XIP
|
||||
select HAS_NRFX
|
||||
select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
|
||||
select HAS_POWEROFF
|
||||
16
soc/nordic/nrf51/Kconfig.defconfig
Normal file
16
soc/nordic/nrf51/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
# Nordic Semiconductor nRF51 MCU line
|
||||
|
||||
# Copyright (c) 2016 Linaro Limited
|
||||
# Copyright (c) 2018 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_NRF51X
|
||||
|
||||
config NUM_IRQS
|
||||
default 26
|
||||
|
||||
# If the kernel has timer support, enable the timer
|
||||
config NRF_RTC_TIMER
|
||||
default y if SYS_CLOCK_EXISTS
|
||||
|
||||
endif # SOC_SERIES_NRF51X
|
||||
24
soc/nordic/nrf51/Kconfig.soc
Normal file
24
soc/nordic/nrf51/Kconfig.soc
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
# Nordic Semiconductor nRF51 MCU line
|
||||
|
||||
# Copyright (c) 2016 Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_NRF51X
|
||||
select SOC_FAMILY_NORDIC_NRF
|
||||
help
|
||||
Enable support for NRF51 MCU series
|
||||
|
||||
config SOC_NRF51822_QFAA
|
||||
bool
|
||||
select SOC_SERIES_NRF51X
|
||||
|
||||
config SOC_NRF51822_QFAB
|
||||
bool
|
||||
select SOC_SERIES_NRF51X
|
||||
|
||||
config SOC_NRF51822_QFAC
|
||||
bool
|
||||
select SOC_SERIES_NRF51X
|
||||
|
||||
config SOC
|
||||
default "nrf51822" if SOC_NRF51822_QFAA || SOC_NRF51822_QFAB || SOC_NRF51822_QFAC
|
||||
34
soc/nordic/nrf51/soc.c
Normal file
34
soc/nordic/nrf51/soc.c
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Nordic Semiconductor ASA
|
||||
* Copyright (c) 2016 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief System/hardware module for Nordic Semiconductor nRF51 family processor
|
||||
*
|
||||
* This module provides routines to initialize and support board-level hardware
|
||||
* for the Nordic Semiconductor nRF51 family processor.
|
||||
*/
|
||||
|
||||
#include <zephyr/kernel.h>
|
||||
#include <hal/nrf_power.h>
|
||||
#include <soc/nrfx_coredep.h>
|
||||
#include <zephyr/logging/log.h>
|
||||
|
||||
#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
|
||||
LOG_MODULE_REGISTER(soc);
|
||||
|
||||
#define DELAY_CALL_OVERHEAD_US 2
|
||||
|
||||
void arch_busy_wait(uint32_t time_us)
|
||||
{
|
||||
if (time_us <= DELAY_CALL_OVERHEAD_US) {
|
||||
return;
|
||||
}
|
||||
|
||||
time_us -= DELAY_CALL_OVERHEAD_US;
|
||||
nrfx_coredep_delay_us(time_us);
|
||||
}
|
||||
23
soc/nordic/nrf51/soc.h
Normal file
23
soc/nordic/nrf51/soc.h
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SoC configuration macros for the Nordic nRF51 family processors.
|
||||
*/
|
||||
|
||||
#ifndef _NORDICSEMI_NRF51_SOC_H_
|
||||
#define _NORDICSEMI_NRF51_SOC_H_
|
||||
|
||||
#include <soc_nrf_common.h>
|
||||
|
||||
#define NRF51_POWER_RAMON_ADDRESS 0x40000524
|
||||
#define NRF51_POWER_RAMONB_ADDRESS 0x40000554
|
||||
#define NRF51_POWER_RAMONx_RAMxON_ONMODE_Msk 0x3
|
||||
|
||||
#define FLASH_PAGE_ERASE_MAX_TIME_US 22300UL
|
||||
#define FLASH_PAGE_MAX_CNT 256UL
|
||||
|
||||
#endif /* _NORDICSEMI_NRF51_SOC_H_ */
|
||||
16
soc/nordic/nrf52/CMakeLists.txt
Normal file
16
soc/nordic/nrf52/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_library_sources(soc.c)
|
||||
zephyr_include_directories(.)
|
||||
|
||||
if(CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58 AND CONFIG_SPI_NRFX_SPIM)
|
||||
message(WARNING "Both SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58 and an NRF SPIM driver are enabled, therefore PAN 58 will apply if RXD.MAXCNT == 1 and TXD.MAXCNT <= 1")
|
||||
endif()
|
||||
|
||||
if(CONFIG_SOC_NRF52832)
|
||||
if(NOT CONFIG_NRF52_ANOMALY_109_WORKAROUND)
|
||||
if (CONFIG_NRFX_SPIS OR CONFIG_NRFX_SPIM OR CONFIG_NRFX_TWIM OR CONFIG_NRFX_PWM)
|
||||
message(WARNING "NRF52_ANOMALY_109_WORKAROUND disabled with SPIS, SPIM, TWIM or PWM enabled. This will occasionally cause the first byte transmitted to be incorrect")
|
||||
endif()
|
||||
endif()
|
||||
endif()
|
||||
106
soc/nordic/nrf52/Kconfig
Normal file
106
soc/nordic/nrf52/Kconfig
Normal file
|
|
@ -0,0 +1,106 @@
|
|||
# Nordic Semiconductor nRF52 MCU line
|
||||
|
||||
# Copyright (c) 2016-2023 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_NRF52X
|
||||
select ARM
|
||||
select SOC_COMPATIBLE_NRF52X
|
||||
select CPU_CORTEX_M4
|
||||
select CPU_HAS_ARM_MPU
|
||||
imply XIP
|
||||
select HAS_NRFX
|
||||
select HAS_NORDIC_DRIVERS
|
||||
select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
|
||||
select HAS_SWO
|
||||
select HAS_POWEROFF
|
||||
|
||||
config SOC_NRF52832
|
||||
select CPU_CORTEX_M_HAS_DWT
|
||||
select CPU_HAS_FPU
|
||||
|
||||
config SOC_NRF52833
|
||||
select SOC_COMPATIBLE_NRF52833
|
||||
select CPU_CORTEX_M_HAS_DWT
|
||||
select CPU_HAS_FPU
|
||||
|
||||
config SOC_NRF52840
|
||||
select CPU_CORTEX_M_HAS_DWT
|
||||
select CPU_HAS_FPU
|
||||
|
||||
if SOC_SERIES_NRF52X
|
||||
|
||||
config SOC_DCDC_NRF52X
|
||||
bool
|
||||
help
|
||||
Enable nRF52 series System on Chip DC/DC converter.
|
||||
|
||||
config SOC_DCDC_NRF52X_HV
|
||||
bool
|
||||
depends on SOC_NRF52840_QIAA
|
||||
help
|
||||
Enable nRF52 series System on Chip High Voltage DC/DC converter.
|
||||
|
||||
config GPIO_AS_PINRESET
|
||||
bool "[DEPRECATED] GPIO as pin reset (reset button)"
|
||||
select DEPRECATED
|
||||
help
|
||||
This option is deprecated, use devicetree instead. Example
|
||||
configuration:
|
||||
|
||||
&uicr {
|
||||
gpio-as-nreset;
|
||||
};
|
||||
|
||||
config NRF_ENABLE_ICACHE
|
||||
bool "The instruction cache (I-Cache)"
|
||||
depends on SOC_NRF52832 || SOC_NRF52833 || SOC_NRF52840
|
||||
default y
|
||||
|
||||
config NRF52_ANOMALY_132_DELAY_US
|
||||
int "Anomaly 132 workaround delay (microseconds)"
|
||||
default 330
|
||||
range 0 330
|
||||
depends on NRF52_ANOMALY_132_WORKAROUND
|
||||
help
|
||||
Due to Anomaly 132 LF RC source may not start if restarted in certain
|
||||
window after stopping (230 us to 330 us). Software reset also stops the
|
||||
clock so if clock is initiated in certain window, the clock may also fail
|
||||
to start at reboot. A delay is added before starting LF clock to ensure
|
||||
that anomaly conditions are not met. Delay should be long enough to ensure
|
||||
that clock is started later than 330 us after reset. If crystal oscillator
|
||||
(XO) is used then low frequency clock initially starts with RC and then
|
||||
seamlessly switches to XO which has much longer startup time thus,
|
||||
depending on application, workaround may also need to be applied.
|
||||
Additional drivers initialization increases initialization time and delay
|
||||
may be shortened. Workaround is disabled by setting delay to 0.
|
||||
|
||||
config NRF52_ANOMALY_198_WORKAROUND
|
||||
bool "Anomaly 198 workaround"
|
||||
default y
|
||||
depends on SOC_NRF52840
|
||||
depends on NRFX_SPIM3
|
||||
help
|
||||
This anomaly applies to IC revisions "Engineering B" up to "3", the most
|
||||
recent one.
|
||||
|
||||
config NRF52_ANOMALY_109_WORKAROUND
|
||||
bool "Anomaly 109 workaround"
|
||||
default y
|
||||
depends on SOC_NRF52832
|
||||
depends on NRFX_SPIS || NRFX_SPIM || NRFX_TWIM || NRFX_PWM
|
||||
help
|
||||
Due to Anomaly 109 the first byte sent out by these peripherals is
|
||||
sometimes wrong. This occurs when the system enters IDLE and stops the
|
||||
64MHz clock at the same time as the peripheral that is using DMA is started.
|
||||
This anomaly applies to IC revisions up to "3", the most recent one.
|
||||
|
||||
config NRF52_ANOMALY_109_WORKAROUND_EGU_INSTANCE
|
||||
int "Anomaly 109 workaround EGU instance"
|
||||
depends on NRF52_ANOMALY_109_WORKAROUND
|
||||
range 0 5
|
||||
default 5
|
||||
help
|
||||
EGU instance used by the nRF52 Anomaly 109 workaround for PWM.
|
||||
|
||||
endif # SOC_SERIES_NRF52X
|
||||
14
soc/nordic/nrf52/Kconfig.defconfig
Normal file
14
soc/nordic/nrf52/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
# Nordic Semiconductor nRF52 MCU line
|
||||
|
||||
# Copyright (c) 2016-2018 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_NRF52X
|
||||
|
||||
rsource "Kconfig.defconfig.nrf52*"
|
||||
|
||||
# If the kernel has timer support, enable the timer
|
||||
config NRF_RTC_TIMER
|
||||
default y if SYS_CLOCK_EXISTS
|
||||
|
||||
endif # SOC_SERIES_NRF52X
|
||||
11
soc/nordic/nrf52/Kconfig.defconfig.nrf52805_CAAA
Normal file
11
soc/nordic/nrf52/Kconfig.defconfig.nrf52805_CAAA
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
# Nordic Semiconductor nRF52805 MCU
|
||||
|
||||
# Copyright (c) 2020 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_NRF52805_CAAA
|
||||
|
||||
config NUM_IRQS
|
||||
default 26
|
||||
|
||||
endif # SOC_NRF52805_CAAA
|
||||
11
soc/nordic/nrf52/Kconfig.defconfig.nrf52810_QFAA
Normal file
11
soc/nordic/nrf52/Kconfig.defconfig.nrf52810_QFAA
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
# Nordic Semiconductor nRF52810 MCU
|
||||
|
||||
# Copyright (c) 2018 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_NRF52810_QFAA
|
||||
|
||||
config NUM_IRQS
|
||||
default 30
|
||||
|
||||
endif # SOC_NRF52810_QFAA
|
||||
11
soc/nordic/nrf52/Kconfig.defconfig.nrf52811_QFAA
Normal file
11
soc/nordic/nrf52/Kconfig.defconfig.nrf52811_QFAA
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
# Nordic Semiconductor nRF52811 MCU
|
||||
|
||||
# Copyright (c) 2019 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_NRF52811_QFAA
|
||||
|
||||
config NUM_IRQS
|
||||
default 30
|
||||
|
||||
endif # SOC_NRF52811_QFAA
|
||||
12
soc/nordic/nrf52/Kconfig.defconfig.nrf52820_QDAA
Normal file
12
soc/nordic/nrf52/Kconfig.defconfig.nrf52820_QDAA
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
# Nordic Semiconductor nRF52820 MCU
|
||||
|
||||
# Copyright (c) 2020 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_NRF52820_QDAA
|
||||
|
||||
config NUM_IRQS
|
||||
int
|
||||
default 40
|
||||
|
||||
endif # SOC_NRF52820_QDAA
|
||||
15
soc/nordic/nrf52/Kconfig.defconfig.nrf52832_CIAA
Normal file
15
soc/nordic/nrf52/Kconfig.defconfig.nrf52832_CIAA
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
# Nordic Semiconductor nRF52832 MCU
|
||||
|
||||
# Copyright (c) 2019 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_NRF52832_CIAA
|
||||
|
||||
config NUM_IRQS
|
||||
default 39
|
||||
|
||||
config NRF52_ANOMALY_132_WORKAROUND
|
||||
bool
|
||||
default y
|
||||
|
||||
endif # SOC_NRF52832_CIAA
|
||||
15
soc/nordic/nrf52/Kconfig.defconfig.nrf52832_QFAA
Normal file
15
soc/nordic/nrf52/Kconfig.defconfig.nrf52832_QFAA
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
# Nordic Semiconductor nRF52832 MCU
|
||||
|
||||
# Copyright (c) 2016 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_NRF52832_QFAA
|
||||
|
||||
config NUM_IRQS
|
||||
default 39
|
||||
|
||||
config NRF52_ANOMALY_132_WORKAROUND
|
||||
bool
|
||||
default y
|
||||
|
||||
endif # SOC_NRF52832_QFAA
|
||||
15
soc/nordic/nrf52/Kconfig.defconfig.nrf52832_QFAB
Normal file
15
soc/nordic/nrf52/Kconfig.defconfig.nrf52832_QFAB
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
# Nordic Semiconductor nRF52832 MCU
|
||||
|
||||
# Copyright (c) 2019 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_NRF52832_QFAB
|
||||
|
||||
config NUM_IRQS
|
||||
default 39
|
||||
|
||||
config NRF52_ANOMALY_132_WORKAROUND
|
||||
bool
|
||||
default y
|
||||
|
||||
endif # SOC_NRF52832_QFAB
|
||||
12
soc/nordic/nrf52/Kconfig.defconfig.nrf52833_QDAA
Normal file
12
soc/nordic/nrf52/Kconfig.defconfig.nrf52833_QDAA
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
# Nordic Semiconductor nRF52833 MCU
|
||||
|
||||
# Copyright (c) 2023 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_NRF52833_QDAA
|
||||
|
||||
config NUM_IRQS
|
||||
int
|
||||
default 48
|
||||
|
||||
endif # SOC_NRF52833_QDAA
|
||||
12
soc/nordic/nrf52/Kconfig.defconfig.nrf52833_QIAA
Normal file
12
soc/nordic/nrf52/Kconfig.defconfig.nrf52833_QIAA
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
# Nordic Semiconductor nRF52833 MCU
|
||||
|
||||
# Copyright (c) 2019 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_NRF52833_QIAA
|
||||
|
||||
config NUM_IRQS
|
||||
int
|
||||
default 48
|
||||
|
||||
endif # SOC_NRF52833_QIAA
|
||||
11
soc/nordic/nrf52/Kconfig.defconfig.nrf52840_QFAA
Normal file
11
soc/nordic/nrf52/Kconfig.defconfig.nrf52840_QFAA
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
# Nordic Semiconductor nRF52840 MCU
|
||||
|
||||
# Copyright (c) 2023 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_NRF52840_QFAA
|
||||
|
||||
config NUM_IRQS
|
||||
default 48
|
||||
|
||||
endif # SOC_NRF52840_QFAA
|
||||
11
soc/nordic/nrf52/Kconfig.defconfig.nrf52840_QIAA
Normal file
11
soc/nordic/nrf52/Kconfig.defconfig.nrf52840_QIAA
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
# Nordic Semiconductor nRF52840 MCU
|
||||
|
||||
# Copyright (c) 2016 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_NRF52840_QIAA
|
||||
|
||||
config NUM_IRQS
|
||||
default 48
|
||||
|
||||
endif # SOC_NRF52840_QIAA
|
||||
90
soc/nordic/nrf52/Kconfig.soc
Normal file
90
soc/nordic/nrf52/Kconfig.soc
Normal file
|
|
@ -0,0 +1,90 @@
|
|||
# Nordic Semiconductor nRF52 MCU line, Zephyr hw model v2 compliant
|
||||
|
||||
# Copyright (c) 2022-2023 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_NRF52X
|
||||
select SOC_FAMILY_NORDIC_NRF
|
||||
help
|
||||
Enable support for NRF52 MCU series
|
||||
|
||||
config SOC_NRF52805
|
||||
bool
|
||||
select SOC_SERIES_NRF52X
|
||||
|
||||
config SOC_NRF52810
|
||||
bool
|
||||
select SOC_SERIES_NRF52X
|
||||
|
||||
config SOC_NRF52811
|
||||
bool
|
||||
select SOC_SERIES_NRF52X
|
||||
|
||||
config SOC_NRF52820
|
||||
bool
|
||||
select SOC_SERIES_NRF52X
|
||||
|
||||
config SOC_NRF52832
|
||||
bool
|
||||
select SOC_SERIES_NRF52X
|
||||
|
||||
config SOC_NRF52833
|
||||
bool
|
||||
select SOC_SERIES_NRF52X
|
||||
|
||||
config SOC_NRF52840
|
||||
bool
|
||||
select SOC_SERIES_NRF52X
|
||||
|
||||
config SOC_NRF52805_CAAA
|
||||
bool
|
||||
select SOC_NRF52805
|
||||
|
||||
config SOC_NRF52810_QFAA
|
||||
bool
|
||||
select SOC_NRF52810
|
||||
|
||||
config SOC_NRF52811_QFAA
|
||||
bool
|
||||
select SOC_NRF52811
|
||||
|
||||
config SOC_NRF52820_QDAA
|
||||
bool
|
||||
select SOC_NRF52820
|
||||
|
||||
config SOC_NRF52832_CIAA
|
||||
bool
|
||||
select SOC_NRF52832
|
||||
|
||||
config SOC_NRF52832_QFAA
|
||||
bool
|
||||
select SOC_NRF52832
|
||||
|
||||
config SOC_NRF52832_QFAB
|
||||
bool
|
||||
select SOC_NRF52832
|
||||
|
||||
config SOC_NRF52833_QDAA
|
||||
bool
|
||||
select SOC_NRF52833
|
||||
|
||||
config SOC_NRF52833_QIAA
|
||||
bool
|
||||
select SOC_NRF52833
|
||||
|
||||
config SOC_NRF52840_QFAA
|
||||
bool
|
||||
select SOC_NRF52840
|
||||
|
||||
config SOC_NRF52840_QIAA
|
||||
bool
|
||||
select SOC_NRF52840
|
||||
|
||||
config SOC
|
||||
default "nrf52805" if SOC_NRF52805_CAAA
|
||||
default "nrf52810" if SOC_NRF52810_QFAA
|
||||
default "nrf52811" if SOC_NRF52811_QFAA
|
||||
default "nrf52820" if SOC_NRF52820_QDAA
|
||||
default "nrf52832" if SOC_NRF52832_CIAA || SOC_NRF52832_QFAA || SOC_NRF52832_QFAB
|
||||
default "nrf52833" if SOC_NRF52833_QDAA || SOC_NRF52833_QIAA
|
||||
default "nrf52840" if SOC_NRF52840_QFAA || SOC_NRF52840_QIAA
|
||||
48
soc/nordic/nrf52/soc.c
Normal file
48
soc/nordic/nrf52/soc.c
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief System/hardware module for Nordic Semiconductor nRF52 family processor
|
||||
*
|
||||
* This module provides routines to initialize and support board-level hardware
|
||||
* for the Nordic Semiconductor nRF52 family processor.
|
||||
*/
|
||||
|
||||
#include <zephyr/kernel.h>
|
||||
#include <zephyr/init.h>
|
||||
#include <hal/nrf_power.h>
|
||||
#include <soc/nrfx_coredep.h>
|
||||
#include <zephyr/logging/log.h>
|
||||
|
||||
#include <cmsis_core.h>
|
||||
|
||||
#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
|
||||
LOG_MODULE_REGISTER(soc);
|
||||
|
||||
static int nordicsemi_nrf52_init(void)
|
||||
{
|
||||
#ifdef CONFIG_NRF_ENABLE_ICACHE
|
||||
/* Enable the instruction cache */
|
||||
NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOC_DCDC_NRF52X)
|
||||
nrf_power_dcdcen_set(NRF_POWER, true);
|
||||
#endif
|
||||
#if NRF_POWER_HAS_DCDCEN_VDDH && defined(CONFIG_SOC_DCDC_NRF52X_HV)
|
||||
nrf_power_dcdcen_vddh_set(NRF_POWER, true);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void arch_busy_wait(uint32_t time_us)
|
||||
{
|
||||
nrfx_coredep_delay_us(time_us);
|
||||
}
|
||||
|
||||
SYS_INIT(nordicsemi_nrf52_init, PRE_KERNEL_1, 0);
|
||||
19
soc/nordic/nrf52/soc.h
Normal file
19
soc/nordic/nrf52/soc.h
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SoC configuration macros for the Nordic Semiconductor nRF52 family processors.
|
||||
*/
|
||||
|
||||
#ifndef _NORDICSEMI_NRF52_SOC_H_
|
||||
#define _NORDICSEMI_NRF52_SOC_H_
|
||||
|
||||
#include <soc_nrf_common.h>
|
||||
|
||||
#define FLASH_PAGE_ERASE_MAX_TIME_US 89700UL
|
||||
#define FLASH_PAGE_MAX_CNT 256UL
|
||||
|
||||
#endif /* _NORDICSEMI_NRF52_SOC_H_ */
|
||||
18
soc/nordic/nrf53/CMakeLists.txt
Normal file
18
soc/nordic/nrf53/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_library_sources(soc.c)
|
||||
zephyr_include_directories(.)
|
||||
|
||||
zephyr_library_sources_ifdef(CONFIG_NRF53_SYNC_RTC sync_rtc.c)
|
||||
|
||||
if (CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED AND
|
||||
NOT CONFIG_SYS_CLOCK_EXISTS)
|
||||
message(WARNING "
|
||||
Your application may be affected by the anomaly 160 that concerns the
|
||||
nRF5340 SoC. The related workaround cannot be applied, because your
|
||||
application has the system clock disabled (CONFIG_SYS_CLOCK_EXISTS=n).
|
||||
Consider enabling the system clock to apply the workaround.
|
||||
" "
|
||||
At your own risk, you can suppress this warning by setting
|
||||
CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED=n.")
|
||||
endif()
|
||||
227
soc/nordic/nrf53/Kconfig
Normal file
227
soc/nordic/nrf53/Kconfig
Normal file
|
|
@ -0,0 +1,227 @@
|
|||
# Nordic Semiconductor nRF53 MCU line
|
||||
|
||||
# Copyright (c) 2019 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_NRF53X
|
||||
bool
|
||||
select ARM
|
||||
select SOC_COMPATIBLE_NRF53X
|
||||
select CPU_CORTEX_M33
|
||||
select CPU_CORTEX_M_HAS_DWT
|
||||
select CPU_HAS_ARM_MPU
|
||||
imply XIP
|
||||
select HAS_NRFX
|
||||
select HAS_NORDIC_DRIVERS
|
||||
select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
|
||||
select HAS_SWO
|
||||
help
|
||||
Enable support for NRF53 MCU series
|
||||
|
||||
config SOC_NRF5340_CPUAPP
|
||||
select CPU_HAS_NRF_IDAU
|
||||
select CPU_HAS_FPU
|
||||
select ARMV8_M_DSP
|
||||
select HAS_POWEROFF
|
||||
select SOC_COMPATIBLE_NRF5340_CPUAPP
|
||||
imply SOC_NRF53_RTC_PRETICK
|
||||
imply SOC_NRF53_ANOMALY_168_WORKAROUND
|
||||
|
||||
config SOC_NRF5340_CPUNET
|
||||
select ARM_ON_EXIT_CPU_IDLE
|
||||
select SOC_COMPATIBLE_NRF5340_CPUNET
|
||||
imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
|
||||
imply SOC_NRF53_RTC_PRETICK if !WDT_NRFX
|
||||
imply SOC_NRF53_ANOMALY_168_WORKAROUND
|
||||
|
||||
if SOC_SERIES_NRF53X
|
||||
|
||||
config SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
|
||||
bool "Workaround for nRF5340 anomaly 160"
|
||||
imply SOC_NRF53_ANOMALY_160_WORKAROUND
|
||||
help
|
||||
Indicates that the workaround for the anomaly 160 that affects
|
||||
the nRF5340 SoC should be applied.
|
||||
This option is enabled by default for the Application MCU when
|
||||
DC/DC mode is enabled for the VREGMAIN or VREGRADIO regulator
|
||||
and always for the Network MCU.
|
||||
If this option is enabled, but the workaround cannot be applied,
|
||||
because the system clock is disabled, a related cmake warning is
|
||||
issued.
|
||||
|
||||
config SOC_NRF53_ANOMALY_160_WORKAROUND
|
||||
bool
|
||||
depends on SYS_CLOCK_EXISTS
|
||||
select ARM_ON_ENTER_CPU_IDLE_HOOK
|
||||
|
||||
config SOC_NRF53_ANOMALY_168_WORKAROUND
|
||||
bool "Workaround for nRF5340 anomaly 168"
|
||||
select ARM_ON_EXIT_CPU_IDLE
|
||||
help
|
||||
Indicates that the workaround for the anomaly 168 that affects
|
||||
the nRF5340 SoC should be applied.
|
||||
The workaround involves execution of 8 NOP instructions when the CPU
|
||||
exist its idle state (when the WFI/WFE instruction returns) and it is
|
||||
enabled by default for both the application and network core.
|
||||
|
||||
config SOC_NRF53_ANOMALY_168_WORKAROUND_FOR_EXECUTION_FROM_RAM
|
||||
bool "Extend the workaround to execution at 128 MHz from RAM"
|
||||
depends on SOC_NRF53_ANOMALY_168_WORKAROUND && SOC_NRF5340_CPUAPP
|
||||
help
|
||||
Indicates that the anomaly 168 workaround is to be extended to cover
|
||||
also a specific case when the WFI/WFE instruction is executed at 128
|
||||
MHz from RAM. Then, 26 instead of 8 NOP instructions needs to be
|
||||
executed after WFI/WFE. This extension is not enabled by default.
|
||||
|
||||
config SOC_NRF53_RTC_PRETICK
|
||||
bool "Pre-tick workaround for nRF5340 anomaly 165"
|
||||
depends on (SYS_CLOCK_EXISTS && SOC_NRF5340_CPUNET) || SOC_NRF5340_CPUAPP
|
||||
select NRFX_DPPI
|
||||
select ARM_ON_ENTER_CPU_IDLE_HOOK if SOC_NRF5340_CPUNET
|
||||
select ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK if SOC_NRF5340_CPUNET
|
||||
help
|
||||
Indicates that the pre-tick workaround for the anomaly 165 that affects
|
||||
the nRF5340 SoC should be applied. The workaround applies to wake ups caused
|
||||
by EVENTS_COMPARE and EVENTS_OVRFLW on RTC0 and RTC1 for which interrupts are
|
||||
enabled through INTENSET register. The case when these events are generated
|
||||
by EVTEN but without interrupts enabled through INTENSET is not handled.
|
||||
The EVENTS_TICK event is not handled.
|
||||
|
||||
if SOC_NRF53_RTC_PRETICK
|
||||
|
||||
config SOC_NRF53_RTC_PRETICK_IPC_CH_FROM_NET
|
||||
int "IPC 0 channel for RTC pretick"
|
||||
range 0 15
|
||||
default 10
|
||||
|
||||
config SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET
|
||||
int "IPC 1 channel for RTC pretick"
|
||||
range 0 15
|
||||
default 11
|
||||
|
||||
endif
|
||||
|
||||
if SOC_NRF5340_CPUAPP
|
||||
|
||||
config SOC_DCDC_NRF53X_APP
|
||||
bool
|
||||
imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
|
||||
help
|
||||
Enable nRF53 series System on Chip Application MCU DC/DC converter.
|
||||
|
||||
config SOC_DCDC_NRF53X_NET
|
||||
bool
|
||||
imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
|
||||
help
|
||||
Enable nRF53 series System on Chip Network MCU DC/DC converter.
|
||||
|
||||
config SOC_DCDC_NRF53X_HV
|
||||
bool
|
||||
help
|
||||
Enable nRF53 series System on Chip High Voltage DC/DC converter.
|
||||
|
||||
config NRF_SPU_FLASH_REGION_SIZE
|
||||
hex
|
||||
default 0x4000
|
||||
help
|
||||
FLASH region size for the NRF_SPU peripheral
|
||||
|
||||
config NRF_SPU_RAM_REGION_SIZE
|
||||
hex
|
||||
default 0x2000
|
||||
help
|
||||
RAM region size for the NRF_SPU peripheral
|
||||
|
||||
config SOC_NRF_GPIO_FORWARDER_FOR_NRF5340
|
||||
bool
|
||||
depends on NRF_SOC_SECURE_SUPPORTED
|
||||
help
|
||||
hidden option for including the nRF GPIO pin forwarding
|
||||
|
||||
if !TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM
|
||||
|
||||
config SOC_ENABLE_LFXO
|
||||
bool "LFXO"
|
||||
default y
|
||||
help
|
||||
Enable the low-frequency oscillator (LFXO) functionality on XL1 and
|
||||
XL2 pins.
|
||||
This option must be enabled if either application or network core is
|
||||
to use the LFXO. Otherwise, XL1 and XL2 pins will behave as regular
|
||||
GPIOs.
|
||||
|
||||
choice SOC_LFXO_LOAD_CAPACITANCE
|
||||
prompt "LFXO load capacitance"
|
||||
depends on SOC_ENABLE_LFXO
|
||||
default SOC_LFXO_CAP_INT_7PF
|
||||
|
||||
config SOC_LFXO_CAP_EXTERNAL
|
||||
bool "Use external load capacitors"
|
||||
|
||||
config SOC_LFXO_CAP_INT_6PF
|
||||
bool "6 pF internal load capacitance"
|
||||
|
||||
config SOC_LFXO_CAP_INT_7PF
|
||||
bool "7 pF internal load capacitance"
|
||||
|
||||
config SOC_LFXO_CAP_INT_9PF
|
||||
bool "9 pF internal load capacitance"
|
||||
|
||||
endchoice
|
||||
|
||||
choice SOC_HFXO_LOAD_CAPACITANCE
|
||||
prompt "HFXO load capacitance"
|
||||
default SOC_HFXO_CAP_DEFAULT
|
||||
|
||||
config SOC_HFXO_CAP_DEFAULT
|
||||
bool "SoC default"
|
||||
help
|
||||
When this option is used, the SoC initialization routine does not
|
||||
touch the XOSC32MCAPS register value, so the default setting for
|
||||
the SoC is in effect. Please note that this may not necessarily be
|
||||
the reset value (0) for the register, as the register can be set
|
||||
during the device trimming in the SystemInit() function.
|
||||
|
||||
config SOC_HFXO_CAP_EXTERNAL
|
||||
bool "Use external load capacitors"
|
||||
|
||||
config SOC_HFXO_CAP_INTERNAL
|
||||
bool "Use internal load capacitors"
|
||||
depends on NRF_SOC_SECURE_SUPPORTED
|
||||
|
||||
endchoice
|
||||
|
||||
config SOC_HFXO_CAP_INT_VALUE_X2
|
||||
int "Doubled value of HFXO internal load capacitors (in pF)"
|
||||
depends on SOC_HFXO_CAP_INTERNAL
|
||||
range 14 40
|
||||
help
|
||||
Internal capacitors ranging from 7.0 pF to 20.0 pF in 0.5 pF steps
|
||||
can be enabled on pins XC1 and XC2. This option specifies doubled
|
||||
capacitance value for the two capacitors. Set it to 14 to get 7.0 pF
|
||||
for each capacitor, 15 to get 7.5 pF, and so on.
|
||||
|
||||
endif # !TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM
|
||||
|
||||
endif # SOC_NRF5340_CPUAPP
|
||||
|
||||
|
||||
config NRF_ENABLE_CACHE
|
||||
bool "Cache"
|
||||
depends on (SOC_NRF5340_CPUAPP && (!TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM)) \
|
||||
|| SOC_NRF5340_CPUNET
|
||||
default y
|
||||
help
|
||||
Instruction and Data cache is available on nRF5340 CPUAPP
|
||||
(Application MCU). It may only be accessed by Secure code.
|
||||
|
||||
Instruction cache only (I-Cache) is available in nRF5340
|
||||
CPUNET (Network MCU).
|
||||
|
||||
config BUILD_WITH_TFM
|
||||
# TF-M nRF53 platform enables the cache unconditionally.
|
||||
select NRF_ENABLE_CACHE if SOC_NRF5340_CPUAPP
|
||||
|
||||
rsource "Kconfig.sync_rtc"
|
||||
|
||||
endif # SOC_SERIES_NRF53X
|
||||
14
soc/nordic/nrf53/Kconfig.defconfig
Normal file
14
soc/nordic/nrf53/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
# Nordic Semiconductor nRF53 MCU line
|
||||
|
||||
# Copyright (c) 2019 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_NRF53X
|
||||
|
||||
rsource "Kconfig.defconfig.nrf53*"
|
||||
|
||||
# If the kernel has timer support, enable the timer
|
||||
config NRF_RTC_TIMER
|
||||
default y if SYS_CLOCK_EXISTS
|
||||
|
||||
endif # SOC_SERIES_NRF53X
|
||||
25
soc/nordic/nrf53/Kconfig.defconfig.nrf5340_CPUAPP_QKAA
Normal file
25
soc/nordic/nrf53/Kconfig.defconfig.nrf5340_CPUAPP_QKAA
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
# Nordic Semiconductor nRF5340 Application MCU
|
||||
|
||||
# Copyright (c) 2019 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_NRF5340_CPUAPP_QKAA
|
||||
|
||||
config NUM_IRQS
|
||||
default 69
|
||||
|
||||
config IEEE802154_NRF5
|
||||
default IEEE802154
|
||||
|
||||
config HEAP_MEM_POOL_ADD_SIZE_SOC
|
||||
def_int 4096
|
||||
depends on NRF_802154_SER_HOST
|
||||
|
||||
if IPC_SERVICE_BACKEND_RPMSG
|
||||
|
||||
config IPC_SERVICE_BACKEND_RPMSG_SHMEM_RESET
|
||||
default y
|
||||
|
||||
endif # IPC_SERVICE_BACKEND_RPMSG
|
||||
|
||||
endif # SOC_NRF5340_CPUAPP_QKAA
|
||||
22
soc/nordic/nrf53/Kconfig.defconfig.nrf5340_CPUNET_QKAA
Normal file
22
soc/nordic/nrf53/Kconfig.defconfig.nrf5340_CPUNET_QKAA
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
# Nordic Semiconductor nRF5340 Network MCU
|
||||
|
||||
# Copyright (c) 2019 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_NRF5340_CPUNET_QKAA
|
||||
|
||||
config NUM_IRQS
|
||||
default 30
|
||||
|
||||
config IEEE802154_NRF5
|
||||
default y
|
||||
depends on IEEE802154
|
||||
|
||||
config HEAP_MEM_POOL_ADD_SIZE_SOC
|
||||
def_int 4096
|
||||
depends on NRF_802154_SER_RADIO
|
||||
|
||||
config LOG_DOMAIN_NAME
|
||||
default "net"
|
||||
|
||||
endif # SOC_NRF5340_CPUNET_QKAA
|
||||
29
soc/nordic/nrf53/Kconfig.soc
Normal file
29
soc/nordic/nrf53/Kconfig.soc
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
# Nordic Semiconductor nRF52 MCU line, Zephyr hw model v2 compliant
|
||||
|
||||
# Copyright (c) 2023 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_NRF53X
|
||||
bool
|
||||
select SOC_FAMILY_NORDIC_NRF
|
||||
help
|
||||
Enable support for NRF53 MCU series
|
||||
|
||||
config SOC_NRF5340_CPUAPP
|
||||
bool
|
||||
select SOC_SERIES_NRF53X
|
||||
|
||||
config SOC_NRF5340_CPUNET
|
||||
bool
|
||||
select SOC_SERIES_NRF53X
|
||||
|
||||
config SOC_NRF5340_CPUAPP_QKAA
|
||||
bool
|
||||
select SOC_NRF5340_CPUAPP
|
||||
|
||||
config SOC_NRF5340_CPUNET_QKAA
|
||||
bool
|
||||
select SOC_NRF5340_CPUNET
|
||||
|
||||
config SOC
|
||||
default "nrf5340" if SOC_NRF5340_CPUAPP_QKAA || SOC_NRF5340_CPUNET_QKAA
|
||||
77
soc/nordic/nrf53/Kconfig.sync_rtc
Normal file
77
soc/nordic/nrf53/Kconfig.sync_rtc
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
# Copyright (c) 2019 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config NRF53_SYNC_RTC
|
||||
bool "RTC clock synchronization"
|
||||
default y if LOG && !LOG_MODE_MINIMAL
|
||||
depends on NRF_RTC_TIMER
|
||||
select NRFX_DPPI
|
||||
select MBOX if !IPM
|
||||
|
||||
if NRF53_SYNC_RTC
|
||||
|
||||
module = SYNC_RTC
|
||||
module-str = Synchronized RTC
|
||||
source "subsys/logging/Kconfig.template.log_config"
|
||||
|
||||
config NRF53_SYNC_RTC_INIT_PRIORITY
|
||||
int "nRF53 Synchronized RTC init priority"
|
||||
default APPLICATION_INIT_PRIORITY
|
||||
help
|
||||
nRF53 Synchronized RTC initialization priority.
|
||||
|
||||
config NRF_RTC_TIMER_USER_CHAN_COUNT
|
||||
default 2 if NRF_802154_RADIO_DRIVER && SOC_COMPATIBLE_NRF5340_CPUNET
|
||||
default 3 if NRF_802154_RADIO_DRIVER
|
||||
default 1
|
||||
|
||||
config NRF53_SYNC_RTC_LOG_TIMESTAMP
|
||||
bool "Use Synchronized RTC for logging timestamp"
|
||||
default y
|
||||
|
||||
config NRF53_SYNC_RTC_IPM_OUT
|
||||
int "IPM channel from APP to NET"
|
||||
range 0 15
|
||||
default 7 if SOC_COMPATIBLE_NRF5340_CPUAPP
|
||||
default 8
|
||||
|
||||
config NRF53_SYNC_RTC_IPM_IN
|
||||
int "IPM channel from APP to NET"
|
||||
range 0 15
|
||||
default 8 if SOC_COMPATIBLE_NRF5340_CPUAPP
|
||||
default 7
|
||||
|
||||
ipm_num = 0
|
||||
rsource "Kconfig.sync_rtc_ipm"
|
||||
ipm_num = 1
|
||||
rsource "Kconfig.sync_rtc_ipm"
|
||||
ipm_num = 2
|
||||
rsource "Kconfig.sync_rtc_ipm"
|
||||
ipm_num = 3
|
||||
rsource "Kconfig.sync_rtc_ipm"
|
||||
ipm_num = 4
|
||||
rsource "Kconfig.sync_rtc_ipm"
|
||||
ipm_num = 5
|
||||
rsource "Kconfig.sync_rtc_ipm"
|
||||
ipm_num = 6
|
||||
rsource "Kconfig.sync_rtc_ipm"
|
||||
ipm_num = 7
|
||||
rsource "Kconfig.sync_rtc_ipm"
|
||||
ipm_num = 8
|
||||
rsource "Kconfig.sync_rtc_ipm"
|
||||
ipm_num = 9
|
||||
rsource "Kconfig.sync_rtc_ipm"
|
||||
ipm_num = 10
|
||||
rsource "Kconfig.sync_rtc_ipm"
|
||||
ipm_num = 11
|
||||
rsource "Kconfig.sync_rtc_ipm"
|
||||
ipm_num = 12
|
||||
rsource "Kconfig.sync_rtc_ipm"
|
||||
ipm_num = 13
|
||||
rsource "Kconfig.sync_rtc_ipm"
|
||||
ipm_num = 14
|
||||
rsource "Kconfig.sync_rtc_ipm"
|
||||
ipm_num = 15
|
||||
rsource "Kconfig.sync_rtc_ipm"
|
||||
|
||||
endif # NRF53_SYNC_RTC
|
||||
12
soc/nordic/nrf53/Kconfig.sync_rtc_ipm
Normal file
12
soc/nordic/nrf53/Kconfig.sync_rtc_ipm
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
# nRF IPM driver configuration
|
||||
|
||||
# Copyright (c) 2021 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config IPM_MSG_CH_$(ipm_num)_ENABLE
|
||||
default y
|
||||
depends on NRF53_SYNC_RTC_IPM_IN = $(ipm_num)
|
||||
|
||||
config IPM_MSG_CH_$(ipm_num)_RX
|
||||
default y
|
||||
depends on NRF53_SYNC_RTC_IPM_IN = $(ipm_num)
|
||||
593
soc/nordic/nrf53/soc.c
Normal file
593
soc/nordic/nrf53/soc.c
Normal file
|
|
@ -0,0 +1,593 @@
|
|||
/*
|
||||
* Copyright (c) 2019 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief System/hardware module for Nordic Semiconductor nRF53 family processor
|
||||
*
|
||||
* This module provides routines to initialize and support board-level hardware
|
||||
* for the Nordic Semiconductor nRF53 family processor.
|
||||
*/
|
||||
|
||||
#include <zephyr/kernel.h>
|
||||
#include <zephyr/init.h>
|
||||
#include <zephyr/sys/barrier.h>
|
||||
#include <soc/nrfx_coredep.h>
|
||||
#include <zephyr/logging/log.h>
|
||||
#include <nrf_erratas.h>
|
||||
#include <hal/nrf_power.h>
|
||||
#include <hal/nrf_ipc.h>
|
||||
#include <helpers/nrfx_gppi.h>
|
||||
#if defined(CONFIG_SOC_NRF5340_CPUAPP)
|
||||
#include <zephyr/drivers/gpio.h>
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <hal/nrf_cache.h>
|
||||
#include <hal/nrf_gpio.h>
|
||||
#include <hal/nrf_oscillators.h>
|
||||
#include <hal/nrf_regulators.h>
|
||||
#elif defined(CONFIG_SOC_NRF5340_CPUNET)
|
||||
#include <hal/nrf_nvmc.h>
|
||||
#endif
|
||||
#if defined(CONFIG_PM_S2RAM)
|
||||
#include <hal/nrf_vmc.h>
|
||||
#endif
|
||||
#include <hal/nrf_wdt.h>
|
||||
#include <hal/nrf_rtc.h>
|
||||
#include <soc_secure.h>
|
||||
|
||||
#include <cmsis_core.h>
|
||||
|
||||
#define PIN_XL1 0
|
||||
#define PIN_XL2 1
|
||||
|
||||
#define RTC1_PRETICK_CC_CHAN (RTC1_CC_NUM - 1)
|
||||
|
||||
/* Mask of CC channels capable of generating interrupts, see nrf_rtc_timer.c */
|
||||
#define RTC1_PRETICK_SELECTED_CC_MASK BIT_MASK(CONFIG_NRF_RTC_TIMER_USER_CHAN_COUNT + 1U)
|
||||
#define RTC0_PRETICK_SELECTED_CC_MASK BIT_MASK(NRF_RTC_CC_COUNT_MAX)
|
||||
|
||||
#if defined(CONFIG_SOC_NRF_GPIO_FORWARDER_FOR_NRF5340)
|
||||
#define GPIOS_PSEL_BY_IDX(node_id, prop, idx) \
|
||||
NRF_DT_GPIOS_TO_PSEL_BY_IDX(node_id, prop, idx),
|
||||
#define ALL_GPIOS_IN_NODE(node_id) \
|
||||
DT_FOREACH_PROP_ELEM(node_id, gpios, GPIOS_PSEL_BY_IDX)
|
||||
#define ALL_GPIOS_IN_FORWARDER(node_id) \
|
||||
DT_FOREACH_CHILD(node_id, ALL_GPIOS_IN_NODE)
|
||||
#endif
|
||||
|
||||
#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
|
||||
LOG_MODULE_REGISTER(soc);
|
||||
|
||||
#if defined(CONFIG_PM_S2RAM)
|
||||
|
||||
#if defined(CONFIG_SOC_NRF5340_CPUAPP)
|
||||
#define RAM_N_BLOCK (8)
|
||||
#elif defined(CONFIG_SOC_NRF5340_CPUNET)
|
||||
#define RAM_N_BLOCK (4)
|
||||
#endif /* CONFIG_SOC_NRF5340_CPUAPP || CONFIG_SOC_NRF5340_CPUNET */
|
||||
|
||||
#define MASK_ALL_SECT (VMC_RAM_POWER_S0RETENTION_Msk | VMC_RAM_POWER_S1RETENTION_Msk | \
|
||||
VMC_RAM_POWER_S2RETENTION_Msk | VMC_RAM_POWER_S3RETENTION_Msk | \
|
||||
VMC_RAM_POWER_S4RETENTION_Msk | VMC_RAM_POWER_S5RETENTION_Msk | \
|
||||
VMC_RAM_POWER_S6RETENTION_Msk | VMC_RAM_POWER_S7RETENTION_Msk | \
|
||||
VMC_RAM_POWER_S8RETENTION_Msk | VMC_RAM_POWER_S9RETENTION_Msk | \
|
||||
VMC_RAM_POWER_S10RETENTION_Msk | VMC_RAM_POWER_S11RETENTION_Msk | \
|
||||
VMC_RAM_POWER_S12RETENTION_Msk | VMC_RAM_POWER_S13RETENTION_Msk | \
|
||||
VMC_RAM_POWER_S14RETENTION_Msk | VMC_RAM_POWER_S15RETENTION_Msk)
|
||||
|
||||
static void enable_ram_retention(void)
|
||||
{
|
||||
/*
|
||||
* Enable RAM retention for *ALL* the SRAM
|
||||
*/
|
||||
for (size_t n = 0; n < RAM_N_BLOCK; n++) {
|
||||
nrf_vmc_ram_block_retention_set(NRF_VMC, n, MASK_ALL_SECT);
|
||||
}
|
||||
|
||||
}
|
||||
#endif /* CONFIG_PM_S2RAM */
|
||||
|
||||
#if defined(CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND)
|
||||
/* This code prevents the CPU from entering sleep again if it already
|
||||
* entered sleep 5 times within last 200 us.
|
||||
*/
|
||||
static bool nrf53_anomaly_160_check(void)
|
||||
{
|
||||
/* System clock cycles needed to cover 200 us window. */
|
||||
const uint32_t window_cycles =
|
||||
DIV_ROUND_UP(200 * CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
|
||||
1000000);
|
||||
static uint32_t timestamps[5];
|
||||
static bool timestamps_filled;
|
||||
static uint8_t current;
|
||||
uint8_t oldest = (current + 1) % ARRAY_SIZE(timestamps);
|
||||
uint32_t now = k_cycle_get_32();
|
||||
|
||||
if (timestamps_filled &&
|
||||
/* + 1 because only fully elapsed cycles need to be counted. */
|
||||
(now - timestamps[oldest]) < (window_cycles + 1)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Check if the CPU actually entered sleep since the last visit here
|
||||
* (WFE/WFI could return immediately if the wake-up event was already
|
||||
* registered).
|
||||
*/
|
||||
if (nrf_power_event_check(NRF_POWER, NRF_POWER_EVENT_SLEEPENTER)) {
|
||||
nrf_power_event_clear(NRF_POWER, NRF_POWER_EVENT_SLEEPENTER);
|
||||
/* If so, update the index at which the current timestamp is
|
||||
* to be stored so that it replaces the oldest one, otherwise
|
||||
* (when the CPU did not sleep), the recently stored timestamp
|
||||
* is updated.
|
||||
*/
|
||||
current = oldest;
|
||||
if (current == 0) {
|
||||
timestamps_filled = true;
|
||||
}
|
||||
}
|
||||
|
||||
timestamps[current] = k_cycle_get_32();
|
||||
|
||||
return true;
|
||||
}
|
||||
#endif /* CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND */
|
||||
|
||||
#if defined(CONFIG_SOC_NRF53_RTC_PRETICK) && defined(CONFIG_SOC_NRF5340_CPUNET)
|
||||
|
||||
BUILD_ASSERT(!IS_ENABLED(CONFIG_WDT_NRFX),
|
||||
"For CONFIG_SOC_NRF53_RTC_PRETICK watchdog is used internally for the pre-tick workaround on nRF5340 cpunet. Application cannot use the watchdog.");
|
||||
|
||||
static inline uint32_t rtc_counter_sub(uint32_t a, uint32_t b)
|
||||
{
|
||||
return (a - b) & NRF_RTC_COUNTER_MAX;
|
||||
}
|
||||
|
||||
static bool rtc_ticks_to_next_event_get(NRF_RTC_Type *rtc, uint32_t selected_cc_mask, uint32_t cntr,
|
||||
uint32_t *ticks_to_next_event)
|
||||
{
|
||||
bool result = false;
|
||||
|
||||
/* Let's preload register to speed-up. */
|
||||
uint32_t reg_intenset = rtc->INTENSET;
|
||||
|
||||
/* Note: TICK event not handled. */
|
||||
|
||||
if (reg_intenset & NRF_RTC_INT_OVERFLOW_MASK) {
|
||||
/* Overflow can generate an interrupt. */
|
||||
*ticks_to_next_event = NRF_RTC_COUNTER_MAX + 1U - cntr;
|
||||
result = true;
|
||||
}
|
||||
|
||||
for (uint32_t chan = 0; chan < NRF_RTC_CC_COUNT_MAX; chan++) {
|
||||
if ((selected_cc_mask & (1U << chan)) &&
|
||||
(reg_intenset & NRF_RTC_CHANNEL_INT_MASK(chan))) {
|
||||
/* The CC is in selected mask and is can generate an interrupt. */
|
||||
uint32_t cc = nrf_rtc_cc_get(rtc, chan);
|
||||
uint32_t ticks_to_fire = rtc_counter_sub(cc, cntr);
|
||||
|
||||
if (ticks_to_fire == 0U) {
|
||||
/* When ticks_to_fire == 0, the event should have been just
|
||||
* generated the interrupt can be already handled or be pending.
|
||||
* However the next event is expected to be after counter wraps.
|
||||
*/
|
||||
ticks_to_fire = NRF_RTC_COUNTER_MAX + 1U;
|
||||
}
|
||||
|
||||
if (!result) {
|
||||
*ticks_to_next_event = ticks_to_fire;
|
||||
result = true;
|
||||
} else if (ticks_to_fire < *ticks_to_next_event) {
|
||||
*ticks_to_next_event = ticks_to_fire;
|
||||
result = true;
|
||||
} else {
|
||||
/* CC that fires no earlier than already found. */
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static void rtc_counter_synchronized_get(NRF_RTC_Type *rtc_a, NRF_RTC_Type *rtc_b,
|
||||
uint32_t *counter_a, uint32_t *counter_b)
|
||||
{
|
||||
do {
|
||||
*counter_a = nrf_rtc_counter_get(rtc_a);
|
||||
barrier_dmem_fence_full();
|
||||
*counter_b = nrf_rtc_counter_get(rtc_b);
|
||||
barrier_dmem_fence_full();
|
||||
} while (*counter_a != nrf_rtc_counter_get(rtc_a));
|
||||
}
|
||||
|
||||
static uint8_t cpu_idle_prepare_monitor_dummy;
|
||||
static bool cpu_idle_prepare_allows_sleep;
|
||||
|
||||
static void cpu_idle_prepare_monitor_begin(void)
|
||||
{
|
||||
__LDREXB(&cpu_idle_prepare_monitor_dummy);
|
||||
}
|
||||
|
||||
/* Returns 0 if no exception preempted since the last call to cpu_idle_prepare_monitor_begin. */
|
||||
static bool cpu_idle_prepare_monitor_end(void)
|
||||
{
|
||||
/* The value stored is irrelevant. If any exception took place after
|
||||
* cpu_idle_prepare_monitor_begin, the the local monitor is cleared and
|
||||
* the store fails returning 1.
|
||||
* See Arm v8-M Architecture Reference Manual:
|
||||
* Chapter B9.2 The local monitors
|
||||
* Chapter B9.4 Exclusive access instructions and the monitors
|
||||
* See Arm Cortex-M33 Processor Technical Reference Manual
|
||||
* Chapter 3.5 Exclusive monitor
|
||||
*/
|
||||
return __STREXB(0U, &cpu_idle_prepare_monitor_dummy);
|
||||
}
|
||||
|
||||
static void rtc_pretick_finish_previous(void)
|
||||
{
|
||||
NRF_IPC->PUBLISH_RECEIVE[CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET] &=
|
||||
~IPC_PUBLISH_RECEIVE_EN_Msk;
|
||||
|
||||
nrf_rtc_event_clear(NRF_RTC1, NRF_RTC_CHANNEL_EVENT_ADDR(RTC1_PRETICK_CC_CHAN));
|
||||
}
|
||||
|
||||
|
||||
void z_arm_on_enter_cpu_idle_prepare(void)
|
||||
{
|
||||
bool ok_to_sleep = true;
|
||||
|
||||
cpu_idle_prepare_monitor_begin();
|
||||
|
||||
uint32_t rtc_counter = 0U;
|
||||
uint32_t rtc_ticks_to_next_event = 0U;
|
||||
uint32_t rtc0_counter = 0U;
|
||||
uint32_t rtc0_ticks_to_next_event = 0U;
|
||||
|
||||
rtc_counter_synchronized_get(NRF_RTC1, NRF_RTC0, &rtc_counter, &rtc0_counter);
|
||||
|
||||
bool rtc_scheduled = rtc_ticks_to_next_event_get(NRF_RTC1, RTC1_PRETICK_SELECTED_CC_MASK,
|
||||
rtc_counter, &rtc_ticks_to_next_event);
|
||||
|
||||
if (rtc_ticks_to_next_event_get(NRF_RTC0, RTC0_PRETICK_SELECTED_CC_MASK, rtc0_counter,
|
||||
&rtc0_ticks_to_next_event)) {
|
||||
/* An event is scheduled on RTC0. */
|
||||
if (!rtc_scheduled) {
|
||||
rtc_ticks_to_next_event = rtc0_ticks_to_next_event;
|
||||
rtc_scheduled = true;
|
||||
} else if (rtc0_ticks_to_next_event < rtc_ticks_to_next_event) {
|
||||
rtc_ticks_to_next_event = rtc0_ticks_to_next_event;
|
||||
} else {
|
||||
/* Event on RTC0 will not happen earlier than already found. */
|
||||
}
|
||||
}
|
||||
|
||||
if (rtc_scheduled) {
|
||||
static bool rtc_pretick_cc_set_on_time;
|
||||
/* The pretick should happen 1 tick before the earliest scheduled event
|
||||
* that can trigger an interrupt.
|
||||
*/
|
||||
uint32_t rtc_pretick_cc_val = (rtc_counter + rtc_ticks_to_next_event - 1U)
|
||||
& NRF_RTC_COUNTER_MAX;
|
||||
|
||||
if (rtc_pretick_cc_val != nrf_rtc_cc_get(NRF_RTC1, RTC1_PRETICK_CC_CHAN)) {
|
||||
/* The CC for pretick needs to be updated. */
|
||||
rtc_pretick_finish_previous();
|
||||
nrf_rtc_cc_set(NRF_RTC1, RTC1_PRETICK_CC_CHAN, rtc_pretick_cc_val);
|
||||
|
||||
if (rtc_ticks_to_next_event >= NRF_RTC_COUNTER_MAX/2) {
|
||||
/* Pretick is scheduled so far in the future, assumed on time. */
|
||||
rtc_pretick_cc_set_on_time = true;
|
||||
} else {
|
||||
/* Let's check if we updated CC on time, so that the CC can
|
||||
* take effect.
|
||||
*/
|
||||
barrier_dmem_fence_full();
|
||||
rtc_counter = nrf_rtc_counter_get(NRF_RTC1);
|
||||
uint32_t pretick_cc_to_counter =
|
||||
rtc_counter_sub(rtc_pretick_cc_val, rtc_counter);
|
||||
|
||||
if ((pretick_cc_to_counter < 3) ||
|
||||
(pretick_cc_to_counter >= NRF_RTC_COUNTER_MAX/2)) {
|
||||
/* The COUNTER value is close enough to the expected
|
||||
* pretick CC or has just expired, so the pretick event
|
||||
* generation is not guaranteed.
|
||||
*/
|
||||
rtc_pretick_cc_set_on_time = false;
|
||||
} else {
|
||||
/* The written rtc_pretick_cc is guaranteed to to trigger
|
||||
* compare event.
|
||||
*/
|
||||
rtc_pretick_cc_set_on_time = true;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
/* The CC for pretick doesn't need to be updated, however
|
||||
* rtc_pretick_cc_set_on_time still holds if we managed to set it on time.
|
||||
*/
|
||||
}
|
||||
|
||||
/* If the CC for pretick is set on time, so the pretick CC event can be reliably
|
||||
* generated then allow to sleep. Otherwise (the CC for pretick cannot be reliably
|
||||
* generated, because CC was set very short to it's fire time) sleep not at all.
|
||||
*/
|
||||
ok_to_sleep = rtc_pretick_cc_set_on_time;
|
||||
} else {
|
||||
/* No events on any RTC timers are scheduled. */
|
||||
}
|
||||
|
||||
if (ok_to_sleep) {
|
||||
NRF_IPC->PUBLISH_RECEIVE[CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET] |=
|
||||
IPC_PUBLISH_RECEIVE_EN_Msk;
|
||||
if (!nrf_rtc_event_check(NRF_RTC1,
|
||||
NRF_RTC_CHANNEL_EVENT_ADDR(RTC1_PRETICK_CC_CHAN))) {
|
||||
NRF_WDT->TASKS_STOP = 1;
|
||||
/* Check if any event did not occur after we checked for
|
||||
* stopping condition. If yes, we might have stopped WDT
|
||||
* when it should be running. Restart it.
|
||||
*/
|
||||
if (nrf_rtc_event_check(NRF_RTC1,
|
||||
NRF_RTC_CHANNEL_EVENT_ADDR(RTC1_PRETICK_CC_CHAN))) {
|
||||
NRF_WDT->TASKS_START = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
cpu_idle_prepare_allows_sleep = ok_to_sleep;
|
||||
}
|
||||
#endif /* CONFIG_SOC_NRF53_RTC_PRETICK && CONFIG_SOC_NRF5340_CPUNET */
|
||||
|
||||
#if defined(CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND) || \
|
||||
(defined(CONFIG_SOC_NRF53_RTC_PRETICK) && defined(CONFIG_SOC_NRF5340_CPUNET))
|
||||
bool z_arm_on_enter_cpu_idle(void)
|
||||
{
|
||||
bool ok_to_sleep = true;
|
||||
|
||||
#if defined(CONFIG_SOC_NRF53_RTC_PRETICK) && defined(CONFIG_SOC_NRF5340_CPUNET)
|
||||
if (cpu_idle_prepare_monitor_end() == 0) {
|
||||
/* No exception happened since cpu_idle_prepare_monitor_begin.
|
||||
* We can trust the outcome of. z_arm_on_enter_cpu_idle_prepare
|
||||
*/
|
||||
ok_to_sleep = cpu_idle_prepare_allows_sleep;
|
||||
} else {
|
||||
/* Exception happened since cpu_idle_prepare_monitor_begin.
|
||||
* The values which z_arm_on_enter_cpu_idle_prepare could be changed
|
||||
* by the exception, so we can not trust to it's outcome.
|
||||
* Do not sleep at all, let's try in the next iteration of idle loop.
|
||||
*/
|
||||
ok_to_sleep = false;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND)
|
||||
if (ok_to_sleep) {
|
||||
ok_to_sleep = nrf53_anomaly_160_check();
|
||||
|
||||
#if (LOG_LEVEL >= LOG_LEVEL_DBG)
|
||||
static bool suppress_message;
|
||||
|
||||
if (ok_to_sleep) {
|
||||
suppress_message = false;
|
||||
} else if (!suppress_message) {
|
||||
LOG_DBG("Anomaly 160 trigger conditions detected.");
|
||||
suppress_message = true;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif /* CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND */
|
||||
|
||||
#if defined(CONFIG_SOC_NRF53_RTC_PRETICK) && defined(CONFIG_SOC_NRF5340_CPUNET)
|
||||
if (!ok_to_sleep) {
|
||||
NRF_IPC->PUBLISH_RECEIVE[CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET] &=
|
||||
~IPC_PUBLISH_RECEIVE_EN_Msk;
|
||||
NRF_WDT->TASKS_STOP = 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
return ok_to_sleep;
|
||||
}
|
||||
#endif /* CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND ||
|
||||
* (CONFIG_SOC_NRF53_RTC_PRETICK && CONFIG_SOC_NRF5340_CPUNET)
|
||||
*/
|
||||
|
||||
#if CONFIG_SOC_NRF53_RTC_PRETICK
|
||||
#ifdef CONFIG_SOC_NRF5340_CPUAPP
|
||||
/* RTC pretick - application core part. */
|
||||
static int rtc_pretick_cpuapp_init(void)
|
||||
{
|
||||
uint8_t ch;
|
||||
nrfx_err_t err;
|
||||
nrf_ipc_event_t ipc_event =
|
||||
nrf_ipc_receive_event_get(CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_FROM_NET);
|
||||
nrf_ipc_task_t ipc_task =
|
||||
nrf_ipc_send_task_get(CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET);
|
||||
uint32_t task_ipc = nrf_ipc_task_address_get(NRF_IPC, ipc_task);
|
||||
uint32_t evt_ipc = nrf_ipc_event_address_get(NRF_IPC, ipc_event);
|
||||
|
||||
err = nrfx_gppi_channel_alloc(&ch);
|
||||
if (err != NRFX_SUCCESS) {
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
nrf_ipc_receive_config_set(NRF_IPC, CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_FROM_NET,
|
||||
BIT(CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_FROM_NET));
|
||||
nrf_ipc_send_config_set(NRF_IPC, CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET,
|
||||
BIT(CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET));
|
||||
|
||||
nrfx_gppi_task_endpoint_setup(ch, task_ipc);
|
||||
nrfx_gppi_event_endpoint_setup(ch, evt_ipc);
|
||||
nrfx_gppi_channels_enable(BIT(ch));
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else /* CONFIG_SOC_NRF5340_CPUNET */
|
||||
|
||||
void rtc_pretick_rtc0_isr_hook(void)
|
||||
{
|
||||
rtc_pretick_finish_previous();
|
||||
}
|
||||
|
||||
void rtc_pretick_rtc1_isr_hook(void)
|
||||
{
|
||||
rtc_pretick_finish_previous();
|
||||
}
|
||||
|
||||
static int rtc_pretick_cpunet_init(void)
|
||||
{
|
||||
uint8_t ppi_ch;
|
||||
nrf_ipc_task_t ipc_task =
|
||||
nrf_ipc_send_task_get(CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_FROM_NET);
|
||||
nrf_ipc_event_t ipc_event =
|
||||
nrf_ipc_receive_event_get(CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET);
|
||||
uint32_t task_ipc = nrf_ipc_task_address_get(NRF_IPC, ipc_task);
|
||||
uint32_t evt_ipc = nrf_ipc_event_address_get(NRF_IPC, ipc_event);
|
||||
uint32_t task_wdt = nrf_wdt_task_address_get(NRF_WDT, NRF_WDT_TASK_START);
|
||||
uint32_t evt_cc = nrf_rtc_event_address_get(NRF_RTC1,
|
||||
NRF_RTC_CHANNEL_EVENT_ADDR(RTC1_PRETICK_CC_CHAN));
|
||||
|
||||
/* Configure Watchdog to allow stopping. */
|
||||
nrf_wdt_behaviour_set(NRF_WDT, WDT_CONFIG_STOPEN_Msk | BIT(4));
|
||||
*((volatile uint32_t *)0x41203120) = 0x14;
|
||||
|
||||
/* Configure IPC */
|
||||
nrf_ipc_receive_config_set(NRF_IPC, CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET,
|
||||
BIT(CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET));
|
||||
nrf_ipc_send_config_set(NRF_IPC, CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_FROM_NET,
|
||||
BIT(CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_FROM_NET));
|
||||
|
||||
/* Allocate PPI channel for RTC Compare event publishers that starts WDT. */
|
||||
nrfx_err_t err = nrfx_gppi_channel_alloc(&ppi_ch);
|
||||
|
||||
if (err != NRFX_SUCCESS) {
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
nrfx_gppi_event_endpoint_setup(ppi_ch, evt_cc);
|
||||
nrfx_gppi_task_endpoint_setup(ppi_ch, task_ipc);
|
||||
nrfx_gppi_event_endpoint_setup(ppi_ch, evt_ipc);
|
||||
nrfx_gppi_task_endpoint_setup(ppi_ch, task_wdt);
|
||||
nrfx_gppi_channels_enable(BIT(ppi_ch));
|
||||
|
||||
nrf_rtc_event_enable(NRF_RTC1, NRF_RTC_CHANNEL_INT_MASK(RTC1_PRETICK_CC_CHAN));
|
||||
nrf_rtc_event_clear(NRF_RTC1, NRF_RTC_CHANNEL_EVENT_ADDR(RTC1_PRETICK_CC_CHAN));
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_SOC_NRF5340_CPUNET */
|
||||
|
||||
static int rtc_pretick_init(void)
|
||||
{
|
||||
#ifdef CONFIG_SOC_NRF5340_CPUAPP
|
||||
return rtc_pretick_cpuapp_init();
|
||||
#else
|
||||
return rtc_pretick_cpunet_init();
|
||||
#endif
|
||||
}
|
||||
#endif /* CONFIG_SOC_NRF53_RTC_PRETICK */
|
||||
|
||||
|
||||
static int nordicsemi_nrf53_init(void)
|
||||
{
|
||||
#if defined(CONFIG_SOC_NRF5340_CPUAPP) && defined(CONFIG_NRF_ENABLE_CACHE)
|
||||
#if !defined(CONFIG_BUILD_WITH_TFM)
|
||||
/* Enable the instruction & data cache.
|
||||
* This can only be done from secure code.
|
||||
* This is handled by the TF-M platform so we skip it when TF-M is
|
||||
* enabled.
|
||||
*/
|
||||
nrf_cache_enable(NRF_CACHE);
|
||||
#endif
|
||||
#elif defined(CONFIG_SOC_NRF5340_CPUNET) && defined(CONFIG_NRF_ENABLE_CACHE)
|
||||
nrf_nvmc_icache_config_set(NRF_NVMC, NRF_NVMC_ICACHE_ENABLE);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOC_ENABLE_LFXO)
|
||||
nrf_oscillators_lfxo_cap_set(NRF_OSCILLATORS,
|
||||
IS_ENABLED(CONFIG_SOC_LFXO_CAP_INT_6PF) ?
|
||||
NRF_OSCILLATORS_LFXO_CAP_6PF :
|
||||
IS_ENABLED(CONFIG_SOC_LFXO_CAP_INT_7PF) ?
|
||||
NRF_OSCILLATORS_LFXO_CAP_7PF :
|
||||
IS_ENABLED(CONFIG_SOC_LFXO_CAP_INT_9PF) ?
|
||||
NRF_OSCILLATORS_LFXO_CAP_9PF :
|
||||
NRF_OSCILLATORS_LFXO_CAP_EXTERNAL);
|
||||
#if !defined(CONFIG_BUILD_WITH_TFM)
|
||||
/* This can only be done from secure code.
|
||||
* This is handled by the TF-M platform so we skip it when TF-M is
|
||||
* enabled.
|
||||
*/
|
||||
nrf_gpio_pin_control_select(PIN_XL1, NRF_GPIO_PIN_SEL_PERIPHERAL);
|
||||
nrf_gpio_pin_control_select(PIN_XL2, NRF_GPIO_PIN_SEL_PERIPHERAL);
|
||||
#endif /* !defined(CONFIG_BUILD_WITH_TFM) */
|
||||
#endif /* defined(CONFIG_SOC_ENABLE_LFXO) */
|
||||
#if defined(CONFIG_SOC_HFXO_CAP_INTERNAL)
|
||||
/* This register is only accessible from secure code. */
|
||||
uint32_t xosc32mtrim = soc_secure_read_xosc32mtrim();
|
||||
/* The SLOPE field is in the two's complement form, hence this special
|
||||
* handling. Ideally, it would result in just one SBFX instruction for
|
||||
* extracting the slope value, at least gcc is capable of producing such
|
||||
* output, but since the compiler apparently tries first to optimize
|
||||
* additions and subtractions, it generates slightly less than optimal
|
||||
* code.
|
||||
*/
|
||||
uint32_t slope_field = (xosc32mtrim & FICR_XOSC32MTRIM_SLOPE_Msk)
|
||||
>> FICR_XOSC32MTRIM_SLOPE_Pos;
|
||||
uint32_t slope_mask = FICR_XOSC32MTRIM_SLOPE_Msk
|
||||
>> FICR_XOSC32MTRIM_SLOPE_Pos;
|
||||
uint32_t slope_sign = (slope_mask - (slope_mask >> 1));
|
||||
int32_t slope = (int32_t)(slope_field ^ slope_sign) - (int32_t)slope_sign;
|
||||
uint32_t offset = (xosc32mtrim & FICR_XOSC32MTRIM_OFFSET_Msk)
|
||||
>> FICR_XOSC32MTRIM_OFFSET_Pos;
|
||||
/* As specified in the nRF5340 PS:
|
||||
* CAPVALUE = (((FICR->XOSC32MTRIM.SLOPE+56)*(CAPACITANCE*2-14))
|
||||
* +((FICR->XOSC32MTRIM.OFFSET-8)<<4)+32)>>6;
|
||||
* where CAPACITANCE is the desired capacitor value in pF, holding any
|
||||
* value between 7.0 pF and 20.0 pF in 0.5 pF steps.
|
||||
*/
|
||||
uint32_t capvalue =
|
||||
((slope + 56) * (CONFIG_SOC_HFXO_CAP_INT_VALUE_X2 - 14)
|
||||
+ ((offset - 8) << 4) + 32) >> 6;
|
||||
|
||||
nrf_oscillators_hfxo_cap_set(NRF_OSCILLATORS, true, capvalue);
|
||||
#elif defined(CONFIG_SOC_HFXO_CAP_EXTERNAL)
|
||||
nrf_oscillators_hfxo_cap_set(NRF_OSCILLATORS, false, 0);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOC_DCDC_NRF53X_APP)
|
||||
nrf_regulators_vreg_enable_set(NRF_REGULATORS, NRF_REGULATORS_VREG_MAIN, true);
|
||||
#endif
|
||||
#if defined(CONFIG_SOC_DCDC_NRF53X_NET)
|
||||
nrf_regulators_vreg_enable_set(NRF_REGULATORS, NRF_REGULATORS_VREG_RADIO, true);
|
||||
#endif
|
||||
#if defined(CONFIG_SOC_DCDC_NRF53X_HV)
|
||||
nrf_regulators_vreg_enable_set(NRF_REGULATORS, NRF_REGULATORS_VREG_HIGH, true);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOC_NRF_GPIO_FORWARDER_FOR_NRF5340)
|
||||
static const uint8_t forwarded_psels[] = {
|
||||
DT_FOREACH_STATUS_OKAY(nordic_nrf_gpio_forwarder, ALL_GPIOS_IN_FORWARDER)
|
||||
};
|
||||
|
||||
for (int i = 0; i < ARRAY_SIZE(forwarded_psels); i++) {
|
||||
soc_secure_gpio_pin_mcu_select(forwarded_psels[i], NRF_GPIO_PIN_SEL_NETWORK);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PM_S2RAM)
|
||||
enable_ram_retention();
|
||||
#endif /* CONFIG_PM_S2RAM */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void arch_busy_wait(uint32_t time_us)
|
||||
{
|
||||
nrfx_coredep_delay_us(time_us);
|
||||
}
|
||||
|
||||
SYS_INIT(nordicsemi_nrf53_init, PRE_KERNEL_1, 0);
|
||||
|
||||
#ifdef CONFIG_SOC_NRF53_RTC_PRETICK
|
||||
SYS_INIT(rtc_pretick_init, POST_KERNEL, 0);
|
||||
#endif
|
||||
25
soc/nordic/nrf53/soc.h
Normal file
25
soc/nordic/nrf53/soc.h
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Copyright (c) 2019 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SoC configuration macros for the
|
||||
* Nordic Semiconductor nRF53 family processors.
|
||||
*/
|
||||
|
||||
#ifndef _NORDICSEMI_NRF53_SOC_H_
|
||||
#define _NORDICSEMI_NRF53_SOC_H_
|
||||
|
||||
#include <soc_nrf_common.h>
|
||||
|
||||
#if defined(CONFIG_SOC_NRF5340_CPUAPP)
|
||||
#define FLASH_PAGE_ERASE_MAX_TIME_US 89700UL
|
||||
#define FLASH_PAGE_MAX_CNT 256UL
|
||||
#elif defined(CONFIG_SOC_NRF5340_CPUNET)
|
||||
#define FLASH_PAGE_ERASE_MAX_TIME_US 89700UL
|
||||
#define FLASH_PAGE_MAX_CNT 128UL
|
||||
#endif
|
||||
|
||||
#endif /* _NORDICSEMI_NRF53_SOC_H_ */
|
||||
26
soc/nordic/nrf53/soc_cpu_idle.h
Normal file
26
soc/nordic/nrf53/soc_cpu_idle.h
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SoC extensions of cpu_idle.S for the Nordic Semiconductor nRF53 processors family.
|
||||
*/
|
||||
|
||||
|
||||
#if defined(_ASMLANGUAGE)
|
||||
|
||||
#if defined(CONFIG_SOC_NRF53_ANOMALY_168_WORKAROUND_FOR_EXECUTION_FROM_RAM)
|
||||
#define SOC_ON_EXIT_CPU_IDLE \
|
||||
.rept 26; \
|
||||
nop; \
|
||||
.endr
|
||||
#elif defined(CONFIG_SOC_NRF53_ANOMALY_168_WORKAROUND)
|
||||
#define SOC_ON_EXIT_CPU_IDLE \
|
||||
.rept 8; \
|
||||
nop; \
|
||||
.endr
|
||||
#endif
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
286
soc/nordic/nrf53/sync_rtc.c
Normal file
286
soc/nordic/nrf53/sync_rtc.c
Normal file
|
|
@ -0,0 +1,286 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Nordic Semiconductor ASA.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <nrfx_dppi.h>
|
||||
#include <hal/nrf_ipc.h>
|
||||
#include <helpers/nrfx_gppi.h>
|
||||
#include <zephyr/drivers/timer/nrf_rtc_timer.h>
|
||||
#include <zephyr/drivers/mbox.h>
|
||||
#include <zephyr/init.h>
|
||||
#include <zephyr/logging/log_ctrl.h>
|
||||
#include <zephyr/logging/log.h>
|
||||
LOG_MODULE_REGISTER(sync_rtc, CONFIG_SYNC_RTC_LOG_LEVEL);
|
||||
|
||||
/* Arbitrary delay is used needed to handle cases when offset between cores is
|
||||
* small and rtc synchronization process might not handle events on time.
|
||||
* Setting high value prolongs synchronization process but setting too low may
|
||||
* lead synchronization failure if offset between cores is small and/or there
|
||||
* are significant interrupt handling latencies.
|
||||
*/
|
||||
#define RTC_SYNC_ARBITRARY_DELAY 100
|
||||
|
||||
static uint32_t sync_cc;
|
||||
static int32_t nrf53_sync_offset = -EBUSY;
|
||||
|
||||
union rtc_sync_channels {
|
||||
uint32_t raw;
|
||||
struct {
|
||||
uint8_t ppi;
|
||||
uint8_t rtc;
|
||||
uint8_t ipc_out;
|
||||
uint8_t ipc_in;
|
||||
} ch;
|
||||
};
|
||||
|
||||
/* Algorithm for establishing RTC offset on the network side.
|
||||
*
|
||||
* Assumptions:
|
||||
* APP starts first thus its RTC is ahead. Only network will need to adjust its
|
||||
* time. Because APP will capture the offset but NET needs it, algorithm
|
||||
* consists of two stages: Getting offset on APP side, passing this offset to
|
||||
* NET core. To keep it simple and independent from IPM protocols, value is passed
|
||||
* using just IPC, PPI and RTC.
|
||||
*
|
||||
* 1st stage:
|
||||
* APP: setup PPI connection from IPC_RECEIVE to RTC CAPTURE, enable interrupt
|
||||
* IPC received.
|
||||
* NET: setup RTC CC for arbitrary offset from now, setup PPI from RTC_COMPARE to IPC_SEND
|
||||
* Record value set to CC.
|
||||
*
|
||||
* When APP will capture the value it needs to be passed to NET since it will be
|
||||
* capable of calculating the offset since it know what counter value corresponds
|
||||
* to the value captured on APP side.
|
||||
*
|
||||
* 2nd stage:
|
||||
* APP: Sets Compare event for value = 2 * captured value + arbitrary offset
|
||||
* NET: setup PPI from IPC_RECEIVE to RTC CAPTURE
|
||||
*
|
||||
* When NET RTC captures IPC event it takes CC value and knowing CC value previously
|
||||
* used by NET and arbitrary offset (which is the same on APP and NET) is able
|
||||
* to calculate exact offset between RTC counters.
|
||||
*
|
||||
* Note, arbitrary delay is used to accommodate for the case when NET-APP offset
|
||||
* is small enough that interrupt latency would impact it. NET-APP offset depends
|
||||
* on when NET core is reset and time when RTC system clock is initialized.
|
||||
*/
|
||||
|
||||
/* Setup or clear connection from IPC_RECEIVE to RTC_CAPTURE
|
||||
*
|
||||
* @param channels Details about channels
|
||||
* @param setup If true connection is setup, else it is cleared.
|
||||
*/
|
||||
static void ppi_ipc_to_rtc(union rtc_sync_channels channels, bool setup)
|
||||
{
|
||||
nrf_ipc_event_t ipc_evt = nrf_ipc_receive_event_get(channels.ch.ipc_in);
|
||||
uint32_t task_addr = z_nrf_rtc_timer_capture_task_address_get(channels.ch.rtc);
|
||||
|
||||
if (setup) {
|
||||
nrfx_gppi_task_endpoint_setup(channels.ch.ppi, task_addr);
|
||||
nrf_ipc_publish_set(NRF_IPC, ipc_evt, channels.ch.ppi);
|
||||
} else {
|
||||
nrfx_gppi_task_endpoint_clear(channels.ch.ppi, task_addr);
|
||||
nrf_ipc_publish_clear(NRF_IPC, ipc_evt);
|
||||
}
|
||||
}
|
||||
|
||||
/* Setup or clear connection from RTC_COMPARE to IPC_SEND
|
||||
*
|
||||
* @param channels Details about channels
|
||||
* @param setup If true connection is setup, else it is cleared.
|
||||
*/
|
||||
static void ppi_rtc_to_ipc(union rtc_sync_channels channels, bool setup)
|
||||
{
|
||||
uint32_t evt_addr = z_nrf_rtc_timer_compare_evt_address_get(channels.ch.rtc);
|
||||
nrf_ipc_task_t ipc_task = nrf_ipc_send_task_get(channels.ch.ipc_out);
|
||||
|
||||
if (setup) {
|
||||
nrf_ipc_subscribe_set(NRF_IPC, ipc_task, channels.ch.ppi);
|
||||
nrfx_gppi_event_endpoint_setup(channels.ch.ppi, evt_addr);
|
||||
} else {
|
||||
nrfx_gppi_event_endpoint_clear(channels.ch.ppi, evt_addr);
|
||||
nrf_ipc_subscribe_clear(NRF_IPC, ipc_task);
|
||||
}
|
||||
}
|
||||
|
||||
/* Free DPPI and RTC channels */
|
||||
static void free_resources(union rtc_sync_channels channels)
|
||||
{
|
||||
nrfx_err_t err;
|
||||
|
||||
nrfx_gppi_channels_disable(BIT(channels.ch.ppi));
|
||||
|
||||
z_nrf_rtc_timer_chan_free(channels.ch.rtc);
|
||||
|
||||
err = nrfx_dppi_channel_free(channels.ch.ppi);
|
||||
__ASSERT_NO_MSG(err == NRFX_SUCCESS);
|
||||
}
|
||||
|
||||
int z_nrf_rtc_timer_nrf53net_offset_get(void)
|
||||
{
|
||||
if (!IS_ENABLED(CONFIG_SOC_COMPATIBLE_NRF5340_CPUNET)) {
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
return nrf53_sync_offset;
|
||||
}
|
||||
|
||||
static void rtc_cb(int32_t id, uint64_t cc_value, void *user_data)
|
||||
{
|
||||
ARG_UNUSED(id);
|
||||
ARG_UNUSED(cc_value);
|
||||
|
||||
union rtc_sync_channels channels;
|
||||
|
||||
channels.raw = (uint32_t)user_data;
|
||||
ppi_rtc_to_ipc(channels, false);
|
||||
if (IS_ENABLED(CONFIG_SOC_COMPATIBLE_NRF5340_CPUAPP)) {
|
||||
/* APP: Synchronized completed */
|
||||
free_resources(channels);
|
||||
} else {
|
||||
/* Compare event generated, reconfigure PPI and wait for
|
||||
* IPC event from APP.
|
||||
*/
|
||||
ppi_ipc_to_rtc(channels, true);
|
||||
}
|
||||
}
|
||||
|
||||
static log_timestamp_t sync_rtc_timestamp_get(void)
|
||||
{
|
||||
return (log_timestamp_t)(sys_clock_tick_get() + nrf53_sync_offset);
|
||||
}
|
||||
|
||||
static void remote_callback(void *user_data)
|
||||
{
|
||||
extern const struct log_link *log_link_ipc_get_link(void);
|
||||
|
||||
union rtc_sync_channels channels;
|
||||
uint32_t cc;
|
||||
|
||||
channels.raw = (uint32_t)user_data;
|
||||
|
||||
cc = z_nrf_rtc_timer_compare_read(channels.ch.rtc);
|
||||
|
||||
/* Clear previous task,event */
|
||||
ppi_ipc_to_rtc(channels, false);
|
||||
|
||||
if (IS_ENABLED(CONFIG_SOC_COMPATIBLE_NRF5340_CPUAPP)) {
|
||||
/* Setup new connection from RTC to IPC and set RTC to a new
|
||||
* interval that contains captured offset.
|
||||
*/
|
||||
ppi_rtc_to_ipc(channels, true);
|
||||
|
||||
z_nrf_rtc_timer_set(channels.ch.rtc, cc + cc + RTC_SYNC_ARBITRARY_DELAY,
|
||||
rtc_cb, (void *)channels.raw);
|
||||
} else {
|
||||
/* Synchronization completed */
|
||||
free_resources(channels);
|
||||
nrf53_sync_offset = cc - RTC_SYNC_ARBITRARY_DELAY - 2 * sync_cc;
|
||||
if (IS_ENABLED(CONFIG_NRF53_SYNC_RTC_LOG_TIMESTAMP)) {
|
||||
uint32_t offset_us =
|
||||
(uint64_t)nrf53_sync_offset * 1000000 /
|
||||
sys_clock_hw_cycles_per_sec();
|
||||
|
||||
log_set_timestamp_func(sync_rtc_timestamp_get,
|
||||
sys_clock_hw_cycles_per_sec());
|
||||
LOG_INF("Updated timestamp to synchronized RTC by %d ticks (%dus)",
|
||||
nrf53_sync_offset, offset_us);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void mbox_callback(const struct device *dev, uint32_t channel,
|
||||
void *user_data, struct mbox_msg *data)
|
||||
{
|
||||
struct mbox_channel ch;
|
||||
int err;
|
||||
|
||||
mbox_init_channel(&ch, dev, channel);
|
||||
err = mbox_set_enabled(&ch, false);
|
||||
|
||||
(void)err;
|
||||
__ASSERT_NO_MSG(err == 0);
|
||||
|
||||
remote_callback(user_data);
|
||||
}
|
||||
|
||||
static int mbox_rx_init(void *user_data)
|
||||
{
|
||||
const struct device *dev;
|
||||
struct mbox_channel channel;
|
||||
int err;
|
||||
|
||||
dev = COND_CODE_1(CONFIG_MBOX, (DEVICE_DT_GET(DT_NODELABEL(mbox))), (NULL));
|
||||
if (dev == NULL) {
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
mbox_init_channel(&channel, dev, CONFIG_NRF53_SYNC_RTC_IPM_IN);
|
||||
|
||||
err = mbox_register_callback(&channel, mbox_callback, user_data);
|
||||
if (err < 0) {
|
||||
return err;
|
||||
}
|
||||
|
||||
return mbox_set_enabled(&channel, true);
|
||||
}
|
||||
|
||||
/* Setup RTC synchronization. */
|
||||
static int sync_rtc_setup(void)
|
||||
{
|
||||
nrfx_err_t err;
|
||||
union rtc_sync_channels channels;
|
||||
int32_t sync_rtc_ch;
|
||||
int rv;
|
||||
|
||||
err = nrfx_dppi_channel_alloc(&channels.ch.ppi);
|
||||
if (err != NRFX_SUCCESS) {
|
||||
rv = -ENODEV;
|
||||
goto bail;
|
||||
}
|
||||
|
||||
sync_rtc_ch = z_nrf_rtc_timer_chan_alloc();
|
||||
if (sync_rtc_ch < 0) {
|
||||
nrfx_dppi_channel_free(channels.ch.ppi);
|
||||
rv = sync_rtc_ch;
|
||||
goto bail;
|
||||
}
|
||||
|
||||
channels.ch.rtc = (uint8_t)sync_rtc_ch;
|
||||
channels.ch.ipc_out = CONFIG_NRF53_SYNC_RTC_IPM_OUT;
|
||||
channels.ch.ipc_in = CONFIG_NRF53_SYNC_RTC_IPM_IN;
|
||||
|
||||
rv = mbox_rx_init((void *)channels.raw);
|
||||
if (rv < 0) {
|
||||
goto bail;
|
||||
}
|
||||
|
||||
nrfx_gppi_channels_enable(BIT(channels.ch.ppi));
|
||||
|
||||
if (IS_ENABLED(CONFIG_SOC_COMPATIBLE_NRF5340_CPUAPP)) {
|
||||
ppi_ipc_to_rtc(channels, true);
|
||||
} else {
|
||||
ppi_rtc_to_ipc(channels, true);
|
||||
|
||||
uint32_t key = irq_lock();
|
||||
|
||||
sync_cc = z_nrf_rtc_timer_read() + RTC_SYNC_ARBITRARY_DELAY;
|
||||
z_nrf_rtc_timer_set(channels.ch.rtc, sync_cc, rtc_cb, (void *)channels.raw);
|
||||
irq_unlock(key);
|
||||
}
|
||||
|
||||
bail:
|
||||
if (rv != 0) {
|
||||
LOG_ERR("Failed synchronized RTC setup (err: %d)", rv);
|
||||
}
|
||||
|
||||
return rv;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MBOX_INIT_PRIORITY)
|
||||
BUILD_ASSERT(CONFIG_NRF53_SYNC_RTC_INIT_PRIORITY > CONFIG_MBOX_INIT_PRIORITY,
|
||||
"RTC Sync must be initialized after MBOX driver.");
|
||||
#endif
|
||||
|
||||
SYS_INIT(sync_rtc_setup, POST_KERNEL, CONFIG_NRF53_SYNC_RTC_INIT_PRIORITY);
|
||||
11
soc/nordic/nrf54h/CMakeLists.txt
Normal file
11
soc/nordic/nrf54h/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
# Copyright (c) 2024 Nordic Semiconductor
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if(CONFIG_SOC_NRF54H20_ENGA_CPUAPP OR CONFIG_SOC_NRF54H20_ENGA_CPURAD)
|
||||
zephyr_include_directories(.)
|
||||
zephyr_library_sources(soc.c)
|
||||
endif()
|
||||
|
||||
# Ensure that image size aligns with 16 bytes so that MRAMC finalizes all writes
|
||||
# for the image correctly
|
||||
zephyr_linker_sources(SECTIONS SORT_KEY zzz_place_align_at_end align.ld)
|
||||
41
soc/nordic/nrf54h/Kconfig
Normal file
41
soc/nordic/nrf54h/Kconfig
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
# Nordic Semiconductor nRF54H MCU line
|
||||
|
||||
# Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_NRF54HX
|
||||
select HAS_NRFX
|
||||
select HAS_NORDIC_DRIVERS
|
||||
|
||||
config SOC_NRF54H20_ENGA_CPUAPP
|
||||
select ARM
|
||||
select ARMV8_M_DSP
|
||||
select CPU_CORTEX_M33
|
||||
select CPU_HAS_ARM_MPU
|
||||
select CPU_HAS_ARM_SAU
|
||||
select CPU_HAS_DCACHE
|
||||
select CPU_HAS_ICACHE
|
||||
select CPU_HAS_FPU
|
||||
select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
|
||||
|
||||
config SOC_NRF54H20_ENGA_CPURAD
|
||||
select ARM
|
||||
select ARMV8_M_DSP
|
||||
select CPU_CORTEX_M33
|
||||
select CPU_HAS_ARM_MPU
|
||||
select CPU_HAS_ARM_SAU
|
||||
select CPU_HAS_DCACHE
|
||||
select CPU_HAS_ICACHE
|
||||
select CPU_HAS_FPU
|
||||
select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
|
||||
|
||||
config SOC_NRF54H20_ENGA_CPUPPR
|
||||
depends on RISCV_CORE_NORDIC_VPR
|
||||
|
||||
if SOC_NRF54H20
|
||||
|
||||
config NRF_ENABLE_ICACHE
|
||||
bool "Instruction cache (I-Cache)"
|
||||
default y
|
||||
|
||||
endif # SOC_NRF54H20
|
||||
36
soc/nordic/nrf54h/Kconfig.defconfig
Normal file
36
soc/nordic/nrf54h/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
# Nordic Semiconductor nRF54H MCU line
|
||||
|
||||
# Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_NRF54HX
|
||||
|
||||
rsource "Kconfig.defconfig.nrf54h*"
|
||||
|
||||
if ARM
|
||||
|
||||
config CACHE_NRF_CACHE
|
||||
default y if EXTERNAL_CACHE
|
||||
|
||||
endif # ARM
|
||||
|
||||
if RISCV
|
||||
|
||||
DT_CHOSEN_Z_SRAM = zephyr,sram
|
||||
DT_CHOSEN_Z_CODE = zephyr,code-partition
|
||||
|
||||
config BUILD_OUTPUT_ADJUST_LMA
|
||||
depends on !XIP
|
||||
default "$(dt_chosen_partition_addr_hex,$(DT_CHOSEN_Z_CODE)) - \
|
||||
$(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM))"
|
||||
|
||||
config BUILD_OUTPUT_HEX
|
||||
default y
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default 1000000 if NRF_GRTC_TIMER
|
||||
default 32768 if NRF_RTC_TIMER
|
||||
|
||||
endif # RISCV
|
||||
|
||||
endif # SOC_SERIES_NRF54HX
|
||||
14
soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuapp
Normal file
14
soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuapp
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
# Nordic Semiconductor nRF54H20 Application MCU
|
||||
|
||||
# Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_NRF54H20_ENGA_CPUAPP
|
||||
|
||||
config NUM_IRQS
|
||||
default 471
|
||||
|
||||
config NRF_REGTOOL_GENERATE_UICR
|
||||
default y
|
||||
|
||||
endif # SOC_NRF54H20_ENGA_CPUAPP
|
||||
12
soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuppr
Normal file
12
soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuppr
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
# Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_NRF54H20_ENGA_CPUPPR
|
||||
|
||||
config NUM_IRQS
|
||||
default 496
|
||||
|
||||
config SYS_CLOCK_TICKS_PER_SEC
|
||||
default 1000
|
||||
|
||||
endif # SOC_NRF54H20_ENGA_CPUPPR
|
||||
14
soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpurad
Normal file
14
soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpurad
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
# Nordic Semiconductor nRF54H20 Radio MCU
|
||||
|
||||
# Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_NRF54H20_ENGA_CPURAD
|
||||
|
||||
config NUM_IRQS
|
||||
default 471
|
||||
|
||||
config NRF_REGTOOL_GENERATE_UICR
|
||||
default y
|
||||
|
||||
endif # SOC_NRF54H20_ENGA_CPURAD
|
||||
31
soc/nordic/nrf54h/Kconfig.soc
Normal file
31
soc/nordic/nrf54h/Kconfig.soc
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
# Nordic Semiconductor nRF54H MCU line
|
||||
|
||||
# Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_NRF54H20
|
||||
bool
|
||||
select SOC_SERIES_NRF54HX
|
||||
help
|
||||
nRF54H20
|
||||
|
||||
config SOC_NRF54H20_ENGA_CPUAPP
|
||||
bool
|
||||
select SOC_NRF54H20
|
||||
help
|
||||
nRF54H20 ENGA CPUAPP
|
||||
|
||||
config SOC_NRF54H20_ENGA_CPURAD
|
||||
bool
|
||||
select SOC_NRF54H20
|
||||
help
|
||||
nRF54H20 ENGA CPURAD
|
||||
|
||||
config SOC_NRF54H20_ENGA_CPUPPR
|
||||
bool
|
||||
select SOC_NRF54H20
|
||||
help
|
||||
nRF54H20 ENGA CPUPPR
|
||||
|
||||
config SOC
|
||||
default "nrf54h20" if SOC_NRF54H20
|
||||
10
soc/nordic/nrf54h/align.ld
Normal file
10
soc/nordic/nrf54h/align.ld
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Nordic Semiconductor ASA.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
SECTION_PROLOGUE(.align16,,)
|
||||
{
|
||||
. = (ALIGN(16) > 0 ? ALIGN(16) : 16) - 1;
|
||||
BYTE(0);
|
||||
} GROUP_LINK_IN(ROMABLE_REGION)
|
||||
104
soc/nordic/nrf54h/soc.c
Normal file
104
soc/nordic/nrf54h/soc.c
Normal file
|
|
@ -0,0 +1,104 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Nordic Semiconductor ASA.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/cache.h>
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/init.h>
|
||||
#include <zephyr/kernel.h>
|
||||
#include <zephyr/logging/log.h>
|
||||
|
||||
#include <hal/nrf_hsfll.h>
|
||||
#include <hal/nrf_lrcconf.h>
|
||||
#include <soc/nrfx_coredep.h>
|
||||
|
||||
LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
|
||||
|
||||
#if defined(NRF_APPLICATION)
|
||||
#define HSFLL_NODE DT_NODELABEL(cpuapp_hsfll)
|
||||
#elif defined(NRF_RADIOCORE)
|
||||
#define HSFLL_NODE DT_NODELABEL(cpurad_hsfll)
|
||||
#endif
|
||||
|
||||
#define FICR_ADDR_GET(node_id, name) \
|
||||
DT_REG_ADDR(DT_PHANDLE_BY_NAME(node_id, nordic_ficrs, name)) + \
|
||||
DT_PHA_BY_NAME(node_id, nordic_ficrs, name, offset)
|
||||
|
||||
static void power_domain_init(void)
|
||||
{
|
||||
/*
|
||||
* Set:
|
||||
* - LRCCONF010.POWERON.MAIN: 1
|
||||
* - LRCCONF010.POWERON.ACT: 1
|
||||
* - LRCCONF010.RETAIN.MAIN: 1
|
||||
* - LRCCONF010.RETAIN.ACT: 1
|
||||
*
|
||||
* This is done here at boot so that when the idle routine will hit
|
||||
* WFI the power domain will be correctly retained.
|
||||
*/
|
||||
|
||||
nrf_lrcconf_poweron_force_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_MAIN, true);
|
||||
nrf_lrcconf_poweron_force_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_DOMAIN_0, true);
|
||||
|
||||
nrf_lrcconf_retain_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_MAIN, true);
|
||||
nrf_lrcconf_retain_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_DOMAIN_0, true);
|
||||
|
||||
#if defined(CONFIG_SOC_NRF54H20_ENGA_CPUAPP)
|
||||
nrf_lrcconf_poweron_force_set(NRF_LRCCONF000, NRF_LRCCONF_POWER_DOMAIN_0, true);
|
||||
#endif
|
||||
}
|
||||
|
||||
static int trim_hsfll(void)
|
||||
{
|
||||
NRF_HSFLL_Type *hsfll = (NRF_HSFLL_Type *)DT_REG_ADDR(HSFLL_NODE);
|
||||
nrf_hsfll_trim_t trim = {
|
||||
.vsup = sys_read32(FICR_ADDR_GET(HSFLL_NODE, vsup)),
|
||||
.coarse = sys_read32(FICR_ADDR_GET(HSFLL_NODE, coarse)),
|
||||
.fine = sys_read32(FICR_ADDR_GET(HSFLL_NODE, fine))
|
||||
};
|
||||
|
||||
LOG_DBG("Trim: HSFLL VSUP: 0x%.8x", trim.vsup);
|
||||
LOG_DBG("Trim: HSFLL COARSE: 0x%.8x", trim.coarse);
|
||||
LOG_DBG("Trim: HSFLL FINE: 0x%.8x", trim.fine);
|
||||
|
||||
nrf_hsfll_clkctrl_mult_set(hsfll,
|
||||
DT_PROP(HSFLL_NODE, clock_frequency) /
|
||||
DT_PROP(DT_CLOCKS_CTLR(HSFLL_NODE), clock_frequency));
|
||||
nrf_hsfll_trim_set(hsfll, &trim);
|
||||
|
||||
nrf_hsfll_task_trigger(hsfll, NRF_HSFLL_TASK_FREQ_CHANGE);
|
||||
#if defined(CONFIG_SOC_NRF54H20_ENGA_CPUAPP) || defined(CONFIG_SOC_NRF54H20_ENGA_CPURAD)
|
||||
/* In this HW revision, HSFLL task frequency change needs to be
|
||||
* triggered additional time to take effect.
|
||||
*/
|
||||
nrf_hsfll_task_trigger(hsfll, NRF_HSFLL_TASK_FREQ_CHANGE);
|
||||
#endif
|
||||
|
||||
LOG_DBG("NRF_HSFLL->TRIM.VSUP = %d", hsfll->TRIM.VSUP);
|
||||
LOG_DBG("NRF_HSFLL->TRIM.COARSE = %d", hsfll->TRIM.COARSE);
|
||||
LOG_DBG("NRF_HSFLL->TRIM.FINE = %d", hsfll->TRIM.FINE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int nordicsemi_nrf54h_init(void)
|
||||
{
|
||||
#if defined(CONFIG_NRF_ENABLE_ICACHE)
|
||||
sys_cache_instr_enable();
|
||||
#endif
|
||||
|
||||
power_domain_init();
|
||||
|
||||
trim_hsfll();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void arch_busy_wait(uint32_t time_us)
|
||||
{
|
||||
nrfx_coredep_delay_us(time_us);
|
||||
}
|
||||
|
||||
SYS_INIT(nordicsemi_nrf54h_init, PRE_KERNEL_1, 0);
|
||||
12
soc/nordic/nrf54h/soc.h
Normal file
12
soc/nordic/nrf54h/soc.h
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef SOC_ARM_NORDIC_NRF_NRF54H_SOC_H_
|
||||
#define SOC_ARM_NORDIC_NRF_NRF54H_SOC_H_
|
||||
|
||||
#include <soc_nrf_common.h>
|
||||
|
||||
#endif /* SOC_ARM_NORDIC_NRF_NRF54H_SOC_H_ */
|
||||
12
soc/nordic/nrf54l/CMakeLists.txt
Normal file
12
soc/nordic/nrf54l/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
# Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_library_sources(
|
||||
soc.c
|
||||
../validate_rram_partitions.c
|
||||
)
|
||||
zephyr_include_directories(.)
|
||||
|
||||
if(CONFIG_ELV_GRTC_LFXO_ALLOWED)
|
||||
message(WARNING "WARNING! ELV mode feature is EXPERIMENTAL and may brick your device!")
|
||||
endif()
|
||||
66
soc/nordic/nrf54l/Kconfig
Normal file
66
soc/nordic/nrf54l/Kconfig
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
# Nordic Semiconductor nRF54 MCU line
|
||||
|
||||
# Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_NRF54LX
|
||||
select HAS_NRFX
|
||||
select HAS_NORDIC_DRIVERS
|
||||
select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
|
||||
|
||||
config SOC_NRF54L15_ENGA_CPUAPP
|
||||
select ARM
|
||||
select ARMV8_M_DSP
|
||||
select CPU_CORTEX_M33
|
||||
select CPU_HAS_ARM_MPU
|
||||
select CPU_HAS_ICACHE
|
||||
select CPU_HAS_ARM_SAU
|
||||
select CPU_HAS_FPU
|
||||
select HAS_HW_NRF_RADIO_IEEE802154
|
||||
select HAS_POWEROFF
|
||||
|
||||
if SOC_SERIES_NRF54LX
|
||||
|
||||
config SOC_NRF54LX_SKIP_CLOCK_CONFIG
|
||||
bool "Skip clock frequency configuration in system initialization"
|
||||
help
|
||||
With this option, the CPU clock frequency is not set during system initialization.
|
||||
The CPU runs with the default, hardware-selected frequency.
|
||||
|
||||
config SOC_NRF_FORCE_CONSTLAT
|
||||
bool "Force constant-latency mode"
|
||||
help
|
||||
In constant latency mode the CPU wakeup latency and the PPI task response
|
||||
will be constant and kept at a minimum. This is secured by forcing a set
|
||||
of base resources on while in sleep. The advantage of having a constant
|
||||
and predictable latency will be at the cost of having increased power consumption.
|
||||
|
||||
config SOC_NRF54L_VREG_MAIN_DCDC
|
||||
bool "NRF54L DC/DC converter."
|
||||
help
|
||||
To enable, an inductor must be connected to the DC/DC converter pin.
|
||||
|
||||
config SOC_NRF54L_NORMAL_VOLTAGE_MODE
|
||||
bool "NRF54L Normal Voltage Mode."
|
||||
|
||||
config SOC_NRF54L_GLITCHDET_WORKAROUND
|
||||
bool "Workaround that disables glitch detector"
|
||||
default y
|
||||
help
|
||||
Temporary workaround - disabling glitch detector to limit power consumption.
|
||||
|
||||
if NRF_GRTC_TIMER
|
||||
|
||||
config ELV_GRTC_LFXO_ALLOWED
|
||||
bool
|
||||
depends on NRF_GRTC_SLEEP_ALLOWED
|
||||
select EXPERIMENTAL
|
||||
help
|
||||
This feature allows using ELV mode when GRTC operates with the LFXO as
|
||||
a low-frequency clock source. The LFXO is automatically activated when
|
||||
preparing to system-off.
|
||||
WARNING! This feature is EXPERIMENTAL and may brick your device!
|
||||
|
||||
endif # NRF_GRTC_TIMER
|
||||
|
||||
endif # SOC_SERIES_NRF54LX
|
||||
16
soc/nordic/nrf54l/Kconfig.defconfig
Normal file
16
soc/nordic/nrf54l/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
# Nordic Semiconductor nRF54L MCU line
|
||||
|
||||
# Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_NRF54LX
|
||||
|
||||
rsource "Kconfig.defconfig.nrf54l*"
|
||||
|
||||
config CORTEX_M_SYSTICK
|
||||
default !NRF_GRTC_TIMER
|
||||
|
||||
config CACHE_NRF_CACHE
|
||||
default y if EXTERNAL_CACHE
|
||||
|
||||
endif # SOC_SERIES_NRF54LX
|
||||
14
soc/nordic/nrf54l/Kconfig.defconfig.nrf54l15_enga_cpuapp
Normal file
14
soc/nordic/nrf54l/Kconfig.defconfig.nrf54l15_enga_cpuapp
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
# Nordic Semiconductor nRF54L15 MCU
|
||||
|
||||
# Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_NRF54L15_ENGA_CPUAPP
|
||||
|
||||
config NUM_IRQS
|
||||
default 271
|
||||
|
||||
config IEEE802154_NRF5
|
||||
default IEEE802154
|
||||
|
||||
endif # SOC_NRF54L15_ENGA_CPUAPP
|
||||
25
soc/nordic/nrf54l/Kconfig.soc
Normal file
25
soc/nordic/nrf54l/Kconfig.soc
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
# Nordic Semiconductor nRF54L MCU line
|
||||
|
||||
# Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_NRF54L15
|
||||
bool
|
||||
select SOC_SERIES_NRF54LX
|
||||
help
|
||||
NRF54L15
|
||||
|
||||
config SOC_NRF54L15_ENGA
|
||||
bool
|
||||
select SOC_NRF54L15
|
||||
help
|
||||
NRF54L15 ENGA
|
||||
|
||||
config SOC_NRF54L15_ENGA_CPUAPP
|
||||
bool
|
||||
select SOC_NRF54L15_ENGA
|
||||
help
|
||||
NRF54L15 ENGA CPUAPP
|
||||
|
||||
config SOC
|
||||
default "nrf54l15" if SOC_NRF54L15
|
||||
136
soc/nordic/nrf54l/soc.c
Normal file
136
soc/nordic/nrf54l/soc.c
Normal file
|
|
@ -0,0 +1,136 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief System/hardware module for Nordic Semiconductor nRF54L family processor
|
||||
*
|
||||
* This module provides routines to initialize and support board-level hardware
|
||||
* for the Nordic Semiconductor nRF54L family processor.
|
||||
*/
|
||||
|
||||
#include <zephyr/kernel.h>
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/init.h>
|
||||
#include <zephyr/logging/log.h>
|
||||
#include <zephyr/cache.h>
|
||||
|
||||
#include <cmsis_core.h>
|
||||
#include <hal/nrf_glitchdet.h>
|
||||
#include <hal/nrf_oscillators.h>
|
||||
#include <hal/nrf_power.h>
|
||||
#include <hal/nrf_regulators.h>
|
||||
#include <soc/nrfx_coredep.h>
|
||||
|
||||
#include <system_nrf54l.h>
|
||||
|
||||
LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
|
||||
|
||||
#define LFXO_NODE DT_NODELABEL(lfxo)
|
||||
#define HFXO_NODE DT_NODELABEL(hfxo)
|
||||
|
||||
static int nordicsemi_nrf54l_init(void)
|
||||
{
|
||||
/* Update the SystemCoreClock global variable with current core clock
|
||||
* retrieved from hardware state.
|
||||
*/
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
/* Enable ICACHE */
|
||||
sys_cache_instr_enable();
|
||||
|
||||
if (IS_ENABLED(CONFIG_SOC_NRF54L_GLITCHDET_WORKAROUND)) {
|
||||
nrf_glitchdet_enable_set(NRF_GLITCHDET, false);
|
||||
}
|
||||
|
||||
#if DT_ENUM_HAS_VALUE(LFXO_NODE, load_capacitors, internal)
|
||||
uint32_t xosc32ktrim = NRF_FICR->XOSC32KTRIM;
|
||||
|
||||
uint32_t offset_k =
|
||||
(xosc32ktrim & FICR_XOSC32KTRIM_OFFSET_Msk) >> FICR_XOSC32KTRIM_OFFSET_Pos;
|
||||
|
||||
uint32_t slope_field_k =
|
||||
(xosc32ktrim & FICR_XOSC32KTRIM_SLOPE_Msk) >> FICR_XOSC32KTRIM_SLOPE_Pos;
|
||||
uint32_t slope_mask_k = FICR_XOSC32KTRIM_SLOPE_Msk >> FICR_XOSC32KTRIM_SLOPE_Pos;
|
||||
uint32_t slope_sign_k = (slope_mask_k - (slope_mask_k >> 1));
|
||||
int32_t slope_k = (int32_t)(slope_field_k ^ slope_sign_k) - (int32_t)slope_sign_k;
|
||||
|
||||
/* As specified in the nRF54L15 PS:
|
||||
* CAPVALUE = round( (CAPACITANCE - 4) * (FICR->XOSC32KTRIM.SLOPE + 0.765625 * 2^9)/(2^9)
|
||||
* + FICR->XOSC32KTRIM.OFFSET/(2^6) );
|
||||
* where CAPACITANCE is the desired capacitor value in pF, holding any
|
||||
* value between 4 pF and 18 pF in 0.5 pF steps.
|
||||
*/
|
||||
uint32_t mid_val =
|
||||
(((DT_PROP(LFXO_NODE, load_capacitance_femtofarad) * 2UL) / 1000UL - 8UL) *
|
||||
(uint32_t)(slope_k + 392)) + (offset_k << 4UL);
|
||||
uint32_t capvalue_k = mid_val >> 10UL;
|
||||
|
||||
/* Round. */
|
||||
if ((mid_val % 1024UL) >= 512UL) {
|
||||
capvalue_k++;
|
||||
}
|
||||
nrf_oscillators_lfxo_cap_set(NRF_OSCILLATORS, (nrf_oscillators_lfxo_cap_t)capvalue_k);
|
||||
#elif DT_ENUM_HAS_VALUE(LFXO_NODE, load_capacitors, external)
|
||||
nrf_oscillators_lfxo_cap_set(NRF_OSCILLATORS, (nrf_oscillators_lfxo_cap_t)0);
|
||||
#endif
|
||||
|
||||
#if DT_ENUM_HAS_VALUE(HFXO_NODE, load_capacitors, internal)
|
||||
uint32_t xosc32mtrim = NRF_FICR->XOSC32MTRIM;
|
||||
/* The SLOPE field is in the two's complement form, hence this special
|
||||
* handling. Ideally, it would result in just one SBFX instruction for
|
||||
* extracting the slope value, at least gcc is capable of producing such
|
||||
* output, but since the compiler apparently tries first to optimize
|
||||
* additions and subtractions, it generates slightly less than optimal
|
||||
* code.
|
||||
*/
|
||||
uint32_t slope_field =
|
||||
(xosc32mtrim & FICR_XOSC32MTRIM_SLOPE_Msk) >> FICR_XOSC32MTRIM_SLOPE_Pos;
|
||||
uint32_t slope_mask = FICR_XOSC32MTRIM_SLOPE_Msk >> FICR_XOSC32MTRIM_SLOPE_Pos;
|
||||
uint32_t slope_sign = (slope_mask - (slope_mask >> 1));
|
||||
int32_t slope_m = (int32_t)(slope_field ^ slope_sign) - (int32_t)slope_sign;
|
||||
uint32_t offset_m =
|
||||
(xosc32mtrim & FICR_XOSC32MTRIM_OFFSET_Msk) >> FICR_XOSC32MTRIM_OFFSET_Pos;
|
||||
/* As specified in the nRF54L15 PS:
|
||||
* CAPVALUE = (((CAPACITANCE-5.5)*(FICR->XOSC32MTRIM.SLOPE+791)) +
|
||||
* FICR->XOSC32MTRIM.OFFSET<<2)>>8;
|
||||
* where CAPACITANCE is the desired total load capacitance value in pF,
|
||||
* holding any value between 4.0 pF and 17.0 pF in 0.25 pF steps.
|
||||
*/
|
||||
uint32_t capvalue =
|
||||
(((((DT_PROP(HFXO_NODE, load_capacitance_femtofarad) * 4UL) / 1000UL) - 22UL) *
|
||||
(uint32_t)(slope_m + 791) / 4UL) + (offset_m << 2UL)) >> 8UL;
|
||||
|
||||
nrf_oscillators_hfxo_cap_set(NRF_OSCILLATORS, true, capvalue);
|
||||
#elif DT_ENUM_HAS_VALUE(HFXO_NODE, load_capacitors, external)
|
||||
nrf_oscillators_hfxo_cap_set(NRF_OSCILLATORS, false, 0);
|
||||
#endif
|
||||
|
||||
if (IS_ENABLED(CONFIG_SOC_NRF_FORCE_CONSTLAT)) {
|
||||
nrf_power_task_trigger(NRF_POWER, NRF_POWER_TASK_CONSTLAT);
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_SOC_NRF54L_VREG_MAIN_DCDC)) {
|
||||
nrf_regulators_vreg_enable_set(NRF_REGULATORS, NRF_REGULATORS_VREG_MAIN, true);
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_SOC_NRF54L_NORMAL_VOLTAGE_MODE)) {
|
||||
nrf_regulators_vreg_enable_set(NRF_REGULATORS, NRF_REGULATORS_VREG_MEDIUM, false);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_ELV_GRTC_LFXO_ALLOWED)
|
||||
nrf_regulators_elv_mode_allow_set(NRF_REGULATORS, NRF_REGULATORS_ELV_ELVGRTCLFXO_MASK);
|
||||
#endif /* CONFIG_ELV_GRTC_LFXO_ALLOWED */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void arch_busy_wait(uint32_t time_us)
|
||||
{
|
||||
nrfx_coredep_delay_us(time_us);
|
||||
}
|
||||
|
||||
SYS_INIT(nordicsemi_nrf54l_init, PRE_KERNEL_1, 0);
|
||||
19
soc/nordic/nrf54l/soc.h
Normal file
19
soc/nordic/nrf54l/soc.h
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SoC configuration macros for the Nordic Semiconductor NRF54L family processors.
|
||||
*/
|
||||
|
||||
#ifndef _NORDICSEMI_NRF54L_SOC_H_
|
||||
#define _NORDICSEMI_NRF54L_SOC_H_
|
||||
|
||||
#include <soc_nrf_common.h>
|
||||
|
||||
#define FLASH_PAGE_ERASE_MAX_TIME_US 8000UL
|
||||
#define FLASH_PAGE_MAX_CNT 381UL
|
||||
|
||||
#endif /* _NORDICSEMI_NRF54L_SOC_H_ */
|
||||
4
soc/nordic/nrf91/CMakeLists.txt
Normal file
4
soc/nordic/nrf91/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_library_sources(soc.c)
|
||||
zephyr_include_directories(.)
|
||||
37
soc/nordic/nrf91/Kconfig
Normal file
37
soc/nordic/nrf91/Kconfig
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
# Nordic Semiconductor nRF91 MCU line
|
||||
|
||||
# Copyright (c) 2018 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_NRF91X
|
||||
select ARM
|
||||
select CPU_CORTEX_M33
|
||||
select CPU_CORTEX_M_HAS_DWT
|
||||
select CPU_HAS_ARM_MPU
|
||||
select CPU_HAS_NRF_IDAU
|
||||
select CPU_HAS_FPU
|
||||
select ARMV8_M_DSP
|
||||
imply XIP
|
||||
select HAS_NRFX
|
||||
select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
|
||||
select HAS_POWEROFF
|
||||
|
||||
if SOC_SERIES_NRF91X
|
||||
|
||||
config NRF_SPU_FLASH_REGION_SIZE
|
||||
hex
|
||||
default 0x8000
|
||||
help
|
||||
FLASH region size for the NRF_SPU peripheral
|
||||
|
||||
config NRF_SPU_RAM_REGION_SIZE
|
||||
hex
|
||||
default 0x2000
|
||||
help
|
||||
RAM region size for the NRF_SPU peripheral
|
||||
|
||||
config NRF_ENABLE_ICACHE
|
||||
bool "Instruction cache (I-Cache)"
|
||||
default y
|
||||
|
||||
endif # SOC_SERIES_NRF91X
|
||||
14
soc/nordic/nrf91/Kconfig.defconfig
Normal file
14
soc/nordic/nrf91/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
# Nordic Semiconductor nRF91 MCU line
|
||||
|
||||
# Copyright (c) 2018 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_NRF91X
|
||||
|
||||
rsource "Kconfig.defconfig.nrf91*"
|
||||
|
||||
# If the kernel has timer support, enable the timer
|
||||
config NRF_RTC_TIMER
|
||||
default y if SYS_CLOCK_EXISTS
|
||||
|
||||
endif # SOC_SERIES_NRF91X
|
||||
11
soc/nordic/nrf91/Kconfig.defconfig.nrf9131_LACA
Normal file
11
soc/nordic/nrf91/Kconfig.defconfig.nrf9131_LACA
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
# Nordic Semiconductor nRF9131 MCU
|
||||
|
||||
# Copyright (c) 2023 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_NRF9131_LACA
|
||||
|
||||
config NUM_IRQS
|
||||
default 65
|
||||
|
||||
endif # SOC_NRF9131_LACA
|
||||
11
soc/nordic/nrf91/Kconfig.defconfig.nrf9151_LACA
Normal file
11
soc/nordic/nrf91/Kconfig.defconfig.nrf9151_LACA
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
# Nordic Semiconductor nRF9151 MCU
|
||||
|
||||
# Copyright (c) 2023 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_NRF9151_LACA
|
||||
|
||||
config NUM_IRQS
|
||||
default 65
|
||||
|
||||
endif # SOC_NRF9151_LACA
|
||||
11
soc/nordic/nrf91/Kconfig.defconfig.nrf9160_SICA
Normal file
11
soc/nordic/nrf91/Kconfig.defconfig.nrf9160_SICA
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
# Nordic Semiconductor nRF9160 MCU
|
||||
|
||||
# Copyright (c) 2018 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_NRF9160_SICA
|
||||
|
||||
config NUM_IRQS
|
||||
default 65
|
||||
|
||||
endif # SOC_NRF9160_SICA
|
||||
11
soc/nordic/nrf91/Kconfig.defconfig.nrf9161_LACA
Normal file
11
soc/nordic/nrf91/Kconfig.defconfig.nrf9161_LACA
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
# Nordic Semiconductor nRF9161 MCU
|
||||
|
||||
# Copyright (c) 2023 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_NRF9161_LACA
|
||||
|
||||
config NUM_IRQS
|
||||
default 65
|
||||
|
||||
endif # SOC_NRF9161_LACA
|
||||
47
soc/nordic/nrf91/Kconfig.soc
Normal file
47
soc/nordic/nrf91/Kconfig.soc
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
# Nordic Semiconductor nRF91 MCU line
|
||||
|
||||
# Copyright (c) 2018 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_NRF91X
|
||||
select SOC_FAMILY_NORDIC_NRF
|
||||
help
|
||||
Enable support for NRF91 MCU series
|
||||
|
||||
config SOC_NRF9120
|
||||
bool
|
||||
select SOC_SERIES_NRF91X
|
||||
|
||||
config SOC_NRF9131_LACA
|
||||
bool
|
||||
select SOC_NRF9120
|
||||
|
||||
config SOC_NRF9151_LACA
|
||||
bool
|
||||
select SOC_NRF9120
|
||||
|
||||
config SOC_NRF9160
|
||||
bool
|
||||
select SOC_SERIES_NRF91X
|
||||
|
||||
config SOC_NRF9160_SICA
|
||||
bool
|
||||
select SOC_NRF9160
|
||||
|
||||
# The nRF9161 is technically a SiP (System-in-Package) that consists of
|
||||
# the nRF9120 SoC and additional components like PMIC, FEM, and XTAL,
|
||||
# so for nrfx/MDK the nRF9120 SoC is to be indicated as the build target,
|
||||
# but since the nRF9161 is what a user can actually see on a board, using
|
||||
# only nRF9120 in the Zephyr build infrastructure might be confusing.
|
||||
# That's why in the top level of SoC definitions (for user-configurable
|
||||
# options in Kconfig, for example) the nRF9161 term is used and nRF9120
|
||||
# underneath.
|
||||
config SOC_NRF9161_LACA
|
||||
bool
|
||||
select SOC_NRF9120
|
||||
|
||||
config SOC
|
||||
default "nrf9131" if SOC_NRF9131_LACA
|
||||
default "nrf9151" if SOC_NRF9151_LACA
|
||||
default "nrf9160" if SOC_NRF9160_SICA
|
||||
default "nrf9161" if SOC_NRF9161_LACA
|
||||
40
soc/nordic/nrf91/soc.c
Normal file
40
soc/nordic/nrf91/soc.c
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief System/hardware module for Nordic Semiconductor nRF91 family processor
|
||||
*
|
||||
* This module provides routines to initialize and support board-level hardware
|
||||
* for the Nordic Semiconductor nRF91 family processor.
|
||||
*/
|
||||
|
||||
#include <zephyr/kernel.h>
|
||||
#include <zephyr/init.h>
|
||||
#include <soc/nrfx_coredep.h>
|
||||
#include <zephyr/logging/log.h>
|
||||
|
||||
#include <cmsis_core.h>
|
||||
|
||||
#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
|
||||
LOG_MODULE_REGISTER(soc);
|
||||
|
||||
static int nordicsemi_nrf91_init(void)
|
||||
{
|
||||
#ifdef CONFIG_NRF_ENABLE_ICACHE
|
||||
/* Enable the instruction cache */
|
||||
NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk;
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void arch_busy_wait(uint32_t time_us)
|
||||
{
|
||||
nrfx_coredep_delay_us(time_us);
|
||||
}
|
||||
|
||||
SYS_INIT(nordicsemi_nrf91_init, PRE_KERNEL_1, 0);
|
||||
19
soc/nordic/nrf91/soc.h
Normal file
19
soc/nordic/nrf91/soc.h
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SoC configuration macros for the Nordic Semiconductor nRF91 family processors.
|
||||
*/
|
||||
|
||||
#ifndef _NORDICSEMI_NRF91_SOC_H_
|
||||
#define _NORDICSEMI_NRF91_SOC_H_
|
||||
|
||||
#include <soc_nrf_common.h>
|
||||
|
||||
#define FLASH_PAGE_ERASE_MAX_TIME_US 89700UL
|
||||
#define FLASH_PAGE_MAX_CNT 256UL
|
||||
|
||||
#endif /* _NORDICSEMI_NRF91_SOC_H_ */
|
||||
39
soc/nordic/soc.yml
Normal file
39
soc/nordic/soc.yml
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
family:
|
||||
- name: nordic_nrf
|
||||
series:
|
||||
- name: nrf51
|
||||
socs:
|
||||
- name: nrf51822
|
||||
- name: nrf52
|
||||
socs:
|
||||
- name: nrf52805
|
||||
- name: nrf52810
|
||||
- name: nrf52811
|
||||
- name: nrf52820
|
||||
- name: nrf52832
|
||||
- name: nrf52833
|
||||
- name: nrf52840
|
||||
- name: nrf53
|
||||
socs:
|
||||
- name: nrf5340
|
||||
cpuclusters:
|
||||
- name: cpuapp
|
||||
- name: cpunet
|
||||
- name: nrf54l
|
||||
socs:
|
||||
- name: nrf54l15
|
||||
cpuclusters:
|
||||
- name: cpuapp
|
||||
- name: nrf54h
|
||||
socs:
|
||||
- name: nrf54h20
|
||||
cpuclusters:
|
||||
- name: cpuapp
|
||||
- name: cpurad
|
||||
- name: cpuppr
|
||||
- name: nrf91
|
||||
socs:
|
||||
- name: nrf9131
|
||||
- name: nrf9151
|
||||
- name: nrf9160
|
||||
- name: nrf9161
|
||||
80
soc/nordic/timing.c
Normal file
80
soc/nordic/timing.c
Normal file
|
|
@ -0,0 +1,80 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/arch/arm/arch.h>
|
||||
#include <zephyr/kernel.h>
|
||||
#include <zephyr/sys_clock.h>
|
||||
#include <zephyr/timing/timing.h>
|
||||
#include <nrfx.h>
|
||||
|
||||
#if defined(CONFIG_NRF_RTC_TIMER)
|
||||
|
||||
#define CYCLES_PER_SEC (16000000 / (1 << NRF_TIMER2->PRESCALER))
|
||||
|
||||
void soc_timing_init(void)
|
||||
{
|
||||
NRF_TIMER2->TASKS_CLEAR = 1; /* Clear Timer */
|
||||
NRF_TIMER2->MODE = 0; /* Timer Mode */
|
||||
NRF_TIMER2->PRESCALER = 0; /* 16M Hz */
|
||||
#if defined(CONFIG_SOC_SERIES_NRF51X)
|
||||
NRF_TIMER2->BITMODE = 0; /* 16 - bit */
|
||||
#else
|
||||
NRF_TIMER2->BITMODE = 3; /* 32 - bit */
|
||||
#endif
|
||||
}
|
||||
|
||||
void soc_timing_start(void)
|
||||
{
|
||||
NRF_TIMER2->TASKS_START = 1;
|
||||
}
|
||||
|
||||
void soc_timing_stop(void)
|
||||
{
|
||||
NRF_TIMER2->TASKS_STOP = 1; /* Stop Timer */
|
||||
}
|
||||
|
||||
timing_t soc_timing_counter_get(void)
|
||||
{
|
||||
NRF_TIMER2->TASKS_CAPTURE[0] = 1;
|
||||
return NRF_TIMER2->CC[0] * ((SystemCoreClock) / CYCLES_PER_SEC);
|
||||
}
|
||||
|
||||
uint64_t soc_timing_cycles_get(volatile timing_t *const start,
|
||||
volatile timing_t *const end)
|
||||
{
|
||||
#if defined(CONFIG_SOC_SERIES_NRF51X)
|
||||
#define COUNTER_SPAN BIT(16)
|
||||
if (*end >= *start) {
|
||||
return (*end - *start);
|
||||
} else {
|
||||
return COUNTER_SPAN + *end - *start;
|
||||
}
|
||||
#else
|
||||
return (*end - *start);
|
||||
#endif
|
||||
}
|
||||
|
||||
uint64_t soc_timing_freq_get(void)
|
||||
{
|
||||
return SystemCoreClock;
|
||||
}
|
||||
|
||||
uint64_t soc_timing_cycles_to_ns(uint64_t cycles)
|
||||
{
|
||||
return (cycles) * (NSEC_PER_SEC) / (SystemCoreClock);
|
||||
}
|
||||
|
||||
uint64_t soc_timing_cycles_to_ns_avg(uint64_t cycles, uint32_t count)
|
||||
{
|
||||
return soc_timing_cycles_to_ns(cycles) / count;
|
||||
}
|
||||
|
||||
uint32_t soc_timing_freq_get_mhz(void)
|
||||
{
|
||||
return (uint32_t)(soc_timing_freq_get() / 1000000);
|
||||
}
|
||||
|
||||
#endif
|
||||
241
soc/nordic/validate_base_addresses.c
Normal file
241
soc/nordic/validate_base_addresses.c
Normal file
|
|
@ -0,0 +1,241 @@
|
|||
/*
|
||||
* Copyright (c) 2019, 2020 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/kernel.h>
|
||||
#include <zephyr/devicetree.h>
|
||||
|
||||
#include <nrfx.h>
|
||||
|
||||
/*
|
||||
* Account for MDK inconsistencies
|
||||
*/
|
||||
|
||||
#if !defined(NRF_CTRLAP) && defined(NRF_CTRL_AP_PERI)
|
||||
#define NRF_CTRLAP NRF_CTRL_AP_PERI
|
||||
#endif
|
||||
|
||||
#if !defined(NRF_GPIOTE0) && defined(NRF_GPIOTE)
|
||||
#define NRF_GPIOTE0 NRF_GPIOTE
|
||||
#endif
|
||||
|
||||
#if !defined(NRF_I2S0) && defined(NRF_I2S)
|
||||
#define NRF_I2S0 NRF_I2S
|
||||
#endif
|
||||
|
||||
#if !defined(NRF_P0) && defined(NRF_GPIO)
|
||||
#define NRF_P0 NRF_GPIO
|
||||
#endif
|
||||
|
||||
#if !defined(NRF_PDM0) && defined(NRF_PDM)
|
||||
#define NRF_PDM0 NRF_PDM
|
||||
#endif
|
||||
|
||||
#if !defined(NRF_QDEC0) && defined(NRF_QDEC)
|
||||
#define NRF_QDEC0 NRF_QDEC
|
||||
#endif
|
||||
|
||||
#if !defined(NRF_SWI0) && defined(NRF_SWI_BASE)
|
||||
#define NRF_SWI0 ((0 * 0x1000) + NRF_SWI_BASE)
|
||||
#endif
|
||||
|
||||
#if !defined(NRF_SWI1) && defined(NRF_SWI_BASE)
|
||||
#define NRF_SWI1 ((1 * 0x1000) + NRF_SWI_BASE)
|
||||
#endif
|
||||
|
||||
#if !defined(NRF_SWI2) && defined(NRF_SWI_BASE)
|
||||
#define NRF_SWI2 ((2 * 0x1000) + NRF_SWI_BASE)
|
||||
#endif
|
||||
|
||||
#if !defined(NRF_SWI3) && defined(NRF_SWI_BASE)
|
||||
#define NRF_SWI3 ((3 * 0x1000) + NRF_SWI_BASE)
|
||||
#endif
|
||||
|
||||
#if !defined(NRF_SWI4) && defined(NRF_SWI_BASE)
|
||||
#define NRF_SWI4 ((4 * 0x1000) + NRF_SWI_BASE)
|
||||
#endif
|
||||
|
||||
#if !defined(NRF_SWI5) && defined(NRF_SWI_BASE)
|
||||
#define NRF_SWI5 ((5 * 0x1000) + NRF_SWI_BASE)
|
||||
#endif
|
||||
|
||||
#if !defined(NRF_WDT0) && defined(NRF_WDT)
|
||||
#define NRF_WDT0 NRF_WDT
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOC_SERIES_NRF51X) || defined(CONFIG_SOC_SERIES_NRF52X)
|
||||
#if !defined(NRF_POWER_GPREGRET1) && defined(NRF_POWER_BASE)
|
||||
#define NRF_POWER_GPREGRET1 (0x51c + NRF_POWER_BASE)
|
||||
#endif
|
||||
|
||||
#if !defined(NRF_POWER_GPREGRET2) && defined(NRF_POWER_BASE)
|
||||
#define NRF_POWER_GPREGRET2 (0x520 + NRF_POWER_BASE)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Check that a devicetree node's "reg" base address matches the
|
||||
* correct value from the MDK.
|
||||
*
|
||||
* Node reg values are checked against MDK addresses regardless of
|
||||
* their status.
|
||||
*
|
||||
* Using a node label allows the same file to work with multiple SoCs
|
||||
* and devicetree configurations.
|
||||
*
|
||||
* @param lbl lowercase-and-underscores devicetree node label to check
|
||||
* @param mdk_addr expected address from the Nordic MDK.
|
||||
*/
|
||||
#define CHECK_DT_REG(lbl, mdk_addr) \
|
||||
BUILD_ASSERT( \
|
||||
UTIL_OR(UTIL_NOT(DT_NODE_EXISTS(DT_NODELABEL(lbl))), \
|
||||
(DT_REG_ADDR(DT_NODELABEL(lbl)) == (uint32_t)(mdk_addr))))
|
||||
|
||||
/**
|
||||
* If a node label "lbl" might have different addresses depending on
|
||||
* its compatible "compat", you can use this macro to pick the right
|
||||
* one.
|
||||
*
|
||||
* @param lbl lowercase-and-underscores devicetree node label to check
|
||||
* @param compat lowercase-and-underscores compatible to check
|
||||
* @param addr_if_match MDK address to return if "lbl" has compatible "compat"
|
||||
* @param addr_if_no_match MDK address to return otherwise
|
||||
*/
|
||||
#define NODE_ADDRESS(lbl, compat, addr_if_match, addr_if_no_match) \
|
||||
COND_CODE_1(DT_NODE_HAS_COMPAT(DT_NODELABEL(lbl), compat), \
|
||||
(addr_if_match), (addr_if_no_match))
|
||||
|
||||
#define CHECK_SPI_REG(lbl, num) \
|
||||
CHECK_DT_REG(lbl, \
|
||||
NODE_ADDRESS(lbl, nordic_nrf_spi, NRF_SPI##num, \
|
||||
NODE_ADDRESS(lbl, nordic_nrf_spim, NRF_SPIM##num, \
|
||||
NRF_SPIS##num)))
|
||||
|
||||
#define CHECK_I2C_REG(lbl, num) \
|
||||
CHECK_DT_REG(lbl, \
|
||||
NODE_ADDRESS(lbl, nordic_nrf_twi, NRF_TWI##num, \
|
||||
NODE_ADDRESS(lbl, nordic_nrf_twim, NRF_TWIM##num, \
|
||||
NRF_TWIS##num)))
|
||||
|
||||
#define CHECK_UART_REG(lbl, num) \
|
||||
CHECK_DT_REG(lbl, \
|
||||
NODE_ADDRESS(lbl, nordic_nrf_uart, NRF_UART##num, \
|
||||
NRF_UARTE##num))
|
||||
|
||||
CHECK_DT_REG(acl, NRF_ACL);
|
||||
CHECK_DT_REG(adc, NODE_ADDRESS(adc, nordic_nrf_adc, NRF_ADC, NRF_SAADC));
|
||||
CHECK_DT_REG(bprot, NRF_BPROT);
|
||||
CHECK_DT_REG(ccm, NRF_CCM);
|
||||
CHECK_DT_REG(clock, NRF_CLOCK);
|
||||
CHECK_DT_REG(comp, NODE_ADDRESS(comp, nordic_nrf_comp, NRF_COMP, NRF_LPCOMP));
|
||||
CHECK_DT_REG(cryptocell, NRF_CRYPTOCELL);
|
||||
CHECK_DT_REG(ctrlap, NRF_CTRLAP);
|
||||
CHECK_DT_REG(dcnf, NRF_DCNF);
|
||||
CHECK_DT_REG(dppic, NRF_DPPIC);
|
||||
CHECK_DT_REG(ecb, NRF_ECB);
|
||||
CHECK_DT_REG(egu0, NRF_EGU0);
|
||||
CHECK_DT_REG(egu1, NRF_EGU1);
|
||||
CHECK_DT_REG(egu2, NRF_EGU2);
|
||||
CHECK_DT_REG(egu3, NRF_EGU3);
|
||||
CHECK_DT_REG(egu4, NRF_EGU4);
|
||||
CHECK_DT_REG(egu5, NRF_EGU5);
|
||||
CHECK_DT_REG(ficr, NRF_FICR);
|
||||
CHECK_DT_REG(flash_controller, NRF_NVMC);
|
||||
CHECK_DT_REG(gpio0, NRF_P0);
|
||||
CHECK_DT_REG(gpio1, NRF_P1);
|
||||
CHECK_DT_REG(gpiote, NRF_GPIOTE);
|
||||
CHECK_DT_REG(gpiote0, NRF_GPIOTE0);
|
||||
CHECK_DT_REG(gpiote1, NRF_GPIOTE1);
|
||||
CHECK_DT_REG(gpiote20, NRF_GPIOTE20);
|
||||
CHECK_DT_REG(gpiote30, NRF_GPIOTE30);
|
||||
CHECK_DT_REG(gpiote130, NRF_GPIOTE130);
|
||||
CHECK_DT_REG(gpiote131, NRF_GPIOTE131);
|
||||
CHECK_I2C_REG(i2c0, 0);
|
||||
CHECK_I2C_REG(i2c1, 1);
|
||||
CHECK_DT_REG(i2c2, NRF_TWIM2);
|
||||
CHECK_DT_REG(i2c3, NRF_TWIM3);
|
||||
CHECK_DT_REG(i2s0, NRF_I2S0);
|
||||
CHECK_DT_REG(ipc, NRF_IPC);
|
||||
CHECK_DT_REG(kmu, NRF_KMU);
|
||||
CHECK_DT_REG(mutex, NRF_MUTEX);
|
||||
CHECK_DT_REG(mwu, NRF_MWU);
|
||||
CHECK_DT_REG(nfct, NRF_NFCT);
|
||||
CHECK_DT_REG(nrf_mpu, NRF_MPU);
|
||||
CHECK_DT_REG(oscillators, NRF_OSCILLATORS);
|
||||
CHECK_DT_REG(pdm0, NRF_PDM0);
|
||||
CHECK_DT_REG(power, NRF_POWER);
|
||||
CHECK_DT_REG(ppi, NRF_PPI);
|
||||
CHECK_DT_REG(pwm0, NRF_PWM0);
|
||||
CHECK_DT_REG(pwm1, NRF_PWM1);
|
||||
CHECK_DT_REG(pwm2, NRF_PWM2);
|
||||
CHECK_DT_REG(pwm3, NRF_PWM3);
|
||||
CHECK_DT_REG(qdec, NRF_QDEC0); /* this should be the same node as qdec0 */
|
||||
CHECK_DT_REG(qdec0, NRF_QDEC0);
|
||||
CHECK_DT_REG(qdec1, NRF_QDEC1);
|
||||
CHECK_DT_REG(radio, NRF_RADIO);
|
||||
CHECK_DT_REG(regulators, NRF_REGULATORS);
|
||||
CHECK_DT_REG(reset, NRF_RESET);
|
||||
CHECK_DT_REG(rng, NRF_RNG);
|
||||
CHECK_DT_REG(rtc0, NRF_RTC0);
|
||||
CHECK_DT_REG(rtc1, NRF_RTC1);
|
||||
CHECK_DT_REG(rtc2, NRF_RTC2);
|
||||
CHECK_SPI_REG(spi0, 0);
|
||||
CHECK_SPI_REG(spi1, 1);
|
||||
CHECK_SPI_REG(spi2, 2);
|
||||
CHECK_DT_REG(spi3, NRF_SPIM3);
|
||||
CHECK_DT_REG(spi4, NRF_SPIM4);
|
||||
CHECK_DT_REG(spu, NRF_SPU);
|
||||
CHECK_DT_REG(swi0, NRF_SWI0);
|
||||
CHECK_DT_REG(swi1, NRF_SWI1);
|
||||
CHECK_DT_REG(swi2, NRF_SWI2);
|
||||
CHECK_DT_REG(swi3, NRF_SWI3);
|
||||
CHECK_DT_REG(swi4, NRF_SWI4);
|
||||
CHECK_DT_REG(swi5, NRF_SWI5);
|
||||
CHECK_DT_REG(temp, NRF_TEMP);
|
||||
CHECK_DT_REG(timer0, NRF_TIMER0);
|
||||
CHECK_DT_REG(timer1, NRF_TIMER1);
|
||||
CHECK_DT_REG(timer2, NRF_TIMER2);
|
||||
CHECK_DT_REG(timer3, NRF_TIMER3);
|
||||
CHECK_DT_REG(timer4, NRF_TIMER4);
|
||||
CHECK_DT_REG(timer00, NRF_TIMER00);
|
||||
CHECK_DT_REG(timer10, NRF_TIMER10);
|
||||
CHECK_DT_REG(timer20, NRF_TIMER20);
|
||||
CHECK_DT_REG(timer21, NRF_TIMER21);
|
||||
CHECK_DT_REG(timer22, NRF_TIMER22);
|
||||
CHECK_DT_REG(timer23, NRF_TIMER23);
|
||||
CHECK_DT_REG(timer24, NRF_TIMER24);
|
||||
CHECK_UART_REG(uart0, 0);
|
||||
CHECK_DT_REG(uart1, NRF_UARTE1);
|
||||
CHECK_DT_REG(uart2, NRF_UARTE2);
|
||||
CHECK_DT_REG(uart3, NRF_UARTE3);
|
||||
CHECK_DT_REG(uart00, NRF_UARTE00);
|
||||
CHECK_DT_REG(uart20, NRF_UARTE20);
|
||||
CHECK_DT_REG(uart21, NRF_UARTE21);
|
||||
CHECK_DT_REG(uart22, NRF_UARTE22);
|
||||
CHECK_DT_REG(uart30, NRF_UARTE30);
|
||||
CHECK_DT_REG(uart120, NRF_UARTE120);
|
||||
CHECK_DT_REG(uart130, NRF_UARTE130);
|
||||
CHECK_DT_REG(uart131, NRF_UARTE131);
|
||||
CHECK_DT_REG(uart132, NRF_UARTE132);
|
||||
CHECK_DT_REG(uart133, NRF_UARTE133);
|
||||
CHECK_DT_REG(uart134, NRF_UARTE134);
|
||||
CHECK_DT_REG(uart135, NRF_UARTE135);
|
||||
CHECK_DT_REG(uart136, NRF_UARTE136);
|
||||
CHECK_DT_REG(uart137, NRF_UARTE137);
|
||||
CHECK_DT_REG(uicr, NRF_UICR);
|
||||
CHECK_DT_REG(usbd, NRF_USBD);
|
||||
CHECK_DT_REG(usbreg, NRF_USBREGULATOR);
|
||||
CHECK_DT_REG(vmc, NRF_VMC);
|
||||
CHECK_DT_REG(wdt, NRF_WDT0); /* this should be the same node as wdt0 */
|
||||
CHECK_DT_REG(wdt0, NRF_WDT0);
|
||||
CHECK_DT_REG(wdt1, NRF_WDT1);
|
||||
CHECK_DT_REG(wdt30, NRF_WDT30);
|
||||
CHECK_DT_REG(wdt31, NRF_WDT31);
|
||||
|
||||
/* nRF51/nRF52-specific addresses */
|
||||
#if defined(CONFIG_SOC_SERIES_NRF51X) || defined(CONFIG_SOC_SERIES_NRF52X)
|
||||
CHECK_DT_REG(gpregret1, NRF_POWER_GPREGRET1);
|
||||
CHECK_DT_REG(gpregret2, NRF_POWER_GPREGRET2);
|
||||
#endif
|
||||
59
soc/nordic/validate_enabled_instances.c
Normal file
59
soc/nordic/validate_enabled_instances.c
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/kernel.h>
|
||||
|
||||
#define I2C_ENABLED(idx) (IS_ENABLED(CONFIG_I2C) && \
|
||||
DT_NODE_HAS_STATUS(DT_NODELABEL(i2c##idx), okay))
|
||||
|
||||
#define SPI_ENABLED(idx) (IS_ENABLED(CONFIG_SPI) && \
|
||||
DT_NODE_HAS_STATUS(DT_NODELABEL(spi##idx), okay))
|
||||
|
||||
#define UART_ENABLED(idx) (IS_ENABLED(CONFIG_SERIAL) && \
|
||||
(IS_ENABLED(CONFIG_SOC_SERIES_NRF53X) || \
|
||||
IS_ENABLED(CONFIG_SOC_SERIES_NRF91X)) && \
|
||||
DT_NODE_HAS_STATUS(DT_NODELABEL(uart##idx), okay))
|
||||
|
||||
/*
|
||||
* In most Nordic SoCs, SPI and TWI peripherals with the same instance number
|
||||
* share certain resources and therefore cannot be used at the same time (in
|
||||
* nRF53 and nRF91 Series this limitation concerns UART peripherals as well).
|
||||
*
|
||||
* In some SoCs, like nRF52810, there are only single instances of
|
||||
* these peripherals and they are arranged in a different way, so this
|
||||
* limitation does not apply.
|
||||
*
|
||||
* The build assertions below check if conflicting peripheral instances are not
|
||||
* enabled simultaneously.
|
||||
*/
|
||||
|
||||
#define CHECK(idx) \
|
||||
!(I2C_ENABLED(idx) && SPI_ENABLED(idx)) && \
|
||||
!(I2C_ENABLED(idx) && UART_ENABLED(idx)) && \
|
||||
!(SPI_ENABLED(idx) && UART_ENABLED(idx))
|
||||
|
||||
#define MSG(idx) \
|
||||
"Only one of the following peripherals can be enabled: " \
|
||||
"SPI"#idx", SPIM"#idx", SPIS"#idx", TWI"#idx", TWIM"#idx", TWIS"#idx \
|
||||
IF_ENABLED(CONFIG_SOC_SERIES_NRF53X, (", UARTE"#idx)) \
|
||||
IF_ENABLED(CONFIG_SOC_SERIES_NRF91X, (", UARTE"#idx)) \
|
||||
". Check nodes with status \"okay\" in zephyr.dts."
|
||||
|
||||
#if (!IS_ENABLED(CONFIG_SOC_NRF52810) && \
|
||||
!IS_ENABLED(CONFIG_SOC_NRF52805) && \
|
||||
!IS_ENABLED(CONFIG_SOC_NRF52811))
|
||||
BUILD_ASSERT(CHECK(0), MSG(0));
|
||||
#endif
|
||||
BUILD_ASSERT(CHECK(1), MSG(1));
|
||||
BUILD_ASSERT(CHECK(2), MSG(2));
|
||||
BUILD_ASSERT(CHECK(3), MSG(3));
|
||||
|
||||
#if defined(CONFIG_SOC_NRF52811)
|
||||
BUILD_ASSERT(!(SPI_ENABLED(1) && I2C_ENABLED(0)),
|
||||
"Only one of the following peripherals can be enabled: "
|
||||
"SPI1, SPIM1, SPIS1, TWI0, TWIM0, TWIS0. "
|
||||
"Check nodes with status \"okay\" in zephyr.dts.");
|
||||
#endif
|
||||
97
soc/nordic/validate_rram_partitions.c
Normal file
97
soc/nordic/validate_rram_partitions.c
Normal file
|
|
@ -0,0 +1,97 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/sys/util_macro.h>
|
||||
#include <zephyr/toolchain.h>
|
||||
|
||||
#define PAIR__(f, sep, arg_first, ...) FOR_EACH_FIXED_ARG(f, sep, arg_first, __VA_ARGS__)
|
||||
#define PAIR_(f, sep, args_to_expand) PAIR__(f, sep, args_to_expand)
|
||||
#define PAIR(n, f, sep, ...) PAIR_(f, sep, GET_ARGS_LESS_N(n, __VA_ARGS__))
|
||||
|
||||
/**
|
||||
* @brief Call a macro on every unique pair of the given variadic arguments.
|
||||
*
|
||||
* For example, FOR_EACH_PAIR(f, (,), 1, 2, 3, 4) should expand to:
|
||||
*
|
||||
* f(2, 1) , f(3, 1) , f(4, 1) , f(3, 2) , f(4, 2) , f(4, 3)
|
||||
*
|
||||
* @param f Macro to call. Must accept two arguments.
|
||||
* @param sep Separator between macro calls. Must be in parentheses.
|
||||
*
|
||||
* @see FOR_EACH
|
||||
*/
|
||||
#define FOR_EACH_PAIR(f, sep, ...) \
|
||||
LISTIFY(NUM_VA_ARGS_LESS_1(__VA_ARGS__), PAIR, sep, f, sep, __VA_ARGS__)
|
||||
|
||||
/**
|
||||
* @brief Get a node's non-secure register block start address.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
*/
|
||||
#define REG_ADDR_NS(node_id) (DT_REG_ADDR(node_id) & 0xEFFFFFFFUL)
|
||||
|
||||
/**
|
||||
* @brief Get a node's non-secure register block end address.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
*/
|
||||
#define REG_END_NS(node_id) (REG_ADDR_NS(node_id) + DT_REG_SIZE(node_id))
|
||||
|
||||
/* clang-format off */
|
||||
|
||||
#define RRAM_BASE REG_ADDR_NS(DT_NODELABEL(rram0))
|
||||
#define RRAM_CONTROLLER DT_NODELABEL(rram_controller)
|
||||
|
||||
#if !DT_NODE_EXISTS(RRAM_CONTROLLER)
|
||||
#error "Missing \"rram-controller\" node"
|
||||
#endif
|
||||
|
||||
#define CHECK_RRAM_NODE_COMPATIBLE(node_id) \
|
||||
BUILD_ASSERT(DT_NODE_HAS_COMPAT(node_id, soc_nv_flash), \
|
||||
"Missing compatible \"soc-nv-flash\" from " DT_NODE_FULL_NAME(node_id) \
|
||||
" (required for all children of " DT_NODE_PATH(RRAM_CONTROLLER) ")")
|
||||
|
||||
#define CHECK_RRAM_PARTITION_WITHIN_PARENT(node_id) \
|
||||
BUILD_ASSERT(RRAM_BASE + REG_ADDR_NS(node_id) >= REG_ADDR_NS(DT_GPARENT(node_id)) && \
|
||||
RRAM_BASE + REG_END_NS(node_id) <= REG_END_NS(DT_GPARENT(node_id)), \
|
||||
DT_NODE_FULL_NAME(node_id) " is not fully contained within its parent " \
|
||||
DT_NODE_PATH(DT_GPARENT(node_id)))
|
||||
|
||||
#define CHECK_NODES_NON_OVERLAPPING(node_id_1, node_id_2) \
|
||||
BUILD_ASSERT(REG_ADDR_NS(node_id_1) >= REG_END_NS(node_id_2) || \
|
||||
REG_ADDR_NS(node_id_2) >= REG_END_NS(node_id_1), \
|
||||
DT_NODE_PATH(node_id_1) " and " DT_NODE_PATH(node_id_2) " are overlapping")
|
||||
|
||||
/* Retrieve all RRAM nodes that are children of "rram-controller". */
|
||||
#define COMMA(x) x,
|
||||
#define RRAM_NODES_LIST LIST_DROP_EMPTY(DT_FOREACH_CHILD(RRAM_CONTROLLER, COMMA))
|
||||
|
||||
#if !IS_EMPTY(RRAM_NODES_LIST)
|
||||
|
||||
/* Check that every RRAM node matches the "soc-nv-flash" compatible. */
|
||||
FOR_EACH(CHECK_RRAM_NODE_COMPATIBLE, (;), RRAM_NODES_LIST);
|
||||
|
||||
/* Check that no two RRAM nodes are overlapping. */
|
||||
FOR_EACH_PAIR(CHECK_NODES_NON_OVERLAPPING, (;), RRAM_NODES_LIST);
|
||||
|
||||
#endif
|
||||
|
||||
/* Retrieve all RRAM partitions by looking for "fixed-partitions" compatibles in each RRAM node. */
|
||||
#define PARTITION_(x) \
|
||||
COND_CODE_1(DT_NODE_HAS_COMPAT(x, fixed_partitions), (DT_FOREACH_CHILD(x, COMMA)), ())
|
||||
#define PARTITION(x, ...) DT_FOREACH_CHILD_STATUS_OKAY(x, PARTITION_)
|
||||
#define RRAM_PARTITION_LIST LIST_DROP_EMPTY(DT_FOREACH_CHILD_VARGS(RRAM_CONTROLLER, PARTITION))
|
||||
|
||||
#if !IS_EMPTY(RRAM_PARTITION_LIST)
|
||||
|
||||
/* Check that every RRAM partition is within the bounds of its parent RRAM node. */
|
||||
FOR_EACH(CHECK_RRAM_PARTITION_WITHIN_PARENT, (;), RRAM_PARTITION_LIST);
|
||||
|
||||
/* Check that no two RRAM partitions are overlapping. */
|
||||
FOR_EACH_PAIR(CHECK_NODES_NON_OVERLAPPING, (;), RRAM_PARTITION_LIST);
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue