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hwmv2: Introduce Hardware model version 2 and convert devices

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This is a squash of the ``collab-hwm`` branch which converts all
in-tree boards to hardware model version 2 including build system
changes, board updates and soc conversions.

This squash is a combination of the following commits:

ca214745a1 soc: Remove soc_legacy folder and move ARM Kconfig
f12cb0979f scripts: ci: check_compliance: remove HWMv1 checks
1807bcf4d4 boards: mimx8mq_evk: port to HWMv2
3ec2299c62 soc: nxp: port imx8mq SOC to HWMv2
8ea02f4e63 boards: verdin_imx8mp: convert to HVMv2
f2eb7652ce boards: phyboard_pollux: move to HVMv2
ab509a5ee0 boards: nxp: mimx8mp_evk: port M7 core to HWMv2
06ad037f99 soc: nxp: imx8mp: port M7 core to HWMv2
3f9e706859 boards: mimx8mm_phyboard: convert to HVMv2
204372d264 boards: imx8mm_evk: port CM4 core to HWMv2
f82c961a46 soc: nxp: imx8mm: port iMX8MM M4 core to HVMv2
6987b2e305 boards: pico_pi: convert to HVMv2
84484e6707 boards: warp7: convert to HWMv2
ae443d1e3c boards: meerkat96: port to HWMv2
e3629c64e6 boards: colibri_imx7d: port to HWMv2
fc835d893d soc: nxp: convert iMX7 Dual core to HWMv2
29ef2f23eb boards: udoo_neo_full: convert to HWMv2
fd49b1749e soc: nxp: convert iMX6 SoloX core to HWMv2
1e59b7a3fd soc: nxp: imxrt11xx: only set
           CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION for M7
69bb0eb258 hwmv2: MAINTAINERS: Fix NXP maintainer yaml
1c4458890f boards: firefly: roc_rk3568_pc: Fix SMP configuration
651a4370ad boards: Fix variants and revisions
196cfda66d tests/samples: Drop default revision identifiers
6ec6b1d75a boards: Drop revision from twister identifiers for
           default revisions
b774cdd59f scripts: utils: board_v1_to_v2: drop board_legacy prefix
7aa36e6640 boards: riscv: esp32c3_luatos_core: make usb variant
fe25709a9c twister: add unit_testing soc and board
f88f211b4e scripts: ci: check_compliance: improve the "not sorted"
           command
b21a455dfb bluetooth: controller: Fix openisa checks
fdc76c48a7 workflow: compliance: Add rename limit
14ecafc67d dts: bindings: vendor-prefixes: Sort entries
dbc366c3c7 soc: nxp: lpc: Move wrong configurations
8e02c08f96 maintainers: Fix invalid paths
b1b85e2495 boards: up: Fix spaces
58cc4013b3 maintainers: Fix xen path
66ce5c0b09 boards/soc: Add missing copyright headers
bb47243254 boards: qemu: x86: Remove pointless file
2e816a8a3a samples: tests: update esp32-based board naming
9aeab17139 samples: tests: remove platform_exclude of esp32 boards
a4fe97b9de boards: shields: m5stack_core2_ext: update board name
615fcab94a samples: ipm_esp32: fix board labels and skip testing
7752f69b7f boards: legacy: remove index entry for xtensa/riscv
           boards.
3eba827956 MAINTAINERS: update Espressif entries
914362bbd5 boards: xtensa: yd_esp32: Convert to v2
a62278fd23 boards: xtensa: xiao_esp32s3: Convert to v2
b6a11ccec4 boards: xtensa: olimex_esp32_evb: Convert to v2
c1067c16d2 boards: xtensa: odroid_go: Convert to v2
b8340b0109 boards: xtensa: m5stickc_plus: Convert to v2
9d81e417be boards: xtensa: m5stack_stamps3: Convert to v2
c296672720 boards: xtensa: m5stack_core2: Convert to v2
fada12aa9d boards: xtensa: m5stack_atoms3_lite: Convert to v2
fe37ebac1e boards: xtensa: m5stack_atoms3: Convert to v2
d32828fe6a boards: xtensa: kincony_kc868_a32: Convert to v2
5afba7855b boards: xtensa: heltec_wireless_stick_lite_v3: Convert to
           v2
ca48c17723 boards: xtensa: heltec_wifi_lora32_v2: Convert to v2
db1fd4d229 boards: xtensa: esp32s3_luatos_core: Convert to v2
a78b2552eb boards: xtensa: esp32s3_devkitm: Convert to v2
cc96061d96 boards: xtensa: esp32s2_saola: Convert to v2
ed854e05d1 boards: xtensa: esp32s2_lolin_mini: Convert to v2
4fa1ae8110 boards: xtensa: esp32s2_franzininho: Convert to v2
5543040a18 boards: xtensa: esp_wrover_kit: Convert to v2
2335ae79b3 boards: xtensa: esp32_ethernet_kit: Convert to v2
f910b7ad4f boards: xtensa: esp32_devkitc_wrover: Convert to v2
32104db555 boards: xtensa: esp32_devkitc_wroom: Convert to v2
e23a41200d boards: riscv: icev_wireless: Convert to v2
3c670e4e53 boards: riscv: xiao_esp32c3: Convert to v2
fc7c6a060b boards: riscv: stamp_c3: Convert to v2
22c2edb89c boards: riscv: esp32c3_luatos_core: Convert to v2
0a96dcb778 boards: riscv: esp32c3_devkitm: Convert to v2
be1ee1c446 vendors: update vendors lists
5e6c62137f soc: espressif_esp32: Port to HWMv2
037a3b52a4 boards: Raspberry Pi pico pwm led adjustment
7277cae6fa samples: blinky_pwm: enable pwm_leds in rpi_pico overlay
da3e49d34e boards: nxp: update selection of
           FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
bc8424dd3b soc: nxp: imxrt: move FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
           to SOC level
041cb52939 soc: brcm: bcm_vk: Rename to bcnvk
576b43a95c soc: Fix SOC_FAMILY name mismatches
e8f3e6494d hwmv2: boards: intel: adsp: Fix runner after paths
           renamed
550399e927 boards: weact: stm32g431_core: Add wrongly deleted file
           back
08708c909e tests: drivers: flash: Renamed missed board rename
06dac41e68 hwmv2: Convert Seagate Faze board to hwmv2
dd8f842b40 hwmv2: nxp: update MAINTAINER paths for hwmv2
b4d1c04978 hwmv2: lpc: updated overlay and conf files in samples and
           tests
067c69089e boards: nxp: convert lpcxpresso55s69 to hwmv2
097205b40a hwmv2: Global fix of lpc54114_m4 overlay and conf files
d8cfa6fb29 boards: nxp: convert lpcxpresso54114 to hwmv2
c29ed228c6 boards: nxp: convert lpcxpresso55s36 to hwmv2
88cfd3d6ac boards: nxp: convert lpcxpresso55s28 to hwmv2
ad30c940ee boards: nxp: convert lpcxpresso55s16 to hwmv2
9e5a10ec80 boards: nxp: convert lpcxpresso55s06 to hwmv2
5650c83268 boards: nxp: convert lpcxpresso51u68 to hwmv2
82cf44be45 boards: nxp:  convert lpcxpresso11u68 to hwmv2
1a9c405a6f soc: nxp: convert LPC SOC family to hardware model V2
f2b536d253 boards: intel: doc: hwmv2: Fix some renamed paths
5ee6058710 samples/tests: Use board revisions
b76687602f boards: Add yaml files for boards missing revisions
32ae4918d0 boards: nordic: Fix board names
cc1dabca65 MAINTAINERS: Update for renamed folders
a37ddce659 soc: xilinx: Rename to xlnx
a1393a07f6 soc: xenvm: Rename to xen
813ed00f67 soc: raspberry_pi: Rename to raspberrypi
71317d6798 soc: cadence: Rename to cdns
8cb0c51ec6 soc: broadcom: Rename to brcm
2b9db15c69 soc: andes: Rename to andestech
0101216ce1 soc: altera: Rename to altr
4b4c3ca65d boards: wurth_elektronik: Rename to we
cdc3ef499f boards: ublox: Rename to u-blox
cabdd4ad05 boards: space_cubics: Rename to sc
4b5bd7ae8a boards: seeed_studio: Rename to seeed
a992785ceb boards: raspberry_pi: Rename to raspberrypi
3c1cdc20fe boards: laird_connect: Rename to lairdconnect
291c7cde2b boards: cadence: Rename to cdns
95db897526 boards: broadcom: Rename to brcm
0a47b94879 boards: beagleboard: Change to beagle
9f9f221c24 boards: andes: Rename to andestech
e7869ca38a boards: altera: Rename to altr
bf2fb5eca3 various: Change SOC_FAMILY_NRF to SOC_FAMILY_NORDIC_NRF
e25730ba56 modules: tf-m: Rename from nordic_nrf to nordic
9e3466606a boards: nordic_nrf: Rename to nordic
09a398dcc8 soc: nordic_nrf: Rename to nordic
cb8ffc74f8 boards: renode: Add documentation index
2291ff4b55 boards: arm: riscv32_virtual: Convert to v2
484b7f1996 soc: riscv_renode_virtual: Port to HWMv2
cc5c2fb0c7 soc: raspberry_pi: Fix SOC_SERIES and SOC mismatch
59cb580513 soc: arm: designstart: Fix SOC_SERIES and SOC mismatch
aa9e0de7af samples: Fix invalid links
a1480cf1cf maintainers: Fix paths
0d719e004b boards: Update documentation links
eb5c3e6f79 boards: wurth_elektronik: Drop duplicate prefix
a34a3640b7 boards: waveshare: Drop duplicate prefix
cf50e950e7 boards: weact: Drop duplicate prefix
737cfb548f boards: sparkfun: Drop duplicate prefix
505494c97a boards: segger: Drop duplicate prefix
4eaf69f37a boards: ruuvi: Drop duplicate prefix
a1335caeae boards: ronoth: Drop duplicate prefix
a9f7f30bf6 boards: raytac: Drop duplicate prefix
80db4c81b3 boards: qemu: Drop duplicate prefix
433d7e9976 boards: particle: Drop duplicate prefix
4ea79d19e7 boards: olimex: Drop duplicate prefix
fd4ae6f6a8 boards: mikroe: Drop duplicate prefix
36080549bd boards: khados: Drop duplicate prefix
169bf8ae1d boards: intel: Drop duplicate prefix
25f04d5222 boards: holyiot: Drop duplicate prefix
11c2af0de8 boards: google: Drop duplicate prefix
d5128f4016 boards: ebyte: Drop duplicate prefix
44fbc68cad boards: dragino: Drop duplicate prefix
f7fe431b44 boards: contextual_electronics: Drop duplicate prefix
9094fea63b boards: circuit_dojo: Drop duplicate prefix
b632acc1fc boards: blue_clover: Drop duplicate prefix
1a3316ebdc boards: bbc: Drop duplicate prefix
71c0344f8c boards: arduino: Drop duplicate prefix
f0176fc25f boards: altera: Drop duplicate prefix
36b920ed0f boards: adi: Drop duplicate prefix
22520368d9 boards: adafruit: Drop duplicate prefix
296acfb2bc boards: actinius: Drop duplicate prefix
55063380b7 boards: 96boards: Drop duplicate prefix
1f93394b55 boards: nxp: convert mimxrt595_evk to hardware model v2
e7a4fd2ec1 soc: nxp: rt5xx: convert RT5xx SOC to HWMv2
01942f1d11 twister: normalize platform name when storing files/data
477c8b84dd twister: tests: test with slashes in platform names
64e3e816c4 soc: Add include guards
3a7aa2fa49 gitignore: update the compliance file list
84e1c17ad9 scripts: ci: check_compliance: add a check for board yml
           file
a90f53ad57 boards: sync up the vendor tags and vendor-list
af9aa65299 dts: vendor-prefixes: add keep-sorted markers
50f0bf05a3 dts: vendor-prefixes: sort the vendor list
a10b614aa4 dts: vendor-prefixes: ensure all prefixes are lowercase
5abe735e93 manifest: update SOF sha for NXP HWMv2
9ab8f64ca9 modules: rename SOC_FAMILY_IMX
483ff8dd4d modules: mcux: remove SOC_FAMILY_NXP_ADSP
f113dd5342 samples: update board name
39b31287d9 boards: nxp: Convert i.MX ADSP boards to hardware model
           v2
1511e356a2 soc: nxp: Port i.MX ADSP family to hardware model v2
c91e25ab47 soc: mec: rename all mec1501x reference to mec15xx
1c231fd939 hwmv2: boards: Convert IMXRT boards
417cff1e60 hwmv2: soc: Port IMXRT family to HWMV2
28d4e41b1b hwmv2: clean up arm64 soc and board empty directory
2b520f83cb hwmv2: port NXP SoC LS1046A to V2
bf7899c645 hwmv2: port nxp_ls1046ardb board to V2
33f7b61866 samples/tests: Rename numaker boards
8f20ea6e93 boards: nuvoton: numaker_pfm: Split into 2 boards
7cf4ff43a1 drivers: pinctrl: imx: align with hwm v2
c68e1fea4e drivers: clock_control: ccm_rev2: align with hwm v2
           update
3b49014a0f hwmv2: move imx8mn EVK board to V2
14f344eeab hwmv2: move imx8mp EVK board to V2
40f3f8f22d hwmv2: move imx8mm EVK board to V2
10bf79ea51 hwmv2: move imx8m soc for a-core to V2
8727d5ca80 hwmv2: move imx93 EVK board to V2
c81ef01563 hwmv2: move imx93 soc to V2
5836c1b699 modules: mcux: introduce CONFIG_MCUX_CORE_SUFFIX
338f6f2bf1 doc: update board porting guide to match new hardware
           model
9639a1b5dc soc: silabs: drop useless defconfigs
981807444e soc: silabs: introduce SOC_GECKO_SDID
5d07e82485 soc: silabs: SOC_FAMILY_* replace SOC_GECKO_SERIES*
2fd081ac86 soc: silabs: align comments with soc tree
66d425f571 soc: silabs: split in families
5bd38f47a9 arch: arch: kconfig: Fix wrong placement of endmenu
00c6ef25be tests/samples: Rename overlay files for renamed boards
0c639b8378 boards: Fix bools and selections
c2ef907d1d drivers: flash: it8xxx2: Add missing Kconfigs
553de2ebc9 soc: ite: ec: it8xxx2: Fix SOC_SERIES being in wrong file
b8ec0080c2 boards: Documentation link fixes
eb7025e50f tests: Update board names for hwmv2
10ef3d4bd2 boards: silab: Add documentation index file
ba9fdaa1d6 boards: arm: efr32_radio: Convert to v2
86c8d4a0ca boards: arm: efm32pg_stk3402a: Convert to v2
575ac5cafb manifest: Update hal_silabs
87b2907304 boards: arm: efr32_thunderboard: Convert to v2
14b30055ab boards: arm: efr32mg_sltb004a: Convert to v2
0012bfc15d boards: arm: efr32xg24_dk2601b: Convert to v2
f526225ead boards: arm: efm32wg_stk3800: Convert to v2
19e7df29df boards: arm: efm32pg_stk3401a: Convert to v2
0bd7d963d6 boards: arm: efm32hg_slstk3400a: Convert to v2
795a90f9bf boards: arm: efm32gg_stk3701a: Convert to v2
43d5540be7 boards: arm: efm32gg_slwstk6121a: Convert to v2
065148d856 boards: arm: efm32gg_sltb009a: Convert to v2
1dc9a8aa17 soc: silabs_exx32: Port to HWMv2
763571e878 tests: Expand names
dae301b8a3 boards: xen: xenvm: Expand name
19e60eef36 boards: qemu: qemu_cortex_a53: Expand names
a0a7c30f28 soc: intel: intel_adsp: Fix issues
df9a4223fe scripts: ci: introduce soc name check in check_compliance
ed401abaff soc: emsdsp: align SoC name defined in soc.yml to Kconfig
           SOC setting
fc78e5eaa4 MAINTAINERS: update RISC-V arch area paths
4e586958ff boards: convert QEMU RISC-V 64 bit board to Zephyr HWMv2
f4c31a2b86 boards: convert QEMU RV32E board to Zephyr HWMv2
5b2ffc652b boards: convert QEMU RISC-V 32 bit board to Zephyr HWMv2
5db061a4c6 soc/riscv: convert the QEMU virt RISCV-32 SoC to HWMv2
6547845e9d boards: convert SparkFun RED-V Things Plus to Zephyr
           HWMv2
95a1f96399 boards: convert SiFive HiFive Unmatched to Zephyr HWMv2
e563eb0a62 soc/sifive/sifive_freedom: add SiFive Freedom FU740 SoC
8914bc58b6 boards: convert SiFive HiFive Unleashed to Zephyr HWMv2
7e8de1e781 soc/sifive/sifive_freedom: add SiFive Freedom U540 SoC
bfcc2ed18f boards: convert SiFive HiFive1 Rev. B to Zephyr HWMv2
330fc38f9f boards: convert SiFive HiFive1 to Zephyr HWMv2
b9e06f4c38 soc/sifive/sifive_freedom: add SiFive Freedom E310 SoC
4b90b30b9d scripts: west_commands: completion: Add hwmv2 complete to
           fish
0f6842e2fa scripts: west_commands: completion: Add hwmv2 complete to
           zsh
b2af1e1737 scripts: west: list_boards: Fix hwmv2 output
686a4b78b8 scripts: west_commands: completion: Add hwmv2 complete to
           bash
396b6bb856 soc: nxp: fix typo in SoC name
765299c627 soc: broadcom: align SoC names defined in soc.yml to
           Kconfig SOC setting
7efd46eb41 soc: arm: align SoC names defined in soc.yml to Kconfig
           SOC setting
505cbc5c42 soc: mec: align SoC names defined in soc.yml to Kconfig
           SOC setting
951a140701 soc: ti: define SOC name in Kconfig
a795d28810 snippets: Initial HWMv2 support
f9a957e6f6 boards: nordic: nrf9160dk: Fix missing nrf52840 config
df994e7ee8 soc: xilinx: zync7000: Remove xilinx from soc series name
8dfabd56ca soc: cypress: Add protection guard to file
447b951593 tests: kernel: tickless: Remove old board name
bad5dfa71f boards: nordic: nrf5340dk: Fix board names
ad2e863f39 soc: atmel: Use new family prefix
3f08e714b2 soc: intel_adsp: hwmv2: Align SOC_SERIES_INTEL_ACE name
           and value
6734597a76 soc: intel_adsp_cavs: hwmv2: Align SOC_SERIES name and
           value
2908af0bcc boards: nrf51dk/dongle: change SoC to nRF51822
d1ceb29fca soc: align CONFIG_SOC values to match soc.yml names
4768ccaf70 tests: drivers: gpio: gpio_api_1pin: exclude hifive1
ebdb0879ad boards: nxp: s32z2xxdc2: convert to hwmv2
ae82580d08 boards: nxp: mr_canhubk3: convert to hwmv2
c5f0defbae boards: nxp: ucans32k1sic: convert to hwmv2
1e46cabce6 soc: nxp: convert NXP S32 family to hwmv2
f2f85133f2 soc: stm32: Rename series path
86642f4e78 soc: stm32: Rename Kconfig SOC_SERIES symbols
c61e807896 soc: stm32: Cleanup Kconfig.defconfig files
ca46c8abc9 tests: Fix board names
fbfed5f48f maintainers: Update synopsys entries
8cd8b1cc47 boards: synopsys: Add documentation index
6f6cc57a04 boards: arc: hsdk4xd: Convert to v2
c4c14a54ca soc: snps_arc_hsdk4xd: Port to HWMv2
06c2054e5c boards: arc: iotdk: Convert to v2
ff0e0fce1b soc: snps_arc_iot: Port to HWMv2
334264c46a boards: arc: emsdp: Convert to v2
8b947a0e91 soc: snps_emsdp: Port to HWMv2
990417bbde tests: Update board names for hwmv2
e12719154a boards: arc: em_starterkit: Convert to v2
437a430fbe soc: snps_emsk: Port to HWMv2
f93387f968 boards: arc: hsdk: Convert to v2
1cf2498b13 soc: snps_arc_hsdk: Port to HWMv2
47abe81256 boards: arc: nsim: Convert to v2
1e33786dc4 soc: snps_nsim: Port to HWMv2
7f081914db boards: arc: qemu_arc: Convert to v2
bc97349dbd soc: snps_qemu: Port to HWMv2
a9902ff58e boards: Use zephyr_file for file links
126e1a4e72 boards: Fix invalid documentation links
899f0257c3 boards: stm32wb: Restore missing .defconfig files
790c10b1ee soc: x86/atom: imply mmu, do not select it
faee62088d boards: x86: remove qemu_x86_tiny_768
c34d186a57 x86: atom: remove soc.h with unused content
1be3a9e9d3 x86: remove legacy ia32, use atom instead
60e6b400f9 boards: qemu: move qemu_x86 -> x86
c4fbac27e8 boards: infineon: Add documentation index
b4dd29a9c4 maintainers: Update paths for hwmv2
380f5fdb2b boards: cypress: Add documentation index
9de981be05 boards: arm: xmc47_relax_kit: Convert to v2
6394e8a348 boards: arm: xmc45_relax_kit: Convert to v2
04dbf17e19 soc: xmc_4xxx: Port to HWMv2
c9731f1bce boards: arm: cy8cproto_063_ble: Convert to v2
53d41869d1 boards: arm: cy8cproto_062_4343w: Convert to v2
46c4f01427 boards: arm: cy8ckit_062s4: Convert to v2
d285e19cf2 boards: arm: cy8ckit_062_wifi_bt: Convert to v2
2bebd7298c boards: arm: cy8ckit_062_ble: Convert to v2
af243274c2 soc: psoc6 and psoc_6: Port to HWMv2
105a2bae84 cmake: modules: boards: Fix board deprecation for HWMv2
dca54e000a cmake: modules: boards: Enhance board aliases for HWMv2
fc314e8e3f cmake: modules: boards: Fix BOARD_ALIAS
9a7c2ce6d5 soc: gaisler: Move Kconfig file
1ac56d0501 soc: soc_legacy: mips: Remove out file
c054381a7a boards: adjust few boards/ paths
4d93b8d9fd boards: convert all microchip MEC boards to hwmv2
ab2fcb1245 soc: convert microchip_mec to hwmv2
ead4b57a7b soc: arm64: intel_socfpga: hwmv2: Rename SoCs
d4c143d306 MAINTAINERS: intel_socfpga: Adjust to HWMv2 move
70a66ac03a boards: arm64: intel_socfpga: Move boards to
           subdirectories
8a85c07799 boards: arm64: intel_socfpga_agilex5_socdk: move to HWMv2
8c253a99fc boards: arm64: intel_socfpga_agilex_socdk: move to HWMv2
ab883b8019 soc: arm64: intel_socfpga: Move and convert to HWMv2
7c8b7a153b soc: arm: intel_socfpga_std: Rename with HWMv2
8dc2b911f6 soc: board: intel_socfpga_std: Align names to 'Cyclone V'
402366117a soc: arm: intel_socfpga_std: Align board subdirectory
f0a8d12745 boards: arm: cyclonev_socdk: Move to HWMv2
2271f17a86 soc: arm: intel_socfpga_std: Move and convert to HWMv2
841c2a9d99 boards: riscv: beaglev_fire: Convert to v2
3b314531ab boards: riscv: mpfs_icicle: Convert to v2
d4ea2bf70b boards: riscv: m2gl025_miv: Convert to v2
5256e9fcc3 soc: microchip_miv: Port to HWMv2
18e5cf1d51 maintainers: Update path for hwmv2
eab8628f98 boards: arm: qemu_cortex_m3: Convert to v2
1532f2fee1 soc: ti_lm3s6965: Port to HWMv2
430ca6a475 maintainers: Update ambiq paths
a9b9b41b91 boards: ambiq: Add index
db0271ecbb boards: arm: apollo4p_blue_kxr_evb: Convert to v2
957e2b2061 boards: arm: apollo4p_evb: Convert to v2
5a90a44454 soc: ambiq: Port to HWMv2
a20c113fbd boards: nxp: convert ip_k66f to hwmv2
34e3852a54 boards: nxp: convert usb_kw24d512 to hwmv2
20ad604de6 boards: nxp: convert twr_kv58f220m to hwmv2
2e2a7b7656 boards: nxp: twr_ke18f: convert to hwmv2
f7dcc2eb5e boards: nxp: convert rddrone_fmuk66 to hwmv2
b58e90a2e9 boards: nxp: convert hexiwear to hwmv2
aae6e9e454 boards: nxp: frdm_kw41z: convert to hwmv2
1d3baac2d6 boards: nxp: convert frdm_kl25z to hwmv2
3b1d21483f boards: nxp: frdm_k82f: port to hwmv2
6046e6ded9 boards: nxp: port frdm_k64f to hwmv2
0a7bf9fd79 boards: nxp: port frdm_k22f to hwmv2
dce697c823 boards: nxp: add toctree placeholder
666a353409 soc: nxp: kinetis: convert kinetis SOC family to hardware
           model V2
89f0a6034b maintainers: Update paths for renesas boards/socs
004bd43c48 tests/samples/snippets: Update board names for hwmv2
a6d756923d boards: arm and arm64: rcar_h3ulcb: Convert to v2
3801216b8d boards: arm64: rcar_salvator_xs_m3: Convert to v2
b7cc30aaea boards: arm: rcar_h3_salvatorx_cr7: Convert to v2
866427ea29 boards: arm: arduino_uno_r4: Convert to v2
2689b3f0ee soc: ra: Port to HWMv2
e7ebc727c8 boards: arm: da1469x_dk_pro: Convert to v2
903265b2bb boards: arm: da14695_dk_usb: Convert to v2
529a78ed51 soc: smartbond: Port to HWMv2
97cf636ae0 boards: arm: rcar_spider_cr52: Convert to v2
6d0c53f3a1 soc: rcar: Port to HWMv2
44e0aa0668 soc: renesas: rzt2m: Move folder structure for more SoCs
85238fc205 boards: misc: Fixed STM32 based boards doc links
dffc08af56 boards: riscv: niosv_m: move and convert to HWMv2
545093abe4 boards: riscv: niosv_g: move and convert to HWMv2
ecfa192f1b soc: riscv: intel_niosv: move and convert to HWMv2
fd1e8cdc30 hwmv2: sof: intel_adsp: submanifest provisional link
8bf067e625 doc: boards: intel_adsp: Re-order pages
4833275ccd MAINTAINERS: intel_adsp: Adjust to HWMv2 move
b9a70e5ea2 soc: intel_adsp: tools: pylint compliance workaround
18c70cc4bf hwmv2: tests: boards: intel_adsp: Adjust board names
ca52baf9de hwmv2: boards: intel_adsp: Overhaul board configurations
d1b3bcce64 soc: boards: xtensa: intel_adsp_ace: Rename with HWMv2
f362a8ae2c doc: soc: boards: intel_adsp_cavs25: Rename with HWMv2
51dee5da92 tests: samples: boards: intel_adsp_cavs25: Rename with
           HWMv2
e66c35e0d0 boards: xtensa: intel_adsp_cavs25: Rename board with
           HWMv2
d1491a4810 soc: boards: xtensa: intel_adsp_cavs25: Rename with HWMv2
fa0fca79c4 scripts: west: runners: intel_adsp: Adjust path to HWMv2
acd18bfaf7 boards: xtensa: intel_adsp_ace20_lnl: move and convert to
           HWMv2
546c94b958 boards: xtensa: intel_adsp_ace15_mtpm: move and convert
           to HWMv2
8aab718c3e boards: xtensa: intel_adsp_cavs25_tgph: change to board
           variant
30f17424a4 boards: xtensa: intel_adsp_cavs25: move and convert to
           HWMv2
35a97cb524 soc: xtensa: intel_adsp: HWMv2 workaround for SOF config
fdc20fdff6 soc: xtensa: intel_adsp: move and convert to HWMv2
22dc2b6391 cmake: improved board handling for revisions
2f1e33a2e6 cmake: improve arch error message for invalid arch
           selection
c47c37d3db sample: basic: blinky_pwm: Exclude rpi_pico w variant
7a788b9a18 boards: raspberry_pi: rpi_pico: Use full name for w
           variant
7046b92d41 tests: atmel_sam: adc: Fix sam4e_xpro adc build
253ee9638c tests: atmel_sam0: Update platform name
ccb4c63324 samples: atmel_sam0: Update platform name
2d4acf9230 boards: arduino_nano_33_iot: Convert to HWMv2
a60d28969a boards: arduino_mkrzero: Convert to HWMv2
0409e51d3f boards: arduino_zero: Convert to HWMv2
1b2528df1b boards: wio_terminal: Convert to HWMv2
af1096e7ca boards: ev11l78a: Convert to HWMv2
0b1db9c53d boards: adafruit_trinket_m0: Convert to HWMv2
e9874671e2 boards: adafruit_itsybitsy_m4_express: Convert to HWMv2
ba6c014071 boards: adafruit_grand_central_m4_express: Convert to
           HWMv2
33ad4a51ca boards: adafruit_feather_m0_lora: Convert to HWMv2
9812f3d54e boards: adafruit_feather_m0_basic_proto: Convert to HWMv2
c76b1fbeca boards: serpente: Convert to HWMv2
649789e433 boards: seeeduino_xiao: Convert to HWMv2
6b3bdb7364 boards: same54_xpro: Convert to HWMv2
93dda5ee4b boards: samr34_xpro: Convert to HWMv2
e48e1f5d5b boards: samc21n_xpro: Convert to HWMv2
f11cf73df1 boards: saml21_xpro: Convert to HWMv2
ac73ed6dcd boards: samd20_xpro: Convert to HWMv2
0fdbe3552e boards: samd21_xpro: Convert to HWMv2
854cff3905 boards: samr21_xpro: Convert to HWMv2
a87ea5bc0a soc: atmel: sam0: Port to HWMv2
706e5d27cd boards: riscv: neorv32: Convert to v2
d1edcdd088 soc: neorv32: Port to HWMv2
0f7add89ca boards: native_sim/posix: Add 64bit versions as variants
b6edad8d68 soc: soc_legacy: remove the arm/st_stm32 folder
c58e0822a6 boards: Convert nucleo_f207zg to HWM v2
b987093a80 soc: v2: stm32: Migrate STM32F2 series
2096fd4652 samples: bluetooth: hci_uart: Fix wrongly converted board
           names
830f9c5a82 MAINTAINERS: Update Atmel entries
527cd9d8cd CODEOWNERS: Update Atmel entries
83af7d0c1c samples: atmel_sam: Update platform name
fd9b84d457 tests: atmel_sam: Update platform name
3c72fe863c boards: arduino_due: Convert to HWMv2
37dfacbf9e boards: RoboKit1: Convert to HWMv2
1108d7b0ed boards: sam_v71_xult: Convert to HWMv2
bed44a5c28 boards: sam_e70_xplained: Convert to HWMv2
40448c5a9f boards: sam4s_xplained: Convert to HWMv2
31273692c0 boards: sam4l_ek: Convert to HWMv2
35b5d33ef0 boards: sam4e_xpro: Convert to HWMv2
3b84b9910a soc: atmel: Port SAM family to HWMv2
da00d0e7b9 boards: Convert nucleo_wba55cg to HWM v2
fb2103f89e boards: Convert nucleo_wba52cg to HWM v2
1f9a533fbc soc: st: stm32: Migrate STM32WBA series
3f92f65b28 boards: fix documentation for alientek and blues boards
7646b74aaf boards: stm32l4: doc: add zephyr_file to defconfig path
fea54ddcd9 boards: Convert adi_eval_adin2111ebz to HWM v2
d47f1878b1 boards: Convert adi_eval_adin1110ebz to HWM v2
ae42be236b boards: Convert swan_r5 to HWM v2
83bd1a9ecc boards: Convert stm32l4r9i_disco to HWM v2
39c26f09ed boards: Convert stm32l496g_disco to HWM v2
29d03c970b boards: Convert stm32l476g_disco to HWM v2
74acec315c boards: Convert sensortile_box to HWM v2
fee6d8676e boards: Convert pandora_stm32l475 to HWM v2
008b5d9392 boards: Convert nucleo_l4r5zi to HWM v2
24e357d623 boards: Convert nucleo_l4a6zg to HWM v2
2c5f9dcce0 boards: Convert nucleo_l496zg to HWM v2
4da061646f boards: Convert nucleo_l476rg to HWM v2
15956a69b8 tests: drivers: flash: stm32: update platform name
80324f7707 boards: Convert nucleo_l452re_p to HWM v2
9893e0d111 boards: Convert nucleo_l452re to HWM v2
46f92b227b boards: Convert nucleo_l433rc_p to HWM v2
ed5d1bb4cd boards: Convert nucleo_l432kc to HWM v2
325f95ec20 boards: Convert nucleo_l412rb_p to HWM v2
d055676307 boards: Convert disco_l475_iot1 to HWM v2
c7a415d92c boards: Convert b_l4s5i_iot01a to HWM v2
d15144f582 soc: st: stm32: Migrate STM32L4 series
a63ff71bcb boards: nrf_bsim: Add new nrf5340 board definitions
b53c6f412c boards: nrf_bsim: Remove redundant option setting
83eb4fc069 MAINTAINERS: intel_ish: Adjust to HWMv2 move
715685b19f boards: x86: intel_ish: move and convert intel_ish boards
           to HWMv2
5b9ef94106 soc: x86: intel_ish: move and convert to HWMv2
12b297707a boards: Convert stm32wb5mmg to HWM v2
cdcea932bc boards: Convert stm32wb5mm_dk to HWM v2
0a3ae2b223 boards: Convert nucleo_wb55rg to HWM v2
20b4ce17d5 soc: st: stm32: Migrate STM32WB series
47c65400d6 soc: st: stm32: fix stm32l0 family
59ec56f9e6 boards: Convert stm32h573i_dk to HWM v2
dc5977dbba boards: Convert nucleo_h563zi to HWM v2
a6e4928543 soc: st: stm32: Migrate STM32H5 series
99f248e048 soc: stm32u5: Fix references after conversion to hw
           modelv2
15f16834e6 boards: Convert stm32u5a9j_dk to HWM v2
c1ee449ef1 boards: Convert sensortile_box_pro to HWM v2
db4deddf9d boards: Convert nucleo_u5a5zj_q to HWM v2
2fd3ed43d2 boards: Convert nucleo_u575zi_q to HWM v2
902fceb173 boards: Convert b_u585i_iot02a to HWM v2
d716ca1a10 soc: st: Migrate stm32u5 series to new hw model
b7abc89428 hwmv2: boards: x86: doc: Adjust common docs to new
           locations
69b334f54b MAINTAINERS: Change paths to native and nrf*bsim boards
614611a528 boards: nrf*_bsim: Convert to HW model v2
5821b9ec2e board: native_sim/posix: Convert to hwmv2
04cbad174e soc: native: Convert to HWMv2
24ca0febfc boards: nrf_bsim: Fix path to pinctrl_soc.h
9a32559a2d cmake: FindHostTools: Fix for hwmv2 for host based
           targets
c4b11e0251 boards: longan_nano: port to HWMv2
97edd05be3 boards: gd32vf103c_starter: port to HWMv2
9cf624c410 boards: gd32vf103v_eval: port to HWMv2
b40bf25e5e soc: gd_gd32: reorganize folders
71600d7e95 soc: gd_gd32: move pinctrl_soc.h content back to soc
           folder
2bd84a1bc5 soc: gd_gd32: port gd32vf103 series to HWMv2
9dc342143b boards: doc: fix a bunch of broken reference
10392d693d doc: boards: split out shields
b2def8ed3a boards: acrn: fix title
bf7d3efe78 boards: riscv: tlsr9518adk80d: Convert to v2
c579770e1d soc: telink_tlsr: Port to HWMv2
9131540109 soc: stm32h7: Couple of tests fixes following migration
2efcefc089 boards: Convert stm32h7b3i_dk to HWM v2
d9b295a85b boards: Convert stm32h750b_dk to HWM v2
a2f56bdcd5 boards: Convert stm32h747i_disco to HWM v2
00314155df boards: Convert stm32h735g_disco to HWM v2
b08819dff7 boards: Convert nucleo_h7a3zi_q to HWM v2
56456c16e5 boards: Convert nucleo_h753zi to HWM v2
91f9198dc4 boards: Convert nucleo_h745zi_q to HWM v2
96f1bafbf9 boards: Convert nucleo_h743zi to HWM v2
b290f25baa boards: Convert nucleo_h723zg to HWM v2
9fbe6bf191 boards: Convert fk7b0m1_vbt6 to HWM v2
44bcfe57c7 boards: Convert arduino_portenta_h7 to HWM v2
4c86af7eae boards: Convert arduino_opta_m4 to HWM v2
b4f852f738 boards: Convert arduino_giga_r1 to HWM v2
bac9789264 soc: st: Migrate stm32h7 series to new hw model
a954e1722d boards: stm32l0: Cleanup board _defconfig files after
           migration
7e8515b241 boards: Convert ronoth_lodev to HWM v2
25246c21ef boards: Convert nucleo_l073rz to HWM v2
09396eb2e6 boards: Convert nucleo_l053r8 to HWM v2
70c004fd83 boards: Convert nucleo_l031k6 to HWM v2
e3daa98e79 boards: Convert nucleo_l011k4 to HWM v2
a2de60c6da boards: Convert dragino_nbsn95 to HWM v2
e877ce9cec boards: Convert dragino_lsn50 to HWM v2
2b50218c23 boards: Convert b_l072z_lrwan1 to HWM v2
4a65f55916 soc: st: Migrate stm32l0 series to new hw model
cc6e6be01f boards: fix few leftover ITE board references
a837303268 soc: stm32: Protect Kconfig symbols by SOC_FAMILY_STM32
88e5959f17 hwm2: Fix unit_testing: it is also a legacy board by now
95e06e8663 cmake: Fix uses of old SOC path
d517d3cc24 soc: set linker script for ra4m1
68f9aeddab soc: ite: add SOC_SERIES_ITE_IT8XXX2 guards around ITE
           options
ccf4f48f01 boards: convert ite boards to hwmv2
4a6e286a3b soc: convert ite_ec to hwmv2
12e375f826 doc: handle arch / soc / board docs in new hardware model
b4db917de9 boards: Add documentation index files
d6e0d27efe samples: bluetooth: hci_uart: Fix wrong named files
bc16a7a727 tests: Update board names for hwmv2
2834883843 boards: riscv: rv32m1_vega: Convert to v2
9c68231ba9 soc: openisa_rv32m1: Port to HWMv2
986e9619fd soc: starfive_jh71xx: Port to HWMv2
e82932e787 boards: riscv: litex_vexriscv: Convert to v2
cb9339f88f soc: litex_vexriscv: Port to HWMv2
1cd4c34654 boards: riscv: opentitan_earlgrey: Convert to v2
92eadf06b8 soc: opentitan: Port to HWMv2
a8659e170b boards: riscv: titanium_ti60_f225: Convert to v2
359133d725 soc: efinix_sapphire: Port to HWMv2
6d466429ed soc: soc_legacy: riscv: litex_vexriscv: Add updated paths
a1ff441eb3 boards: riscv: adp_xc7k_ae350: Convert to v2
ef82a8255c soc: ae350: Port to HWMv2
282204758a samples: boards: stm32: ccm: fix include path
8ca9341195 samples: basic: threads: fix broken reference
8a947f446d boards: nrf52840dk: fix rst syntax
324cb41153 boards: nordic_nrf: fix broken references
963c74df1c boards: intel_(ish|adl|ehl|rpl), up_squared: fix include
           paths
8d518ce504 boards: legacy: drop empty folders
0fef0cef5b boards: mps2: fix table formatting
e52ccc244f boards: add HWMv2 board index
c7426eca5e boards: arm: add legacy tag
1eba9d8a8f boards: acrn: create vendor folder
8d92edc727 tests: kernel: Adjust qemu_x86_tiny_768 configuration
           HWMv2
75117d1b2d scripts: ensure posix path is used with --cmakeformat
0b0384b56a maintainers: update paths after HWMv2 changes
c1b77b223d boards: arm: pan1783: Convert to v2
91a077b2ab boards: posix: nrf_bsim: Update paths
413b6c2a40 cmake: modules: configuration_files: Add board identifier
           overlay file
4f572ba24f treewide: Update board names for hwmv2
cb348c7edf boards: arm: nrf54l15pdk_nrf54l15: Convert to v2
811ad90566 boards: arm: nrf54h20pdk_nrf54h20: Convert to v2
d44ef90cf8 soc: nordic_nrf: Migrate nRF54H/nRF54L to v2 and fix nrf
c860f205de boards: arm: nrf9151dk_nrf9151: Convert to v2
fba98a1763 soc: nordic_nrf: Migrate nRF9151 to v2
5c156a2d35 boards: arm: 96b_carbon_nrf51: Convert to v2
cfc47a3a4b boards: arm: nrf9161dk_nrf9161: Convert to v2
37129b4e44 boards: arm: nrf9131ek_nrf9131: Convert to v2
a923beba5d boards: arm: bl5340_dvk: Convert to v2
d242b2703b boards: arm: raytac_mdbt53v_db_40_nrf5340: Convert to v2
9c80d4e644 boards: arm: raytac_mdbt53_db_40: Convert to v2
28268c4938 boards: arm: nrf5340_audio_dk_nrf5340: Convert to v2
33ad2b5bc6 boards: arm: thingy53_nrf5340: Convert to v2
40daa94f2d boards: arm: nrf9160_innblue22: Convert to v2
2b0dbb9d51 boards: arm: nrf9160_innblue21: Convert to v2
ee6f7697ac boards: arm: sparkfun_thing_plus_nrf9160: Convert to v2
594e4bad6b boards: arm: circuitdojo_feather_nrf9160: Convert to v2
a5803ba099 boards: arm: actinius_icarus: Convert to v2
db8c275456 boards: arm: actinius_icarus_bee: Convert to v2
30177cf53d boards: arm: actinius_icarus_som: Convert to v2
486504cf24 boards: arm: actinius_icarus_som_dk: Convert to v2
dd0672a64c boards: arm: nrf9160dk_*: Convert to v2
c1565b3d14 boards: arm: xiao_ble: Convert to v2
6dd2723314 boards: arm: qemu_cortex_m0: Convert to v2
ee1ce24a42 boards: arm: bbc_microbit: Convert to v2
1952d559f2 boards: arm: rm1xx_dvk: Convert to v2
9e12c3d8bd boards: arm: nrf51dongle_nrf51422: Convert to v2
0ffbc1da33 boards: arm: nrf51_blenano: Convert to v2
be52dfb7b6 boards: arm: nrf51_vbluno51: Convert to v2
4c29d1827f boards: arm: nrf51_ble400: Convert to v2
5b4a9556fd boards: arm: raytac_mdbt53_db_40_nrf5340: Fix typo
69e5d87a15 boards: arm: contextualelectronics_abc: Convert to v2
5e4ace1bbe boards: arm: degu_evk: Convert to v2
2762460a64 boards: arm: pan1781_evb: Convert to v2
fdc3913e76 boards: arm: ubx_evkninab1_nrf52832: Convert to v2
9c9c3a09a1 boards: arm: holyiot_yj16019: Convert to v2
109edc296f boards: arm: blueclover_plt_demo_v2_nrf52832: Convert to
           v2
7bfcdbbe8f boards: arm: decawave_dwm1001_dev: Convert to v2
0fbb543983 boards: arm: acn52832: Convert to v2
073e0f8080 boards: arm: we_proteus2ev_nrf52832: Convert to v2
197a19f396 boards: arm: ebyte_e73_tbb_nrf52832: Convert to v2
1616fc8ae5 boards: arm: nrf52_vbluno52: Convert to v2
5622077738 boards: arm: nrf52_sparkfun: Convert to v2
a6289516e4 boards: arm: 96b_nitrogen: Convert to v2
439d836883 boards: arm: nrf52_blenano2: Convert to v2
16e65f09c4 boards: arm: arduino_nicla_sense_me: Convert to v2
862efd5a21 boards: arm: thingy52_nrf52832: Convert to v2
dede0f6cd3 boards: arm: nrf52_adafruit_feather: Convert to v2
91e864ea29 boards: arm: nrf52832_mdk: Convert to v2
47ec3e416b boards: arm: ruuvi_ruuvitag: Convert to v2
52f797a227 boards: arm: pinetime_devkit0: Convert to v2
433db339f9 boards: arm: ubx_evkannab1_nrf52832: Convert to v2
a646d3f2d5 boards: arm: ubx_bmd300eval_nrf52832: Convert to v2
d0d434bf86 cmake: print identifier instead of variant
c3f5ed8157 boards: arm: we_proteus3ev_nrf52840: Convert to v2
eecff8ee7a boards: arm: nrf52840_mdk_usb_dongle: Convert to v2
34507614f6 boards: arm: nrf52840_mdk: Convert to v2
f02b56cb96 boards: arm: nrf52840_blip: Convert to v2
600c55c92a boards: arm: nrf52840_papyr: Convert to v2
f294bfc5e4 boards: arm: reel_board: Convert to v2
882524d2a0 boards: arm: nrf21540dk_nrf52840: Convert to v2
4bce0e9b39 boards: arm: nrf52840dongle_nrf52840: Convert to v2
d0229c771f boards: arm: particle_argon: Convert to v2
23a0570e64 boards: arm: particle_boron: Convert to v2
b6d3e1764f boards: arm: particle_xenon: Convert to v2
499f3e7902 boards: arm: rak5010_nrf52840: Convert to v2
9ae6b1804d boards: arm: rak4631_nrf52840: Convert to v2
fe2c90da5c boards: arm: pinnacle_100_dvk: Convert to v2
3d4d46698c boards: arm: ubx_evkninab3_nrf52840: Convert to v2
b1afbf0158 boards: arm: ubx_bmd380eval_nrf52840: Convert to v2
9f9897c872 boards: arm: ubx_bmd345eval_nrf52840: Convert to v2
f7fb2030c7 boards: arm: ubx_bmd340eval_nrf52840: Convert to v2
7186432662 boards: arm: raytac_mdbt50q_db_40_nrf52840: Convert to v2
32c4bdc0c4 boards: arm: pan1780_evb: Convert to v2
7b64c638a8 boards: arm: pan1770_evb: Convert to v2
156ee8ad8a boards: arm: mg100: Convert to v2
3d33dadeb0 boards: arm: arduino_nano_33_ble: Convert to v2
4fee7371d2 boards: arm: adafruit_itsybitsy_nrf52840: Convert to v2
ad37a0c222 boards: arm: adafruit_feather_nrf52840: Convert to v2
cf85b7169f boards: arm: bt510: Convert to v2
44b67ac430 boards: arm: bt610: Convert to v2
7dbb65d371 boards: arm: ubx_evkninab4_nrf52833: Convert to v2
5e79cb957d boards: arm: raytac_mdbt50q_db_33_nrf52833: Convert to v2
12bd83a218 boards: arm: pan1782_evb: Convert to v2
1a135ec352 boards: arm: bbc_microbit_v2: Convert to v2
4dbe97e5ea boards: arm: nrf52833dk: Convert to v2
d632b90043 boards: arm: ubx_bmd360eval_nrf52811: Convert to v2
cc1a30f24b boards: arm: we_ophelia1ev_nrf52805: Convert to v2
df0df9000b boards: arm: ubx_bmd330eval_nrf52810: Convert to v2
d2c7972a9a boards: arm: nrf52dk: Convert to v2
202c2bf447 boards: arm: bl654_sensor_board: Convert to v2
c3e36f2042 boards: arm: bl654_usb: Convert to v2
b9dd58aea1 boards: arm: bl654_dvk: Convert to v2
0e1898b093 boards: arm: bl653_dvk: Convert to v2
286f4a7524 boards: arm: bl652_dvk: Convert to v2
d1709cdb37 boards: update nRF51dk board to board scheme v2.
8f040cff2c boards: Update nrf5340dk_nrf5340 to HWMv2 scheme
8c90fae8e0 boards: update nRF52840dk_nrf52840/nrf52811 board to
           board scheme v2.
c828dcc60e boards: common: openocd-nrf5: Add HWMv2 support
c79f1b0d94 kconfig: soc: adopt Nordic SoC series to support hw model
           v2 scheme
3584b30fc1 tests: Update board names for hwmv2
94024d940e boards: arm: arty_a7: Convert to v2
8053c3a8df boards: arm: scobc_module1: Convert to v2
d5473b76fe soc: designstart: Port to HWMv2
f5792b05e7 boards: arm: fvp_baser_aemv8r_aarch32: Convert to v2
ff202daa8e soc: fvp_aemv8r_aarch32: Port to HWMv2
e66cbc2945 boards: arm: v2m_musca_s1: Convert to v2
33b47b2edb boards: arm: v2m_musca_b1: Convert to v2
baeebd31d2 soc: musca: Port to HWMv2
73b257a3f9 boards: arm: v2m_beetle: Convert to v2
85de0888ec soc: beetle: Port to HWMv2
867960a891 manifest: Update modules
6ca677ed3a boards: arm: mps2: Convert to v2
bcf4ad19d4 twister: build_dir: convert / to _ to support hwmv2
0ac386683f soc: Kconfig.v2: Add SOC_PART_NUMBER
9242c3c78f soc: stm32: soc.yml: reorder series
248d17f160 boards: stm32: cleanup
0a67265e99 boards: stm32: fix for boards with revisions
f8d44317ee soc: stm32l5: Rename overlays for nucleo_l552ze_q ns
           target.
400343d17e soc: stm32: Set default on USE_DT_CODE_PARTITION
d783ef549a soc: stm32l5: Update stm32l5 non secure targets in
           various places
643aeac552 boards: Convert stm32l562e_dk to HWM v2
e601d64344 boards: Convert nucleo_l552ze_q to HWM v2
2f7a387b32 soc: st: Migrate stm32l5 series to new hw model
519752efcd boards: xenvm: doc: Remove reference to deleted file
06263dd717 boards: xenvm: Unset HEAP_MEM_POOL_SIZE in gicv3 variant
66b0df5526 boards: qemu_cortex_a53: Fix Kconfig warnings in SMP
           variant
fa07bd9419 boards: mps3: Fix non-secure variant
8f6f0726dd boards: Move xenvm under xen
7b155a7031 boards: Raspberry Pi vendor fix
804697afa5 boards: Move 96b_aerocore to 96boards
d2f001e320 boards: x86: acrn: move and convert to HWMv2
ec7f7b3c30 tests: kernel: qemu_x86: adjust to the HWMv2
89dfcddc7e boards: x86: qemu_x86_tiny@768: change to board variant
eb724eb6a7 boards: x86: qemu_x86: optimize default HWMv2
           configurations
6f1043cde6 boards: x86: qemu_x86: move and convert to HWMv2
cab924cbfb soc: x86: ia32: move and convert to HWMv2
237fdff918 soc: x86: lakemont: move and convert to HWMv2
03042b7704 boards: move 96b_carbon to 96boards folder
767b94414e boards: rename vendor seeed to seeed_studio
07fa3a3d79 boards: Convert olimex_lora_stm32wl_devkit to HWM v2
ba01d3beca boards: Convert nucleo_wl55jc to HWM v2
7ce84f4041 boards: Convert lora_e5_mini to HWM v2
b988bae576 boards: Convert lora_e5_dev_board to HWM v2
6fbf39c726 soc: v2: stm32: Migrate STM32WL series
4a41878442 soc: st: stm32g4: add missing include
1e79ba15f6 boards: Convert weact_stm32g431_core to HWM v2
ffdcb60185 boards: Convert nucleo_g474re to HWM v2
d6acb08d3e boards: Convert nucleo_g431rb to HWM v2
90e592ffd1 boards: Convert b_g474e_dpow1 to HWM v2
eb8a7e3441 soc: st: stm32: Migrate STM32G4 series
ada469f237 tests: Update board names for hwmv2
0342433187 boards: arm: npcx9m6f_evb: Convert to v2
c10248d964 boards: arm: npcx7m6fb_evb: Convert to v2
21ddc5e6a6 boards: arm: npcx4m8f_evb: Convert to v2
5500f3ef21 soc: npcx*: Port to HWMv2
e7baf09ede soc: m48x: Port to HWMv2
5bae4a6480 boards: arm: numaker_pfm_m467: Convert to v2
3b0bd70c8c soc: m46x: Port to HWMv2
d52eab9e83 boards: Convert stm32g081b_eval to HWM v2
6f2835cb11 boards: Convert stm32g071b_disco to HWM v2
ca36d331d2 boards: Convert stm32g0316_disco to HWM v2
662cc4e09b boards: Convert nucleo_g0b1re to HWM v2
dd9bc29769 boards: Convert nucleo_g071rb to HWM v2
353da23ffb boards: Convert nucleo_g070rb to HWM v2
acc932b424 boards: Convert nucleo_g031k8 to HWM v2
cea9b140fd boards: Convert google_twinkie_v2 to HWM v2
52e025943a soc: st: stm32: Migrate STM32G0 series
1c7347686a ci: update check_compliance to not create duplicate lines
           in Kconfig
9debd98799 hwmv2: boards: up_squared_pro_700: Add missed intel_adl
           changes
adab07c42f boards: Convert msp_exp432p401r_launchxl to HWM v2
642aacdcdf soc: ti_simplelink: Add missing SoC
48637066d3 boards: Fix file paths in documentation
e983bc2a23 samples/tests: Fix mps3 board name
61e0f32716 boards: Convert stm32f3_seco_d23 to HWM v2
a1688ff641 boards: Convert stm32f3_disco to HWM v2
35fb228599 boards: Convert stm32373c_eval to HWM v2
10e5d1122b boards: Convert nucleo_f334r8 to HWM v2
c319cb19f0 boards: Convert nucleo_f303re to HWM v2
11725ccac1 boards: Convert nucleo_f303k8 to HWM v2
400f7f6a4f boards: Convert nucleo_f302r8 to HWM v2
8d84861390 soc: v2: stm32: Migrate STM32F3 series
85b9eee7e8 boards: arm: kv260_r5: Convert to v2
dafbd638e4 boards: arm: mercury_xu: Convert to v2
3ecd12f415 boards: arm: qemu_cortex_r5: Convert to v2
5db2390e9d soc: xilinx_zyncmp: Port to HWMv2
9ba8195cdc boards: arm: qemu_cortex_a9: Convert to v2
8e94b85361 boards: arm: zybo: Convert to v2
c970127fc2 soc: xilinx_zynq7000: Port to HWMv2
394c75373c boards: arm: ast1030_evb: Convert to v2
f2a1cc8714 soc: ast10x0: Port to HWMv2
28f3f25945 boards: arm: cc3235sf_launchxl: Convert to v2
c3e480f740 boards: arm: cc3220sf_launchxl: Convert to v2
fd5847123f boards: arm: beagleconnect_freedom: Convert to v2
76ba9a0587 boards: arm: cc1352p1_launchxl: Convert to v2
719baa8850 boards: arm: cc1352r1_launchxl: Convert to v2
5060a61ae1 boards: arm: cc1352r_sensortag: Convert to v2
99584be1c5 boards: arm: cc26x2r1_launchxl: Convert to v2
2dc8933942 soc: ti_simplelink: Port to HWMv2
a5b004663b scripts/utils/board_v1_to_v2.py: couple of fixes
77c2c333e5 boards: move 96b_stm32_sensor_mez to 96boards
c14ff98650 boards: stm32f411e_disco: delete obsolete file
bcdc268ccf boards: Convert stm32mp157c_dk2 to HWM v2
0c8ba92e1f boards: Convert 96b_avenger96 to HWM v2
b54fe33077 soc: v2: stm32: Migrate STM32MP1 series
2ba3639b2a boards: Convert nucleo_c031c6 to HWM v2
dbc5ed79f5 soc: st: stm32: Migrate STM32C0 series
ce6d493aa3 boards: Convert stm32l1_disco to HWM v2
a28086a9ca boards: Convert nucleo_l152re to HWM v2
1b2a511d06 boards: Convert 96b_wistrio to HWM v2
ce281f09ab soc: v2: stm32: Migrate STM32L1 series
cdb5364fd7 boards: Convert stm32f769i_disco to HWM v2
768f173dcb boards: Convert stm32f7508_dk to HWM v2
21bbbbd9cb boards: Convert stm32f746g_disco to HWM v2
bab4265693 boards: Convert stm32f723e_disco to HWM v2
58f8fe82ba boards: Convert nucleo_f767zi to HWM v2
37e9084070 boards: Convert nucleo_f756zg to HWM v2
d467e7053a boards: Convert nucleo_f746zg to HWM v2
5f2808d7cc boards: Convert nucleo_f722ze to HWM v2
bbb73e7550 soc: st: Migrate stm32f7 series to new hw model
e9094afc4d soc: st: stm32: stm32f4: change SOC_STM32F405XG to
           SOC_STM32F405XX
a1712cdd53 boards: Convert stm32f4_disco to HWM v2
5be404b365 boards: Convert stm32f469i_disco to HWM v2
baaa697ab2 boards: Convert stm32f429i_disc1 to HWM v2
69ecab3c90 boards: Convert stm32f412g_disco to HWM v2
2a572e3fb0 boards: Convert stm32f411e_disco to HWM v2
ecfbf42757 boards: Convert stm32f401_mini to HWM v2
e0191d03bb boards: Convert steval_fcu001v1 to HWM v2
4454648976 boards: Convert segger_trb_stm32f407 to HWM v2
f0ad6ee6b8 boards: Convert olimex_stm32_p405 to HWM v2
1f5e228ec8 boards: Convert olimex_stm32_h407 to HWM v2
834bdb615e boards: Convert olimex_stm32_h405 to HWM v2
8f27fa8de2 boards: Convert olimex_stm32_e407 to HWM v2
f8633a9038 boards: Convert nucleo_f446ze to HWM v2
07e0bd2c07 boards: Convert nucleo_f446re to HWM v2
24d7f625dc boards: Convert nucleo_f429zi to HWM v2
157a8cde53 boards: Convert nucleo_f413zh to HWM v2
4ec99c31b0 boards: Convert nucleo_f412zg to HWM v2
a21546140a boards: Convert nucleo_f411re to HWM v2
43f01ab6de boards: Convert nucleo_f410rb to HWM v2
60c16bcb8b boards: Convert nucleo_f401re to HWM v2
2db228d730 boards: Convert mikroe_mini_m4_for_stm32 to HWM v2
73fc26225c boards: Convert mikroe_clicker_2 to HWM v2
6b62d90114 boards: Convert google_dragonclaw to HWM v2
fa845af309 boards: Convert blackpill_f411ce to HWM v2
5c8c3c3be0 boards: Convert blackpill_f401ce to HWM v2
3c02db1290 boards: Convert blackpill_f401cc to HWM v2
7eeb723cb7 boards: Convert black_f407zg_pro to HWM v2
4f9461d068 boards: Convert black_f407ve to HWM v2
a821de8532 boards: Convert az3166_iotdevkit to HWM v2
ba580c7236 boards: Convert adi_sdp_k1 to HWM v2
eb272ddf19 boards: Convert adafruit_feather_stm32f405 to HWM v2
58ed121c3a boards: Convert 96b_stm32_sensor_mez to HWM v2
b0d70959d3 boards: Convert 96b_neonkey to HWM v2
b1088baadc boards: Convert 96b_carbon to HWM v2
18d867b0a9 boards: Convert 96b_argonkey to HWM v2
ee6ede7119 boards: Convert 96b_aerocore2 to HWM v2
b48e70ead9 soc: v2: stm32: Migrate STM32F4 series
14d2b955da cmake: convert path to CMake style before writing Kconfig
           files
9c4ac6a202 boards: posix: bsim: Update paths
14b57f56d7 tests: drivers: gpio: gpio_ite_it8xxx2_v2: Temp fix
f3b173be18 scripts: board_v1_to_v2: Update following move to
           boards_legacy
05b50f6691 cmake: CMake soc dir variable improvements for HWMv2
a188e01a12 hwmv2: move all ported boards and socs to their final
           location
22c53e97b5 hwmv2: move all non-ported legacy boards and socs to
           legacy folders
53f3b181b0 soc: ti_k3: Port to HWMv2
9f19a2075a soc: rk3568: Port to HWMv2
b8928b1628 soc: rk3399: Port to HWMv2
cda3a74868 boards: arm64: qemu_kvm_arm64: Convert to v2
70d704bd20 soc: x86: atom: move and convert to HWMv2
4789e1068e boards: x86: intel_rpl: move and convert raptor_lake
           boards to HWMv2
384307e3dc soc: x86: raptor_lake: move and convert to HWMv2
ed025df674 boards: x86: intel_ehl: move and convert elkhart_lake
           boards to HWMv2
994b6e1731 soc: x86: elkhart_lake: move and convert to HWMv2
73b30a04cf boards: x86: up_squared_pro_7000: move and convert to
           HWMv2
83b133c207 boards: x86: intel_adl: move and convert alder_lake
           boards to HWMv2
847a12f1e4 soc: alder_lake: move and convert to HWMv2
67f4c8d2a1 samples: up_squared: adjust gpio_counter to HWMv2
5326b5bfc0 boards: x86: up_squared: move and convert to HWMv2
cfd5e691b4 soc: apollo_lake: move and convert to HWMv2
ac9c235741 boards: xtensa: qemu_xtensa: Convert to v2
f198c3a761 ci: update to osource for soc/Kconfig.defconfig files
e438e6cad4 ci: add SOC_SERIES_ as false positive in
           check_compliance.py
95e34da7c1 soc: v2: Convert st_stm32 to st/stm32
313717df76 soc: mps3: Fix missing family
392c3969ed boards: arm: am62x_m4: Convert to v2
8f245d764d tests: Update board names for hwmv2
8f71bb7b4f boards: arm64: khadas_edgev: Convert to v2
e27d23aad0 soc: rk3399: Port to HWMv2
80823b860e boards: arm64: roc_rk3568_pc: Convert to v2
72e4483dec soc: rk3568: Port to HWMv2
bed94669e3 boards: arm64: phycore_am62x_a53: Convert to v2
c01af5a7b8 soc: ti_k3: Port to HWMv2
1e563b4ca3 boards: arm64: xenvm: Convert to v2
76e484adae soc: xenvm: Port to HWMv2
34412f7fe2 boards: arm64: rpi_4b: Convert to v2
9be50e2ca9 soc: bcm2711: Port to HWMv2
bbbed12c2f boards: arm64: qemu_kvm_arm64: Convert to v2
4f5ec7ff8f soc: qemu_virt_arm64: Port to HWMv2
d8d1b9f200 boards: arm64: qemu_cortex_a53: Convert to v2
30bd34b31e soc: qemu_cortex_a53: Port to HWMv2
c20d0dcbb6 boards: arm64: fvp_baser_aemv8r: Convert to v2
02ed6af463 boards: arm64: fvp_base_revc_2xaemv8a: Convert to v2
1b175003a4 soc: fvp_aemv8*: Port to HWMv2
de231b911d boards: v2: Clean up obsolete comments
aa9597f6d9 boards: Convert waveshare_open103z to HWM v2
9644828c81 boards: Convert stm32vl_disco to HWM v2
86ab2bd430 boards: Convert stm32_min_dev to HWM v2
d88d3ddcc4 boards: Convert stm32f103_mini to HWM v2
0ccc0204e1 boards: Convert stm3210c_eval to HWM v2
dd9972d782 boards: Convert olimex_stm32_h103 to HWM v2
a2c2e1406d boards: Convert olimexino_stm32 to HWM v2
2d9c62e118 boards: Convert nucleo_f103rb to HWM v2
e8ba99dc59 soc: v2: stm32: Migrate STM32F1 series
9a93916604 tests: Update board names for hwmv2
9c4d94844d boards: arm: bcm958401m2: Convert to v2
feaf4ffba1 boards: arm: bcm958402m2: Convert to v2
87f0827121 soc: bcm_vk: Port to HWMv2
4526be24a5 boards: arm: quick_feather: Convert to v2
cd921d2b97 boards: arm: qomu: Convert to v2
b3c04051fc soc: quicklogic_eos_s3: Port to HWMv2
a73a9e7533 boards: v2: Clean up obsolete comments
8d87bcc167 boards: Convert stm32f0_disco to HWM v2
1933585785 boards: Convert stm32f072_eval to HWM v2
6f9fe5429d boards: Convert stm32f072b_disco to HWM v2
9dc78e4025 boards: Convert stm32f030_demo to HWM v2
35113e8923 boards: Convert nucleo_f091rc to HWM v2
b276aee9a4 boards: Convert nucleo_f070rb to HWM v2
795f8d611b boards: Convert nucleo_f042k6 to HWM v2
2d82646443 boards: Convert nucleo_f031k6 to HWM v2
959786f12d boards: Convert nucleo_f030r8 to HWM v2
81670db2e9 boards: Convert legend to HWM v2
8980430aad boards: Convert google_kukui to HWM v2
ac020f66e0 dts: stm32f0: fix few warnings
5140e4551a boards: v2: doc: Add vendors
77d640e0c9 soc: v2: stm32: Migrate STM32F0 series
0131e1c159 soc: v2: Add st_stm32 structure and common folder
36b63787a7 boards: v2: Add documentation index for converted boards
ae02fc5047 boards: sparc: qemu_leon3: Convert to v2
f38f7bb223 boards: sparc: gr716a: Convert to v2
d3cca3580e soc: gr716a: Port to HWMv2
6a8a0c1647 boards: sparc: generic_leon3: Convert to v2
faf22185ce soc: leon3: Port to HWMv2
e94762ecdc tests: Update board names for hwmv2
9afcc27e05 boards: xtensa: qemu_xtensa: Convert to v2
3e4a17018f soc: dc233c: Port to HWMv2
9188fdcd78 boards: xtensa: xt-sim: Convert to v2
fcaa41cb5d soc: xtensa_sample_controller: Port to HWMv2
dbc413f7f7 scripts: board_v1_to_v2: Fix CONFIG_SOC_SERIES_ exclusion
6be3d4bc80 kconfig: remove Kconfig BOARD_RPI_PICO_W safe guard.
f4442fa698 boards: v2: Add documentation index for converted boards
ec5fbd67f7 boards: nios2: qemu_nios2: Convert to v2
d3ef220460 soc: nios2-qemu: Port to HWMv2
a223f284b5 boards: nios2: altera_max10: Convert to v2
c381edcb73 soc: nios2f-zephyr: Port to HWMv2
97401c7d2a boards: mips: qemu_malta: Convert to v2
e7a3243a24 soc: qemu_malta: Port to HWMv2
bec82c690d boards: v2: Add documentation index for converted boards
94f6f9b636 boards: arm: w5500_evb_pico: Convert to v2
209235ab6e boards: arm: sparkfun_pro_micro_rp2040: Convert to v2
e5b1885907 boards: arm: adafruit_qt_py_rp2040: Convert to v2
4c750818f9 boards: arm: adafruit_kb2040: Convert to v2
8d3896caa4 boards: arm: rpi_pico: Convert to v2
42cff42c42 soc: rpi_pico: Port to HWMv2
c2df4ca9cb scripts: improve yaml schema and board.yml validation for
           revisions
3970f90f71 cmake: clear BOARD_CACHE when invalid board identifier is
           given
3a70ee9ccd cmake: improve board revision handling
3cda715fae scripts: board_v1_to_v2: Don't add select
           CONFIG_SOC_SERIES_FOO
dc56a543f3 scripts: board_v1_to_v2: Add License + copyright
87147f88c4 cmake: prefer cache BOARD_IDENTIFIER over extracting from
           BOARD
65f5dc5b8c cmake: fail when board identifier is applied in legacy hw
           model
7db2b6efd8 cmake: cache BOARD_IDENTIFIER to preserve it between
           CMake invocations
85dddac5a2 scripts: using extend in list_boards for variant list
6ae5c4e7fd scripts: utils: add board v1->v2 conversion utility
ef834a12d0 maintainers: update Renesas RZT2M path
3ab7830625 boards: renesas: add documentation entry
a0c2ca0491 boards: arm: add documentation entry
27ff3654b7 boards: gigadevice: add documentation entry
6e02f43c0a maintainers: update GD32 paths
1bfcf1d974 boards: gd32l233r_eval: convert to HWMv2
6e621ee43f boards: gd32f470i_eval: convert to HWMv2
219b149768 boards: gd32f450z_eval: convert to HWMv2
91c52b0d39 boards: gd32f450v_start: convert to HWMv2
f0e0a973f6 boards: gd32f407v_start: convert to HWMv2
6f592b64c9 boards: gd32f403z_eval: convert to HWMv2
4bcb4b2ac8 boards: gd32f350r_eval: convert to HWMv2
fdc7ed6eb0 boards: gd32e507z_eval: convert to HWMv2
770376250d boards: gd32e507v_start: convert to HWMv2
a6d8b92e86 boards: gd32e103v_eval: convert to HWMv2
a5f8e5daa1 boards: gd32a503v_eval: convert to HWMv2
5ee799cc5f boards: gd32f450i_eval: convert to HWMv2
8aa8ce4ac8 soc: gigadevice: port to HWMv2
4e203c14c7 cmake: enhanced board entry file handling
312265ee04 scripts: make SoC field mandatory in board.yml
c12ae3bcbc boards: update Renesas rzt2m board.yml to contain SoC
           information
c5321c1dbe cmake: make SoC optional for boards containing a single
           SoC
bcc06c60ae scripts: support SoC list output for boards
db9e46010c twister: update testcase.yaml and sample.yaml to
           mps3/an547 identifier
a988adee7d boards: update arm mps3 an547 board to HWMv2 scheme
7dc2c9db0c soc: use HWMv2 for arm mps3 SoC
c506675b7c boards: update Renesas Starter Kit+ for RZ/T2M board to
           HWMv2 scheme
3abb792073 soc: use HWMv2 for renesas_rzt2m SoC
4f52bc646e cmake: support hw model v2 in arch/Kconfig tree
a712b5005b scripts: extend kconfig compliance to verify board / SoC
           scheme v2
baa55141a1 twister: update twister testplan.py to handle HWMv2
           boards
1f026f70eb boards: extend list_boards.py and update boards CMake
           module
bd854a3af8 cmake: introduce arch and soc cmake modules for hw model
           v2
c9edefa8fd arch: add existing archs to archs.yml for HWMv2 support
61bbfb5ba2 scripts: introduce list_hardware.py for listing of
           architectures and SoCs
a4d1980c35 build: board/ soc: introduce hw model v2 scheme

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
Signed-off-by: David Leach <david.leach@nxp.com>
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This commit is contained in:
Torsten Rasmussen 2022-09-14 22:23:15 +02:00 • committed by Anas Nashif
commit 8dc3f85622
13315 changed files with 159282 additions and 157416 deletions
Download patch file Download diff file Expand all files Collapse all files

4
soc/microchip/mec/CMakeLists.txt Normal file
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# SPDX-License-Identifier: Apache-2.0
add_subdirectory(${SOC_SERIES})
add_subdirectory(common)

226
soc/microchip/mec/Kconfig Normal file
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# Microchip MEC MCU line
# Copyright (c) 2018, Intel Corporation
# Copyright (c) 2022, Microchip Technology Inc.
# SPDX-License-Identifier: Apache-2.0
if SOC_FAMILY_MICROCHIP_MEC
menuconfig MCHP_MEC_UNSIGNED_HEADER
bool "Create an unsigned output binary with MCHP MEC binary header"
help
On Microchip MEC series chip, the ROM code loads firmware image from flash
to RAM using a TAG to locate a Header which specifies the location and
size of the firmware image. Enable this to invoke the mec_spi_gen tool
which generates an SPI image with TAG, Header, and firmware binary. This
tool does not produce a signed image which can be authenticated by the
Boot-ROM. Use the full Microchip SPI image generator program for
authentication and all other Boot-ROM loader features. Refer to the MCHP
EVB boards for an example.
if MCHP_MEC_UNSIGNED_HEADER
config MCHP_MEC_HEADER_CHIP
string
default "mec15xx" if SOC_SERIES_MEC15XX
default "mec172x" if SOC_SERIES_MEC172X
choice MCHP_MEC_HEADER_SPI_FREQ_MHZ_CHOICE
prompt "Clock rate to use for SPI flash"
default MCHP_MEC_HEADER_SPI_FREQ_MHZ_12
help
This selects the SPI clock frequency that will be used for loading
firmware binary from flash to RAM.
config MCHP_MEC_HEADER_SPI_FREQ_MHZ_12
bool "SPI flash clock rate of 12 MHz"
config MCHP_MEC_HEADER_SPI_FREQ_MHZ_16
bool "SPI flash clock rate of 16 MHz"
config MCHP_MEC_HEADER_SPI_FREQ_MHZ_24
bool "SPI flash clock rate of 24 MHz"
config MCHP_MEC_HEADER_SPI_FREQ_MHZ_48
bool "SPI flash clock rate of 48 MHz"
endchoice
config MCHP_MEC_HEADER_SPI_FREQ_MHZ
int
default 12 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_12
default 25 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_16
default 24 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_24
default 48 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_48
choice MCHP_MEC_HEADER_SPI_READ_MODE_CHOICE
prompt "Reading mode used by the SPI flash"
default MCHP_MEC_HEADER_SPI_READ_MODE_FAST
help
This sets the reading mode that can be used by the SPI flash.
Reading modes supported are normal, fast, dual, and quad.
config MCHP_MEC_HEADER_SPI_READ_MODE_NORMAL
bool "SPI flash operates full-duplex with frequency (< 25 MHz)"
config MCHP_MEC_HEADER_SPI_READ_MODE_FAST
bool "SPI flash operates full-duplex with fast reading mode"
config MCHP_MEC_HEADER_SPI_READ_MODE_DUAL
bool "SPI flash operates with dual data reading mode"
config MCHP_MEC_HEADER_SPI_READ_MODE_QUAD
bool "SPI flash operates with quad data reading mode"
endchoice
config MCHP_MEC_HEADER_SPI_READ_MODE
string
default "slow" if MCHP_MEC_HEADER_SPI_READ_MODE_NORMAL
default "fast" if MCHP_MEC_HEADER_SPI_READ_MODE_FAST
default "dual" if MCHP_MEC_HEADER_SPI_READ_MODE_DUAL
default "quad" if MCHP_MEC_HEADER_SPI_READ_MODE_QUAD
choice MCHP_MEC_HEADER_FLASH_SIZE_CHOICE
prompt "Flash size"
default MCHP_MEC_HEADER_FLASH_SIZE_16M
help
This sets the SPI flash size.
config MCHP_MEC_HEADER_FLASH_SIZE_256K
bool "SPI flash size 256K Bytes"
help
The SPI flash size is 256K Bytes.
config MCHP_MEC_HEADER_FLASH_SIZE_512K
bool "SPI flash size 512K Bytes"
help
The SPI flash size is 512K Bytes.
config MCHP_MEC_HEADER_FLASH_SIZE_1M
bool "SPI flash size 1M Bytes"
help
The SPI flash size is 1M Bytes.
config MCHP_MEC_HEADER_FLASH_SIZE_2M
bool "SPI flash size 2M Bytes"
help
The SPI flash size is 2M Bytes.
config MCHP_MEC_HEADER_FLASH_SIZE_4M
bool "SPI flash size 4M Bytes"
help
The SPI flash size is 4M Bytes.
config MCHP_MEC_HEADER_FLASH_SIZE_8M
bool "SPI flash size 8M Bytes"
help
The SPI flash size is 8M Bytes.
config MCHP_MEC_HEADER_FLASH_SIZE_16M
bool "SPI flash size 16M Bytes"
help
The SPI flash size is 16M Bytes.
endchoice
config MCHP_MEC_HEADER_FLASH_SIZE
int
default 256 if MCHP_MEC_HEADER_FLASH_SIZE_256K
default 512 if MCHP_MEC_HEADER_FLASH_SIZE_512K
default 1024 if MCHP_MEC_HEADER_FLASH_SIZE_1M
default 2048 if MCHP_MEC_HEADER_FLASH_SIZE_2M
default 4096 if MCHP_MEC_HEADER_FLASH_SIZE_4M
default 8192 if MCHP_MEC_HEADER_FLASH_SIZE_8M
default 16384 if MCHP_MEC_HEADER_FLASH_SIZE_16M
choice MCHP_MEC_HEADER_SPI_DRVSTR_CHOICE
prompt "Flash drive strength"
default MCHP_MEC_HEADER_SPI_DRVSTR_1X
help
This sets the SPI flash size.
config MCHP_MEC_HEADER_SPI_DRVSTR_1X
bool "SPI flash drive strength multiplier 1"
help
The SPI flash size is 256K Bytes.
config MCHP_MEC_HEADER_SPI_DRVSTR_2X
bool "SPI flash drive strength multiplier 2"
help
The SPI flash size is 256K Bytes.
config MCHP_MEC_HEADER_SPI_DRVSTR_4X
bool "SPI flash drive strength multiplier 4"
help
The SPI flash size is 512K Bytes.
config MCHP_MEC_HEADER_SPI_DRVSTR_6X
bool "SPI flash drive strength multiplier 6"
help
The SPI flash size is 1M Bytes.
endchoice
config MCHP_MEC_HEADER_SPI_DRVSTR
string
default "1x" if MCHP_MEC_HEADER_SPI_DRVSTR_1X
default "2x" if MCHP_MEC_HEADER_SPI_DRVSTR_2X
default "4x" if MCHP_MEC_HEADER_SPI_DRVSTR_4X
default "6x" if MCHP_MEC_HEADER_SPI_DRVSTR_6X
choice MCHP_MEC_HEADER_SPI_SLEW_RATE_CHOICE
prompt "Slew rate of SPI pins"
default MCHP_MEC_HEADER_SPI_SLEW_RATE_SLOW
help
This sets the slew rate of the SPI pins. Default is slow
slew rate which is 1/2 the AHB clock rate. Fast slew is the
AHB clock rate.
config MCHP_MEC_HEADER_SPI_SLEW_RATE_SLOW
bool "SPI pins slew rate is 1/2 AHB frequency"
config MCHP_MEC_HEADER_SPI_SLEW_RATE_FAST
bool "SPI pins slew rate is 1x AHB frequency"
endchoice
config MCHP_MEC_HEADER_SPI_SLEW_RATE
string
default "slow" if MCHP_MEC_HEADER_SPI_SLEW_RATE_SLOW
default "fast" if MCHP_MEC_HEADER_SPI_SLEW_RATE_FAST
config MCHP_MEC_HEADER_FLASH_SPI_MODE
int "Flash SPI Mode"
range 0 7
default 0
help
This three bit value corresponds to the QMSPI controllers clock idle and
input/output data phases. Bits[0:2] are CPOL:CPHA_MOSI:CPHA_MISO. Refer
to the data sheet. Default value is 0 corresponding to SPI Mode 0
signalling.
Setting this field to 0 selects mode 0, CPOL=0, CPHA_MOSI=0, CPHA_MISO=0
Setting this filed to 7 selects mode 3, CPOL=1, CPHA_MOSI=1, CPHA_MISO=1
config MCHP_HEADER_VERBOSE_OUTPUT
bool "Debug console output"
default n
help
Enable print output from SPI generator script for debug
endif # MCHP_MEC_UNSIGNED_HEADER
config SOC_MEC_PROC_CLK_DIV
int "PROC_CLK_DIV"
default 1
range 1 48
help
This divisor defines a ratio between processor clock (HCLK)
and main 96 MHz clock (MCK):
HCLK = MCK / PROC_CLK_DIV
Allowed divider values: 1, 3, 4, 16, and 48.
# Select SoC Part No. and configuration options
rsource "*/Kconfig"
endif # SOC_FAMILY_MICROCHIP_MEC

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# Copyright (c) 2024, Microchip Technology Inc.
# SPDX-License-Identifier: Apache-2.0
if SOC_FAMILY_MICROCHIP_MEC
rsource "*/Kconfig.defconfig.series"
endif # SOC_FAMILY_MICROCHIP_MEC

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# Microchip MEC172x, MEC1501 MCU line
# Copyright (c) 2018 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_FAMILY_MICROCHIP_MEC
bool
config SOC_FAMILY
default "microchip_mec" if SOC_FAMILY_MICROCHIP_MEC
rsource "*/Kconfig.soc"

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# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(.)
zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_MEC172X
soc_i2c.c
)
if (DEFINED CONFIG_MCHP_HEADER_VERBOSE_OUTPUT)
set(MCHP_HEADER_VERBOSE_OPTION "-v")
endif()
if (DEFINED CONFIG_MCHP_MEC_UNSIGNED_HEADER)
set(MCHP_MEC_BIN_NAME ${CONFIG_KERNEL_BIN_NAME}.mchp.bin)
set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/soc/microchip/mec/common/spigen/mec_spi_gen.py
-i ${KERNEL_BIN_NAME}
-o ${MCHP_MEC_BIN_NAME}
-c ${CONFIG_MCHP_MEC_HEADER_CHIP}
-s ${CONFIG_MCHP_MEC_HEADER_FLASH_SIZE}
-f ${CONFIG_MCHP_MEC_HEADER_SPI_FREQ_MHZ}
-r ${CONFIG_MCHP_MEC_HEADER_SPI_READ_MODE}
-m ${CONFIG_MCHP_MEC_HEADER_FLASH_SPI_MODE}
--drvstr ${CONFIG_MCHP_MEC_HEADER_SPI_DRVSTR}
--slewrate ${CONFIG_MCHP_MEC_HEADER_SPI_SLEW_RATE}
${MCHP_HEADER_VERBOSE_OPTION}
)
endif()

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/*
* Copyright (c) 2020 Linaro Ltd.
* Copyright (c) 2021 Nordic Semiconductor ASA
* Copyright (c) 2021 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* Microchip XEC SoC specific helpers for pinctrl driver
*/
#ifndef ZEPHYR_SOC_ARM_MICROCHIP_XEC_COMMON_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_MICROCHIP_XEC_COMMON_PINCTRL_SOC_H_
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
#include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>
#ifdef __cplusplus
extern "C" {
#endif
/** @cond INTERNAL_HIDDEN */
/* Type for MCHP XEC pin. */
typedef uint32_t pinctrl_soc_pin_t;
/* initialize pinmux member fields of pinctrl_pin_t */
#define Z_PINCTRL_MCHP_XEC_PINMUX_INIT(node_id) (uint32_t)(DT_PROP(node_id, pinmux))
#define Z_PINCTRL_STATE_PINCFG_INIT(node_id) \
((DT_PROP(node_id, bias_disable) << MCHP_XEC_NO_PUD_POS) \
| (DT_PROP(node_id, bias_pull_down) << MCHP_XEC_PD_POS) \
| (DT_PROP(node_id, bias_pull_up) << MCHP_XEC_PU_POS) \
| (DT_PROP(node_id, drive_push_pull) << MCHP_XEC_PUSH_PULL_POS) \
| (DT_PROP(node_id, drive_open_drain) << MCHP_XEC_OPEN_DRAIN_POS) \
| (DT_PROP(node_id, output_disable) << MCHP_XEC_OUT_DIS_POS) \
| (DT_PROP(node_id, output_enable) << MCHP_XEC_OUT_EN_POS) \
| (DT_PROP(node_id, output_high) << MCHP_XEC_OUT_HI_POS) \
| (DT_PROP(node_id, output_low) << MCHP_XEC_OUT_LO_POS) \
| (DT_PROP(node_id, low_power_enable) << MCHP_XEC_PIN_LOW_POWER_POS) \
| (DT_PROP(node_id, microchip_output_func_invert) << MCHP_XEC_FUNC_INV_POS) \
| (DT_ENUM_IDX(node_id, slew_rate) << MCHP_XEC_SLEW_RATE_POS) \
| (DT_ENUM_IDX(node_id, drive_strength) << MCHP_XEC_DRV_STR_POS))
/* initialize pin structure members */
#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx) \
(Z_PINCTRL_MCHP_XEC_PINMUX_INIT(DT_PROP_BY_IDX(node_id, state_prop, idx)) \
| Z_PINCTRL_STATE_PINCFG_INIT(DT_PROP_BY_IDX(node_id, state_prop, idx))),
/* Use DT FOREACH macro to initialize each used pin */
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
{DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT)}
/** @endcond */
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_SOC_ARM_MICROCHIP_XEC_COMMON_PINCTRL_SOC_H_ */

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MEC_ACPI_EC_H
#define _MEC_ACPI_EC_H
#include <stdint.h>
#include <stddef.h>
#define MCHP_ACPI_EC_SPACING 0x0400u
#define MCHP_ACPI_EC_SPACING_PWROF2 10
/* EC_STS and OS_CMD_STS(read) bit definitions */
#define MCHP_ACPI_EC_STS_OBF_POS 0
#define MCHP_ACPI_EC_STS_OBF BIT(MCHP_ACPI_EC_STS_OBF_POS)
#define MCHP_ACPI_EC_STS_IBF_POS 1
#define MCHP_ACPI_EC_STS_IBF BIT(MCHP_ACPI_EC_STS_IBF_POS)
#define MCHP_ACPI_EC_STS_UD1A_POS 2
#define MCHP_ACPI_EC_STS_UD1A BIT(MCHP_ACPI_EC_STS_UD1A_POS)
#define MCHP_ACPI_EC_STS_CMD_POS 3
#define MCHP_ACPI_EC_STS_CMD BIT(MCHP_ACPI_EC_STS_CMD_POS)
#define MCHP_ACPI_EC_STS_BURST_POS 4
#define MCHP_ACPI_EC_STS_BURST BIT(MCHP_ACPI_EC_STS_BURST_POS)
#define MCHP_ACPI_EC_STS_SCI_POS 5
#define MCHP_ACPI_EC_STS_SCI BIT(MCHP_ACPI_EC_STS_SCI_POS)
#define MCHP_ACPI_EC_STS_SMI_POS 6
#define MCHP_ACPI_EC_STS_SMI BIT(MCHP_ACPI_EC_STS_SMI_POS)
#define MCHP_ACPI_EC_STS_UD0A_POS 7
#define MCHP_ACPI_EC_STS_UD0A BIT(MCHP_ACPI_EC_STS_UD0A_POS)
/* EC_BYTE_CTRL and OS_BYTE_CTRL */
#define MCHP_ACPI_EC_BYTE_CTRL_4B_POS 0
#define MCHP_ACPI_EC_BYTE_CTRL_4B_EN BIT(MCHP_ACPI_EC_BYTE_CTRL_4B_POS)
/* ACPI_PM1 peripheral */
/* ACPI_PM1 RT/EC Status 1 */
#define MCHP_ACPI_PM1_RT_STS1_REG_OFS 0
#define MCHP_ACPI_PM1_EC_STS1_REG_OFS 0x0100u
#define MCHP_ACPI_PM1_STS1_REG_MASK 0x0000u
/* ACPI_PM1 RT/EC Status 2 */
#define MCHP_ACPI_PM1_RT_STS2_REG_OFS 1u
#define MCHP_ACPI_PM1_EC_STS2_REG_OFS 0x0101u
#define MCHP_ACPI_PM1_STS2_REG_MASK 0x008fu
#define MCHP_ACPI_PM1_STS2_PWRBTN BIT(0)
#define MCHP_ACPI_PM1_STS2_SLPBTN BIT(1)
#define MCHP_ACPI_PM1_STS2_RTC BIT(2)
#define MCHP_ACPI_PM1_STS2_PWRBTNOR BIT(3)
#define MCHP_ACPI_PM1_STS2_WAK BIT(7)
/* ACPI_PM1 RT/EC Enable 1 */
#define MCHP_ACPI_PM1_RT_EN1_REG_OFS 0x0002u
#define MCHP_ACPI_PM1_EC_EN1_REG_OFS 0x0102u
#define MCHP_ACPI_PM1_EN1_REG_MASK 0u
/* ACPI_PM1 RT/EC Enable 2 */
#define MCHP_ACPI_PM1_RT_EN2_REG_OFS 3u
#define MCHP_ACPI_PM1_EC_EN2_REG_OFS 0x0103u
#define MCHP_ACPI_PM1_EN2_REG_MASK 0x0007u
#define MCHP_ACPI_PM1_EN2_PWRBTN BIT(0)
#define MCHP_ACPI_PM1_EN2_SLPBTN BIT(1)
#define MCHP_ACPI_PM1_EN2_RTC BIT(2)
/* ACPI_PM1 RT/EC Control 1 */
#define MCHP_ACPI_PM1_RT_CTRL1_REG_OFS 4u
#define MCHP_ACPI_PM1_EC_CTRL1_REG_OFS 0x0104u
#define MCHP_ACPI_PM1_CTRL1_REG_MASK 0u
/* ACPI_PM1 RT/EC Control 2 */
#define MCHP_ACPI_PM1_RT_CTRL2_REG_OFS 5ul
#define MCHP_ACPI_PM1_EC_CTRL2_REG_OFS 0x0105u
#define MCHP_ACPI_PM1_CTRL2_REG_MASK 0x003eu
#define MCHP_ACPI_PM1_CTRL2_PWRBTNOR_EN BIT(1)
#define MCHP_ACPI_PM1_CTRL2_SLP_TYPE_POS 2
#define MCHP_ACPI_PM1_CTRL2_SLP_TYPE_MASK SHLU32(3, 2)
#define MCHP_ACPI_PM1_CTRL2_SLP_EN BIT(5)
/* ACPI_PM1 RT/EC Control 21 */
#define MCHP_ACPI_PM1_RT_CTRL21_REG_OFS 0x0006u
#define MCHP_ACPI_PM1_EC_CTRL21_REG_OFS 0x0106u
#define MCHP_ACPI_PM1_CTRL21_REG_MASK 0u
/* ACPI_PM1 RT/EC Control 22 */
#define MCHP_ACPI_PM1_RT_CTRL22_REG_OFS 7u
#define MCHP_ACPI_PM1_EC_CTRL22_REG_OFS 0x0107u
#define MCHP_ACPI_PM1_CTRL22_REG_MASK 0u
/* ACPI_PM1 EC PM Status register */
#define MCHP_ACPI_PM1_EC_PM_STS_REG_OFS 0x0110u
#define MCHP_ACPI_PM1_EC_PM_STS_REG_MASK 0x01u
#define MCHP_ACPI_PM1_EC_PM_STS_SCI 0x01u
/** @brief ACPI EC Registers (ACPI_EC) */
struct acpi_ec_regs {
volatile uint32_t OS_DATA;
volatile uint8_t OS_CMD_STS;
volatile uint8_t OS_BYTE_CTRL;
uint8_t RSVD1[0x100u - 0x06u];
volatile uint32_t EC2OS_DATA;
volatile uint8_t EC_STS;
volatile uint8_t EC_BYTE_CTRL;
uint8_t RSVD2[2];
volatile uint32_t OS2EC_DATA;
};
/** @brief ACPI PM1 Registers (ACPI_PM1) */
struct acpi_pm1_regs {
volatile uint8_t RT_STS1;
volatile uint8_t RT_STS2;
volatile uint8_t RT_EN1;
volatile uint8_t RT_EN2;
volatile uint8_t RT_CTRL1;
volatile uint8_t RT_CTRL2;
volatile uint8_t RT_CTRL21;
volatile uint8_t RT_CTRL22;
uint8_t RSVD1[(0x100u - 0x008u)];
volatile uint8_t EC_STS1;
volatile uint8_t EC_STS2;
volatile uint8_t EC_EN1;
volatile uint8_t EC_EN2;
volatile uint8_t EC_CTRL1;
volatile uint8_t EC_CTRL2;
volatile uint8_t EC_CTRL21;
volatile uint8_t EC_CTRL22;
uint8_t RSVD2[(0x0110u - 0x0108u)];
volatile uint8_t EC_PM_STS;
uint8_t RSVD3[3];
};
#endif /* #ifndef _MEC_ACPI_EC_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MEC_ADC_H
#define _MEC_ADC_H
#include <stdint.h>
#include <stddef.h>
/* Eight ADC channels numbered 0 - 7 */
#define MCHP_ADC_MAX_CHAN 8u
#define MCHP_ADC_MAX_CHAN_MASK 0x07u
/* Control register */
#define MCHP_ADC_CTRL_REG_OFS 0u
#define MCHP_ADC_CTRL_REG_MASK 0xdfu
#define MCHP_ADC_CTRL_REG_RW_MASK 0x1fu
#define MCHP_ADC_CTRL_REG_RW1C_MASK 0xc0u
#define MCHP_ADC_CTRL_ACTV BIT(0)
#define MCHP_ADC_CTRL_START_SNGL BIT(1)
#define MCHP_ADC_CTRL_START_RPT BIT(2)
#define MCHP_ADC_CTRL_PWRSV_DIS BIT(3)
#define MCHP_ADC_CTRL_SRST BIT(4)
#define MCHP_ADC_CTRL_RPT_DONE_STS BIT(6) /* R/W1C */
#define MCHP_ADC_CTRL_SNGL_DONE_STS BIT(7) /* R/W1C */
/* Delay register. Start and repeat delays in units of 40 us */
#define MCHP_ADC_DELAY_REG_OFS 4u
#define MCHP_ADC_DELAY_REG_MASK 0xffffffffu
#define MCHP_ADC_DELAY_START_POS 0u
#define MCHP_ADC_DELAY_START_MASK 0xffffu
#define MCHP_ADC_DELAY_RPT_POS 16u
#define MCHP_ADC_DELAY_RPT_MASK 0xffff0000u
/* Status register. 0 <= n < MCHP_ADC_MAX_CHAN */
#define MCHP_ADC_STATUS_REG_OFS 8u
#define MCHP_ADC_STATUS_REG_MASK 0xffffu
#define MCHP_ADC_STATUS_CHAN(n) BIT(n)
/* Single Conversion Select register */
#define MCHP_ADC_SCS_REG_OFS 0x0cu
#define MCHP_ADC_SCS_REG_MASK 0xffu
#define MCHP_ADC_SCS_CH_0_7 0xffu
#define MCHP_ADC_SCS_CH(n) BIT(((n) & 0x07u))
/* Repeat Conversion Select register */
#define MCHP_ADC_RCS_REG_OFS 0x10u
#define MCHP_ADC_RCS_REG_MASK 0xffu
#define MCHP_ADC_RCS_CH_0_7 0xffu
#define MCHP_ADC_RCS_CH(n) BIT(((n) & 0x07u))
/* Channel reading registers */
#define MCHP_ADC_RDCH_REG_MASK 0xfffu
#define MCHP_ADC_RDCH0_REG_OFS 0x14u
#define MCHP_ADC_RDCH1_REG_OFS 0x18u
#define MCHP_ADC_RDCH2_REG_OFS 0x1cu
#define MCHP_ADC_RDCH3_REG_OFS 0x20u
#define MCHP_ADC_RDCH4_REG_OFS 0x24u
#define MCHP_ADC_RDCH5_REG_OFS 0x28u
#define MCHP_ADC_RDCH6_REG_OFS 0x2cu
#define MCHP_ADC_RDCH7_REG_OFS 0x30u
/* Configuration register */
#define MCHP_ADC_CFG_REG_OFS 0x7cu
#define MCHP_ADC_CFG_REG_MASK 0xffffu
#define MCHP_ADC_CFG_CLK_LO_TIME_POS 0
#define MCHP_ADC_CFG_CLK_LO_TIME_MASK0 0xffu
#define MCHP_ADC_CFG_CLK_LO_TIME_MASK 0xffu
#define MCHP_ADC_CFG_CLK_HI_TIME_POS 8
#define MCHP_ADC_CFG_CLK_HI_TIME_MASK0 0xffu
#define MCHP_ADC_CFG_CLK_HI_TIME_MASK SHLU32(0xffu, 8)
/* Channel Vref Select register */
#define MCHP_ADC_CH_VREF_SEL_REG_OFS 0x80u
#define MCHP_ADC_CH_VREF_SEL_REG_MASK 0x00ffffffu
#define MCHP_ADC_CH_VREF_SEL_MASK(n) SHLU32(0x03u, (((n) & 0x07) * 2u))
#define MCHP_ADC_CH_VREF_SEL_PAD(n) 0u
#define MCHP_ADC_CH_VREF_SEL_GPIO(n) SHLU32(0x01u, (((n) & 0x07) * 2u))
/* Vref Control register */
#define MCHP_ADC_VREF_CTRL_REG_OFS 0x84u
#define MCHP_ADC_VREF_CTRL_REG_MASK 0xffffffffu
#define MCHP_ADC_VREF_CTRL_CHRG_DEL_POS 0
#define MCHP_ADC_VREF_CTRL_CHRG_DEL_MASK0 0xffffu
#define MCHP_ADC_VREF_CTRL_CHRG_DEL_MASK 0xffffu
#define MCHP_ADC_VREF_CTRL_SW_DEL_POS 16
#define MCHP_ADC_VREF_CTRL_SW_DEL_MASK0 0x1fffu
#define MCHP_ADC_VREF_CTRL_SW_DEL_MASK SHLU32(0x1fffu, 16)
#define MCHP_ADC_VREF_CTRL_PAD_POS 29
#define MCHP_ADC_VREF_CTRL_PAD_UNUSED_FLOAT 0u
#define MCHP_ADC_VREF_CTRL_PAD_UNUSED_DRIVE_LO BIT(29)
#define MCHP_ADC_VREF_CTRL_SEL_STS_POS 30
#define MCHP_ADC_VREF_CTRL_SEL_STS_MASK0 0x03u
#define MCHP_ADC_VREF_CTRL_SEL_STS_MASK SHLU32(3u, 30)
/* SAR ADC Control register */
#define MCHP_ADC_SAR_CTRL_REG_OFS 0x88u
#define MCHP_ADC_SAR_CTRL_REG_MASK 0x0001ff8fu
/* Select single ended or differential operation */
#define MCHP_ADC_SAR_CTRL_SELDIFF_POS 0
#define MCHP_ADC_SAR_CTRL_SELDIFF_DIS 0u
#define MCHP_ADC_SAR_CTRL_SELDIFF_EN BIT(0)
/* Select resolution */
#define MCHP_ADC_SAR_CTRL_RES_POS 1
#define MCHP_ADC_SAR_CTRL_RES_MASK0 0x03u
#define MCHP_ADC_SAR_CTRL_RES_MASK 0x06u
#define MCHP_ADC_SAR_CTRL_RES_10_BITS 0x04u
#define MCHP_ADC_SAR_CTRL_RES_12_BITS 0x06u
/* Shift data in reading register */
#define MCHP_ADC_SAR_CTRL_SHIFTD_POS 3
#define MCHP_ADC_SAR_CTRL_SHIFTD_DIS 0u
#define MCHP_ADC_SAR_CTRL_SHIFTD_EN BIT(3)
/* Warm up delay in ADC clock cycles */
#define MCHP_ADC_SAR_CTRL_WUP_DLY_POS 7
#define MCHP_ADC_SAR_CTRL_WUP_DLY_MASK0 0x3ffu
#define MCHP_ADC_SAR_CTRL_WUP_DLY_MASK SHLU32(0x3ffu, 7)
#define MCHP_ADC_SAR_CTRL_WUP_DLY_DFLT SHLU32(0x202u, 7)
/* Register interface */
#define MCHP_ADC_CH_NUM(n) ((n) & MCHP_ADC_MAX_CHAN_MASK)
#define MCHP_ADC_CH_OFS(n) (MCHP_ADC_CH_NUM(n) * 4u)
#define MCHP_ADC_CH_ADDR(n) (MCHP_ADC_BASE_ADDR + MCHP_ADC_CH_OFS(n))
/** @brief Analog to Digital Converter Registers (ADC) */
struct adc_regs {
volatile uint32_t CONTROL;
volatile uint32_t DELAY;
volatile uint32_t STATUS;
volatile uint32_t SINGLE;
volatile uint32_t REPEAT;
volatile uint32_t RD[8];
uint8_t RSVD1[0x7c - 0x34];
volatile uint32_t CONFIG;
volatile uint32_t VREF_CHAN_SEL;
volatile uint32_t VREF_CTRL;
volatile uint32_t SARADC_CTRL;
};
#endif /* #ifndef _MEC_ADC_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MEC_GLOBAL_CFG_H
#define _MEC_GLOBAL_CFG_H
#include <stdint.h>
#include <stddef.h>
/*
* Device and Revision ID 32-bit register
* b[7:0] = Revision
* b[15:8] = Device Sub-ID
* b[31:16] = Device ID
* This register can be accesses as bytes or a single 32-bit read from
* the EC. Host access byte access via the Host visible configuration
* register space at 0x2E/0x2F (default).
*/
#define MCHP_GCFG_DEV_ID_REG32_OFS 28u
#define MCHP_GCFG_DEV_ID_REG_MASK GENMASK(31, 0)
#define MCHP_GCFG_REV_ID_POS 0
#define MCHP_GCFG_DID_REV_MASK GENMASK(7, 0)
#define MCHP_GCFG_DID_SUB_ID_POS 8
#define MCHP_GCFG_DID_SUB_ID_MASK GENMASK(15, 8)
#define MCHP_GCFG_DID_DEV_ID_POS 16
#define MCHP_GCFG_DID_DEV_ID_MASK GENMASK(31, 16)
/* Byte[0] at offset 0x1c is the 8-bit revision ID */
#define MCHP_GCFG_REV_A1 2u
#define MCHP_GCFG_REV_B0 3u
/*
* Byte[1] at offset 0x1D is the 8-bit Sub-ID
* bits[3:0] = package type
* bits[7:4] = chip family
*/
#define MCHP_GCFG_SUB_ID_OFS 0x1du
#define MCHP_GCFG_SUB_ID_PKG_POS 0
#define MCHP_GCFG_SUB_ID_PKG_MASK GENMASK(3, 0)
#define MCHP_GCFG_SUB_ID_PKG_UNDEF 0u
#define MCHP_GCFG_SUB_ID_PKG_64_PIN 1u
#define MCHP_GCFG_SUB_ID_PKG_84_PIN 2u
#define MCHP_GCFG_SUB_ID_PKG_128_PIN 3u
#define MCHP_GCFG_SUB_ID_PKG_144_PIN 4u
#define MCHP_GCFG_SUB_ID_PKG_176_PIN 7u
/* chip family field */
#define MCHP_GCFG_SUB_ID_FAM_POS 4u
#define MCHP_GCFG_SUB_ID_FAM_MASK GENMASK(7, 4)
#define MCHP_GCFG_SUB_ID_FAM_UNDEF 0u
#define MCHP_GCFG_SUB_ID_FAM_1 0x10u
#define MCHP_GCFG_SUB_ID_FAM_2 0x20u
#define MCHP_GCFG_SUB_ID_FAM_3 0x30u
#define MCHP_GCFG_SUB_ID_FAM_4 0x40u
#define MCHP_GCFG_SUB_ID_FAM_5 0x50u
#define MCHP_GCFG_SUB_ID_FAM_6 0x60u
#define MCHP_GCFG_SUB_ID_FAM_7 0x70u
#define MCHP_GCFG_DEV_ID_LSB_OFS 0x1eu
#define MCHP_GCFG_DEV_ID_MSB_OFS 0x1fu
#define MCHP_GCFG_DEV_ID_172X 0x0022u
#define MCHP_GCFG_DEV_ID_172X_LSB 0x22u
#define MCHP_GCFG_DEV_ID_172X_MSB 0x00u
/* SZ 144-pin package parts */
#define MCHP_GCFG_DEVID_1723_144 0x00223400u
#define MCHP_GCFG_DEVID_1727_144 0x00227400u
/* LJ 176-pin package parts */
#define MCHP_GCFG_DID_1721_176 0x00222700u
#define MCHP_GCFG_DID_1723_176 0x00223700u
#define MCHP_GCFG_DID_1727_176 0x00227700u
/* Legacy Device ID value */
#define MCHP_CCFG_LEGACY_DID_REG_OFS 0x20u
#define MCHP_GCFG_LEGACY_DEV_ID 0xfeu
/* Host access via configuration port (default I/O locations 0x2E/0x2F) */
#define MCHP_HOST_CFG_INDEX_IO_DFLT 0x2eu
#define MCHP_HOST_CFG_DATA_IO_DFLT 0x2fu
#define MCHP_HOST_CFG_UNLOCK 0x55u
#define MCHP_HOST_CFG_LOCK 0xaau
/* Logical Device Configuration Indices */
#define MCHP_HOST_CFG_LDN_IDX 7u
#define MCHP_HOST_CFG_LD_ACTIVATE_IDX 0x30u
#define MCHP_HOST_CFG_LD_BASE_ADDR_IDX 0x34u
#define MCHP_HOST_CFG_LD_CFG_SEL_IDX 0xf0u
/* Global Configuration Registers */
struct global_cfg_regs {
volatile uint8_t RSVD0[2];
volatile uint8_t TEST02;
volatile uint8_t RSVD1[4];
volatile uint8_t LOG_DEV_NUM;
volatile uint8_t RSVD2[20];
volatile uint32_t DEV_REV_ID;
volatile uint8_t LEGACY_DEV_ID;
volatile uint8_t RSVD3[14];
};
#endif /* #ifndef _MEC_GLOBAL_CFG_H */

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/*
* Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MEC_GPIO_H
#define _MEC_GPIO_H
#include <stdint.h>
#include <stddef.h>
#define MCHP_XEC_PINCTRL_REG_IDX(pin) ((pin >> 5) * 32 + (pin & 0x1f))
/** @brief All GPIO register as arrays of registers */
struct gpio_regs {
volatile uint32_t CTRL[174];
uint32_t RESERVED[18];
volatile uint32_t PARIN[6];
uint32_t RESERVED1[26];
volatile uint32_t PAROUT[6];
uint32_t RESERVED2[20];
volatile uint32_t LOCK[6];
uint32_t RESERVED3[64];
volatile uint32_t CTRL2[174];
};
#endif /* #ifndef _MEC_GPIO_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MEC_KBC_H
#define _MEC_KBC_H
#include <stdint.h>
#include <stddef.h>
/* ---- EM8042 Keyboard Controller (KBC) ---- */
/* EC_KBC_STS and KBC_STS_RD bit definitions */
#define MCHP_KBC_STS_OBF_POS 0u
#define MCHP_KBC_STS_OBF BIT(MCHP_KBC_STS_OBF_POS)
#define MCHP_KBC_STS_IBF_POS 1u
#define MCHP_KBC_STS_IBF BIT(MCHP_KBC_STS_IBF_POS)
#define MCHP_KBC_STS_UD0_POS 2u
#define MCHP_KBC_STS_UD0 BIT(MCHP_KBC_STS_UD0_POS)
#define MCHP_KBC_STS_CD_POS 3u
#define MCHP_KBC_STS_CD BIT(MCHP_KBC_STS_CD_POS)
#define MCHP_KBC_STS_UD1_POS 4u
#define MCHP_KBC_STS_UD1 BIT(MCHP_KBC_STS_UD1_POS)
#define MCHP_KBC_STS_AUXOBF_POS 5u
#define MCHP_KBC_STS_AUXOBF BIT(MCHP_KBC_STS_AUXOBF_POS)
#define MCHP_KBC_STS_UD2_POS 6u
#define MCHP_KBC_STS_UD2_MASK0 0x03u
#define MCHP_KBC_STS_UD2_MASK 0xc0u
#define MCHP_KBC_STS_UD2_0_POS 6u
#define MCHP_KBC_STS_UD2_0 BIT(6)
#define MCHP_KBC_STS_UD2_1 BIT(7)
/* KBC_CTRL bit definitions */
#define MCHP_KBC_CTRL_UD3_POS 0u
#define MCHP_KBC_CTRL_UD3 BIT(MCHP_KBC_CTRL_UD3_POS)
#define MCHP_KBC_CTRL_SAEN_POS 1u
#define MCHP_KBC_CTRL_SAEN BIT(MCHP_KBC_CTRL_SAEN_POS)
#define MCHP_KBC_CTRL_PCOBFEN_POS 2u
#define MCHP_KBC_CTRL_PCOBFEN BIT(MCHP_KBC_CTRL_PCOBFEN_POS)
#define MCHP_KBC_CTRL_UD4_POS 3u
#define MCHP_KBC_CTRL_UD4_MASK0 0x03u
#define MCHP_KBC_CTRL_UD4_MASK 0x18u
#define MCHP_KBC_CTRL_OBFEN_POS 5u
#define MCHP_KBC_CTRL_OBFEN BIT(MCHP_KBC_CTRL_OBFEN_POS)
#define MCHP_KBC_CTRL_UD5_POS 6u
#define MCHP_KBC_CTRL_UD5 BIT(MCHP_KBC_CTRL_UD5_POS)
#define MCHP_KBC_CTRL_AUXH_POS 7u
#define MCHP_KBC_CTRL_AUXH BIT(MCHP_KBC_CTRL_AUXH_POS)
/* PCOBF register bit definitions */
#define MCHP_KBC_PCOBF_EN_POS 0u
#define MCHP_KBC_PCOBF_EN BIT(MCHP_KBC_PCOBF_EN_POS)
/* KBC_PORT92_EN register bit definitions */
#define MCHP_KBC_PORT92_EN_POS 0u
#define MCHP_KBC_PORT92_EN BIT(MCHP_KBC_PORT92_EN_POS)
/* HOST Port 92h emulation registers */
#define MCHP_PORT92_HOST_MASK GENMASK(1, 0)
#define MCHP_PORT92_HOST_ALT_CPU_RST_POS 0
#define MCHP_PORT92_HOST_ALT_CPU_RST BIT(0)
#define MCHP_PORT92_HOST_ALT_GA20_POS 1
#define MCHP_PORT92_HOST_ALT_GA20 BIT(1)
/* GATEA20_CTRL */
#define MCHP_PORT92_GA20_CTRL_MASK BIT(0)
#define MCHP_PORT92_GA20_CTRL_VAL_POS 0
#define MCHP_PORT92_GA20_CTRL_VAL_HI BIT(0)
/*
* SETGA20L - writes of any data to this register causes
* GATEA20 latch to be set.
*/
#define MCHP_PORT92_SETGA20L_MASK BIT(0)
#define MCHP_PORT92_SETGA20L_SET_POS 0
#define MCHP_PORT92_SETGA20L_SET BIT(0)
/*
* RSTGA20L - writes of any data to this register causes
* the GATEA20 latch to be reset
*/
#define MCHP_PORT92_RSTGA20L_MASK BIT(0)
#define MCHP_PORT92_RSTGA20L_SET_POS 0
#define MCHP_PORT92_RSTGA20L_RST BIT(0)
/* ACTV */
#define MCHP_PORT92_ACTV_MASK BIT(0)
#define MCHP_PORT92_ACTV_ENABLE BIT(0)
/** @brief 8042 Emulated Keyboard controller. Size = 820(0x334) */
struct kbc_regs {
volatile uint32_t HOST_AUX_DATA;
volatile uint32_t KBC_STS_RD;
uint8_t RSVD1[0x100 - 0x08];
volatile uint32_t EC_DATA;
volatile uint32_t EC_KBC_STS;
volatile uint32_t KBC_CTRL;
volatile uint32_t EC_AUX_DATA;
uint32_t RSVD2[1];
volatile uint32_t PCOBF;
uint8_t RSVD3[0x0330 - 0x0118];
volatile uint32_t KBC_PORT92_EN;
};
/** @brief Fast Port92h Registers (PORT92) */
struct port92_regs {
volatile uint32_t HOST_P92;
uint8_t RSVD1[0x100u - 0x04u];
volatile uint32_t GATEA20_CTRL;
uint32_t RSVD2[1];
volatile uint32_t SETGA20L;
volatile uint32_t RSTGA20L;
uint8_t RSVD3[0x0330ul - 0x0110ul];
volatile uint32_t ACTV;
};
#endif /* #ifndef _MEC_KBC_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MEC_KSCAN_H
#define _MEC_KSCAN_H
#include <stdint.h>
#include <stddef.h>
/* KSO_SEL */
#define MCHP_KSCAN_KSO_SEL_REG_MASK 0xffu
#define MCHP_KSCAN_KSO_LINES_POS 0u
#define MCHP_KSCAN_KSO_LINES_MASK0 0x1fu
#define MCHP_KSCAN_KSO_LINES_MASK 0x1fu
#define MCHP_KSCAN_KSO_ALL_POS 5u
#define MCHP_KSCAN_KSO_ALL BIT(5)
#define MCHP_KSCAN_KSO_EN_POS 6u
#define MCHP_KSCAN_KSO_EN BIT(6)
#define MCHP_KSCAN_KSO_INV_POS 7u
#define MCHP_KSCAN_KSO_INV BIT(7)
/* KSI_IN */
#define MCHP_KSCAN_KSI_IN_REG_MASK 0xffu
/* KSI_STS */
#define MCHP_KSCAN_KSI_STS_REG_MASK 0xffu
/* KSI_IEN */
#define MCHP_KSCAN_KSI_IEN_REG_MASK 0xffu
/* EXT_CTRL */
#define MCHP_KSCAN_EXT_CTRL_REG_MASK 0x01u
#define MCHP_KSCAN_EXT_CTRL_PREDRV_EN 0x01u
/** @brief Keyboard scan matrix controller. Size = 24(0x18) */
struct kscan_regs {
uint32_t RSVD[1];
volatile uint32_t KSO_SEL;
volatile uint32_t KSI_IN;
volatile uint32_t KSI_STS;
volatile uint32_t KSI_IEN;
volatile uint32_t EXT_CTRL;
};
#endif /* #ifndef _MEC_KSCAN_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MEC_PECI_H
#define _MEC_PECI_H
#include <stdint.h>
#include <stddef.h>
/* Write Data register */
#define MCHP_PECI_WR_DATA_REG_OFS 0u
#define MCHP_PECI_WR_DATA_MASK 0xffu
/* Read Data register */
#define MCHP_PECI_RD_DATA_REG_OFS 4u
#define MCHP_PECI_RD_DATA_MASK 0xffu
/* Control register */
#define MCHP_PECI_CTRL_REG_OFS 8u
#define MCHP_PECI_CTRL_MASK 0xe9u
#define MCHP_PECI_CTRL_PD_POS 0
#define MCHP_PECI_CTRL_PD BIT(MCHP_PECI_CTRL_PD_POS)
#define MCHP_PECI_CTRL_RST_POS 3
#define MCHP_PECI_CTRL_RST BIT(MCHP_PECI_CTRL_RST_POS)
#define MCHP_PECI_CTRL_FRST_POS 5
#define MCHP_PECI_CTRL_FRST BIT(MCHP_PECI_CTRL_FRST_POS)
#define MCHP_PECI_CTRL_TXEN_POS 6
#define MCHP_PECI_CTRL_TXEN BIT(MCHP_PECI_CTRL_TXEN_POS)
#define MCHP_PECI_CTRL_MIEN_POS 7
#define MCHP_PECI_CTRL_MIEN BIT(MCHP_PECI_CTRL_MIEN_POS)
/* Status 1 register. RW1C and read-only bits. */
#define MCHP_PECI_STS1_REG_OFS 0x0cu
#define MCHP_PECI_STS1_MASK 0xbfu
#define MCHP_PECI_STS1_BOF_POS 0
#define MCHP_PECI_STS1_BOF BIT(MCHP_PECI_STS1_BOF_POS)
#define MCHP_PECI_STS1_EOF_POS 1
#define MCHP_PECI_STS1_EOF BIT(MCHP_PECI_STS1_EOF_POS)
/* Error is read-only */
#define MCHP_PECI_STS1_ERR_POS 2
#define MCHP_PECI_STS1_ERR BIT(MCHP_PECI_STS1_ERR_POS)
/* Ready is read-only */
#define MCHP_PECI_STS1_RDY_POS 3
#define MCHP_PECI_STS1_RDY BIT(MCHP_PECI_STS1_RDY_POS)
#define MCHP_PECI_STS1_RDYLO_POS 4
#define MCHP_PECI_STS1_RDYLO BIT(MCHP_PECI_STS1_RDYLO_POS)
#define MCHP_PECI_STS1_RDYHI_POS 5
#define MCHP_PECI_STS1_RDYHI BIT(MCHP_PECI_STS1_RDYHI_POS)
/* MINT is read-only */
#define MCHP_PECI_STS1_MINT_POS 7
#define MCHP_PECI_STS1_MINT BIT(MCHP_PECI_STS1_MINT_POS)
/* Status 2 register. Read-only bits. */
#define MCHP_PECI_STS2_REG_OFS 0x10u
#define MCHP_PECI_STS2_MASK 0x8fu
#define MCHP_PECI_STS2_WFF_POS 0
#define MCHP_PECI_STS2_WFF BIT(MCHP_PECI_STS2_WFF_POS)
#define MCHP_PECI_STS2_WFE_POS 1
#define MCHP_PECI_STS2_WFE BIT(MCHP_PECI_STS2_WFE_POS)
#define MCHP_PECI_STS2_RFF_POS 2
#define MCHP_PECI_STS2_RFF BIT(MCHP_PECI_STS2_RFF_POS)
#define MCHP_PECI_STS2_RFE_POS 3
#define MCHP_PECI_STS2_RFE BIT(MCHP_PECI_STS2_RFE_POS)
#define MCHP_PECI_STS2_IDLE_POS 7
#define MCHP_PECI_STS2_IDLE BIT(MCHP_PECI_STS2_IDLE_POS)
/* Error register. R/W1C bits. */
#define MCHP_PECI_ERR_REG_OFS 0x14u
#define MCHP_PECI_ERR_MASK 0xf3u
#define MCHP_PECI_ERR_FERR_POS 0
#define MCHP_PECI_ERR_FERR BIT(MCHP_PECI_ERR_FERR_POS)
#define MCHP_PECI_ERR_BERR_POS 1
#define MCHP_PECI_ERR_BERR BIT(MCHP_PECI_ERR_BERR_POS)
#define MCHP_PECI_ERR_WROV_POS 4
#define MCHP_PECI_ERR_WROV BIT(MCHP_PECI_ERR_WROV_POS)
#define MCHP_PECI_ERR_WRUN_POS 5
#define MCHP_PECI_ERR_WRUN BIT(MCHP_PECI_ERR_WRUN_POS)
#define MCHP_PECI_ERR_RDOV_POS 6
#define MCHP_PECI_ERR_RDOV BIT(MCHP_PECI_ERR_RDOV_POS)
#define MCHP_PECI_ERR_CLK_POS 7
#define MCHP_PECI_ERR_CLK BIT(MCHP_PECI_ERR_CLK_POS)
/* Interrupt Enable 1 register. */
#define MCHP_PECI_IEN1_REG_OFS 0x18u
#define MCHP_PECI_IEN1_MASK 0x37u
#define MCHP_PECI_IEN1_BIEN_POS 0
#define MCHP_PECI_IEN1_BIEN BIT(MCHP_PECI_IEN1_BIEN_POS)
#define MCHP_PECI_IEN1_EIEN_POS 1
#define MCHP_PECI_IEN1_EIEN BIT(MCHP_PECI_IEN1_EIEN_POS)
#define MCHP_PECI_IEN1_EREN_POS 2
#define MCHP_PECI_IEN1_EREN BIT(MCHP_PECI_IEN1_EREN_POS)
#define MCHP_PECI_IEN1_RLEN_POS 4
#define MCHP_PECI_IEN1_RLEN BIT(MCHP_PECI_IEN1_RLEN_POS)
#define MCHP_PECI_IEN1_RHEN_POS 5
#define MCHP_PECI_IEN1_RHEN BIT(MCHP_PECI_IEN1_RHEN_POS)
/* Interrupt Enable 2 register. */
#define MCHP_PECI_IEN2_REG_OFS 0x1cu
#define MCHP_PECI_IEN2_MASK 0x06u
#define MCHP_PECI_IEN2_ENWFE_POS 1
#define MCHP_PECI_IEN2_ENWFE BIT(MCHP_PECI_IEN2_ENWFE_POS)
#define MCHP_PECI_IEN2_ENRFF_POS 2
#define MCHP_PECI_IEN2_ENRFF BIT(MCHP_PECI_IEN2_ENRFF_POS)
/* Optimal Bit Time LSB register. */
#define MCHP_PECI_OPT_BT_LSB_REG_OFS 0x20u
#define MCHP_PECI_OPT_BT_LSB_MASK 0xffu
/* Optimal Bit Time MSB register. */
#define MCHP_PECI_OPT_BT_MSB_REG_OFS 0x24u
#define MCHP_PECI_OPT_BT_MSB_MASK 0xffu
/** @brief PECI controller. Size = 76(0x4c) */
struct peci_regs {
volatile uint8_t WR_DATA;
uint8_t RSVD1[3];
volatile uint8_t RD_DATA;
uint8_t RSVD2[3];
volatile uint8_t CONTROL;
uint8_t RSVD3[3];
volatile uint8_t STATUS1;
uint8_t RSVD4[3];
volatile uint8_t STATUS2;
uint8_t RSVD5[3];
volatile uint8_t ERROR;
uint8_t RSVD6[3];
volatile uint8_t INT_EN1;
uint8_t RSVD7[3];
volatile uint8_t INT_EN2;
uint8_t RSVD8[3];
volatile uint8_t OPT_BIT_TIME_LSB;
uint8_t RSVD9[3];
volatile uint8_t OPT_BIT_TIME_MSB;
uint8_t RSVD10[3];
volatile uint8_t REQ_TMR_LSB;
uint8_t RSVD11[3];
volatile uint8_t REQ_TMR_MSB;
uint8_t RSVD12[3];
volatile uint8_t BAUD_CTRL;
uint8_t RSVD13[3];
uint32_t RSVD14[3];
volatile uint8_t BLK_ID;
uint8_t RSVD15[3];
volatile uint8_t BLK_REV;
uint8_t RSVD16[3];
volatile uint8_t SST_CTL1;
uint8_t RSVD17[3];
};
#endif /* #ifndef _MEC_PECI_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MEC_PS2_H
#define _MEC_PS2_H
#include <stdint.h>
#include <stddef.h>
/*
* PS2 TRX Buffer register
* Writes -> Transmit buffer
* Read <- Receive buffer
*/
#define MCHP_PS2_TRX_BUFF_REG_MASK 0xffu
/* PS2 Control register */
#define MCHP_PS2_CTRL_REG_MASK 0x3fu
/* Select Transmit or Receive */
#define MCHP_PS2_CTRL_TR_POS 0u
#define MCHP_PS2_CTRL_TR_RX 0u
#define MCHP_PS2_CTRL_TR_TX BIT(MCHP_PS2_CTRL_TR_POS)
/* Enable PS2 state machine */
#define MCHP_PS2_CTRL_EN_POS 1u
#define MCHP_PS2_CTRL_EN BIT(MCHP_PS2_CTRL_EN_POS)
/* Protocol parity selection */
#define MCHP_PS2_CTRL_PAR_POS 2u
#define MCHP_PS2_CTRL_PAR_MASK0 0x03u
#define MCHP_PS2_CTRL_PAR_MASK 0x0cu
#define MCHP_PS2_CTRL_PAR_ODD 0u
#define MCHP_PS2_CTRL_PAR_EVEN 0x04u
#define MCHP_PS2_CTRL_PAR_IGNORE 0x08u
#define MCHP_PS2_CTRL_PAR_RSVD 0x0cu
/* Protocol stop bit selection */
#define MCHP_PS2_CTRL_STOP_POS 4u
#define MCHP_PS2_CTRL_STOP_MASK0 0x03u
#define MCHP_PS2_CTRL_STOP_MASK 0x30u
#define MCHP_PS2_CTRL_STOP_ACT_HI 0u
#define MCHP_PS2_CTRL_STOP_ACT_LO 0x10u
#define MCHP_PS2_CTRL_STOP_IGNORE 0x20u
#define MCHP_PS2_CTRL_STOP_RSVD 0x30u
/* PS2 Status register */
#define MCHP_PS2_STATUS_REG_MASK 0xffu
#define MCHP_PS2_STATUS_RW1C_MASK 0xaeu
#define MCHP_PS2_STATUS_RO_MASK 0x51u
/* RX Data Ready(Read-Only) */
#define MCHP_PS2_STATUS_RXD_RDY_POS 0
#define MCHP_PS2_STATUS_RXD_RDY BIT(MCHP_PS2_STATUS_RXD_RDY_POS)
/* RX Timeout(R/W1C) */
#define MCHP_PS2_STATUS_RX_TMOUT_POS 1
#define MCHP_PS2_STATUS_RX_TMOUT BIT(MCHP_PS2_STATUS_RX_TMOUT_POS)
/* Parity Error(R/W1C) */
#define MCHP_PS2_STATUS_PE_POS 2
#define MCHP_PS2_STATUS_PE BIT(MCHP_PS2_STATUS_PE_POS)
/* Framing Error(R/W1C) */
#define MCHP_PS2_STATUS_FE_POS 3
#define MCHP_PS2_STATUS_FE BIT(MCHP_PS2_STATUS_FE_POS)
/* Transmitter is Idle(Read-Only) */
#define MCHP_PS2_STATUS_TX_IDLE_POS 4
#define MCHP_PS2_STATUS_TX_IDLE BIT(MCHP_PS2_STATUS_TX_IDLE_POS)
/* Transmitter timeout(R/W1C) */
#define MCHP_PS2_STATUS_TX_TMOUT_POS 5
#define MCHP_PS2_STATUS_TX_TMOUT BIT(MCHP_PS2_STATUS_TX_TMOUT_POS)
/* RX is Busy(Read-Only) */
#define MCHP_PS2_STATUS_RX_BUSY_POS 6
#define MCHP_PS2_STATUS_RX_BUSY BIT(MCHP_PS2_STATUS_RX_BUSY_POS)
/* Transmitter start timeout(R/W1C) */
#define MCHP_PS2_STATUS_TX_ST_TMOUT_POS 7
#define MCHP_PS2_STATUS_TX_ST_TMOUT BIT(MCHP_PS2_STATUS_TX_ST_TMOUT_POS)
/* PS2 Protocol bit positions */
#define MCHP_PS2_PROT_START_BIT_POS 1
#define MCHP_PS2_PROT_DATA_BIT0_POS 2
#define MCHP_PS2_PROT_DATA_BIT1_POS 3
#define MCHP_PS2_PROT_DATA_BIT2_POS 4
#define MCHP_PS2_PROT_DATA_BIT3_POS 5
#define MCHP_PS2_PROT_DATA_BIT4_POS 6
#define MCHP_PS2_PROT_DATA_BIT5_POS 7
#define MCHP_PS2_PROT_DATA_BIT6_POS 8
#define MCHP_PS2_PROT_DATA_BIT7_POS 9
#define MCHP_PS2_PROT_PARITY_POS 10
#define MCHP_PS2_PROT_STOP_BIT_POS 11
/** @brief PS/2 controller */
struct ps2_regs {
volatile uint32_t TRX_BUFF;
volatile uint32_t CTRL;
volatile uint32_t STATUS;
};
#endif /* #ifndef _MEC_PS2_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MEC_PWM_H
#define _MEC_PWM_H
#include <stdint.h>
#include <stddef.h>
#define MCHP_PWM_INST_SPACING 0x10u
#define MCHP_PWM_INST_SPACING_P2 4u
/* PWM Count On register */
#define MCHP_PWM_COUNT_ON_REG_OFS 0u
#define MCHP_PWM_COUNT_ON_MASK 0xffffu
/* PWM Count Off register */
#define MCHP_PWM_COUNT_OFF_REG_OFS 4u
#define MCHP_PWM_COUNT_OFF_MASK 0xffffu
/* PWM Configuration Register */
#define MCHP_PWM_CONFIG_REG_OFS 8u
#define MCHP_PWM_CONFIG_MASK 0x7fu
/*
* Enable and start PWM. Clearing this bit resets internal counters.
* COUNT_ON and COUNT_OFF registers are not affected by enable bit.
*/
#define MCHP_PWM_CFG_ENABLE_POS 0
#define MCHP_PWM_CFG_ENABLE BIT(MCHP_PWM_CFG_ENABLE_POS)
/* Clock select */
#define MCHP_PWM_CFG_CLK_SEL_POS 1u
#define MCHP_PWM_CFG_CLK_SEL_48M 0u
#define MCHP_PWM_CFG_CLK_SEL_100K BIT(MCHP_PWM_CFG_CLK_SEL_POS)
/*
* ON state polarity.
* Default ON state is High.
*/
#define MCHP_PWM_CFG_ON_POL_POS 2u
#define MCHP_PWM_CFG_ON_POL_HI 0u
#define MCHP_PWM_CFG_ON_POL_LO BIT(MCHP_PWM_CFG_ON_POL_POS)
/*
* Clock pre-divider
* Clock divider value = pre-divider + 1
*/
#define MCHP_PWM_CFG_CLK_PRE_DIV_POS 3u
#define MCHP_PWM_CFG_CLK_PRE_DIV_MASK0 0x0fU
#define MCHP_PWM_CFG_CLK_PRE_DIV_MASK \
SHLU32(0x0fu, MCHP_PWM_CFG_CLK_PRE_DIV_POS)
#define MCHP_PWM_CFG_CLK_PRE_DIV(n) \
SHLU32((n) & MCHP_PWM_CFG_CLK_PRE_DIV_MASK0, \
MCHP_PWM_CFG_CLK_PRE_DIV_POS)
/* PWM input frequencies selected in configuration register. */
#define MCHP_PWM_INPUT_FREQ_HI 48000000u
#define MCHP_PWM_INPUT_FREQ_LO 100000u
/*
* PWM Frequency =
* (1 / (pre_div + 1)) * PWM_INPUT_FREQ / ((COUNT_ON+1) + (COUNT_OFF+1))
*
* PWM Duty Cycle =
* (COUNT_ON+1) / ((COUNT_ON+1) + (COUNT_OFF + 1))
*/
/** @brief PWM controller */
struct pwm_regs {
volatile uint32_t COUNT_ON;
volatile uint32_t COUNT_OFF;
volatile uint32_t CONFIG;
};
#endif /* #ifndef _MEC_PWM_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MEC_TACH_H
#define _MEC_TACH_H
#include <stdint.h>
#include <stddef.h>
#define MCHP_TACH_INST_SPACING 0x10ul
#define MCHP_TACH_INST_SPACING_P2 4u
/* TACH Control register */
#define MCHP_TACH_CONTROL_REG_OFS 0U
#define MCHP_TACH_CONTROL_MASK 0xffffdd03U
/* Enable exceed high or low limit detection */
#define MCHP_TACH_CTRL_EXCEED_LIM_EN_POS 0
#define MCHP_TACH_CTRL_EXCEED_LIM_EN BIT(0)
/* Enable TACH operation */
#define MCHP_TACH_CTRL_EN_POS 1
#define MCHP_TACH_CTRL_EN BIT(MCHP_TACH_CTRL_EN_POS)
/* Enable input filter */
#define MCHP_TACH_CTRL_FILTER_EN_POS 8
#define MCHP_TACH_CTRL_FILTER_EN BIT(MCHP_TACH_CTRL_FILTER_EN_POS)
/* Select read mode. Latch data on rising edge of selected trigger */
#define MCHP_TACH_CTRL_READ_MODE_SEL_POS 10
#define MCHP_TACH_CTRL_READ_MODE_INPUT 0U
#define MCHP_TACH_CTRL_READ_MODE_100K_CLOCK BIT(10)
/* Select TACH edges for counter increment */
#define MCHP_TACH_CTRL_NUM_EDGES_POS 11
#define MCHP_TACH_CTRL_NUM_EDGES_MASK0 0x03U
#define MCHP_TACH_CTRL_NUM_EDGES_MASK SHLU32(0x03U, 11)
#define MCHP_TACH_CTRL_EDGES_2 0U
#define MCHP_TACH_CTRL_EDGES_3 SHLU32(1u, 11)
#define MCHP_TACH_CTRL_EDGES_5 SHLU32(2u, 11)
#define MCHP_TACH_CTRL_EDGES_9 SHLU32(3u, 11)
/* Enable count ready interrupt */
#define MCHP_TACH_CTRL_CNT_RDY_INT_EN_POS 14
#define MCHP_TACH_CTRL_CNT_RDY_INT_EN BIT(14)
/* Enable input toggle interrupt */
#define MCHP_TACH_CTRL_TOGGLE_INT_EN_POS 15
#define MCHP_TACH_CTRL_TOGGLE_INT_EN BIT(15)
/* Read-only latched TACH pulse counter */
#define MCHP_TACH_CTRL_COUNTER_POS 16
#define MCHP_TACH_CTRL_COUNTER_MASK0 0xfffful
#define MCHP_TACH_CTRL_COUNTER_MASK SHLU32(0xffffU, 16)
/*
* TACH Status register
* bits[0, 2-3] are R/W1C
* bit[1] is Read-Only
*/
#define MCHP_TACH_STATUS_REG_OFS 4U
#define MCHP_TACH_STATUS_MASK 0x0FU
#define MCHP_TACH_STS_EXCEED_LIMIT_POS 0
#define MCHP_TACH_STS_EXCEED_LIMIT BIT(MCHP_TACH_STS_EXCEED_LIMIT_POS)
#define MCHP_TACH_STS_PIN_STATE_POS 1
#define MCHP_TACH_STS_PIN_STATE_HI BIT(MCHP_TACH_STS_PIN_STATE_POS)
#define MCHP_TACH_STS_TOGGLE_POS 2
#define MCHP_TACH_STS_TOGGLE BIT(MCHP_TACH_STS_TOGGLE_POS)
#define MCHP_TACH_STS_CNT_RDY_POS 3
#define MCHP_TACH_STS_CNT_RDY BIT(MCHP_TACH_STS_CNT_RDY_POS)
/* TACH High Limit Register */
#define MCHP_TACH_HI_LIMIT_REG_OFS 8U
#define MCHP_TACH_HI_LIMIT_MASK 0xffffU
/* TACH Low Limit Register */
#define MCHP_TACH_LO_LIMIT_REG_OFS 0x0CU
#define MCHP_TACH_LO_LIMIT_MASK 0xffffU
/** @brief Tachometer Registers (TACH) */
struct tach_regs {
volatile uint32_t CONTROL;
volatile uint32_t STATUS;
volatile uint32_t LIMIT_HI;
volatile uint32_t LIMIT_LO;
};
#endif /* #ifndef _MEC_TACH_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MEC_TFDP_H
#define _MEC_TFDP_H
#include <stdint.h>
#include <stddef.h>
#define MCHP_TFDP_CTRL_REG_MASK 0x7fu
#define MCHP_TFDP_CTRL_EN_POS 0u
#define MCHP_TFDP_CTRL_EDGE_SEL_POS 1u
#define MCHP_TFDP_CTRL_DIV_SEL_POS 2u
#define MCHP_TFDP_CTRL_IP_DLY_POS 4u
#define MCHP_TFDP_CTRL_EN BIT(0)
#define MCHP_TFDP_OUT_ON_FALLING_EDGE BIT(1)
#define MCHP_TFDP_CLK_AHB_DIV_2 0
#define MCHP_TFDP_CLK_AHB_DIV_4 0x04u
#define MCHP_TFDP_CLK_AHB_DIV_8 0x08u
#define MCHP_TFDP_CLK_AHB_DIV_2_ALT 0x0cu
/* Number of AHB clocks between each byte shifted out */
#define MCHP_TFDP_IP_DLY_1 0
#define MCHP_TFDP_IP_DLY_2 0x10u
#define MCHP_TFDP_IP_DLY_3 0x20u
#define MCHP_TFDP_IP_DLY_4 0x30u
#define MCHP_TFDP_IP_DLY_5 0x40u
#define MCHP_TFDP_IP_DLY_6 0x50u
#define MCHP_TFDP_IP_DLY_7 0x60u
#define MCHP_TFDP_IP_DLY_8 0x70u
/* First byte indicates start of packet */
#define MCHP_TFDP_PKT_START 0xfdu
/** @brief Trace FIFO Debug Port Registers (TFDP) */
struct tfdp_regs {
volatile uint8_t DATA_OUT;
uint8_t RSVD1[3];
volatile uint32_t CTRL;
};
#endif /* #ifndef _MEC_TFDP_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MEC_TIMERS_H
#define _MEC_TIMERS_H
#include <stdint.h>
#include <stddef.h>
/* Basic timers */
/* Offset between instances of the Basic Timer blocks */
#define MCHP_BTMR_INSTANCE_POS 5ul
#define MCHP_BTMR_INSTANCE_OFS 0x20u
/* Base frequency of all basic timers is AHB clock */
#define MCHP_BTMR_BASE_FREQ 48000000u
#define MCHP_BTMR_MIN_FREQ (MCHP_BTMR_BASE_FREQ / 0x10000u)
/*
* Basic Timer Count Register (Offset +00h)
* 32-bit R/W
* 16-bit Basic timers: bits[15:0]=R/W, bits[31:15]=RO=0
*/
#define MCHP_BTMR_CNT_OFS 0x00u
/*
* Basic Timer Preload Register (Offset +04h)
* 32-bit R/W
* 16-bit Basic timers: bits[15:0]=R/W, bits[31:15]=RO=0
*/
#define MCHP_BTMR_PRELOAD_OFS 0x04u
/* Basic Timer Status Register (Offset +08h) R/W1C */
#define MCHP_BTMR_STS_OFS 0x08u
#define MCHP_BTMR_STS_MASK 0x01u
#define MCHP_BTMR_STS_ACTIVE_POS 0
#define MCHP_BTMR_STS_ACTIVE 0x01u
/* Basic Timer Interrupt Enable Register (Offset +0Ch) */
#define MCHP_BTMR_INTEN_OFS 0x0cu
#define MCHP_BTMR_INTEN_MASK 0x01u
#define MCHP_BTMR_INTEN_POS 0
#define MCHP_BTMR_INTEN 0x01u
#define MCHP_BTMR_INTDIS 0u
/* Basic Timer Control Register (Offset +10h) */
#define MCHP_BTMR_CTRL_OFS 0x10u
#define MCHP_BTMR_CTRL_MASK 0xffff00fdu
#define MCHP_BTMR_CTRL_PRESCALE_POS 16u
#define MCHP_BTMR_CTRL_PRESCALE_MASK0 0xffffu
#define MCHP_BTMR_CTRL_PRESCALE_MASK 0xffff0000u
#define MCHP_BTMR_CTRL_HALT 0x80u
#define MCHP_BTMR_CTRL_RELOAD 0x40u
#define MCHP_BTMR_CTRL_START 0x20u
#define MCHP_BTMR_CTRL_SOFT_RESET 0x10u
#define MCHP_BTMR_CTRL_AUTO_RESTART 0x08u
#define MCHP_BTMR_CTRL_COUNT_UP 0x04u
#define MCHP_BTMR_CTRL_ENABLE 0x01u
/* */
#define MCHP_BTMR_CTRL_HALT_POS 7u
#define MCHP_BTMR_CTRL_RELOAD_POS 6u
#define MCHP_BTMR_CTRL_START_POS 5u
#define MCHP_BTMR_CTRL_SRESET_POS 4u
#define MCHP_BTMR_CTRL_AUTO_RESTART_POS 3u
#define MCHP_BTMR_CTRL_COUNT_DIR_POS 2u
#define MCHP_BTMR_CTRL_ENABLE_POS 0u
/** @brief Basic Timer(32 and 16 bit) registers. Total size = 20(0x14) bytes */
struct btmr_regs {
volatile uint32_t CNT;
volatile uint32_t PRLD;
volatile uint8_t STS;
uint8_t RSVDC[3];
volatile uint8_t IEN;
uint8_t RSVDD[3];
volatile uint32_t CTRL;
};
/*
* Hibernation Timer
* Set count resolution in bit[0]
* 0 = 30.5 us (32786 Hz)
* 1 = 125 ms (8 Hz)
*/
#define MCHP_HTMR_CTRL_REG_MASK 0x01u
#define MCHP_HTMR_CTRL_RESOL_POS 0u
#define MCHP_HTMR_CTRL_RESOL_MASK BIT(MCHP_HTMR_CTRL_EN_POS)
#define MCHP_HTMR_CTRL_RESOL_30US 0u
#define MCHP_HTMR_CTRL_RESOL_125MS BIT(MCHP_HTMR_CTRL_EN_POS)
/*
* Hibernation timer is started and stopped by writing a value
* to the CNT (count) register.
* Writing a non-zero value resets and start the counter counting down.
* Writing 0 stops the timer.
*/
#define MCHP_HTMR_CNT_STOP_VALUE 0
/** @brief Hibernation Timer (HTMR) */
struct htmr_regs {
volatile uint16_t PRLD;
uint16_t RSVD1[1];
volatile uint16_t CTRL;
uint16_t RSVD2[1];
volatile uint16_t CNT;
uint16_t RSVD3[1];
};
/* Capture/Compare Timer */
/* Control register at offset 0x00. Must use 32-bit access */
#define MCHP_CCT_CTRL_ACTIVATE BIT(0)
#define MCHP_CCT_CTRL_FRUN_EN BIT(1)
#define MCHP_CCT_CTRL_FRUN_RESET BIT(2) /* self clearing bit */
#define MCHP_CCT_CTRL_TCLK_MASK0 0x07u
#define MCHP_CCT_CTRL_TCLK_MASK SHLU32(MCHP_CCT_CTRL_TCLK_MASK0, 4)
#define MCHP_CCT_CTRL_TCLK_DIV_1 0u
#define MCHP_CCT_CTRL_TCLK_DIV_2 SHLU32(1, 4)
#define MCHP_CCT_CTRL_TCLK_DIV_4 SHLU32(2, 4)
#define MCHP_CCT_CTRL_TCLK_DIV_8 SHLU32(3, 4)
#define MCHP_CCT_CTRL_TCLK_DIV_16 SHLU32(4, 4)
#define MCHP_CCT_CTRL_TCLK_DIV_32 SHLU32(5, 4)
#define MCHP_CCT_CTRL_TCLK_DIV_64 SHLU32(6, 4)
#define MCHP_CCT_CTRL_TCLK_DIV_128 SHLU32(7, 4)
#define MCHP_CCT_CTRL_COMP0_EN BIT(8)
#define MCHP_CCT_CTRL_COMP1_EN BIT(9)
#define MCHP_CCT_CTRL_COMP1_SET BIT(16) /* R/WS */
#define MCHP_CCT_CTRL_COMP0_SET BIT(17) /* R/WS */
#define MCHP_CCT_CTRL_COMP1_CLR BIT(24) /* R/W1C */
#define MCHP_CCT_CTRL_COMP0_CLR BIT(25) /* R/W1C */
/** @brief Capture/Compare Timer */
struct cct_regs {
volatile uint32_t CTRL;
volatile uint32_t CAP0_CTRL;
volatile uint32_t CAP1_CTRL;
volatile uint32_t FREE_RUN;
volatile uint32_t CAP0;
volatile uint32_t CAP1;
volatile uint32_t CAP2;
volatile uint32_t CAP3;
volatile uint32_t CAP4;
volatile uint32_t CAP5;
volatile uint32_t COMP0;
volatile uint32_t COMP1;
};
/* RTOS Timer */
#define MCHP_RTMR_FREQ_HZ 32768u
#define MCHP_RTMR_CTRL_MASK 0x1fu
#define MCHP_RTMR_CTRL_BLK_EN_POS 0
#define MCHP_RTMR_CTRL_BLK_EN_MASK BIT(MCHP_RTMR_CTRL_BLK_EN_POS)
#define MCHP_RTMR_CTRL_BLK_EN BIT(MCHP_RTMR_CTRL_BLK_EN_POS)
#define MCHP_RTMR_CTRL_AUTO_RELOAD_POS 1u
#define MCHP_RTMR_CTRL_AUTO_RELOAD_MASK BIT(MCHP_RTMR_CTRL_AUTO_RELOAD_POS)
#define MCHP_RTMR_CTRL_AUTO_RELOAD BIT(MCHP_RTMR_CTRL_AUTO_RELOAD_POS)
#define MCHP_RTMR_CTRL_START_POS 2u
#define MCHP_RTMR_CTRL_START_MASK BIT(MCHP_RTMR_CTRL_START_POS)
#define MCHP_RTMR_CTRL_START BIT(MCHP_RTMR_CTRL_START_POS)
#define MCHP_RTMR_CTRL_HW_HALT_EN_POS 3u
#define MCHP_RTMR_CTRL_HW_HALT_EN_MASK BIT(MCHP_RTMR_CTRL_HW_HALT_EN_POS)
#define MCHP_RTMR_CTRL_HW_HALT_EN BIT(MCHP_RTMR_CTRL_HW_HALT_EN_POS)
#define MCHP_RTMR_CTRL_FW_HALT_EN_POS 4u
#define MCHP_RTMR_CTRL_FW_HALT_EN_MASK BIT(MCHP_RTMR_CTRL_FW_HALT_EN_POS)
#define MCHP_RTMR_CTRL_FW_HALT_EN BIT(MCHP_RTMR_CTRL_FW_HALT_EN_POS)
/** @brief RTOS Timer (RTMR) */
struct rtmr_regs {
volatile uint32_t CNT;
volatile uint32_t PRLD;
volatile uint32_t CTRL;
volatile uint32_t SOFTIRQ;
};
/* Week Timer */
#define MCHP_WKTMR_CTRL_MASK 0x41u
#define MCHP_WKTMR_CTRL_WT_EN_POS 0
#define MCHP_WKTMR_CTRL_WT_EN_MASK BIT(MCHP_WKTMR_CTRL_WT_EN_POS)
#define MCHP_WKTMR_CTRL_WT_EN BIT(MCHP_WKTMR_CTRL_WT_EN_POS)
#define MCHP_WKTMR_CTRL_PWRUP_EV_EN_POS 6u
#define MCHP_WKTMR_CTRL_PWRUP_EV_EN_MASK BIT(MCHP_WKTMR_CTRL_PWRUP_EV_EN_POS)
#define MCHP_WKTMR_CTRL_PWRUP_EV_EN BIT(MCHP_WKTMR_CTRL_PWRUP_EV_EN_POS)
#define MCHP_WKTMR_ALARM_CNT_MASK 0x0fffffffu
#define MCHP_WKTMR_TMR_CMP_MASK 0x0fffffffu
#define MCHP_WKTMR_CLK_DIV_MASK 0x7fffu
/* Sub-second interrupt select at +0x10 */
#define MCHP_WKTMR_SS_MASK 0x0fu
#define MCHP_WKTMR_SS_RATE_DIS 0x00u
#define MCHP_WKTMR_SS_RATE_2HZ 0x01u
#define MCHP_WKTMR_SS_RATE_4HZ 0x02u
#define MCHP_WKTMR_SS_RATE_8HZ 0x03u
#define MCHP_WKTMR_SS_RATE_16HZ 0x04u
#define MCHP_WKTMR_SS_RATE_32HZ 0x05u
#define MCHP_WKTMR_SS_RATE_64HZ 0x06u
#define MCHP_WKTMR_SS_RATE_128HZ 0x07u
#define MCHP_WKTMR_SS_RATE_256HZ 0x08u
#define MCHP_WKTMR_SS_RATE_512HZ 0x09u
#define MCHP_WKTMR_SS_RATE_1024HZ 0x0au
#define MCHP_WKTMR_SS_RATE_2048HZ 0x0bu
#define MCHP_WKTMR_SS_RATE_4096HZ 0x0cu
#define MCHP_WKTMR_SS_RATE_8192HZ 0x0du
#define MCHP_WKTMR_SS_RATE_16384HZ 0x0eu
#define MCHP_WKTMR_SS_RATE_32768HZ 0x0fu
/* Sub-week control at +0x14 */
#define MCHP_WKTMR_SWKC_MASK 0x3f3u
#define MCHP_WKTMR_SWKC_PWRUP_EV_STS_POS 0ul
#define MCHP_WKTMR_SWKC_PWRUP_EV_STS_MASK \
BIT(MCHP_WKTMR_SWKC_PWRUP_EV_STS_POS)
#define MCHP_WKTMR_SWKC_PWRUP_EV_STS \
BIT(MCHP_WKTMR_SWKC_PWRUP_EV_STS_POS)
#define MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_POS 4
#define MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_MASK \
BIT(MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_POS)
#define MCHP_WKTMR_SWKC_SYSPWR_PRES_STS \
BIT(MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_POS)
#define MCHP_WKTMR_SWKC_SYSPWR_PRES_EN_POS 5
#define MCHP_WKTMR_SWKC_SYSPWR_PRES_EN_MASK \
BIT(MCHP_WKTMR_SWKC_SYSPWR_PRES_EN_POS)
#define MCHP_WKTMR_SWKC_SYSPWR_PRES_EN \
BIT(MCHP_WKTMR_SWKC_SYSPWR_PRES_EN_POS)
#define MCHP_WKTMR_SWKC_AUTO_RELOAD_POS 6
#define MCHP_WKTMR_SWKC_AUTO_RELOAD_MASK \
BIT(MCHP_WKTMR_SWKC_AUTO_RELOAD_POS)
#define MCHP_WKTMR_SWKC_AUTO_RELOAD \
BIT(MCHP_WKTMR_SWKC_AUTO_RELOAD_POS)
/* Sub-week alarm counter at +0x18 */
#define MCHP_WKTMR_SWAC_MASK 0x1ff01ffu
#define MCHP_WKTMR_SWAC_LOAD_POS 0
#define MCHP_WKTMR_SWAC_CNT_RO_POS 16
#define MCHP_WKTMR_SWAC_LOAD_MASK GENMASK(8, 0)
#define MCHP_WKTMR_SWAC_CNT_RO_MASK GENMASK(24, 16)
/* Week timer BGPO Data at +0x1c */
#define MCHP_WKTMR_BGPO_DATA_MASK GENMASK(5, 0)
/* Week timer BGPO Power at +0x20 */
#define MCHP_WKTMR_BGPO_PWR_MASK GENMASK(5, 0)
#define MCHP_WKTMR_BGPO_0_PWR_RO BIT(0)
/* Week timer BGPO Reset at +0x24 */
#define MCHP_WKTMR_BGPO_RST_MASK GENMASK(5, 0)
#define MCHP_WKTMR_BGPO_RST_VBAT(n) BIT(n)
/** @brief Week Timer (WKTMR) */
struct wktmr_regs {
volatile uint32_t CTRL;
volatile uint32_t ALARM_CNT;
volatile uint32_t TMR_CMP;
volatile uint32_t CLKDIV;
volatile uint32_t SUBSEC_ISEL;
volatile uint32_t SUBWK_CTRL;
volatile uint32_t SUBWK_ALARM_CNT;
volatile uint32_t BGPO_DATA;
volatile uint32_t BGPO_PWR;
volatile uint32_t BGPO_RST;
};
#endif /* #ifndef _MEC_TIMERS_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MEC_UART_H
#define _MEC_UART_H
#include <stdint.h>
#include <stddef.h>
#define MCHP_UART_RX_FIFO_MAX_LEN 16u
#define MCHP_UART_TX_FIFO_MAX_LEN 16u
#define MCHP_UART_BAUD_RATE_MIN 50u
#define MCHP_UART_BAUD_RATE_MAX 1500000u
#define MCHP_UART_SPACING 0x400u
/*
* LCR DLAB=0
* Transmit buffer(WO), Receive buffer(RO)
* LCR DLAB=1, BAUD rate divisor LSB
*/
#define MCHP_UART_RTXB_OFS 0u
#define MCHP_UART_BRGD_LSB_OFS 0u
/*
* LCR DLAB=0
* Interrupt Enable Register, R/W
* LCR DLAB=1, BAUD rate divisor MSB
*/
#define MCHP_UART_BRGD_MSB_OFS 1u
#define MCHP_UART_IER_OFS 1u
#define MCHP_UART_IER_MASK 0x0fu
#define MCHP_UART_IER_ERDAI 0x01u /* Received data available and timeouts */
#define MCHP_UART_IER_ETHREI 0x02u /* TX Holding register empty */
#define MCHP_UART_IER_ELSI 0x04u /* Errors: Overrun, Parity, Framing, and Break */
#define MCHP_UART_IER_EMSI 0x08u /* Modem Status */
#define MCHP_UART_IER_ALL 0x0fu
/* FIFO Control Register, Write-Only */
#define MCHP_UART_FCR_OFS 2u
#define MCHP_UART_FCR_MASK 0xcfu
#define MCHP_UART_FCR_EXRF 0x01u /* Enable TX & RX FIFO's */
#define MCHP_UART_FCR_CLR_RX_FIFO 0x02u /* Clear RX FIFO, bit is self-clearing */
#define MCHP_UART_FCR_CLR_TX_FIFO 0x04u /* Clear TX FIFO, bit is self-clearing */
#define MCHP_UART_FCR_DMA_EN 0x08u /* DMA Mode Enable. Not implemented */
#define MCHP_UART_FCR_RX_FIFO_LVL_MASK 0xc0u /* RX FIFO trigger level mask */
#define MCHP_UART_FCR_RX_FIFO_LVL_1 0x00u
#define MCHP_UART_FCR_RX_FIFO_LVL_4 0x40u
#define MCHP_UART_FCR_RX_FIFO_LVL_8 0x80u
#define MCHP_UART_FCR_RX_FIFO_LVL_14 0xc0u
/* Interrupt Identification Register, Read-Only */
#define MCHP_UART_IIR_OFS 2u
#define MCHP_UART_IIR_MASK 0xcfu
#define MCHP_UART_IIR_NOT_IPEND 0x01u
#define MCHP_UART_IIR_INTID_MASK0 0x07u
#define MCHP_UART_IIR_INTID_POS 1u
#define MCHP_UART_IIR_INTID_MASK 0x0eu
#define MCHP_UART_IIR_FIFO_EN_MASK 0xc0u
/*
* interrupt values
* Highest priority: Line status, overrun, framing, or break
* Highest-1. RX data available or RX FIFO trigger level reached
* Highest-2. RX timeout
* Highest-3. TX Holding register empty
* Highest-4. MODEM status
*/
#define MCHP_UART_IIR_INT_NONE 0x01u
#define MCHP_UART_IIR_INT_LS 0x06u
#define MCHP_UART_IIR_INT_RX 0x04u
#define MCHP_UART_IIR_INT_RX_TMOUT 0x0cu
#define MCHP_UART_IIR_INT_THRE 0x02u
#define MCHP_UART_IIR_INT_MS 0x00u
/* Line Control Register R/W */
#define MCHP_UART_LCR_OFS 3u
#define MCHP_UART_LCR_WORD_LEN_MASK 0x03u
#define MCHP_UART_LCR_WORD_LEN_5 0x00u
#define MCHP_UART_LCR_WORD_LEN_6 0x01u
#define MCHP_UART_LCR_WORD_LEN_7 0x02u
#define MCHP_UART_LCR_WORD_LEN_8 0x03u
#define MCHP_UART_LCR_STOP_BIT_1 0x00u
#define MCHP_UART_LCR_STOP_BIT_2 0x04u
#define MCHP_UART_LCR_PARITY_NONE 0x00u
#define MCHP_UART_LCR_PARITY_EN 0x08u
#define MCHP_UART_LCR_PARITY_ODD 0x00u
#define MCHP_UART_LCR_PARITY_EVEN 0x10u
#define MCHP_UART_LCR_STICK_PARITY 0x20u
#define MCHP_UART_LCR_BREAK_EN 0x40u
#define MCHP_UART_LCR_DLAB_EN 0x80u
/* MODEM Control Register R/W */
#define MCHP_UART_MCR_OFS 4u
#define MCHP_UART_MCR_MASK 0x1fu
#define MCHP_UART_MCR_DTRn 0x01u
#define MCHP_UART_MCR_RTSn 0x02u
#define MCHP_UART_MCR_OUT1 0x04u
#define MCHP_UART_MCR_OUT2 0x08u
#define MCHP_UART_MCR_LOOPBCK_EN 0x10u
/* Line Status Register RO */
#define MCHP_UART_LSR_OFS 5u
#define MCHP_UART_LSR_DATA_RDY 0x01u
#define MCHP_UART_LSR_OVERRUN 0x02u
#define MCHP_UART_LSR_PARITY 0x04u
#define MCHP_UART_LSR_FRAME 0x08u
#define MCHP_UART_LSR_RX_BREAK 0x10u
#define MCHP_UART_LSR_THRE 0x20u
#define MCHP_UART_LSR_TEMT 0x40u
#define MCHP_UART_LSR_FIFO_ERR 0x80u
#define MCHP_UART_LSR_ANY 0xffu
/* MODEM Status Register RO */
#define MCHP_UART_MSR_OFS 6u
#define MCHP_UART_MSR_DCTS 0x01u
#define MCHP_UART_MSR_DDSR 0x02u
#define MCHP_UART_MSR_TERI 0x04u
#define MCHP_UART_MSR_DDCD 0x08u
#define MCHP_UART_MSR_CTS 0x10u
#define MCHP_UART_MSR_DSR 0x20u
#define MCHP_UART_MSR_RI 0x40u
#define MCHP_UART_MSR_DCD 0x80u
/* Scratch Register RO */
#define MCHP_UART_SCR_OFS 7u
/* UART Logical Device Activate Register */
#define MCHP_UART_LD_ACT_OFS 0x330u
#define MCHP_UART_LD_ACTIVATE 0x01u
/* UART Logical Device Config Register */
#define MCHP_UART_LD_CFG_OFS 0x3f0u
#define MCHP_UART_LD_CFG_INTCLK 0u
#define MCHP_UART_LD_CFG_NO_INVERT 0u
#define MCHP_UART_LD_CFG_RESET_SYS 0u
#define MCHP_UART_LD_CFG_EXTCLK BIT(0)
#define MCHP_UART_LD_CFG_RESET_VCC BIT(1)
#define MCHP_UART_LD_CFG_INVERT BIT(2)
/* BAUD rate generator */
#define MCHP_UART_INT_CLK_24M BIT(15)
/* 1.8MHz internal clock source */
#define MCHP_UART_1P8M_BAUD_50 2304u
#define MCHP_UART_1P8M_BAUD_110 1536u
#define MCHP_UART_1P8M_BAUD_150 768u
#define MCHP_UART_1P8M_BAUD_300 384u
#define MCHP_UART_1P8M_BAUD_1200 96u
#define MCHP_UART_1P8M_BAUD_2400 48u
#define MCHP_UART_1P8M_BAUD_9600 12u
#define MCHP_UART_1P8M_BAUD_19200 6u
#define MCHP_UART_1P8M_BAUD_38400 3u
#define MCHP_UART_1P8M_BAUD_57600 2u
#define MCHP_UART_1P8M_BAUD_115200 1u
/* 24MHz internal clock source. n = 24e6 / (BAUD * 16) = 1500000 / BAUD */
#define MCHP_UART_24M_BAUD_115200 ((13u) + (MCHP_UART_INT_CLK_24M))
#define MCHP_UART_24M_BAUD_57600 ((26u) + (MCHP_UART_INT_CLK_24M))
/** @brief 16550 compatible UART. Size = 1012(0x3f4) */
struct uart_regs {
volatile uint8_t RTXB;
volatile uint8_t IER;
volatile uint8_t IIR_FCR;
volatile uint8_t LCR;
volatile uint8_t MCR;
volatile uint8_t LSR;
volatile uint8_t MSR;
volatile uint8_t SCR;
uint8_t RSVDA[0x330 - 0x08];
volatile uint8_t ACTV;
uint8_t RSVDB[0x3f0 - 0x331];
volatile uint8_t CFG_SEL;
};
#endif /* #ifndef _MEC_MCHP_UART_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MEC_VCI_H
#define _MEC_VCI_H
#include <stdint.h>
#include <stddef.h>
/* VCI Config register */
#define MCHP_VCI_CFG_REG_OFS 0u
#define MCHP_VCI_CFG_REG_MASK 0x71f8fu
#define MCHP_VCI_CFG_IN_MASK 0x7fu
#define MCHP_VCI_CFG_IN0_HI 0x01u
#define MCHP_VCI_CFG_IN1_HI 0x02u
#define MCHP_VCI_CFG_IN2_HI 0x04u
#define MCHP_VCI_CFG_IN3_HI 0x08u
#define MCHP_VCI_CFG_IN4_HI 0x10u
#define MCHP_VCI_VCI_OVRD_IN_HI BIT(8)
#define MCHP_VCI_VCI_OUT_HI BIT(9)
#define MCHP_VCI_FW_CTRL_EN BIT(10)
#define MCHP_VCI_FW_EXT_SEL BIT(11)
#define MCHP_VCI_FILTER_BYPASS BIT(12)
#define MCHP_VCI_WEEK_ALARM BIT(16)
#define MCHP_VCI_RTC_ALARM BIT(17)
#define MCHP_VCI_SYS_PWR_PRES BIT(18)
/* VCI Latch Enable register */
/* VCI Latch Reset register */
#define MCHP_VCI_LE_REG_OFS 4u
#define MCHP_VCI_LR_REG_OFS 8u
#define MCHP_VCI_LER_REG_MASK 0x3007fu
#define MCHP_VCI_LER_IN_MASK 0x7fu
#define MCHP_VCI_LER_IN0 0x01u
#define MCHP_VCI_LER_IN1 0x02u
#define MCHP_VCI_LER_IN2 0x04u
#define MCHP_VCI_LER_IN3 0x08u
#define MCHP_VCI_LER_IN4 0x10u
#define MCHP_VCI_LER_WEEK_ALARM BIT(16)
#define MCHP_VCI_LER_RTC_ALARM BIT(17)
/* VCI Input Enable register */
#define MCHP_VCI_INPUT_EN_REG_OFS 0x0cu
#define MCHP_VCI_INPUT_EN_REG_MASK 0x7fu
#define MCHP_VCI_INPUT_EN_IE_MASK 0x7fu
#define MCHP_VCI_INPUT_EN_IN0 0x01u
#define MCHP_VCI_INPUT_EN_IN1 0x02u
#define MCHP_VCI_INPUT_EN_IN2 0x04u
#define MCHP_VCI_INPUT_EN_IN3 0x08u
#define MCHP_VCI_INPUT_EN_IN4 0x10u
/* VCI Hold Off Count register */
#define MCHP_VCI_HDO_REG_OFS 0x10u
#define MCHP_VCI_HDO_REG_MASK 0xffu
/* VCI Polarity register */
#define MCHP_VCI_POL_REG_OFS 0x14u
#define MCHP_VCI_POL_REG_MASK 0x7fu
#define MCHP_VCI_POL_IE30_MASK 0x0Fu
#define MCHP_VCI_POL_ACT_HI_IN0 0x01u
#define MCHP_VCI_POL_ACT_HI_IN1 0x02u
#define MCHP_VCI_POL_ACT_HI_IN2 0x04u
#define MCHP_VCI_POL_ACT_HI_IN3 0x08u
#define MCHP_VCI_POL_ACT_HI_IN4 0x10u
/* VCI Positive Edge Detect register */
#define MCHP_VCI_PDET_REG_OFS 0x18u
#define MCHP_VCI_PDET_REG_MASK 0x7fu
#define MCHP_VCI_PDET_IN0 0x01u
#define MCHP_VCI_PDET_IN1 0x02u
#define MCHP_VCI_PDET_IN2 0x04u
#define MCHP_VCI_PDET_IN3 0x08u
#define MCHP_VCI_PDET_IN4 0x10u
/* VCI Positive Edge Detect register */
#define MCHP_VCI_NDET_REG_OFS 0x1cu
#define MCHP_VCI_NDET_REG_MASK 0x7fu
#define MCHP_VCI_NDET_IN0 0x01u
#define MCHP_VCI_NDET_IN1 0x02u
#define MCHP_VCI_NDET_IN2 0x04u
#define MCHP_VCI_NDET_IN3 0x08u
#define MCHP_VCI_NDET_IN4 0x10u
/* VCI Buffer Enable register */
#define MCHP_VCI_BEN_REG_OFS 0x20u
#define MCHP_VCI_BEN_REG_MASK 0x7fu
#define MCHP_VCI_BEN_IE30_MASK 0x0fu
#define MCHP_VCI_BEN_IN0 0x01u
#define MCHP_VCI_BEN_IN1 0x02u
#define MCHP_VCI_BEN_IN2 0x04u
#define MCHP_VCI_BEN_IN3 0x08u
#define MCHP_VCI_BEN_IN4 0x10u
/** @brief VBAT powered control interface (VCI) */
struct vci_regs {
volatile uint32_t CONFIG;
volatile uint32_t LATCH_EN;
volatile uint32_t LATCH_RST;
volatile uint32_t INPUT_EN;
volatile uint32_t HOLD_OFF;
volatile uint32_t POLARITY;
volatile uint32_t PEDGE_DET;
volatile uint32_t NEDGE_DET;
volatile uint32_t BUFFER_EN;
};
#endif /* #ifndef _MEC_VCI_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MEC_WDT_H
#define _MEC_WDT_H
#include <stdint.h>
#include <stddef.h>
/* Load register */
#define MCHP_WDT_LOAD_REG_OFS 0x00u
#define MCHP_WDT_LOAD_REG_MASK 0xffffu
/* Control register */
#define MCHP_WDT_CTRL_REG_OFS 0x04u
#define MCHP_WDT_CTRL_REG_MASK 0x021du
#define MCHP_WDT_CTRL_EN_POS 0u
#define MCHP_WDT_CTRL_EN_MASK BIT(MCHP_WDT_CTRL_EN_POS)
#define MCHP_WDT_CTRL_EN BIT(MCHP_WDT_CTRL_EN_POS)
#define MCHP_WDT_CTRL_HTMR_STALL_POS 2u
#define MCHP_WDT_CTRL_HTMR_STALL_MASK BIT(MCHP_WDT_CTRL_HTMR_STALL_POS)
#define MCHP_WDT_CTRL_HTMR_STALL_EN BIT(MCHP_WDT_CTRL_HTMR_STALL_POS)
#define MCHP_WDT_CTRL_WKTMR_STALL_POS 3u
#define MCHP_WDT_CTRL_WKTMR_STALL_MASK BIT(MCHP_WDT_CTRL_WKTMR_STALL_POS)
#define MCHP_WDT_CTRL_WKTMR_STALL_EN BIT(MCHP_WDT_CTRL_WKTMR_STALL_POS)
#define MCHP_WDT_CTRL_JTAG_STALL_POS 4u
#define MCHP_WDT_CTRL_JTAG_STALL_MASK BIT(MCHP_WDT_CTRL_JTAG_STALL_POS)
#define MCHP_WDT_CTRL_JTAG_STALL_EN BIT(MCHP_WDT_CTRL_JTAG_STALL_POS)
/*
* WDT mode selecting action taken upon count expiration.
* 0 = Generate chip reset
* 1 = Clear this bit,
* Set event status
* Generate interrupt if event IEN bit is set
* Kick WDT causing it to reload from LOAD register
* If interrupt is enabled in GIRQ21 and NVIC then the EC will jump
* to the WDT ISR.
*/
#define MCHP_WDT_CTRL_MODE_POS 9u
#define MCHP_WDT_CTRL_MODE_MASK BIT(MCHP_WDT_CTRL_MODE_POS)
#define MCHP_WDT_CTRL_MODE_RESET 0u
#define MCHP_WDT_CTRL_MODE_IRQ BIT(MCHP_WDT_CTRL_MODE_POS)
/* WDT Kick register. Write any value to reload counter */
#define MCHP_WDT_KICK_REG_OFS 0x08u
#define MCHP_WDT_KICK_REG_MASK 0xffu
#define MCHP_WDT_KICK_VAL 0
/* WDT Count register. Read only */
#define MCHP_WDT_CNT_RO_REG_OFS 0x0cu
#define MCHP_WDT_CNT_RO_REG_MASK 0xffffu
/* Status Register */
#define MCHP_WDT_STS_REG_OFS 0x10u
#define MCHP_WDT_STS_REG_MASK 0x01u
#define MCHP_WDT_STS_EVENT_IRQ_POS 0u
#define MCHP_WDT_STS_EVENT_IRQ BIT(MCHP_WDT_STS_EVENT_IRQ_POS)
/* Interrupt Enable Register */
#define MCHP_WDT_IEN_REG_OFS 0x14u
#define MCHP_WDT_IEN_REG_MASK 0x01u
#define MCHP_WDT_IEN_EVENT_IRQ_POS 0u
#define MCHP_WDT_IEN_EVENT_IRQ_MASK BIT(MCHP_WDT_IEN_EVENT_IRQ_POS)
#define MCHP_WDT_IEN_EVENT_IRQ_EN BIT(MCHP_WDT_IEN_EVENT_IRQ_POS)
/** @brief Watchdog timer. Size = 24(0x18) */
struct wdt_regs {
volatile uint16_t LOAD;
uint8_t RSVD1[2];
volatile uint16_t CTRL;
uint8_t RSVD2[2];
volatile uint8_t KICK;
uint8_t RSVD3[3];
volatile uint16_t CNT;
uint8_t RSVD4[2];
volatile uint16_t STS;
uint8_t RSVD5[2];
volatile uint8_t IEN;
};
#endif /* #ifndef _MEC_WDT_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc. All Rights Reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MICROCHIP_XEC_SOC_DT_H_
#define _MICROCHIP_XEC_SOC_DT_H_
#include <zephyr/devicetree.h>
#define MCHP_XEC_PIN_FEAT_EN 0x1
#define MCHP_XEC_NO_PULL 0x1
#define MCHP_XEC_PULL_UP 0x1
#define MCHP_XEC_PULL_DOWN 0x1
#define MCHP_XEC_PUSH_PULL 0x1
#define MCHP_XEC_OPEN_DRAIN 0x1
#define MCHP_XEC_OUT_DIS 0x1
#define MCHP_XEC_OUT_EN 0x1
#define MCHP_XEC_OUT_DRV_LOW 0x1
#define MCHP_XEC_OUT_DRV_HIGH 0x1
#define MCHP_XEC_DRVSTR_NONE 0x0
#define MCHP_XEC_DRVSTR_2MA 0x1
#define MCHP_XEC_DRVSTR_4MA 0x2
#define MCHP_XEC_DRVSTR_8MA 0x3
#define MCHP_XEC_DRVSTR_12MA 0x4
#define MCHP_XEC_FUNC_INVERT 0x1
#define MCHP_XEC_PIN_INPUT_DIS 0x1
#define MCHP_DT_ESPI_VW_FLAG_STATUS_POS 0
#define MCHP_DT_ESPI_VW_FLAG_DIR_POS 1
#define MCHP_DT_ESPI_VW_FLAG_RST_STATE_POS 2
#define MCHP_DT_ESPI_VW_FLAG_RST_STATE_MSK0 0x3
#define MCHP_DT_ESPI_VW_FLAG_RST_SRC_POS 4
#define MCHP_DT_ESPI_VW_FLAG_RST_SRC_MSK0 0x7
#define MCHP_DT_NODE_FROM_VWTABLE(name) DT_CHILD(DT_PATH(mchp_xec_espi_vw_routing), name)
#define MCHP_DT_VW_NODE_HAS_STATUS(name) DT_NODE_HAS_STATUS(MCHP_DT_NODE_FROM_VWTABLE(name), okay)
/* Macro to store eSPI virtual wire DT flags
* b[0] = DT status property 0 is disabled, 1 enabled,
* b[1] = VW direction 0(EC target to host controller), 1(host controller to EC target)
* b[3:2] = default virtual wire state 0(HW default), 1(low), 2(high)
* b[6:4] = virtual wire state reset event:
* 0(HW default), 1(ESPI_RESET), 2(RESET_SYS), 3(RESET_SIO), 4(PLTRST)
*/
#define MCHP_DT_ESPI_VW_FLAGS(vw) \
((uint8_t)(MCHP_DT_VW_NODE_HAS_STATUS(vw)) & 0x01U) | \
((((uint8_t)DT_PROP_BY_IDX(MCHP_DT_NODE_FROM_VWTABLE(vw), vw_reg, 1)) & 0x1) << 1) | \
((((uint8_t)DT_ENUM_IDX_OR(MCHP_DT_NODE_FROM_VWTABLE(vw), reset_state, 0)) & 0x3) << 2) | \
((((uint8_t)DT_ENUM_IDX_OR(MCHP_DT_NODE_FROM_VWTABLE(vw), reset_source, 0)) & 0x7) << 4)
/* Macro for the eSPI driver VW table entries.
* e is a symbol from enum espi_vwire_signal.
* vw is a node from the XEC ESPI VW routing file.
*/
#define MCHP_DT_ESPI_VW_ENTRY(e, vw) \
[(e)] = { \
.host_idx = DT_PROP_BY_IDX(MCHP_DT_NODE_FROM_VWTABLE(vw), vw_reg, 0), \
.bit = DT_PROP_BY_IDX(MCHP_DT_NODE_FROM_VWTABLE(vw), vw_reg, 3), \
.xec_reg_idx = DT_PROP_BY_IDX(MCHP_DT_NODE_FROM_VWTABLE(vw), vw_reg, 2), \
.flags = MCHP_DT_ESPI_VW_FLAGS(vw), \
}
#endif /* _MICROCHIP_XEC_SOC_DT_H_ */

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/*
* Copyright (c) 2019 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_ESPI_CHANNELS_H_
#define _SOC_ESPI_CHANNELS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* Channel 0 - Peripheral Channel */
/* 8042 event data */
#define E8042_ISR_DATA_POS 8U
#define E8042_ISR_CMD_DATA_POS 0U
#ifdef __cplusplus
}
#endif
#endif /* _SOC_ESPI_CHANNELS_H_ */

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/*
* Copyright (c) 2019 Intel Corporation
* SPDX-License-Identifier: Apache-2.0
*/
/** @file
* @brief Microchip XEC MCU family General Purpose Input Output (GPIO) defines.
*
*/
#ifndef _MICROCHIP_MEC_SOC_GPIO_H_
#define _MICROCHIP_MEC_SOC_GPIO_H_
#define MCHP_GPIO_000_036 0
#define MCHP_GPIO_040_076 1
#define MCHP_GPIO_100_136 2
#define MCHP_GPIO_140_176 3
#define MCHP_GPIO_200_236 4
#define MCHP_GPIO_240_276 5
#define MCHP_GPIO_MAX_PORT 6
#define MCHP_NUM_GPIO_PORTS 6
#endif /* _MICROCHIP_MEC_SOC_GPIO_H_ */

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/*
* Copyright (c) 2021 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/sys/__assert.h>
#include <soc.h>
#include "soc_i2c.h"
/* pinctrl Node contains the base address of the GPIO Control Registers */
#define MCHP_XEC_GPIO_REG_BASE ((struct gpio_regs *)DT_REG_ADDR(DT_NODELABEL(pinctrl)))
/* Too many MEC1501 HAL bugs */
#ifndef MEC_I2C_PORT_MASK
#define MEC_I2C_PORT_MASK 0xFFFFU
#endif
/* encode GPIO pin number and alternate function for an I2C port */
struct mec_i2c_port {
uint8_t scl_pin_no;
uint8_t scl_func;
uint8_t sda_pin_no;
uint8_t sda_func;
};
/*
* indexed by port number: all on VTR1 except as commented
* NOTE: MCHP MECxxxx data sheets specify GPIO pin numbers in octal.
* TODO: MEC15xx and MEC172x handle ports with alternate pins.
*/
static const struct mec_i2c_port mec_i2c_ports[] = {
#if defined(CONFIG_SOC_SERIES_MEC172X) || defined(CONFIG_SOC_SERIES_MEC15XX)
{ 0004, 1, 0003, 1 },
{ 0131, 1, 0130, 1 }, /* VTR2. ALT on eSPI VTR3 {0073, 2, 0072, 2} */
{ 0155, 1, 0154, 1 },
{ 0010, 1, 0007, 1 },
{ 0144, 1, 0143, 1 },
{ 0142, 1, 0141, 1 },
{ 0140, 1, 0132, 1 },
{ 0013, 1, 0012, 1 }, /* VTR2. ALT { 0024, 3, 0152, 3 } VTR1 */
#if defined(CONFIG_SOC_SERIES_MEC172X)
{ 0230, 1, 0231, 1 }, /* VTR2 176 pin only */
#else
{ 0212, 1, 0211, 1 }, /* VTR1 MEC1523 SZ and 3Y only */
#endif
{ 0146, 1, 0145, 1 },
{ 0107, 3, 0030, 2 },
{ 0062, 2, 0000, 3 }, /* SCL on VTR1, SDA on VBAT. ALT 176 pin only */
{ 0027, 3, 0026, 3 },
{ 0065, 2, 0066, 2 }, /* VTR3 */
{ 0071, 2, 0070, 2 }, /* VTR3 */
{ 0150, 1, 0147, 1 }
#endif
};
/*
* Read pin states of specified I2C port.
* We GPIO control register always active RO pad input bit.
* lines b[0]=SCL pin state at pad, b[1]=SDA pin state at pad
*/
int soc_i2c_port_lines_get(uint8_t port, uint32_t *lines)
{
struct gpio_regs *regs = MCHP_XEC_GPIO_REG_BASE;
uint32_t idx_scl = 0;
uint32_t idx_sda = 0;
uint32_t pinval = 0;
if (!(BIT(port) & MEC_I2C_PORT_MASK) || !lines) {
return -EINVAL;
}
idx_scl = (uint32_t)mec_i2c_ports[port].scl_pin_no;
idx_sda = (uint32_t)mec_i2c_ports[port].sda_pin_no;
if ((idx_scl == 0xFF) || (idx_sda == 0xFF)) {
return -EINVAL;
}
if (regs->CTRL[idx_scl] & BIT(MCHP_GPIO_CTRL_INPAD_VAL_POS)) {
pinval |= BIT(SOC_I2C_SCL_POS);
}
if (regs->CTRL[idx_sda] & BIT(MCHP_GPIO_CTRL_INPAD_VAL_POS)) {
pinval |= BIT(SOC_I2C_SDA_POS);
}
*lines = pinval;
return 0;
}

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/*
* Copyright (c) 2021 Microchip Technology Inc.
* SPDX-License-Identifier: Apache-2.0
*/
/** @file
* @brief Microchip XEC MCU family I2C port support.
*
*/
#ifndef _MICROCHIP_MEC_SOC_I2C_H_
#define _MICROCHIP_MEC_SOC_I2C_H_
/* 144-pin package I2C port masks */
#if defined(CONFIG_SOC_MEC172X_NSZ)
#define MEC_I2C_PORT_MASK 0xFEFFU
#elif defined(CONFIG_SOC_MEC1501_HSZ)
#define MEC_I2C_PORT_MASK 0xFEFFU
#endif
#define MCHP_I2C_PORT_0 0
#define MCHP_I2C_PORT_1 1
#define MCHP_I2C_PORT_2 2
#define MCHP_I2C_PORT_3 3
#define MCHP_I2C_PORT_4 4
#define MCHP_I2C_PORT_5 5
#define MCHP_I2C_PORT_6 6
#define MCHP_I2C_PORT_7 7
#define MCHP_I2C_PORT_8 8
#define MCHP_I2C_PORT_9 9
#define MCHP_I2C_PORT_10 10
#define MCHP_I2C_PORT_11 11
#define MCHP_I2C_PORT_12 12
#define MCHP_I2C_PORT_13 13
#define MCHP_I2C_PORT_14 14
#define MCHP_I2C_PORT_15 15
#define MCHP_I2C_PORT_MAX 16
/*
* Read pin states of specified I2C port.
* We GPIO control register always active RO pad input bit.
* lines b[0]=SCL pin state at pad, b[1]=SDA pin state at pad
* Returns 0 success or -EINVAL if port is not support or lines is NULL.
*/
#define SOC_I2C_SCL_POS 0
#define SOC_I2C_SDA_POS 1
int soc_i2c_port_lines_get(uint8_t port, uint32_t *lines);
#endif /* _MICROCHIP_MEC_SOC_I2C_H_ */

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/*
* Copyright (c) 2021 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_MCHP_PCR_H_
#define _SOC_MCHP_PCR_H_
#ifdef __cplusplus
extern "C" {
#endif
/* slp_idx = [0, 4], bitpos = [0, 31] refer above */
#define MCHP_XEC_PCR_SCR_ENCODE(slp_idx, bitpos, domain) \
((((uint32_t)(domain) & 0xff) << 24) | (((bitpos) & 0x1f) << 3) \
| ((uint32_t)(slp_idx) & 0x7))
#define MCHP_XEC_PCR_SCR_GET_IDX(e) ((e) & 0x7u)
#define MCHP_XEC_PCR_SCR_GET_BITPOS(e) (((e) & 0xf8u) >> 3)
/* cpu clock divider */
#define MCHP_XEC_CLK_CPU_MASK GENMASK(7, 0)
#define MCHP_XEC_CLK_CPU_CLK_DIV_1 1u
#define MCHP_XEC_CLK_CPU_CLK_DIV_2 2u
#define MCHP_XEC_CLK_CPU_CLK_DIV_4 4u
#define MCHP_XEC_CLK_CPU_CLK_DIV_8 8u
#define MCHP_XEC_CLK_CPU_CLK_DIV_16 16u
#define MCHP_XEC_CLK_CPU_CLK_DIV_48 48u
/* slow clock divider */
#define MCHP_XEC_CLK_SLOW_MASK GENMASK(8, 0)
#define MCHP_XEC_CLK_SLOW_CLK_DIV_100K 480u
#define MCHP_XEC_CLK_SRC_POS 24
#define MCHP_XEC_CLK_SRC_MASK GENMASK(31, 24)
#define MCHP_XEC_CLK_SRC_GET(n) \
(((n) & MCHP_XEC_CLK_SRC_MASK) >> MCHP_XEC_CLK_SRC_POS)
#define MCHP_XEC_CLK_SRC_SET(v, c) (((v) & ~MCHP_XEC_CLK_SRC_MASK) |\
(((c) << MCHP_XEC_CLK_SRC_POS) & MCHP_XEC_CLK_SRC_MASK))
/*
* b[31:24] = clock source
* b[23:0] = clock source specific format
*/
struct mchp_xec_pcr_clk_ctrl {
uint32_t pcr_info;
};
#ifdef __cplusplus
}
#endif
#endif /* _SOC_MCHP_PCR_H_ */

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/*
* Copyright (c) 2019 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_MCHP_GPIOS_H_
#define _SOC_MCHP_GPIOS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* Begin Port A */
#define MCHP_GPIO_000 (0U)
#define MCHP_GPIO_001 (1U)
#define MCHP_GPIO_002 (2U)
#define MCHP_GPIO_003 (3U)
#define MCHP_GPIO_004 (4U)
#define MCHP_GPIO_005 (5U)
#define MCHP_GPIO_006 (6U)
#define MCHP_GPIO_007 (7U)
#define MCHP_GPIO_010 (8U)
#define MCHP_GPIO_011 (9U)
#define MCHP_GPIO_012 (10U)
#define MCHP_GPIO_013 (11U)
#define MCHP_GPIO_014 (12U)
#define MCHP_GPIO_015 (13U)
#define MCHP_GPIO_016 (14U)
#define MCHP_GPIO_017 (15U)
#define MCHP_GPIO_020 (16U)
#define MCHP_GPIO_021 (17U)
#define MCHP_GPIO_022 (18U)
#define MCHP_GPIO_023 (19U)
#define MCHP_GPIO_024 (20U)
#define MCHP_GPIO_025 (21U)
#define MCHP_GPIO_026 (22U)
#define MCHP_GPIO_027 (23U)
#define MCHP_GPIO_030 (24U)
#define MCHP_GPIO_031 (25U)
#define MCHP_GPIO_032 (26U)
#define MCHP_GPIO_033 (27U)
#define MCHP_GPIO_034 (28U)
#define MCHP_GPIO_035 (29U)
#define MCHP_GPIO_036 (30U)
/* End Port A */
/* Begin Port B */
#define MCHP_GPIO_040 (0U)
#define MCHP_GPIO_041 (1U)
#define MCHP_GPIO_042 (2U)
#define MCHP_GPIO_043 (3U)
#define MCHP_GPIO_044 (4U)
#define MCHP_GPIO_045 (5U)
#define MCHP_GPIO_046 (6U)
#define MCHP_GPIO_047 (7U)
#define MCHP_GPIO_050 (8U)
#define MCHP_GPIO_051 (9U)
#define MCHP_GPIO_052 (10U)
#define MCHP_GPIO_053 (11U)
#define MCHP_GPIO_054 (12U)
#define MCHP_GPIO_055 (13U)
#define MCHP_GPIO_056 (14U)
#define MCHP_GPIO_057 (15U)
#define MCHP_GPIO_060 (16U)
#define MCHP_GPIO_061 (17U)
#define MCHP_GPIO_062 (18U)
#define MCHP_GPIO_063 (19U)
#define MCHP_GPIO_064 (20U)
#define MCHP_GPIO_065 (21U)
#define MCHP_GPIO_066 (22U)
#define MCHP_GPIO_067 (23U)
#define MCHP_GPIO_070 (24U)
#define MCHP_GPIO_071 (25U)
#define MCHP_GPIO_072 (26U)
#define MCHP_GPIO_073 (27U)
#define MCHP_GPIO_074 (28U)
#define MCHP_GPIO_075 (29U)
#define MCHP_GPIO_076 (30U)
/* End Port B */
/* Begin Port C */
#define MCHP_GPIO_100 (0U)
#define MCHP_GPIO_101 (1U)
#define MCHP_GPIO_102 (2U)
#define MCHP_GPIO_103 (3U)
#define MCHP_GPIO_104 (4U)
#define MCHP_GPIO_105 (5U)
#define MCHP_GPIO_106 (6U)
#define MCHP_GPIO_107 (7U)
#define MCHP_GPIO_110 (8U)
#define MCHP_GPIO_111 (9U)
#define MCHP_GPIO_112 (10U)
#define MCHP_GPIO_113 (11U)
#define MCHP_GPIO_114 (12U)
#define MCHP_GPIO_115 (13U)
#define MCHP_GPIO_116 (14U)
#define MCHP_GPIO_117 (15U)
#define MCHP_GPIO_120 (16U)
#define MCHP_GPIO_121 (17U)
#define MCHP_GPIO_122 (18U)
#define MCHP_GPIO_123 (19U)
#define MCHP_GPIO_124 (20U)
#define MCHP_GPIO_125 (21U)
#define MCHP_GPIO_126 (22U)
#define MCHP_GPIO_127 (23U)
#define MCHP_GPIO_130 (24U)
#define MCHP_GPIO_131 (25U)
#define MCHP_GPIO_132 (26U)
#define MCHP_GPIO_133 (27U)
#define MCHP_GPIO_134 (28U)
#define MCHP_GPIO_135 (29U)
#define MCHP_GPIO_136 (30U)
/* End Port C */
/* Begin Port D */
#define MCHP_GPIO_140 (0U)
#define MCHP_GPIO_141 (1U)
#define MCHP_GPIO_142 (2U)
#define MCHP_GPIO_143 (3U)
#define MCHP_GPIO_144 (4U)
#define MCHP_GPIO_145 (5U)
#define MCHP_GPIO_146 (6U)
#define MCHP_GPIO_147 (7U)
#define MCHP_GPIO_150 (8U)
#define MCHP_GPIO_151 (9U)
#define MCHP_GPIO_152 (10U)
#define MCHP_GPIO_153 (11U)
#define MCHP_GPIO_154 (12U)
#define MCHP_GPIO_155 (13U)
#define MCHP_GPIO_156 (14U)
#define MCHP_GPIO_157 (15U)
#define MCHP_GPIO_160 (16U)
#define MCHP_GPIO_161 (17U)
#define MCHP_GPIO_162 (18U)
#define MCHP_GPIO_163 (19U)
#define MCHP_GPIO_164 (20U)
#define MCHP_GPIO_165 (21U)
#define MCHP_GPIO_166 (22U)
#define MCHP_GPIO_167 (23U)
#define MCHP_GPIO_170 (24U)
#define MCHP_GPIO_171 (25U)
#define MCHP_GPIO_172 (26U)
#define MCHP_GPIO_173 (27U)
#define MCHP_GPIO_174 (28U)
#define MCHP_GPIO_175 (29U)
#define MCHP_GPIO_176 (30U)
/* End Port D */
/* Begin Port E */
#define MCHP_GPIO_200 (0U)
#define MCHP_GPIO_201 (1U)
#define MCHP_GPIO_202 (2U)
#define MCHP_GPIO_203 (3U)
#define MCHP_GPIO_204 (4U)
#define MCHP_GPIO_205 (5U)
#define MCHP_GPIO_206 (6U)
#define MCHP_GPIO_207 (7U)
#define MCHP_GPIO_210 (8U)
#define MCHP_GPIO_211 (9U)
#define MCHP_GPIO_212 (10U)
#define MCHP_GPIO_213 (11U)
#define MCHP_GPIO_214 (12U)
#define MCHP_GPIO_215 (13U)
#define MCHP_GPIO_216 (14U)
#define MCHP_GPIO_217 (15U)
#define MCHP_GPIO_220 (16U)
#define MCHP_GPIO_221 (17U)
#define MCHP_GPIO_222 (18U)
#define MCHP_GPIO_223 (19U)
#define MCHP_GPIO_224 (20U)
#define MCHP_GPIO_225 (21U)
#define MCHP_GPIO_226 (22U)
#define MCHP_GPIO_227 (23U)
#define MCHP_GPIO_230 (24U)
#define MCHP_GPIO_231 (25U)
#define MCHP_GPIO_232 (26U)
#define MCHP_GPIO_233 (27U)
#define MCHP_GPIO_234 (28U)
#define MCHP_GPIO_235 (29U)
#define MCHP_GPIO_236 (30U)
/* End Port E */
/* Begin Port F */
#define MCHP_GPIO_240 (0U)
#define MCHP_GPIO_241 (1U)
#define MCHP_GPIO_242 (2U)
#define MCHP_GPIO_243 (3U)
#define MCHP_GPIO_244 (4U)
#define MCHP_GPIO_245 (5U)
#define MCHP_GPIO_246 (6U)
#define MCHP_GPIO_247 (7U)
#define MCHP_GPIO_250 (8U)
#define MCHP_GPIO_251 (9U)
#define MCHP_GPIO_252 (10U)
#define MCHP_GPIO_253 (11U)
#define MCHP_GPIO_254 (12U)
#define MCHP_GPIO_255 (13U)
/* End Port F */
#ifdef __cplusplus
}
#endif
#endif /* _SOC_MCHP_GPIOS_H_ */

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#!/usr/bin/env python3
# Copyright (c) 2022 Microchip Technology Inc.
# SPDX-License-Identifier: Apache-2.0
import sys
import argparse
import hashlib
verbose_mode = False
# Header parameters
HDR_SIZE = 0x140
HDR_VER_MEC172X = 0x03
HDR_VER_MEC152X = 0x02
HDR_SPI_CLK_12MHZ = 0x3
HDR_SPI_CLK_16MHZ = 0x2
HDR_SPI_CLK_24MHZ = 0x1
HDR_SPI_CLK_48MHZ = 0
HDR_SPI_DRV_STR_1X = 0
HDR_SPI_DRV_STR_2X = 0x4
HDR_SPI_DRV_STR_4X = 0x8
HDR_SPI_DRV_STR_6X = 0xc
HDR_SPI_SLEW_SLOW = 0
HDR_SPI_SLEW_FAST = 0x10
HDR_SPI_CPOL_LO = 0
HDR_SPI_CPOL_HI = 0x20
HDR_SPI_CHPHA_MOSI_EDGE_2 = 0
HDR_SPI_CHPHA_MOSI_EDGE_1 = 0x40
HDR_SPI_CHPHA_MISO_EDGE_1 = 0
HDR_SPI_CHPHA_MISO_EDGE_2 = 0x80
# User defined constants HDR_SPI_RD_ (0, 1, 2, 3) as per boot rom spec.
# 1st digit - number of I/O pins used to transmit the opcode
# 2nd digit - number of I/O pins used to transmit the SPI address
# 3rd digit - number of pins used to read data from flash
# 4th digit (if present) - dummy clocks between address and data phase
HDR_SPI_RD_111 = 0
HDR_SPI_RD_1118 = 1
HDR_SPI_RD_1128 = 2
HDR_SPI_RD_1148 = 3
# Payload parameters
PLD_LOAD_ADDR = 0xc0000
PLD_LOAD_ADDR_MEC172X = 0xc0000
PLD_LOAD_ADDR_MEC152X = 0xe0000
PLD_ENTRY_ADDR = 0
PLD_GRANULARITY = 128
PLD_PAD_SIZE = 128
PLD_PAD_BYTE = b'\xff'
MCHP_CHAR_P = 0x50
MCHP_CHAR_H = 0x48
MCHP_CHAR_C = 0x43
MCHP_CHAR_M = 0x4D
EC_INFO_BLOCK_SIZE = 128
ENCR_KEY_HDR_SIZE = 128
COSIG_SIZE = 96
TRAILER_SIZE = 160
TRAILER_PAD_BYTE = b'\xff'
TAG_SPI_LOC = 0
HDR_SPI_LOC = 0x100
PLD_SPI_LOC = 0x1000
CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15,
0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d]
CHIP_DICT = {
'mec15xx': { 'sram_base': 0xe0000, 'sram_size': 0x40000, 'header_ver': 2 },
'mec172x': { 'sram_base': 0xc0000, 'sram_size': 0x68000, 'header_ver': 3 },
}
CHIP_DEFAULT = 'mec172x'
SPI_READ_MODE_DEFAULT = 'fast'
SPI_FREQ_MHZ_DEFAULT = 12
SPI_MODE_DEFAULT = 0
SPI_MODE_MIN = 0
SPI_MODE_MAX = 7
SPI_DRIVE_STRENGTH_MULT_DEFAULT = "1x"
SPI_SLEW_RATE_DEFAULT = "slow"
def print_bytes(title, b):
"""Print bytes or bytearray as hex values"""
print("{0} = {{ ".format(title), end='')
count = 1
for v in b:
print("0x{0:02x}, ".format(v), end='')
if (count % 8) == 0:
print("")
count = count + 1
print("}")
def crc8(crc, data):
"""Update CRC8 value.
CRC8-ITU calculation
"""
for v in data:
crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)])
crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xf)])
return crc ^ 0x55
def build_tag(hdr_spi_loc):
"""Build MEC172x Boot-ROM TAG
MEC172x Boot-ROM TAG is 4 bytes
bits[23:0] = bits[31:8] of the Header SPI address
Header location must be a mutliple of 256 bytes
bits[31:24] = CRC8-ITU of bits[23:0]
return immutable bytes type
"""
tag = bytearray([(hdr_spi_loc >> 8) & 0xff,
(hdr_spi_loc >> 16) & 0xff,
(hdr_spi_loc >> 24) & 0xff])
tag.append(crc8(0, tag))
return bytes(tag)
def build_header(chip, spi_config, hdr_spi_loc, pld_spi_loc, pld_entry_addr, pld_len):
"""Build MEC152x/MEC172x Boot-ROM SPI image header
Args:
chip: mec15xx or mec172x
spi_config: spi configuration
hdr_spi_loc: Header location in SPI Image
pld_spi_loc: Payload(FW binary) location in SPI Image
pld_entry_addr: Payload load address in MEC172x SPI SRAM
Payload entry point address: index 0 instructs Boot-ROM to assume
ARM vector table at beginning of payload and reset handler
address is at offset 4 of payload.
pld_len: Payload length, must be multiple of PLD_GRANULARITY
return: immutable bytes type for built header
"""
hdr = bytearray(HDR_SIZE)
hdr[0] = MCHP_CHAR_P
hdr[1] = MCHP_CHAR_H
hdr[2] = MCHP_CHAR_C
hdr[3] = MCHP_CHAR_M
hdr[4] = CHIP_DICT[chip]['header_ver'] & 0xff
if spi_config['spi_freq_mhz'] == 48:
hdr[5] = HDR_SPI_CLK_48MHZ
elif spi_config['spi_freq_mhz'] == 24:
hdr[5] = HDR_SPI_CLK_24MHZ
elif spi_config['spi_freq_mhz'] == 16:
hdr[5] = HDR_SPI_CLK_16MHZ
else:
hdr[5] = HDR_SPI_CLK_12MHZ
if spi_config['spi_mode'] & 0x01:
hdr[5] |= HDR_SPI_CPOL_HI
if spi_config['spi_mode'] & 0x02:
hdr[5] |= HDR_SPI_CHPHA_MOSI_EDGE_1
if spi_config['spi_mode'] & 0x04:
hdr[5] |= HDR_SPI_CHPHA_MISO_EDGE_2
# translate 1x, 2x, 4x, 6x to 0, 1, 2, 3
if spi_config['spi_drive_str'] == "6x":
hdr[5] |= HDR_SPI_DRV_STR_6X
elif spi_config['spi_drive_str'] == "4x":
hdr[5] |= HDR_SPI_DRV_STR_4X
elif spi_config['spi_drive_str'] == "2x":
hdr[5] |= HDR_SPI_DRV_STR_2X
else:
hdr[5] |= HDR_SPI_DRV_STR_1X
# translate "slow", "fast" to 0, 1
if spi_config['spi_slew_rate'] == "fast":
hdr[5] |= HDR_SPI_SLEW_FAST
# MEC172x b[0]=0 do not allow 96MHz SPI clock
hdr[6] = 0 # not using authentication or encryption
if spi_config['spi_read_mode'] == 'quad':
hdr[7] = HDR_SPI_RD_1148
elif spi_config['spi_read_mode'] == 'dual':
hdr[7] = HDR_SPI_RD_1128
elif spi_config['spi_read_mode'] == 'normal':
hdr[7] = HDR_SPI_RD_111
else:
hdr[7] = HDR_SPI_RD_1118
# payload load address in SRAM
pld_load_addr = CHIP_DICT[chip]['sram_base']
hdr[8] = pld_load_addr & 0xff
hdr[9] = (pld_load_addr >> 8) & 0xff
hdr[0xA] = (pld_load_addr >> 16) & 0xff
hdr[0xB] = (pld_load_addr >> 24) & 0xff
# payload entry point address in SRAM
hdr[0xC] = pld_entry_addr & 0xff
hdr[0xD] = (pld_entry_addr >> 8) & 0xff
hdr[0xE] = (pld_entry_addr >> 16) & 0xff
hdr[0xF] = (pld_entry_addr >> 24) & 0xff
# payload size (16-bit) in granularity units
pld_units = pld_len // PLD_GRANULARITY
hdr[0x10] = pld_units & 0xff
hdr[0x11] = (pld_units >> 8) & 0xff
# hdr[0x12:0x13] = 0 reserved
# Unsigned offset from start of Header to start of FW Binary
# FW binary(payload) must always be located after header
pld_offset = pld_spi_loc - hdr_spi_loc
hdr[0x14] = pld_offset & 0xff
hdr[0x15] = (pld_offset >> 8) & 0xff
hdr[0x16] = (pld_offset >> 16) & 0xff
hdr[0x17] = (pld_offset >> 24) & 0xff
# hdr[0x18] = 0 not using authentication
# hdr[0x19] = 0 not adjusting SPI flash device drive strength
# hdr[0x1A through 0x1F] = 0 reserved
# hdr[0x20 through 0x27] = 0 not adjust SPI flash device drive strength
# hdr[0x28 through 0x47] = 0 reserved
# hdr[0x48 through 0x4F] = 0 reserved
# hdr[0x50 through 0x7F] = ECDSA P-384 Public key x-component
# hdr[0x80 through 0xAF] = ECDSA P-384 Public key y-component
# hdr[0xB0 through 0xDF] = SHA-384 digest of hdr[0 through 0xAF] Always required
# hdr[0xE0 through 0x10F] = ECDSA signature R-component of hdr[0 through 0xDF]
# hdr[0x110 through 0x13F] = ECDSA signature S-component of hdr[0 through 0xDF]
h = hashlib.sha384()
h.update(hdr[0:0xB0])
hdr_digest = h.digest()
if verbose_mode:
print_bytes("hdr_sha384_digest", hdr_digest)
hdr[0xB0:0xE0] = hdr_digest
return bytes(hdr)
def parse_args():
parser = argparse.ArgumentParser(allow_abbrev=False)
# Use a lambda to handle base 10 or base 16 (hex) input
parser.add_argument("-c",
type=str,
dest="chip",
choices = ["mec15xx", "mec172x"],
default="mec172x",
help="Chip name: mec172x(default) or mec15xx")
parser.add_argument("-i",
type=str,
dest="infilename",
default="zephyr.bin",
help="Input firmware binary file path/name (default: %(default)s)")
parser.add_argument("-o",
type=str,
dest="outfilename",
default="zephyr.mchp.bin",
help="Output SPI image file path/name (default: %(default)s)")
parser.add_argument("-s",
type=int,
dest="spi_size_kb",
default=256,
help="SPI image size in kilobytes (default: %(default)s)")
parser.add_argument("-e",
type=int,
dest="entry_point",
default=0,
help="FW entry point address Lookup in image (default: %(default)s)")
parser.add_argument("-f",
type=int,
dest="spi_freq_mhz",
choices = [12, 16, 24, 48],
default=12,
help="SPI frequency: 12, 16, 24, or 48 MHz")
parser.add_argument("-r",
type=str,
dest="spi_read_mode",
choices = ["normal", "fast", "dual", "quad"],
default="fast",
help="SPI read mode: normal, fast, dual or quad")
parser.add_argument("-m",
type=int,
dest="spi_mode",
choices = [0, 1, 2, 3, 4, 5, 6, 7],
default=0,
help="SPI signalling mode 3-bit field: 0-7")
parser.add_argument("--drvstr",
type=str,
dest="spi_drive_strength",
choices = ["1x", "2x", "4x", "6x"],
default="1x",
help="SPI pin driver strength multiplier encoded")
parser.add_argument("--slewrate",
type=str,
dest="spi_slew_rate",
choices = ["slow", "fast"],
default="slow",
help="SPI pins slew rate")
parser.add_argument("--fill",
dest="fill",
action='store_true',
help="Fill with 0xFF to flash size")
parser.add_argument("-v",
dest="verbose",
action='store_true',
help="Enable messages to console")
ret_args = parser.parse_args()
return ret_args
def main():
"""MEC SPI Gen"""
args = parse_args()
verbose_mode = args.verbose
if verbose_mode:
print("Command line arguments/defaults")
print(" chip = {0}".format(args.chip))
print(" infilename = {0}".format(args.infilename))
print(" outfilename = {0}".format(args.outfilename))
print(" SPI size (kilobytes) = {0}".format(args.spi_size_kb))
print(" Entry point address = {0}".format(args.entry_point))
print(" SPI frequency MHz = {0}".format(args.spi_freq_mhz))
print(" SPI Read Mode = {0}".format(args.spi_read_mode))
print(" SPI Signalling Mode = {0}".format(args.spi_mode))
print(" SPI drive strength = {0}".format(args.spi_drive_strength))
print(" SPI slew rate fast = {0}".format(args.spi_slew_rate))
print(" Verbose = {0}".format(args.verbose))
if args.infilename is None:
print("ERROR: Specify input binary file name with -i")
sys.exit(-1)
if args.outfilename is None:
print("ERROR: Specify output binary file name with -o")
sys.exit(-1)
chip = args.chip
spi_read_mode = args.spi_read_mode
spi_freq_mhz = args.spi_freq_mhz
spi_mode = args.spi_mode
spi_drive_str_mult = args.spi_drive_strength
spi_slew = args.spi_slew_rate
spi_size = args.spi_size_kb * 1024
indata = None
with open(args.infilename, "rb") as fin:
indata = fin.read()
indata_len = len(indata)
if verbose_mode:
print("Read input FW binary: length = {0}".format(indata_len))
# if necessary pad input data to PLD_GRANULARITY required by Boot-ROM loader
pad_len = 0
if (indata_len % PLD_GRANULARITY) != 0:
pad_len = PLD_GRANULARITY - (indata_len % PLD_GRANULARITY)
# NOTE: MCHP Production SPI Image Gen. pads with 0
padding = PLD_PAD_BYTE * pad_len
indata = indata + padding
indata_len += pad_len
if verbose_mode:
print("Padded FW binary: length = {0}".format(indata_len))
# Do we have enough space for 4KB block containing TAG and Header, padded FW binary,
# EC Info Block, Co-Sig Block, and Trailer?
mec_add_info_size = PLD_SPI_LOC + EC_INFO_BLOCK_SIZE + COSIG_SIZE + TRAILER_SIZE
if indata_len > (spi_size - mec_add_info_size):
print("ERROR: FW binary exceeds flash size! indata_len = {0} spi_size = {1}".format(indata_len, spi_size))
sys.exit(-1)
entry_point = args.entry_point
if args.entry_point == 0:
# Look up entry point in image
# Assumes Cortex-M4 vector table
# at beginning of image and second
# word in table is address of reset handler
entry_point = int.from_bytes(indata[4:8], byteorder="little")
tag = build_tag(HDR_SPI_LOC)
if verbose_mode:
print_bytes("TAG", tag)
print("Build Header at {0}: Load Address = 0x{1:0x} Entry Point Address = 0x{2:0x}".format(
HDR_SPI_LOC, PLD_LOAD_ADDR, entry_point))
spi_config_info = {
"spi_freq_mhz": spi_freq_mhz,
"spi_mode": spi_mode,
"spi_read_mode": spi_read_mode,
"spi_drive_str": spi_drive_str_mult,
"spi_slew_rate": spi_slew,
}
header = build_header(chip, spi_config_info, HDR_SPI_LOC, PLD_SPI_LOC, entry_point, indata_len)
if verbose_mode:
print_bytes("HEADER", header)
print("")
# appended to end of padded payload
ec_info_block = bytearray(EC_INFO_BLOCK_SIZE)
ec_info_loc = PLD_SPI_LOC + len(indata)
# appended to end of (padded payload + ec_info_block)
cosig = bytearray(b'\xff' * COSIG_SIZE)
cosig_loc = ec_info_loc + EC_INFO_BLOCK_SIZE
# appended to end of (padded payload + ec_info_block + cosig)
# trailer[0:0x30] = SHA384(indata || ec_info_block || cosig)
# trailer[0x30:] = 0xFF
trailer = bytearray(b'\xff' * TRAILER_SIZE)
trailer_loc = cosig_loc + COSIG_SIZE
h = hashlib.sha384()
h.update(indata)
h.update(ec_info_block)
h.update(cosig)
image_digest = h.digest()
trailer[0:len(image_digest)] = image_digest
if verbose_mode:
print("SHA-384 digest (paddedFW || ec_info_block || cosig)")
print_bytes("digest", image_digest)
spi_bufs = []
spi_bufs.append(("TAG", TAG_SPI_LOC, tag))
spi_bufs.append(("HEADER", HDR_SPI_LOC, header))
spi_bufs.append(("PAYLOAD", PLD_SPI_LOC, indata))
spi_bufs.append(("EC_INFO", ec_info_loc, ec_info_block))
spi_bufs.append(("COSIG", cosig_loc, cosig))
spi_bufs.append(("TRAILER", trailer_loc, trailer))
spi_bufs.sort(key=lambda x: x[1])
if verbose_mode:
i = 0
for sb in spi_bufs:
print("buf[{0}]: {1} location=0x{2:0x} length=0x{3:0x}".format(i, sb[0], sb[1], len(sb[2])))
print("")
fill = bytes(b'\xff' * 256)
if verbose_mode:
print("len(fill) = {0}".format(len(fill)))
loc = 0
with open(args.outfilename, "wb") as fout:
for sb in spi_bufs:
if verbose_mode:
print("sb: {0} location=0x{1:0x} len=0x{2:0x}".format(sb[0], sb[1], len(sb[2])))
if loc < sb[1]:
fill_len = sb[1] - loc
if verbose_mode:
print("loc = 0x{0:0x}: Fill with 0xFF len=0x{1:0x}".format(loc, fill_len))
nfill = fill_len // 256
rem = fill_len % 256
for _ in range(nfill):
fout.write(fill)
if rem > 0:
fout.write(fill[0:rem])
loc = loc + fill_len
if verbose_mode:
print("loc = 0x{0:0x}: write {1} len=0x{2:0x}".format(loc, sb[0], len(sb[2])))
fout.write(sb[2])
loc = loc + len(sb[2])
if args.fill and (loc < spi_size):
fill_len = spi_size - loc
nfill = fill_len // 256
rem = fill_len % 256
for _ in range(nfill):
fout.write(fill)
if rem > 0:
fout.write(fill[0:rem])
loc = loc + fill_len
if verbose_mode:
print("Final loc = 0x{0:0x}".format(loc))
if verbose_mode:
print("MEC SPI Gen done")
if __name__ == '__main__':
main()

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#
# Copyright (c) 2019, Microchip Technology Inc.
#
# SPDX-License-Identifier: Apache-2.0
#
zephyr_sources(soc.c)
zephyr_include_directories(.)
zephyr_sources_ifdef(CONFIG_PM
device_power.c
power.c
)
if(CONFIG_SOC_HAS_TIMING_FUNCTIONS AND NOT CONFIG_BOARD_HAS_TIMING_FUNCTIONS)
if(CONFIG_TIMING_FUNCTIONS)
# Use MEC15xx timing calculations only if DWT is not present
if(NOT CONFIG_CORTEX_M_DWT)
zephyr_library_sources(timing.c)
endif()
endif()
endif()
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

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# Microchip MEC1501 MCU core series
# Copyright (c) 2018 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_MEC15XX
select ARM
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ARM_MPU
select HAS_PM
config SOC_MEC1501_HSZ
select HAS_MEC_HAL
if SOC_SERIES_MEC15XX
config RTOS_TIMER
bool "MEC1501 RTOS timer"
config SOC_MEC1501_PROC_CLK_DIV
int "PROC_CLK_DIV"
default 1
range 1 48
help
This divisor defines a ratio between processor clock (HCLK)
and master clock (MCK):
HCLK = MCK / PROC_CLK_DIV
Allowed divider values: 1, 3, 4, 16, and 48.
config SOC_MEC1501_VTR3_1_8V
bool "VTR3 power rail is tied to 1.8V"
help
Set this is if VTR3 power sourcejumper in the board is changed.
config SOC_MEC1501_VCI_PINS_AS_GPIOS
bool "Use VCI block pins as GPIOS"
default y
help
By default these pins are not GPIOs, but HW controlled.
Set this if VCI pin block HW logic is not required in the board
design.
choice
prompt "MEC1501 debug interface general configuration"
default SOC_MEC1501_DEBUG_WITHOUT_TRACING
depends on SOC_SERIES_MEC15XX
help
Select Debug SoC interface support for MEC15xx SoC family
config SOC_MEC1501_DEBUG_DISABLED
bool "Disable debug support"
help
Debug port is disabled, JTAG/SWD cannot be enabled. JTAG_RST#
pin is ignored. All other JTAG pins can be used as GPIOs
or other non-JTAG alternate functions.
config SOC_MEC1501_DEBUG_WITHOUT_TRACING
bool "Debug support via Serial wire debug"
help
JTAG port in SWD mode. UART2 and ADC00-03 can be used.
config SOC_MEC1501_DEBUG_AND_TRACING
bool "Debug support via Serial wire debug with tracing enabled"
help
JTAG port is enabled in SWD mode. Refer to tracing options
to see if ADC00-03 can be used or not.
endchoice
choice
prompt "MEC1501 debug interface trace configuration"
default SOC_MEC1501_DEBUG_AND_ETM_TRACING
depends on SOC_MEC1501_DEBUG_AND_TRACING
help
Select tracing mode for debug interface
config SOC_MEC1501_DEBUG_AND_ETM_TRACING
bool "Debug support via Serial wire debug"
help
JTAG port in SWD mode and SWV as tracing method.
UART2 can be used, but ADC00-03 cannot.
config SOC_MEC1501_DEBUG_AND_SWV_TRACING
bool "debug support via Serial Wire Debug and Viewer"
help
JTAG port in SWD mode and SWV as tracing method.
UART2 cannot be used. ADC00-03 can be used.
endchoice
# GPIO initialization depends on SOC initialization, which happen at
# CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, so GPIO_INIT_PRIORITY needs to be
# higher than that.
if GPIO
config GPIO_INIT_PRIORITY
default 41
endif # GPIO
endif # SOC_SERIES_MEC15XX

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# Microchip MEC1501HSZ MCU
# Copyright (c) 2018 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
if SOC_MEC1501_HSZ
config GPIO
default y
config ESPI_XEC
default y
depends on ESPI
config PS2_XEC
default y
depends on PS2
endif # SOC_MEC1501_HSZ

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# Microchip MEC MCU series configuration options
# Copyright (c) 2018 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_MEC15XX
config NUM_IRQS
# must be >= the highest interrupt number used
# - include the UART interrupts
# All NVIC external sources.
default 174
rsource "Kconfig.defconfig.mec1501*"
if RTOS_TIMER
config SOC_HAS_TIMING_FUNCTIONS
default y if !CORTEX_M_DWT
config ARCH_HAS_CUSTOM_BUSY_WAIT
default y
endif # RTOS_TIMER
config CORTEX_M_SYSTICK
depends on !RTOS_TIMER
endif # SOC_SERIES_MEC15XX

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# Microchip MEC1501 MCU core series
# Copyright (c) 2018 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_MEC15XX
bool
select SOC_FAMILY_MICROCHIP_MEC
help
Enable support for Microchip MEC Cortex-M4 MCU series
config SOC_SERIES
default "mec15xx" if SOC_SERIES_MEC15XX
config SOC_MEC1501_HSZ
bool
select SOC_SERIES_MEC15XX
config SOC
default "mec1501_hsz" if SOC_MEC1501_HSZ

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/*
* Copyright (c) 2019 Microchip Technology Inc.
* Copyright (c) 2016 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/pm/pm.h>
#include <soc.h>
/*
* CPU will spin up to DEEP_SLEEP_WAIT_SPIN_CLK_REQ times
* waiting for PCR CLK_REQ bits to clear except for the
* CPU bit itself. This is not necessary as the sleep hardware
* will wait for all CLK_REQ to clear once WFI has executed.
* Once all CLK_REQ signals are clear the hardware will transition
* to the low power state.
*/
/* #define DEEP_SLEEP_WAIT_ON_CLK_REQ_ENABLE */
#define DEEP_SLEEP_WAIT_SPIN_CLK_REQ 1000
/*
* Some peripherals if enabled always assert their CLK_REQ bits.
* For example, any peripheral with a clock generator such as
* timers, counters, UART, etc. We save the enables for these
* peripherals, disable them, and restore the enabled state upon
* wake.
*/
#define DEEP_SLEEP_PERIPH_SAVE_RESTORE
/*
* Light sleep: PLL remains on. Fastest wake latency.
*/
void soc_lite_sleep_enable(void)
{
SCB->SCR &= ~(1ul << 2);
PCR_REGS->SYS_SLP_CTRL = MCHP_PCR_SYS_SLP_LIGHT;
}
/*
* Deep sleep: PLL is turned off. Wake is fast. PLL requires
* a minimum of 3ms to lock. During this time the main clock
* will be ramping up from ~16 to 24 MHz.
*/
void soc_deep_sleep_enable(void)
{
SCB->SCR = (1ul << 2); /* Cortex-M4 SLEEPDEEP */
PCR_REGS->SYS_SLP_CTRL = MCHP_PCR_SYS_SLP_HEAVY;
}
/*
* Clear PCR Sleep control sleep all causing HW to de-assert all peripheral
* SLP_EN signals. HW will does this automatically only if it vectors to an
* ISR after wake. We are masking ISR's from running until we restore
* peripheral state therefore we force HW to de-assert the SLP_EN signals.
*/
void soc_deep_sleep_disable(void)
{
PCR_REGS->SYS_SLP_CTRL = 0U;
SCB->SCR &= ~(1ul << 2); /* disable Cortex-M4 SLEEPDEEP */
}
void soc_deep_sleep_wait_clk_idle(void)
{
#ifdef DEEP_SLEEP_WAIT_ON_CLK_REQ_ENABLE
uint32_t clkreq, cnt;
cnt = DEEP_SLEEP_WAIT_CLK_REQ;
do {
clkreq = PCR_REGS->CLK_REQ0 | PCR_REGS->CLK_REQ1
| PCR_REGS->CLK_REQ2 | PCR_REGS->CLK_REQ3
| PCR_REGS->CLK_REQ4;
} while ((clkreq != (1ul << MCHP_PCR1_CPU_POS)) && (cnt-- != 0));
#endif
}
/*
* Allow peripherals connected to external masters to wake the PLL but not
* the EC. Once the peripheral has serviced the external master the PLL
* will be turned back off. For example, if the eSPI master requests eSPI
* configuration information or state of virtual wires the EC doesn't need
* to be involved. The hardware can power on the PLL long enough to service
* the request and then turn the PLL back off. The SMBus and I2C peripherals
* in slave mode can also make use of this feature.
*/
void soc_deep_sleep_non_wake_en(void)
{
#ifdef CONFIG_ESPI_XEC
GIRQ22_REGS->SRC = 0xfffffffful;
GIRQ22_REGS->EN_SET = (1ul << 9);
#endif
}
void soc_deep_sleep_non_wake_dis(void)
{
#ifdef CONFIG_ESPI_XEC
GIRQ22_REGS->EN_CLR = 0xfffffffful;
GIRQ22_REGS->SRC = 0xfffffffful;
#endif
}
/* Variables used to save various HW state */
#ifdef DEEP_SLEEP_PERIPH_SAVE_RESTORE
static uint32_t ecs[1];
static void deep_sleep_save_ecs(void)
{
ecs[0] = ECS_REGS->ETM_CTRL;
ECS_REGS->ETM_CTRL = 0;
}
struct ds_timer_info {
uintptr_t addr;
uint32_t restore_mask;
};
const struct ds_timer_info ds_timer_tbl[] = {
{
(uintptr_t)&B16TMR0_REGS->CTRL, 0
},
{
(uintptr_t)&B16TMR1_REGS->CTRL, 0
},
{
(uintptr_t)&B32TMR0_REGS->CTRL, 0
},
{
(uintptr_t)&B32TMR1_REGS->CTRL, 0
},
{
(uintptr_t)&CCT_REGS->CTRL,
(MCHP_CCT_CTRL_COMP1_SET | MCHP_CCT_CTRL_COMP0_SET),
},
};
#define NUM_DS_TIMER_ENTRIES \
(sizeof(ds_timer_tbl) / sizeof(struct ds_timer_info))
static uint32_t timers[NUM_DS_TIMER_ENTRIES];
static uint8_t uart_activate[3];
static void deep_sleep_save_uarts(void)
{
uart_activate[0] = UART0_REGS->ACTV;
if (uart_activate[0]) {
while ((UART0_REGS->LSR & MCHP_UART_LSR_TEMT) == 0) {
}
}
UART0_REGS->ACTV = 0;
uart_activate[1] = UART1_REGS->ACTV;
if (uart_activate[1]) {
while ((UART1_REGS->LSR & MCHP_UART_LSR_TEMT) == 0) {
}
}
UART1_REGS->ACTV = 0;
uart_activate[2] = UART2_REGS->ACTV;
if (uart_activate[2]) {
while ((UART2_REGS->LSR & MCHP_UART_LSR_TEMT) == 0) {
}
}
UART2_REGS->ACTV = 0;
}
static void deep_sleep_save_timers(void)
{
const struct ds_timer_info *p;
uint32_t i;
p = &ds_timer_tbl[0];
for (i = 0; i < NUM_DS_TIMER_ENTRIES; i++) {
timers[i] = REG32(p->addr);
REG32(p->addr) = 0;
p++;
}
}
static void deep_sleep_restore_ecs(void)
{
ECS_REGS->ETM_CTRL = ecs[0];
}
static void deep_sleep_restore_uarts(void)
{
UART0_REGS->ACTV = uart_activate[0];
UART1_REGS->ACTV = uart_activate[1];
UART2_REGS->ACTV = uart_activate[2];
}
static void deep_sleep_restore_timers(void)
{
const struct ds_timer_info *p;
uint32_t i;
p = &ds_timer_tbl[0];
for (i = 0; i < NUM_DS_TIMER_ENTRIES; i++) {
REG32(p->addr) = timers[i] & ~p->restore_mask;
p++;
}
}
void soc_deep_sleep_periph_save(void)
{
deep_sleep_save_uarts();
deep_sleep_save_ecs();
deep_sleep_save_timers();
}
void soc_deep_sleep_periph_restore(void)
{
deep_sleep_restore_ecs();
deep_sleep_restore_uarts();
deep_sleep_restore_timers();
}
#else
void soc_deep_sleep_periph_save(void)
{
}
void soc_deep_sleep_periph_restore(void)
{
}
#endif /* DEEP_SLEEP_PERIPH_SAVE_RESTORE */

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/*
* Copyright (c) 2019 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __DEVICE_POWER_H
#define __DEVICE_POWER_H
#ifndef _ASMLANGUAGE
void soc_lite_sleep_enable(void);
void soc_deep_sleep_enable(void);
void soc_deep_sleep_disable(void);
void soc_deep_sleep_periph_save(void);
void soc_deep_sleep_periph_restore(void);
void soc_deep_sleep_wait_clk_idle(void);
void soc_deep_sleep_non_wake_en(void);
void soc_deep_sleep_non_wake_dis(void);
#endif
#endif

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/*
* Copyright (c) 2019 Microchip Technology Inc.
* Copyright (c) 2016 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/sys/barrier.h>
#include <zephyr/pm/pm.h>
#include <soc.h>
#include "device_power.h"
/*
* Deep Sleep
* Pros:
* Lower power dissipation, 48MHz PLL is off
* Cons:
* Longer wake latency. CPU start running on ring oscillator
* between 16 to 25 MHz. Minimum 3ms until PLL reaches lock
* frequency of 48MHz.
*
* Implementation Notes:
* We touch the Cortex-M's primary mask and base priority registers
* because we do not want to enter an ISR immediately upon wake.
* We must restore any hardware state that was modified upon sleep
* entry before allowing interrupts to be serviced. Zephyr arch level
* does not provide API's to manipulate both primary mask and base priority.
*
* DEBUG NOTES:
* If a JTAG/SWD debug probe is connected driving TRST# high and
* possibly polling the DUT then MEC1501 will not shut off its 48MHz
* PLL. Firmware should not disable JTAG/SWD in the EC subsystem
* while a probe is using the interface. This can leave the JTAG/SWD
* TAP controller in a state of requesting clocks preventing the PLL
* from being shut off.
*/
static void z_power_soc_deep_sleep(void)
{
/* Mask all exceptions and interrupts except NMI and HardFault */
__set_PRIMASK(1);
soc_deep_sleep_periph_save();
soc_deep_sleep_enable();
soc_deep_sleep_wait_clk_idle();
soc_deep_sleep_non_wake_en();
/*
* Unmask all interrupts in BASEPRI. PRIMASK is used above to
* prevent entering an ISR after unmasking in BASEPRI.
*/
__set_BASEPRI(0);
barrier_dsync_fence_full();
__WFI(); /* triggers sleep hardware */
__NOP();
__NOP();
soc_deep_sleep_disable();
soc_deep_sleep_non_wake_dis();
/* Wait for PLL to lock */
while ((PCR_REGS->OSC_ID & MCHP_PCR_OSC_ID_PLL_LOCK) == 0) {
}
soc_deep_sleep_periph_restore();
/*
* pm_state_exit_post_ops() is not being called
* after exiting deep sleep, so need to unmask exceptions
* and interrupts here.
*/
__set_PRIMASK(0);
}
/*
* Light Sleep
* Pros:
* Fast wake response:
* Cons:
* Higher power dissipation, 48MHz PLL remains on.
*/
static void z_power_soc_sleep(void)
{
__set_PRIMASK(1);
soc_lite_sleep_enable();
__set_BASEPRI(0); /* Make sure wake interrupts are not masked! */
barrier_dsync_fence_full();
__WFI(); /* triggers sleep hardware */
__NOP();
__NOP();
}
/*
* Called from pm_system_suspend(int32_t ticks) in subsys/power.c
* For deep sleep pm_system_suspend has executed all the driver
* power management call backs.
*/
void pm_state_set(enum pm_state state, uint8_t substate_id)
{
ARG_UNUSED(substate_id);
switch (state) {
case PM_STATE_SUSPEND_TO_IDLE:
z_power_soc_sleep();
break;
case PM_STATE_SUSPEND_TO_RAM:
z_power_soc_deep_sleep();
break;
default:
break;
}
}
/*
* Zephyr PM code expects us to enabled interrupts at post op exit. Zephyr used
* arch_irq_lock() which sets BASEPRI to a non-zero value masking all interrupts
* preventing wake. MCHP z_power_soc_(deep)_sleep sets PRIMASK=1 and BASEPRI=0
* allowing wake from any enabled interrupt and prevents the CPU from entering
* an ISR on wake except for faults. We re-enable interrupts by setting PRIMASK
* to 0.
*/
void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
{
ARG_UNUSED(substate_id);
switch (state) {
case PM_STATE_SUSPEND_TO_IDLE:
case PM_STATE_SUSPEND_TO_RAM:
__set_PRIMASK(0);
barrier_isync_fence_full();
break;
default:
irq_unlock(0);
break;
}
}

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/*
* Copyright (c) 2019 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <cmsis_core.h>
/*
* Initialize MEC1501 EC Interrupt Aggregator (ECIA) and external NVIC
* inputs.
*/
static int soc_ecia_init(void)
{
GIRQ_Type *pg;
uint32_t n;
mchp_pcr_periph_slp_ctrl(PCR_ECIA, MCHP_PCR_SLEEP_DIS);
ECS_REGS->INTR_CTRL |= MCHP_ECS_ICTRL_DIRECT_EN;
/* gate off all aggregated outputs */
ECIA_REGS->BLK_EN_CLR = 0xFFFFFFFFul;
/* gate on GIRQ's that are aggregated only */
ECIA_REGS->BLK_EN_SET = MCHP_ECIA_AGGR_BITMAP;
/* Clear all GIRQn source enables and source status */
pg = &ECIA_REGS->GIRQ08;
for (n = MCHP_FIRST_GIRQ; n <= MCHP_LAST_GIRQ; n++) {
pg->EN_CLR = 0xFFFFFFFFul;
pg->SRC = 0xFFFFFFFFul;
pg++;
}
/* Clear all external NVIC enables and pending status */
for (n = 0u; n < MCHP_NUM_NVIC_REGS; n++) {
NVIC->ICER[n] = 0xFFFFFFFFul;
NVIC->ICPR[n] = 0xFFFFFFFFul;
}
return 0;
}
static void configure_debug_interface(void)
{
/* No debug support */
ECS_REGS->DEBUG_CTRL = 0;
ECS_REGS->ETM_CTRL = 0;
#ifdef CONFIG_SOC_MEC1501_DEBUG_WITHOUT_TRACING
/* Release JTAG TDI and JTAG TDO pins so they can be
* controlled by their respective PCR register (UART2).
* For more details see table 44-1
*/
ECS_REGS->DEBUG_CTRL = (MCHP_ECS_DCTRL_DBG_EN |
MCHP_ECS_DCTRL_MODE_SWD);
#elif defined(CONFIG_SOC_MEC1501_DEBUG_AND_TRACING)
#if defined(CONFIG_SOC_MEC1501_DEBUG_AND_ETM_TRACING)
#pragma error "TRACE DATA are not exposed in HW connector"
#elif defined(CONFIG_SOC_MEC1501_DEBUG_AND_SWV_TRACING)
ECS_REGS->DEBUG_CTRL = (MCHP_ECS_DCTRL_DBG_EN |
MCHP_ECS_DCTRL_MODE_SWD_SWV);
#endif /* CONFIG_SOC_MEC1501_DEBUG_AND_TRACING */
#endif /* CONFIG_SOC_MEC1501_DEBUG_WITHOUT_TRACING */
}
static int soc_init(void)
{
uint32_t isave;
isave = __get_PRIMASK();
__disable_irq();
soc_ecia_init();
/* Configure GPIO bank before usage
* VTR1 is not configurable
* VTR2 doesn't need configuration if setting VTR2_STRAP
*/
#ifdef CONFIG_SOC_MEC1501_VTR3_1_8V
ECS_REGS->GPIO_BANK_PWR |= MCHP_ECS_VTR3_LVL_18;
#endif
configure_debug_interface();
if (!isave) {
__enable_irq();
}
return 0;
}
SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

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/*
* Copyright (c) 2019 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __MEC_SOC_H
#define __MEC_SOC_H
#define SYSCLK_DEFAULT_IOSC_HZ MHZ(48)
#ifndef _ASMLANGUAGE
#include "MEC1501hsz.h"
#include "regaccess.h"
/* common SoC API */
#include "../common/soc_dt.h"
#include "../common/soc_gpio.h"
#include "../common/soc_pcr.h"
#include "../common/soc_pins.h"
#include "../common/soc_espi_channels.h"
#include "soc_espi_saf_v1.h"
/* common peripheral register defines */
#include "../common/reg/mec_gpio.h"
#endif
#endif

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/*
* Copyright (c) 2020 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file Header containing definitions for MCHP eSPI SAF
*/
#ifndef _SOC_ESPI_SAF_H_
#define _SOC_ESPI_SAF_H_
#include <stdint.h>
#include <zephyr/sys/util.h>
#include <soc.h>
#define MCHP_SAF_MAX_FLASH_DEVICES 2U
/*
* SAF hardware state machine timings
* poll timeout is in 32KHz clock periods
* poll interval is in AHB clock(48MHz) units.
* suspend resume interval is in 32KHz clock periods.
* consecutive read timeout is in AHB clock periods.
* suspend check delay is in AHB clock(48MHz) periods.
*/
#define MCHP_SAF_FLASH_POLL_TIMEOUT 0x28000U
#define MCHP_SAF_FLASH_POLL_INTERVAL 0U
#define MCHP_SAF_FLASH_SUS_RSM_INTERVAL 8U
#define MCHP_SAF_FLASH_CONSEC_READ_TIMEOUT 2U
#define MCHP_SAF_FLASH_SUS_CHK_DELAY 0U
/* Default SAF Map of eSPI TAG numbers to master numbers */
#define MCHP_SAF_TAG_MAP0_DFLT 0x23221100
#define MCHP_SAF_TAG_MAP1_DFLT 0x77677767
#define MCHP_SAF_TAG_MAP2_DFLT 0x00000005
/*
* Default QMSPI clock divider and chip select timing.
* QMSPI master clock is 48MHz AHB clock.
*/
#define MCHP_SAF_QMSPI_CLK_DIV 2U
#define MCHP_SAF_QMSPI_CS_TIMING 0x03000101U
/* SAF QMSPI programming */
#define MCHP_SAF_QMSPI_NUM_FLASH_DESCR 6U
#define MCHP_SAF_QMSPI_CS0_START_DESCR 0U
#define MCHP_SAF_QMSPI_CS1_START_DESCR \
(MCHP_SAF_QMSPI_CS0_START_DESCR + MCHP_SAF_QMSPI_NUM_FLASH_DESCR)
/* SAF engine requires start indices of descriptor chains */
#define MCHP_SAF_CM_EXIT_START_DESCR 12U
#define MCHP_SAF_CM_EXIT_LAST_DESCR 13U
#define MCHP_SAF_POLL_STS_START_DESCR 14U
#define MCHP_SAF_POLL_STS_END_DESCR 15U
#define MCHP_SAF_NUM_GENERIC_DESCR 4U
/* QMSPI descriptors 12-15 for all SPI flash devices */
/* #define SAF_QMSPI_DESCR12 0x0002D40E */
/*
* QMSPI descriptors 12-13 are exit continuous mode
*/
#define MCHP_SAF_EXIT_CM_DESCR12 \
(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_ONES | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | \
MCHP_QMSPI_C_NEXT_DESCR(13) | \
MCHP_QMSPI_C_XFR_NUNITS(1))
#define MCHP_SAF_EXIT_CM_DESCR13 \
(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_EN | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | \
MCHP_QMSPI_C_NEXT_DESCR(0) | \
MCHP_QMSPI_C_XFR_NUNITS(9) | \
MCHP_QMSPI_C_DESCR_LAST)
/*
* QMSPI descriptors 14-15 are poll 16-bit flash status
* Transmit one byte opcode at 1X (no DMA).
* Receive two bytes at 1X (no DMA).
*/
#define MCHP_SAF_POLL_DESCR14 \
(MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DATA | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | \
MCHP_QMSPI_C_NEXT_DESCR(15) | \
MCHP_QMSPI_C_XFR_NUNITS(1))
#define MCHP_SAF_POLL_DESCR15 \
(MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DIS | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_EN | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | \
MCHP_QMSPI_C_NEXT_DESCR(0) | \
MCHP_QMSPI_C_XFR_NUNITS(2) | \
MCHP_QMSPI_C_DESCR_LAST)
/* SAF Pre-fetch optimization mode */
#define MCHP_SAF_PREFETCH_MODE MCHP_SAF_FL_CFG_MISC_PFOE_DFLT
#define MCHP_SAF_CFG_MISC_PREFETCH_EXPEDITED 0x03U
/*
* SAF Opcode 32-bit register value.
* Each byte contain a SPI flash 8-bit opcode.
* NOTE1: opcode value of 0 = flash does not support this operation
* NOTE2:
* SAF Opcode A
* op0 = SPI flash write-enable opcode
* op1 = SPI flash program/erase suspend opcode
* op2 = SPI flash program/erase resume opcode
* op3 = SPI flash read STATUS1 opcode
* SAF Opcode B
* op0 = SPI flash erase 4KB sector opcode
* op1 = SPI flash erase 32KB sector opcode
* op2 = SPI flash erase 64KB sector opcode
* op3 = SPI flash page program opcode
* SAF Opcode C
* op0 = SPI flash read 1-4-4 continuous mode opcode
* op1 = SPI flash op0 mode byte value for non-continuous mode
* op2 = SPI flash op0 mode byte value for continuous mode
* op3 = SPI flash read STATUS2 opcode
*/
#define MCHP_SAF_OPCODE_REG_VAL(op0, op1, op2, op3) \
(((uint32_t)(op0)&0xffU) | (((uint32_t)(op1)&0xffU) << 8) | \
(((uint32_t)(op2)&0xffU) << 16) | (((uint32_t)(op3)&0xffU) << 24))
/*
* SAF Flash Config CS0/CS1 QMSPI descriptor indices register value
* e = First QMSPI descriptor index for enter continuous mode chain
* r = First QMSPI descriptor index for continuous mode read chain
* s = Index of QMSPI descriptor in continuous mode read chain that
* contains the data length field.
*/
#define MCHP_SAF_CS_CFG_DESCR_IDX_REG_VAL(e, r, s) (((uint32_t)(e)&0xfU) | \
(((uint32_t)(r)&0xfU) << 8) | (((uint32_t)(s)&0xfU) << 12))
/* W25Q128 SPI flash device connected size in bytes */
#define MCHP_W25Q128_SIZE (16U * 1024U * 1024U)
/*
* Six QMSPI descriptors describe SPI flash opcode protocols.
* Example: W25Q128
*/
/* Continuous mode read: transmit-quad 24-bit address and mode byte */
#define MCHP_W25Q128_CM_RD_D0 \
(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DATA | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(4))
/* Continuous mode read: transmit-quad 4 dummy clocks with I/O tri-stated */
#define MCHP_W25Q128_CM_RD_D1 \
(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(2))
/* Continuous mode read: read N bytes */
#define MCHP_W25Q128_CM_RD_D2 \
(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_EN | \
MCHP_QMSPI_C_RX_DMA_4B | MCHP_QMSPI_C_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(0) | \
MCHP_QMSPI_C_DESCR_LAST)
/* Enter Continuous mode: transmit-single CM quad read opcode */
#define MCHP_W25Q128_ENTER_CM_D0 \
(MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DATA | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(1))
/* Enter Continuous mode: transmit-quad 24-bit address and mode byte */
#define MCHP_W25Q128_ENTER_CM_D1 \
(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DATA | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(4))
/* Enter Continuous mode: read-quad 3 bytes */
#define MCHP_W25Q128_ENTER_CM_D2 \
(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(3) | \
MCHP_QMSPI_C_DESCR_LAST)
#define MCHP_W25Q128_OPA MCHP_SAF_OPCODE_REG_VAL(0x06U, 0x75U, 0x7aU, 0x05U)
#define MCHP_W25Q128_OPB MCHP_SAF_OPCODE_REG_VAL(0x20U, 0x52U, 0xd8U, 0x02U)
#define MCHP_W25Q128_OPC MCHP_SAF_OPCODE_REG_VAL(0xebU, 0xffU, 0xa5U, 0x35U)
/* W25Q128 STATUS2 bit[7] == 0 part is NOT in suspend state */
#define MCHP_W25Q128_POLL2_MASK 0xff7fU
/*
* SAF Flash Continuous Mode Prefix register value
* b[7:0] = continuous mode prefix opcode
* b[15:8] = continuous mode prefix opcode data
* Some SPI flash devices require a prefix command before
* they will enter continuous mode.
* A zero value means the SPI flash does not require a prefix
* command.
*/
#define MCHP_W25Q128_CONT_MODE_PREFIX_VAL 0U
#define MCHP_W25Q128_FLAGS 0U
/* W25Q256 SPI flash device connected size in bytes */
#define MCHP_W25Q256_SIZE (32U * 1024U * 1024U)
/*
* Six QMSPI descriptors describe SPI flash opcode protocols.
* W25Q256 device.
*/
/* Continuous Mode Read: Transmit-quad opcode plus 32-bit address */
#define MCHP_W25Q256_CM_RD_D0 \
(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DATA | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(5))
#define MCHP_W25Q256_CM_RD_D1 \
(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(2))
#define MCHP_W25Q256_CM_RD_D2 \
(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_EN | \
MCHP_QMSPI_C_RX_DMA_4B | MCHP_QMSPI_C_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(0) | \
MCHP_QMSPI_C_DESCR_LAST)
/* Enter Continuous mode: transmit-single CM quad read opcode */
#define MCHP_W25Q256_ENTER_CM_D0 \
(MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DATA | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(1))
/* Enter Continuous mode: transmit-quad 32-bit address and mode byte */
#define MCHP_W25Q256_ENTER_CM_D1 \
(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DATA | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(5))
/* Enter Continuous mode: read-quad 3 bytes */
#define MCHP_W25Q256_ENTER_CM_D2 \
(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(3) | \
MCHP_QMSPI_C_DESCR_LAST)
#define MCHP_W25Q256_OPA MCHP_SAF_OPCODE_REG_VAL(0x06U, 0x75U, 0x7aU, 0x05U)
#define MCHP_W25Q256_OPB MCHP_SAF_OPCODE_REG_VAL(0x20U, 0x52U, 0xd8U, 0x02U)
#define MCHP_W25Q256_OPC MCHP_SAF_OPCODE_REG_VAL(0xebU, 0xffU, 0xa5U, 0x35U)
#define MCHP_W25Q256_POLL2_MASK 0xff7fU
#define MCHP_W25Q256_CONT_MODE_PREFIX_VAL 0U
#define MCHP_W25Q256_FLAGS 0U
/* SAF Flash Config CS0 QMSPI descriptor indices */
#define MCHP_CS0_CFG_DESCR_IDX_REG_VAL \
MCHP_SAF_CS_CFG_DESCR_IDX_REG_VAL(3U, 0U, 2U)
/* SAF Flash Config CS1 QMSPI descriptor indices */
#define MCHP_CS1_CFG_DESCR_IDX_REG_VAL \
MCHP_SAF_CS_CFG_DESCR_IDX_REG_VAL(9U, 6U, 8U)
#define MCHP_SAF_HW_CFG_FLAG_FREQ 0x01U
#define MCHP_SAF_HW_CFG_FLAG_CSTM 0x02U
#define MCHP_SAF_HW_CFG_FLAG_CPHA 0x04U
/* enable SAF prefetch */
#define MCHP_SAF_HW_CFG_FLAG_PFEN 0x10U
/* Use expedited prefetch instead of default */
#define MCHP_SAF_HW_CFG_FLAG_PFEXP 0x20U
/*
* Override the default tag map value when this bit is set
* in a tag_map[].
*/
#define MCHP_SAF_HW_CFG_TAGMAP_USE BIT(31)
struct espi_saf_hw_cfg {
uint32_t qmspi_freq_hz;
uint32_t qmspi_cs_timing;
uint8_t qmspi_cpha;
uint8_t flags;
uint32_t generic_descr[MCHP_SAF_NUM_GENERIC_DESCR];
uint32_t tag_map[MCHP_ESPI_SAF_TAGMAP_MAX];
};
/*
* SAF local flash configuration.
* SPI flash device size in bytes
* SPI opcodes for SAF Opcode A register
* SPI opcodes for SAF Opcode B register
* SPI opcodes for SAF Opcode C register
* QMSPI descriptors describing SPI opcode transmit and
* data read.
* SAF controller Poll2 Mast value specific for this flash device
* SAF continuous mode prefix register value for those flashes requiring
* a prefix byte transmitted before the enter continuous mode command.
* Start QMSPI descriptor numbers.
* miscellaneous flags.
*/
/* Flags */
#define MCHP_FLASH_FLAG_ADDR32 BIT(0)
struct espi_saf_flash_cfg {
uint32_t flashsz;
uint32_t opa;
uint32_t opb;
uint32_t opc;
uint16_t poll2_mask;
uint16_t cont_prefix;
uint16_t cs_cfg_descr_ids;
uint16_t flags;
uint32_t descr[MCHP_SAF_QMSPI_NUM_FLASH_DESCR];
};
/*
* 17 flash protection regions
* Each region is described by:
* SPI start address. 20-bits = bits[31:12] of SPI address
* SPI limit address. 20-bits = bits[31:12] of last SPI address
* 8-bit bit map of eSPI master write-erase permission
* 8-bit bit map of eSPI master read permission
* eSPI master numbers 0 - 7 correspond to bits 0 - 7.
*
* Protection region lock:
* One 32-bit register with bits[16:0] -> protection regions 16:0
*
* eSPI Host maps threads by a tag number to master numbers.
* Thread numbers are 4-bit
* Master numbers are 3-bit
* Master number Thread numbers Description
* 0 0h, 1h Host PCH HW init
* 1 2h, 3h Host CPU access(HW/BIOS/SMM/SW)
* 2 4h, 5h Host PCH ME
* 3 6h Host PCH LAN
* 4 N/A Not defined/used
* 5 N/A EC Firmware portal access
* 6 9h, Dh Host PCH IE
* 7 N/A Not defined/used
*
* NOTE: eSPI SAF specification allows master 0 (Host PCH HW) full
* access to all protection regions.
*
* SAF TAG Map registers 0 - 2 map eSPI TAG values 0h - Fh to
* the three bit master number. Each 32-bit register contains 3-bit
* fields aligned on nibble boundaries holding the master number
* associated with the eSPI tag (thread) number.
* A master value of 7h in a field indicates a non-existent map entry.
*
* bit map of registers to program
* b[2:0] = TAG Map[2:0]
* b[20:4] = ProtectionRegions[16:0]
* bit map of PR's to lock
* b[20:4] = ProtectionRegions[16:0]
*
*/
#define MCHP_SAF_PR_FLAG_ENABLE 0x01U
#define MCHP_SAF_PR_FLAG_LOCK 0x02U
#define MCHP_SAF_MSTR_HOST_PCH 0U
#define MCHP_SAF_MSTR_HOST_CPU 1U
#define MCHP_SAF_MSTR_HOST_PCH_ME 2U
#define MCHP_SAF_MSTR_HOST_PCH_LAN 3U
#define MCHP_SAF_MSTR_RSVD4 4U
#define MCHP_SAF_MSTR_EC 5U
#define MCHP_SAF_MSTR_HOST_PCH_IE 6U
struct espi_saf_pr {
uint32_t start;
uint32_t size;
uint8_t master_bm_we;
uint8_t master_bm_rd;
uint8_t pr_num;
uint8_t flags; /* bit[0]==1 is lock the region */
};
struct espi_saf_protection {
size_t nregions;
const struct espi_saf_pr *pregions;
};
#endif /* _SOC_ESPI_SAF_H_ */

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/*
* Copyright (c) 2020 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/arch/arm/arch.h>
#include <zephyr/kernel.h>
#include <zephyr/sys_clock.h>
#include <zephyr/timing/timing.h>
#include <soc.h>
void soc_timing_init(void)
{
/* Setup counter */
B32TMR1_REGS->CTRL = MCHP_BTMR_CTRL_ENABLE |
MCHP_BTMR_CTRL_AUTO_RESTART |
MCHP_BTMR_CTRL_COUNT_UP;
B32TMR1_REGS->PRLD = 0; /* Preload */
B32TMR1_REGS->CNT = 0; /* Counter value */
B32TMR1_REGS->IEN = 0; /* Disable interrupt */
B32TMR1_REGS->STS = 1; /* Clear interrupt */
}
void soc_timing_start(void)
{
B32TMR1_REGS->CTRL |= MCHP_BTMR_CTRL_START;
}
void soc_timing_stop(void)
{
B32TMR1_REGS->CTRL &= ~MCHP_BTMR_CTRL_START;
}
timing_t soc_timing_counter_get(void)
{
return B32TMR1_REGS->CNT;
}
uint64_t soc_timing_cycles_get(volatile timing_t *const start,
volatile timing_t *const end)
{
return (*end - *start);
}
uint64_t soc_timing_freq_get(void)
{
return CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
}
uint64_t soc_timing_cycles_to_ns(uint64_t cycles)
{
return (cycles) * (NSEC_PER_SEC) / (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
}
uint64_t soc_timing_cycles_to_ns_avg(uint64_t cycles, uint32_t count)
{
return (uint32_t)soc_timing_cycles_to_ns(cycles) / count;
}
uint32_t soc_timing_freq_get_mhz(void)
{
return (uint32_t)(soc_timing_freq_get() / 1000000);
}

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#
# Copyright (c) 2021, Microchip Technology Inc.
#
# SPDX-License-Identifier: Apache-2.0
#
zephyr_include_directories(${ZEPHYR_BASE}/drivers)
zephyr_sources(soc.c)
zephyr_include_directories(.)
if(CONFIG_PM)
zephyr_library_sources(power.c device_power.c)
endif()
if(CONFIG_SOC_HAS_TIMING_FUNCTIONS AND NOT CONFIG_BOARD_HAS_TIMING_FUNCTIONS)
if(CONFIG_TIMING_FUNCTIONS)
# Use MEC172x timing calculations only if DWT is not present
if(NOT CONFIG_CORTEX_M_DWT)
zephyr_library_sources(timing.c)
endif()
endif()
endif()
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

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# Microchip MEC172X MCU core series
# Copyright (c) 2021 Microchip Technology Inc.
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_MEC172X
select ARM
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select CPU_HAS_ARM_MPU
select HAS_SWO
select HAS_PM
if SOC_SERIES_MEC172X
config RTOS_TIMER
bool "MEC172x RTOS Timer(32KHz) as kernel timer"
choice
prompt "MEC172x debug interface general configuration"
default SOC_MEC172X_DEBUG_WITHOUT_TRACING
depends on SOC_SERIES_MEC172X
help
Select Debug SoC interface support for MEC172X SoC family
config SOC_MEC172X_DEBUG_DISABLED
bool "Disable debug support"
help
Debug port is disabled, JTAG/SWD cannot be enabled. JTAG_RST#
pin is ignored. All other JTAG pins can be used as GPIOs
or other non-JTAG alternate functions.
config SOC_MEC172X_DEBUG_WITHOUT_TRACING
bool "Debug support via Serial wire debug"
help
JTAG port in SWD mode. I2C09 and ADC00-03 can be used.
config SOC_MEC172X_DEBUG_AND_TRACING
bool "Debug support via Serial wire debug with tracing enabled"
help
JTAG port is enabled in SWD mode. Refer to tracing options
to see if ADC00-03 can be used or not.
endchoice
choice
prompt "MEC172X debug interface trace configuration"
default SOC_MEC172X_DEBUG_AND_ETM_TRACING
depends on SOC_MEC172X_DEBUG_AND_TRACING
help
Select tracing mode for debug interface
config SOC_MEC172X_DEBUG_AND_ETM_TRACING
bool "Debug support via Serial wire debug"
help
JTAG port in SWD mode and ETM as tracing method.
I2C09 can be used, but ADC00-03 cannot.
config SOC_MEC172X_DEBUG_AND_SWV_TRACING
bool "debug support via Serial Wire Debug and Viewer"
help
JTAG port in SWD mode and SWV as tracing method.
I2C09 cannot be used. ADC00-03 can be used.
endchoice
# GPIO initialization depends on ECIA initialization, which happen at
# CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, so GPIO_INIT_PRIORITY needs to be
# higher than that.
if GPIO
config GPIO_INIT_PRIORITY
default 41
endif # GPIO
endif # SOC_SERIES_MEC172X

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# Microchip MEC172XNLJ MCU
# Copyright (c) 2022 Silicom Connectivity Solutions
# SPDX-License-Identifier: Apache-2.0
if SOC_MEC172X_NLJ
config GPIO
default y
config ESPI_XEC_V2
default y
depends on ESPI
config EEPROM_XEC
default y
depends on EEPROM
endif # SOC_MEC172X_NLJ

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# Microchip MEC172XNSZ MCU
# Copyright (c) 2021 Microchip Technology Inc.
# SPDX-License-Identifier: Apache-2.0
if SOC_MEC172X_NSZ
config GPIO
default y
endif # SOC_MEC172X_NSZ

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# Microchip MEC MCU series configuration options
# Copyright (c) 2021 Microchip Technology Inc.
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_MEC172X
config NUM_IRQS
# must be >= the highest interrupt number used
# - include the UART interrupts
# All NVIC external sources.
default 181
rsource "Kconfig.defconfig.mec172x*"
if RTOS_TIMER
config SOC_HAS_TIMING_FUNCTIONS
default y if !CORTEX_M_DWT
config ARCH_HAS_CUSTOM_BUSY_WAIT
default y
endif # RTOS_TIMER
config CORTEX_M_SYSTICK
depends on !RTOS_TIMER
config PS2_XEC
default y
depends on PS2
endif # SOC_SERIES_MEC172X

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# Microchip MEC172x MCU core series
# Copyright (c) 2021 Microchip Technology Inc.
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_MEC172X
bool
select SOC_FAMILY_MICROCHIP_MEC
help
Enable support for Microchip MEC Cortex-M4F MCU series
config SOC_SERIES
default "mec172x" if SOC_SERIES_MEC172X
config SOC_MEC172X_NSZ
bool
select SOC_SERIES_MEC172X
config SOC_MEC172X_NLJ
bool
select SOC_SERIES_MEC172X
config SOC
default "mec172x_nsz" if SOC_MEC172X_NSZ
default "mec172x_nlj" if SOC_MEC172X_NLJ

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/*
* Copyright (c) 2019 Microchip Technology Inc.
* Copyright (c) 2016 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/pm/pm.h>
#include <soc.h>
#include "device_power.h"
#define ADC_0_XEC_REG_BASE \
((struct adc_regs *)(DT_REG_ADDR(DT_NODELABEL(adc0))))
#define ECIA_XEC_REG_BASE \
((struct ecia_named_regs *)(DT_REG_ADDR(DT_NODELABEL(ecia))))
#define ECS_XEC_REG_BASE \
((struct ecs_regs *)(DT_REG_ADDR(DT_NODELABEL(ecs))))
#define PECI_XEC_REG_BASE \
((struct peci_regs *)(DT_REG_ADDR(DT_NODELABEL(peci0))))
#define PCR_XEC_REG_BASE \
((struct pcr_regs *)(DT_REG_ADDR(DT_NODELABEL(pcr))))
#define TFDP_0_XEC_REG_BASE \
((struct tfdp_regs *)(DT_REG_ADDR(DT_NODELABEL(tfdp0))))
#define UART_0_XEC_REG_BASE \
((struct uart_regs *)(DT_REG_ADDR(DT_NODELABEL(uart0))))
#define UART_1_XEC_REG_BASE \
((struct uart_regs *)(DT_REG_ADDR(DT_NODELABEL(uart1))))
#define VBATR_XEC_REG_BASE \
((struct vbatr_regs *)(DT_REG_ADDR_BY_NAME(DT_NODELABEL(pcr), vbatr)))
#define VBATM_XEC_BASE_ADDR \
((uintptr_t)(DT_REG_ADDR(DT_NODELABEL(bbram))))
#define BTMR16_0_ADDR DT_REG_ADDR(DT_NODELABEL(timer0))
#define BTMR16_1_ADDR DT_REG_ADDR(DT_NODELABEL(timer1))
#define BTMR16_2_ADDR DT_REG_ADDR(DT_NODELABEL(timer2))
#define BTMR16_3_ADDR DT_REG_ADDR(DT_NODELABEL(timer3))
#define BTMR32_0_ADDR DT_REG_ADDR(DT_NODELABEL(timer4))
#define BTMR32_1_ADDR DT_REG_ADDR(DT_NODELABEL(timer5))
#define VBATM_XEC_ADDR DT_REG_ADDR(DT_NODELABEL(vbr))
#ifdef DEBUG_DEEP_SLEEP_CLK_REQ
void soc_debug_sleep_clk_req(void)
{
struct ecs_regs *ecs = ECS_XEC_REG_BASE;
struct pcr_regs *pcr = PCR_XEC_REG_BASE;
uintptr_t vbm_addr = VBATM_XEC_BASE_ADDR;
/* Save status to debug LPM been blocked */
for (int i = 0; i < 5; i++) {
sys_write32(pcr->CLK_REQ[i], vbm_addr);
vbm_addr += 4;
}
sys_write32(pcr->SYS_SLP_CTRL, vbm_addr);
vbm_addr += 4;
sys_write32(ecs->SLP_STS_MIRROR, vbm_addr);
}
#endif
/*
* Allow peripherals connected to external masters to wake the PLL but not
* the EC. Once the peripheral has serviced the external master the PLL
* will be turned back off. For example, if the eSPI master requests eSPI
* configuration information or state of virtual wires the EC doesn't need
* to be involved. The hardware can power on the PLL long enough to service
* the request and then turn the PLL back off. The SMBus and I2C peripherals
* in slave mode can also make use of this feature.
*/
void soc_deep_sleep_non_wake_en(void)
{
#ifdef CONFIG_ESPI
struct ecia_named_regs *regs = ECIA_XEC_REG_BASE;
regs->GIRQ22.SRC = UINT32_MAX;
regs->GIRQ22.EN_SET = MCHP_ESPI_WK_CLK_GIRQ_BIT;
#endif
}
void soc_deep_sleep_non_wake_dis(void)
{
#ifdef CONFIG_ESPI
struct ecia_named_regs *regs = ECIA_XEC_REG_BASE;
regs->GIRQ22.EN_CLR = UINT32_MAX;
regs->GIRQ22.SRC = UINT32_MAX;
#endif
}
/* When MEC172x drivers are power-aware this should be move there */
void soc_deep_sleep_wake_en(void)
{
#if defined(CONFIG_KSCAN) || \
(!defined(CONFIG_PM_DEVICE) && DT_NODE_HAS_STATUS(DT_NODELABEL(ps2_0), okay))
struct ecia_named_regs *regs = ECIA_XEC_REG_BASE;
#if defined(CONFIG_KSCAN)
/* Enable PLL wake via KSCAN */
regs->GIRQ21.SRC = MCHP_KEYSCAN_GIRQ_BIT;
regs->GIRQ21.EN_SET = MCHP_KEYSCAN_GIRQ_BIT;
#endif
#if !defined(CONFIG_PM_DEVICE) && DT_NODE_HAS_STATUS(DT_NODELABEL(ps2_0), okay)
/* Enable PS2_0B_WK */
regs->GIRQ21.SRC = MCHP_PS2_0_PORT0B_WK_GIRQ_BIT;
regs->GIRQ21.EN_SET = MCHP_PS2_0_PORT0B_WK_GIRQ_BIT;
#endif
#endif
}
void soc_deep_sleep_wake_dis(void)
{
#if !defined(CONFIG_PM_DEVICE) && DT_NODE_HAS_STATUS(DT_NODELABEL(ps2_0), okay)
struct ecia_named_regs *regs = ECIA_XEC_REG_BASE;
/* Enable PS2_0B_WK */
regs->GIRQ21.EN_CLR = MCHP_PS2_0_PORT0B_WK_GIRQ_BIT;
regs->GIRQ21.SRC = MCHP_PS2_0_PORT0B_WK_GIRQ_BIT;
#endif
}
/* Variables used to save various HW state */
#ifdef DEEP_SLEEP_PERIPH_SAVE_RESTORE
const struct ds_timer_info ds_timer_tbl[NUM_DS_TIMER_ENTRIES] = {
{
(uintptr_t)(BTMR16_0_ADDR + MCHP_BTMR_CTRL_OFS),
MCHP_BTMR_CTRL_HALT, 0
},
{
(uintptr_t)(BTMR16_1_ADDR + MCHP_BTMR_CTRL_OFS),
MCHP_BTMR_CTRL_HALT, 0
},
{
(uintptr_t)(BTMR16_2_ADDR + MCHP_BTMR_CTRL_OFS),
MCHP_BTMR_CTRL_HALT, 0
},
{
(uintptr_t)(BTMR16_3_ADDR + MCHP_BTMR_CTRL_OFS),
MCHP_BTMR_CTRL_HALT, 0
},
{
(uintptr_t)(BTMR32_0_ADDR + MCHP_BTMR_CTRL_OFS),
MCHP_BTMR_CTRL_HALT, 0
},
{
(uintptr_t)(BTMR32_1_ADDR + MCHP_BTMR_CTRL_OFS),
MCHP_BTMR_CTRL_HALT, 0
},
};
static struct ds_dev_info ds_ctx;
static void deep_sleep_save_ecs(void)
{
struct ecs_regs *regs = ECS_XEC_REG_BASE;
ds_ctx.ecs[0] = regs->ETM_CTRL;
ds_ctx.ecs[1] = regs->DEBUG_CTRL;
#ifdef DEEP_SLEEP_JTAG
regs->ETM_CTRL = 0;
regs->DEBUG_CTRL = 0x00;
#endif
}
#ifdef DEEP_SLEEP_UART_SAVE_RESTORE
static void deep_sleep_save_uarts(void)
{
struct uart_regs *regs = UART_0_XEC_REG_BASE;
ds_ctx.uart_info[0] = regs->ACTV;
if (ds_ctx.uart_info[0]) {
while ((regs->LSR & MCHP_UART_LSR_TEMT) == 0) {
}
}
regs->ACTV = 0;
regs = UART_1_XEC_REG_BASE;
ds_ctx.uart_info[1] = regs->ACTV;
if (ds_ctx.uart_info[1]) {
while ((regs->LSR & MCHP_UART_LSR_TEMT) == 0) {
}
}
regs->ACTV = 0;
}
#endif
static void deep_sleep_save_timers(void)
{
const struct ds_timer_info *p;
uint32_t i;
p = &ds_timer_tbl[0];
for (i = 0; i < NUM_DS_TIMER_ENTRIES; i++) {
ds_ctx.timers[i] = sys_read32(p->addr);
if (p->stop_mask) {
sys_write32(ds_ctx.timers[i] | p->stop_mask, p->addr);
} else {
sys_write32(0, p->addr);
}
p++;
}
}
static void deep_sleep_restore_ecs(void)
{
#ifdef DEEP_SLEEP_JTAG
struct ecs_regs *regs = ECS_XEC_REG_BASE;
regs->ETM_CTRL = ds_ctx.ecs[0];
regs->DEBUG_CTRL = ds_ctx.ecs[1];
#endif
}
#ifdef DEEP_SLEEP_UART_SAVE_RESTORE
static void deep_sleep_restore_uarts(void)
{
struct uart_regs *regs0 = UART_0_XEC_REG_BASE;
struct uart_regs *regs1 = UART_1_XEC_REG_BASE;
regs0->ACTV = ds_ctx.uart_info[0];
regs1->ACTV = ds_ctx.uart_info[1];
}
#endif
static void deep_sleep_restore_timers(void)
{
const struct ds_timer_info *p;
uint32_t i, temp;
p = &ds_timer_tbl[0];
for (i = 0; i < NUM_DS_TIMER_ENTRIES; i++) {
if (p->stop_mask) {
temp = sys_read32(p->addr) & ~(p->stop_mask);
sys_write32(temp, p->addr);
} else {
sys_write32(ds_ctx.timers[i] & ~p->restore_mask,
p->addr);
}
p++;
}
}
#ifdef DEEP_SLEEP_PERIPH_SAVE_RESTORE_EXTENDED
static void deep_sleep_save_blocks(void)
{
struct tfdp_regs *tfdp = TFDP_0_XEC_REG_BASE;
struct ecs_regs *ecs = ECS_XEC_REG_BASE;
#ifdef CONFIG_ADC
struct adc_regs *adc0 = ADC_0_XEC_REG_BASE;
/* ADC deactivate */
adc0->CONTROL &= ~(MCHP_ADC_CTRL_ACTV);
#endif
#ifdef CONFIG_PECI
struct peci_regs *peci = PECI_XEC_REG_BASE;
ds_ctx.peci_info.peci_ctrl = peci->CONTROL;
ds_ctx.peci_info.peci_dis = ecs->PECI_DIS;
ecs->PECI_DIS |= MCHP_ECS_PECI_DISABLE;
#endif
#ifdef CONFIG_I2C
for (size_t n = 0; n < MCHP_I2C_SMB_INSTANCES; n++) {
uint32_t addr = MCHP_I2C_SMB_BASE_ADDR(n) +
MCHP_I2C_SMB_CFG_OFS;
uint32_t regval = sys_read32(addr);
ds_ctx.smb_info[n] = regval;
sys_write32(regval & ~(MCHP_I2C_SMB_CFG_ENAB), addr);
}
#endif
/* Disable comparator if enabled */
if (ecs->CMP_CTRL & BIT(0)) {
ds_ctx.comp_en = 1;
ecs->CMP_CTRL &= ~(MCHP_ECS_ACC_EN0);
}
#if defined(CONFIG_TACH_XEC) || defined(CONFIG_PWM_XEC)
struct pcr_regs *pcr = PCR_XEC_REG_BASE;
/* This low-speed clock derived from the 48MHz clock domain is used as
* a time base for PWMs and TACHs
* Set SLOW_CLOCK_DIVIDE = CLKOFF to save additional power
*/
ds_ctx.slwclk_info = pcr->SLOW_CLK_CTRL;
pcr->SLOW_CLK_CTRL &= (~MCHP_PCR_SLOW_CLK_CTRL_100KHZ &
MCHP_PCR_SLOW_CLK_CTRL_MASK);
#endif
/* TFDP HW block is not expose to any Zephyr subsystem */
if (tfdp->CTRL & MCHP_TFDP_CTRL_EN) {
ds_ctx.tfdp_en = 1;
tfdp->CTRL &= ~MCHP_TFDP_CTRL_EN;
}
/* Port 80 TODO Do we need to do anything? MEC172x BDP does not
* include a timer so it should de-assert its CLK_REQ in response
* to SLP_EN 0->1.
*/
}
static void deep_sleep_restore_blocks(void)
{
struct tfdp_regs *tfdp = TFDP_0_XEC_REG_BASE;
struct ecs_regs *ecs = ECS_XEC_REG_BASE;
#ifdef CONFIG_ADC
struct adc_regs *adc0 = ADC_0_XEC_REG_BASE;
adc0->CONTROL |= MCHP_ADC_CTRL_ACTV;
#endif
#ifdef CONFIG_PECI
struct peci_regs *peci = PECI_XEC_REG_BASE;
ecs->PECI_DIS = ds_ctx.peci_info.peci_dis;
peci->CONTROL = ds_ctx.peci_info.peci_ctrl;
#endif
#ifdef CONFIG_I2C
for (size_t n = 0; n < MCHP_I2C_SMB_INSTANCES; n++) {
uint32_t addr = MCHP_I2C_SMB_BASE_ADDR(n) +
MCHP_I2C_SMB_CFG_OFS;
sys_write32(ds_ctx.smb_info[n], addr);
}
#endif
/* Restore comparator control values */
if (ds_ctx.comp_en) {
ecs->CMP_CTRL |= MCHP_ECS_ACC_EN0;
}
#if defined(CONFIG_TACH_XEC) || defined(CONFIG_PWM_XEC)
struct pcr_regs *pcr = PCR_XEC_REG_BASE;
/* Restore slow clock control */
pcr->SLOW_CLK_CTRL = ds_ctx.slwclk_info;
#endif
/* TFDP HW block is not expose to any Zephyr subsystem */
if (ds_ctx.tfdp_en) {
tfdp->CTRL |= MCHP_TFDP_CTRL_EN;
}
}
#endif /* DEEP_SLEEP_PERIPH_SAVE_RESTORE_EXTENDED */
void soc_deep_sleep_periph_save(void)
{
#ifdef DEEP_SLEEP_PERIPH_SAVE_RESTORE_EXTENDED
deep_sleep_save_blocks();
#endif
deep_sleep_save_ecs();
deep_sleep_save_timers();
#ifdef DEEP_SLEEP_UART_SAVE_RESTORE
deep_sleep_save_uarts();
#endif
}
void soc_deep_sleep_periph_restore(void)
{
deep_sleep_restore_ecs();
#ifdef DEEP_SLEEP_UART_SAVE_RESTORE
deep_sleep_restore_uarts();
#endif
deep_sleep_restore_timers();
#ifdef DEEP_SLEEP_PERIPH_SAVE_RESTORE_EXTENDED
deep_sleep_restore_blocks();
#endif
}
#else
void soc_deep_sleep_periph_save(void)
{
}
void soc_deep_sleep_periph_restore(void)
{
}
#endif /* DEEP_SLEEP_PERIPH_SAVE_RESTORE */

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/*
* Copyright (c) 2019 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __DEVICE_POWER_H
#define __DEVICE_POWER_H
#ifndef _ASMLANGUAGE
#define DEBUG_SLEEP
#define DEBUG_DEEP_SLEEP_CLK_REQ
/*
* Disable UART deep sleep save/restore. If a UART TX FIFO has data on deep
* sleep entry it will de-assert its CLK_REQ once TX FIFO empties. If the
* UART has TX empty interrupt enabled then the system will wake.
*/
/* #define DEEP_SLEEP_UART_SAVE_RESTORE */
/* Comment out to use JTAG without interruptions.
* Beware this blocks PLL going off, hence should be enabled
* for power consumption measurements
* Note: To attach JTAG for any debug need to be performed with breakpoint
* prior to deep sleep entry.
*/
/* #define DEEP_SLEEP_JTAG */
/*
* Enabling this would take a snapshot from clock requested values,
* these can be dump on exit to identify which HW block is blocking.
*/
#define DEEP_SLEEP_CLK_REQ_DUMP
/*
* Some peripherals if enabled always assert their CLK_REQ bits.
* For example, any peripheral with a clock generator such as
* timers, counters, UART, etc. We save the enables for these
* peripherals, disable them, and restore the enabled state upon
* wake.
*/
#define DEEP_SLEEP_PERIPH_SAVE_RESTORE
/* Power optimization if certain HW blocks are not used.
* These are not part of any Zephyr subsystem.
* #define DEEP_SLEEP_PERIPH_SAVE_RESTORE_EXTENDED
*/
#define DEEP_SLEEP_PERIPH_SAVE_RESTORE_EXTENDED
#define NUM_DS_TIMER_ENTRIES 6
struct ds_timer_info {
uintptr_t addr;
uint32_t stop_mask;
uint32_t restore_mask;
};
struct ds_peci_info {
uint32_t peci_ctrl;
uint32_t peci_dis;
};
struct ds_dev_info {
uint32_t ecs[2];
uint32_t timers[NUM_DS_TIMER_ENTRIES];
#ifdef DEEP_SLEEP_UART_SAVE_RESTORE
uint8_t uart_info[MCHP_UART_INSTANCES];
#endif
/* Analog power */
#ifdef CONFIG_PECI
struct ds_peci_info peci_info;
#endif
#ifdef CONFIG_I2C
uint32_t smb_info[MCHP_I2C_SMB_INSTANCES];
#endif
uint32_t slwclk_info;
uint8_t tfdp_en;
uint8_t comp_en;
};
void soc_deep_sleep_periph_save(void);
void soc_deep_sleep_periph_restore(void);
void soc_deep_sleep_non_wake_en(void);
void soc_deep_sleep_non_wake_dis(void);
void soc_deep_sleep_wake_en(void);
void soc_deep_sleep_wake_dis(void);
#ifdef DEBUG_DEEP_SLEEP_CLK_REQ
void soc_debug_sleep_clk_req(void);
#endif
#endif /* _ASMLANGUAGE */
#endif /* __DEVICE_POWER_H */

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/*
* Copyright (c) 2019 Microchip Technology Inc.
* Copyright (c) 2016 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/pm/pm.h>
#include <soc.h>
#include <zephyr/arch/cpu.h>
#include <cmsis_core.h>
#include "device_power.h"
#include "soc_power_debug.h"
#define HTMR_0_XEC_REG_BASE \
((struct htmr_regs *)(DT_REG_ADDR(DT_NODELABEL(hibtimer0))))
#define PCR_XEC_REG_BASE \
((struct pcr_regs *)(DT_REG_ADDR(DT_NODELABEL(pcr))))
/*
* Deep Sleep
* Pros:
* Lower power dissipation, 48MHz PLL is off
* Cons:
* Longer wake latency. CPU start running on ring oscillator
* between 16 to 25 MHz. Minimum 3ms until PLL reaches lock
* frequency of 48MHz.
*
* Implementation Notes:
* We touch the Cortex-M's primary mask and base priority registers
* because we do not want to enter an ISR immediately upon wake.
* We must restore any hardware state that was modified upon sleep
* entry before allowing interrupts to be serviced. Zephyr arch level
* does not provide API's to manipulate both primary mask and base priority.
*
* DEBUG NOTES:
* If a JTAG/SWD debug probe is connected driving TRST# high and
* possibly polling the DUT then MEC1501 will not shut off its 48MHz
* PLL. Firmware should not disable JTAG/SWD in the EC subsystem
* while a probe is using the interface. This can leave the JTAG/SWD
* TAP controller in a state of requesting clocks preventing the PLL
* from being shut off.
*/
/* NOTE: Zephyr masks interrupts using BASEPRI before calling PM subsystem */
static void z_power_soc_deep_sleep(void)
{
struct pcr_regs *pcr = PCR_XEC_REG_BASE;
struct htmr_regs *htmr0 = HTMR_0_XEC_REG_BASE;
uint32_t basepri = 0U;
uint32_t temp = 0U;
PM_DP_ENTER();
__disable_irq();
basepri = __get_BASEPRI();
soc_deep_sleep_periph_save();
soc_deep_sleep_wake_en();
soc_deep_sleep_non_wake_en();
/*
* Enable deep sleep mode in CM4 and MEC172x.
* Enable CM4 deep sleep and sleep signals assertion on WFI.
* Set MCHP Heavy sleep (PLL OFF when all CLK_REQ clear) and SLEEP_ALL
* to assert SLP_EN to all peripherals on WFI.
* Set PRIMASK = 1 so on wake the CPU will not vector to any ISR.
* Set BASEPRI = 0 to allow any priority to wake.
*/
SCB->SCR |= BIT(2);
pcr->SYS_SLP_CTRL = MCHP_PCR_SYS_SLP_HEAVY;
pcr->OSC_ID = pcr->SYS_SLP_CTRL;
#ifdef DEBUG_DEEP_SLEEP_CLK_REQ
soc_debug_sleep_clk_req();
#endif
__set_BASEPRI(0);
__WFI(); /* triggers sleep hardware */
__NOP();
__NOP();
/*
* Clear SLEEP_ALL manually since we are not vectoring to an ISR until
* PM post ops. This de-asserts peripheral SLP_EN signals.
*/
pcr->SYS_SLP_CTRL = 0U;
SCB->SCR &= ~BIT(2);
/* Wait for PLL to lock with timeout */
htmr0->PRLD = 0U; /* make sure its stopped */
htmr0->CTRL = 0U; /* 30.5 us per tick */
htmr0->PRLD = 216U; /* ~6.6 ms 2x the expected lock time */
temp = htmr0->PRLD;
while ((pcr->OSC_ID & MCHP_PCR_OSC_ID_PLL_LOCK) == 0) {
temp = htmr0->PRLD;
if (!temp) {
break;
}
}
htmr0->PRLD = 0U; /* stop */
__set_BASEPRI(basepri);
soc_deep_sleep_non_wake_dis();
soc_deep_sleep_wake_dis();
soc_deep_sleep_periph_restore();
PM_DP_EXIT();
}
/*
* Light Sleep
* Pros:
* Fast wake response:
* Cons:
* Higher power dissipation, 48MHz PLL remains on.
*
* When the kernel calls this it has masked interrupt by setting NVIC BASEPRI
* equal to a value equal to the highest Zephyr ISR priority. Only NVIC
* exceptions will be served.
*/
static void z_power_soc_sleep(void)
{
struct pcr_regs *pcr = PCR_XEC_REG_BASE;
__disable_irq();
SCB->SCR &= ~BIT(2);
pcr->SYS_SLP_CTRL = MCHP_PCR_SYS_SLP_LIGHT;
pcr->OSC_ID = pcr->SYS_SLP_CTRL;
__set_BASEPRI(0);
__WFI(); /* triggers sleep hardware */
__NOP();
__NOP();
pcr->SYS_SLP_CTRL = 0U;
}
/*
* Called from pm_system_suspend(int32_t ticks) in subsys/power.c
* For deep sleep pm_system_suspend has executed all the driver
* power management call backs.
*/
void pm_state_set(enum pm_state state, uint8_t substate_id)
{
ARG_UNUSED(substate_id);
switch (state) {
case PM_STATE_SUSPEND_TO_IDLE:
z_power_soc_sleep();
break;
case PM_STATE_SUSPEND_TO_RAM:
z_power_soc_deep_sleep();
break;
default:
break;
}
}
/*
* Zephyr PM code expects us to enabled interrupt at post op exit. Zephyr used
* arch_irq_lock() which sets BASEPRI to a non-zero value masking interrupts at
* >= numerical priority. MCHP z_power_soc_(deep)_sleep sets PRIMASK=1 and BASEPRI=0
* allowing wake from any enabled interrupt and prevents the CPU from entering any
* ISR on wake except for faults. We re-enable interrupts by undoing global disable
* and alling irq_unlock with the same value, 0 zephyr core uses.
*/
void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
{
__enable_irq();
irq_unlock(0);
}

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MEC172X_GPIO_LJ_H
#define _MEC172X_GPIO_LJ_H
#define MCHP_GPIO_PORT_A_BITMAP 0x7FFFFFFFu /* GPIO_0000 - 0036 GIRQ11 */
#define MCHP_GPIO_PORT_B_BITMAP 0x7FFFFFFFu /* GPIO_0040 - 0076 GIRQ10 */
#define MCHP_GPIO_PORT_C_BITMAP 0x3FFFFFF7u /* GPIO_0100 - 0136 GIRQ09 */
#define MCHP_GPIO_PORT_D_BITMAP 0x3F67FFFFu /* GPIO_0140 - 0176 GIRQ08 */
#define MCHP_GPIO_PORT_E_BITMAP 0x7FFFFFFFu /* GPIO_0200 - 0236 GIRQ12 */
#define MCHP_GPIO_PORT_F_BITMAP 0x00003F7Fu /* GPIO_0240 - 0276 GIRQ26 */
#endif /* #ifndef _MEC172X_GPIO_LJ_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MEC172X_GPIO_SZ_H
#define _MEC172X_GPIO_SZ_H
#include <stdint.h>
#include <stddef.h>
/* MEC172XH-B0-SZ (144-pin) */
#define MCHP_GPIO_PORT_A_BITMAP 0x7FFFFF9Du /* GPIO_0000 - 0036 GIRQ11 */
#define MCHP_GPIO_PORT_B_BITMAP 0x7FFFFFFDu /* GPIO_0040 - 0076 GIRQ10 */
#define MCHP_GPIO_PORT_C_BITMAP 0x07FFFCF7u /* GPIO_0100 - 0136 GIRQ09 */
#define MCHP_GPIO_PORT_D_BITMAP 0x272EFFFFu /* GPIO_0140 - 0176 GIRQ08 */
#define MCHP_GPIO_PORT_E_BITMAP 0x00DE00FFu /* GPIO_0200 - 0236 GIRQ12 */
#define MCHP_GPIO_PORT_F_BITMAP 0x0000397Fu /* GPIO_0240 - 0276 GIRQ26 */
#endif /* #ifndef _MEC172X_GPIO_SZ_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef MEC172X_DEFS_H
#define MEC172X_DEFS_H
#include <stddef.h>
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
* Delay register address. Write n to delay for n + 1 microseconds where
* 0 <= n <= 31.
* Implementation stalls the CPU fetching instructions including blocking
* interrupts.
*/
#define MCHP_DELAY_US_ADDR 0x08000000u
/* ARM Cortex-M4 input clock from PLL */
#define MCHP_EC_CLOCK_INPUT_HZ 96000000u
#define MCHP_ACMP_INSTANCES 1
#define MCHP_ACPI_EC_INSTANCES 5
#define MCHP_ACPI_PM1_INSTANCES 1
#define MCHP_ADC_INSTANCES 1
#define MCHP_BCL_INSTANCES 1
#define MCHP_BTMR16_INSTANCES 4
#define MCHP_BTMR32_INSTANCES 2
#define MCHP_CCT_INSTANCES 1
#define MCHP_CTMR_INSTANCES 4
#define MCHP_DMA_INSTANCES 1
#define MCHP_ECIA_INSTANCES 1
#define MCHP_EMI_INSTANCES 3
#define MCHP_HTMR_INSTANCES 2
#define MCHP_I2C_INSTANCES 0
#define MCHP_I2C_SMB_INSTANCES 5
#define MCHP_LED_INSTANCES 4
#define MCHP_MBOX_INSTANCES 1
#define MCHP_OTP_INSTANCES 1
#define MCHP_P80BD_INSTANCES 1
#define MCHP_PECI_INSTANCES 1
#define MCHP_PROCHOT_INSTANCES 1
#define MCHP_PS2_INSTANCES 1
#define MCHP_PWM_INSTANCES 9
#define MCHP_QMSPI_INSTANCES 1
#define MCHP_RCID_INSTANCES 3
#define MCHP_RPMFAN_INSTANCES 2
#define MCHP_RTC_INSTANCES 1
#define MCHP_RTMR_INSTANCES 1
#define MCHP_SPIP_INSTANCES 1
#define MCHP_TACH_INSTANCES 4
#define MCHP_TFDP_INSTANCES 1
#define MCHP_UART_INSTANCES 2
#define MCHP_WDT_INSTANCES 1
#define MCHP_WKTMR_INSTANCES 1
#define MCHP_ACMP_CHANNELS 2
#define MCHP_ADC_CHANNELS 8
#define MCHP_BGPO_GPIO_PINS 2
#define MCHP_DMA_CHANNELS 16
#define MCHP_ESPI_SAF_TAGMAP_MAX 3
#define MCHP_GIRQS 19
#define MCHP_GPIO_PINS 123
#define MCHP_GPIO_PORTS 6
#define MCHP_GPTP_PORTS 6
#define MCHP_I2C_SMB_PORTS 15
#define MCHP_I2C_PORTMAP 0xf7ffu
#define MCHP_QMSPI_PORTS 3
#define MCHP_PS2_PORTS 2
#define MCHP_VCI_IN_PINS 4
#define MCHP_VCI_OUT_PINS 1
#define MCHP_VCI_OVRD_IN_PINS 1
#define SHLU32(v, n) ((uint32_t)(v) << (n))
#ifdef __cplusplus
}
#endif
#endif /* MEC172X_DEFS_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <stddef.h>
#ifndef _MEC172X_ECS_H
#define _MEC172X_ECS_H
/* AHB Error Address, write any value to clear */
#define MCHP_ECS_AHB_ERR_ADDR_OFS 0x04u
/* AHB Error Control */
#define MCHP_ECS_AHB_ERR_CTRL_OFS 0x14u
#define MCHP_ECS_AHB_ERR_CTRL_DIS_POS 0
#define MCHP_ECS_AHB_ERR_CTRL_DIS BIT(MCHP_ECS_AHB_ERR_CTRL_DIS_POS)
/* Interrupt Control */
#define MCHP_ECS_ICTRL_OFS 0x18u
#define MCHP_ECS_ICTRL_DIRECT_POS 0
#define MCHP_ECS_ICTRL_DIRECT_EN BIT(MCHP_ECS_ICTRL_DIRECT_POS)
/* ETM Control Register */
#define MCHP_ECS_ETM_CTRL_OFS 0x1cu
#define MCHP_ECS_ETM_CTRL_EN_POS 0
#define MCHP_ECS_ETM_CTRL_EN BIT(MCHP_ECS_ETM_CTRL_EN_POS)
/* Debug Control Register */
#define MCHP_ECS_DCTRL_OFS 0x20u
#define MCHP_ECS_DCTRL_MASK 0x1fu
#define MCHP_ECS_DCTRL_DBG_EN_POS 0u
#define MCHP_ECS_DCTRL_DBG_EN BIT(MCHP_ECS_DCTRL_DBG_EN_POS)
#define MCHP_ECS_DCTRL_MODE_POS 1u
#define MCHP_ECS_DCTRL_MODE_MASK0 0x03u
#define MCHP_ECS_DCTRL_MODE_MASK \
SHLU32(MCHP_ECS_DCTRL_DBG_MODE_MASK0, MCHP_ECS_DCTRL_DBG_MODE_POS)
#define MCHP_ECS_DCTRL_DBG_MODE_POS 1u
#define MCHP_ECS_DCTRL_MODE_JTAG 0x00u
#define MCHP_ECS_DCTRL_MODE_SWD SHLU32(0x02u, 1u)
#define MCHP_ECS_DCTRL_MODE_SWD_SWV SHLU32(0x01u, 1u)
#define MCHP_ECS_DCTRL_PUEN_POS 3u
#define MCHP_ECS_DCTRL_PUEN BIT(MCHP_ECS_DCTRL_PUEN_POS)
#define MCHP_ECS_DCTRL_BSCAN_POS 4u
#define MCHP_ECS_DCTRL_BSCAN_EN BIT(MCHP_ECS_DCTRL_BSCAN_POS)
/* WDT Event Count */
#define MCHP_ECS_WDT_EVC_OFS 0x28u
#define MCHP_ECS_WDT_EVC_MASK 0x0fu
/* PECI Disable */
#define MCHP_ECS_PECI_DIS_OFS 0x40u
#define MCHP_ECS_PECI_DIS_MASK 0x01u
#define MCHP_ECS_PECI_DIS_POS 0
#define MCHP_ECS_PECI_DISABLE BIT(0)
/* VCI FW Override */
#define MCHP_ECS_VCI_FW_OVR_OFS 0x50u
#define MCHP_ECS_VCI_FW_OVR_MASK 0x01u
#define MCHP_ECS_VCI_FW_OVR_SSHD_POS 0
#define MCHP_ECS_VCI_FW_OVR_SSHD BIT(0)
/* Boot-ROM Status */
#define MCHP_ECS_BROM_STS_OFS 0x54u
#define MCHP_ECS_BROM_STS_MASK 0x03u
#define MCHP_ECS_BROM_STS_VTR_POS 0
#define MCHP_ECS_BROM_STS_WDT_POS 1
#define MCHP_ECS_BROM_STS_VTR BIT(0)
#define MCHP_ECS_BROM_STS_WDT BIT(1)
/* JTAG Controller Config */
#define MCHP_ECS_JTCC_OFS 0x70u
#define MCHP_ECS_JTCC_MASK 0x0fu
#define MCHP_ECS_JTCC_CLK_POS 0
#define MCHP_ECS_JTCC_CLK_DFLT 3u
#define MCHP_ECS_JTCC_CLK_24M 1u
#define MCHP_ECS_JTCC_CLK_12M 2u
#define MCHP_ECS_JTCC_CLK_6M 3u
#define MCHP_ECS_JTCC_CLK_3M 4u
#define MCHP_ECS_JTCC_CLK_1500K 5u
#define MCHP_ECS_JTCC_CLK_750K 6u
#define MCHP_ECS_JTCC_CLK_375K 7u
#define MCHP_ECS_JTCC_MS_POS 3
#define MCHP_ECS_JTCC_M BIT(3)
/* JTAG Controller Status */
#define MCHP_ECS_JTST_OFS 0x74u
#define MCHP_ECS_JTST_MASK 0x01u
#define MCHP_ECS_JTST_DONE BIT(0)
#define MCHP_ECS_JT_TDO_OFS 0x78u
#define MCHP_ECS_JT_TDI_OFS 0x7cu
#define MCHP_ECS_JT_TMS_OFS 0x80u
/* JTAG Controller Command */
#define MCHP_ECS_JT_CMD_OFS 0x84u
#define MCHP_ECS_JT_CMD_MASK 0x1fu
/* VWire Source Configuration */
#define MCHP_ECS_VWSC_OFS 0x90u
#define MCHP_ECS_VWSC_MASK 0x07u
#define MCHP_ECS_VWSC_DFLT 0x07u
#define MCHP_ECS_VWSC_EC_SCI_DIS BIT(0)
#define MCHP_ECS_VWSC_MBH_SMI_DIS BIT(1)
/* Analog Comparator Control */
#define MCHP_ECS_ACC_OFS 0x94u
#define MCHP_ECS_ACC_MASK 0x15u
#define MCHP_ECS_ACC_EN0 BIT(0)
#define MCHP_ECS_ACC_CFG_LOCK0 BIT(2)
#define MCHP_ECS_ACC_EN1 BIT(4)
/* Analog Comparator Sleep Control */
#define MCHP_ECS_ACSC_OFS 0x98u
#define MCHP_ECS_ACSC_MASK 0x03u
#define MCHP_ECS_ACSC_DSLP_EN0 BIT(0)
#define MCHP_ECS_ACSC_DSLP_EN1 BIT(1)
/* Embedded Reset Enable */
#define MCHP_ECS_EMBR_EN_OFS 0xb0u
#define MCHP_ECS_EMBR_EN_MASK 0x01u
#define MCHP_ECS_EMBR_EN_ON BIT(0)
/* Embedded Reset Timeout value */
#define MCHP_ECS_EMBR_TMOUT_OFS 0xb4u
#define MCHP_ECS_EMBR_TMOUT_MASK 0x07u
#define MCHP_ECS_EMBR_TMOUT_6S 0u
#define MCHP_ECS_EMBR_TMOUT_7S 1u
#define MCHP_ECS_EMBR_TMOUT_8S 2u
#define MCHP_ECS_EMBR_TMOUT_9S 3u
#define MCHP_ECS_EMBR_TMOUT_10S 4u
#define MCHP_ECS_EMBR_TMOUT_11S 5u
#define MCHP_ECS_EMBR_TMOUT_12S 6u
#define MCHP_ECS_EMBR_TMOUT_14S 7u
/* Embedded Reset Status */
#define MCHP_ECS_EMBR_STS_OFS 0xb8u
#define MCHP_ECS_EMBR_STS_MASK 0x01u
#define MCHP_ECS_EMBR_STS_RST BIT(0)
/* Embedded Reset Count (RO) */
#define MCHP_ECS_EMBR_CNT_OFS 0xbcu
#define MCHP_ECS_EMBR_CNT_MASK 0x7ffffu
/** @brief EC Subsystem (ECS) */
struct ecs_regs {
uint32_t RSVD1[1];
volatile uint32_t AHB_ERR_ADDR; /* +0x04 */
uint32_t RSVD2[2];
volatile uint32_t OSC_ID; /* +0x10 */
volatile uint32_t AHB_ERR_CTRL; /* +0x14 */
volatile uint32_t INTR_CTRL; /* +0x18 */
volatile uint32_t ETM_CTRL; /* +0x1c */
volatile uint32_t DEBUG_CTRL; /* +0x20 */
volatile uint32_t OTP_LOCK; /* +0x24 */
volatile uint32_t WDT_CNT; /* +0x28 */
uint32_t RSVD3[5];
volatile uint32_t PECI_DIS; /* +0x40 */
uint32_t RSVD4[3];
volatile uint32_t VCI_FW_OVR; /* +0x50 */
volatile uint32_t BROM_STS; /* +0x54 */
volatile uint32_t CRYPTO_CFG; /* +0x58 */
uint32_t RSVD6[5];
volatile uint32_t JTAG_MCFG; /* +0x70 */
volatile uint32_t JTAG_MSTS; /* +0x74 */
volatile uint32_t JTAG_MTDO; /* +0x78 */
volatile uint32_t JTAG_MTDI; /* +0x7c */
volatile uint32_t JTAG_MTMS; /* +0x80 */
volatile uint32_t JTAG_MCMD; /* +0x84 */
volatile uint32_t VCI_OUT_SEL; /* +0x88 */
uint32_t RSVD7[1];
volatile uint32_t VW_FW_OVR; /* +0x90 */
volatile uint32_t CMP_CTRL; /* +0x94 */
volatile uint32_t CMP_SLP_CTRL; /* +0x98 */
uint32_t RSVD8[(0xb0 - 0x9c) / 4];
volatile uint32_t EMB_RST_EN1; /* +0xb0 */
volatile uint32_t EMB_RST_TMOUT1; /* +0xb4 */
volatile uint32_t EMB_RST_STS; /* +0xb8 */
volatile uint32_t EMB_RST_CNT; /* +0xbc */
uint32_t RSVD9[(0x144 - 0xc0) / 4];
volatile uint32_t SLP_STS_MIRROR; /* +0x144 */
};
#endif /* #ifndef _MEC172X_ECS_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MEC172X_EMI_H
#define _MEC172X_EMI_H
#include <stdint.h>
#include <stddef.h>
/** @brief Embedded Memory Interface (EMI) Registers */
struct emi_regs {
volatile uint8_t RT_HOST_TO_EC;
volatile uint8_t RT_EC_TO_HOST;
volatile uint8_t EC_ADDR_LSB;
volatile uint8_t EC_ADDR_MSB;
volatile uint8_t EC_DATA_0; /* +0x04 */
volatile uint8_t EC_DATA_1;
volatile uint8_t EC_DATA_2;
volatile uint8_t EC_DATA_3;
volatile uint8_t INTR_SRC_LSB; /* +0x08 */
volatile uint8_t INTR_SRC_MSB;
volatile uint8_t INTR_MSK_LSB;
volatile uint8_t INTR_MSK_MSB;
volatile uint8_t APPID; /* +0x0C */
uint8_t RSVD1[3];
volatile uint8_t APPID_ASSGN; /* +0x10 */
uint8_t RSVD2[3];
uint32_t RSVD3[(0x100 - 0x14) / 4];
volatile uint8_t HOST_TO_EC; /* +0x100 */
volatile uint8_t EC_TO_HOST;
uint16_t RSVD4[1];
volatile uint32_t MEM_BA_0; /* +0x104 */
volatile uint16_t MEM_RL_0; /* +0x108 */
volatile uint16_t MEM_WL_0;
volatile uint32_t MEM_BA_1; /* +0x10C */
volatile uint16_t MEM_RL_1; /* +0x110 */
volatile uint16_t MEM_WL_1;
volatile uint16_t INTR_SET; /* +0x114 */
volatile uint16_t HOST_CLR_EN; /* +0x116 */
uint32_t RSVD5[2];
volatile uint32_t APPID_STS_1; /* +0x120 */
volatile uint32_t APPID_STS_2;
volatile uint32_t APPID_STS_3;
volatile uint32_t APPID_STS_4;
};
#endif /* #ifndef _MEC172X_EMI_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MEC172X_ESPI_IO_H
#define _MEC172X_ESPI_IO_H
#include <stdint.h>
#include <stddef.h>
/* Offsets from base for various register groups */
#define MCHP_ESPI_IO_PC_OFS 0x0100u
#define MCHP_ESPI_IO_HOST_BAR_OFS 0x0120u
#define MCHP_ESPI_IO_LTR_OFS 0x0220u
#define MCHP_ESPI_IO_OOB_OFS 0x0240u
#define MCHP_ESPI_IO_FC_OFS 0x0280u
#define MCHP_ESPI_IO_CAP_OFS 0x02b0u
#define MCHP_ESPI_IO_SIRQ_OFS 0x03a0u
/* eSPI Global Capabilities 0 */
#define MCHP_ESPI_GBL_CAP0_MASK 0x0fu
#define MCHP_ESPI_GBL_CAP0_PC_SUPP BIT(0)
#define MCHP_ESPI_GBL_CAP0_VW_SUPP BIT(1)
#define MCHP_ESPI_GBL_CAP0_OOB_SUPP BIT(2)
#define MCHP_ESPI_GBL_CAP0_FC_SUPP BIT(3)
/* eSPI Global Capabilities 1 */
#define MCHP_ESPI_GBL_CAP1_MASK 0xffu
#define MCHP_ESPI_GBL_CAP1_MAX_FREQ_POS 0u
#define MCHP_ESPI_GBL_CAP1_MAX_FREQ_MASK 0x07u
#define MCHP_ESPI_GBL_CAP1_MAX_FREQ_20M 0x00u
#define MCHP_ESPI_GBL_CAP1_MAX_FREQ_25M 0x01u
#define MCHP_ESPI_GBL_CAP1_MAX_FREQ_33M 0x02u
#define MCHP_ESPI_GBL_CAP1_MAX_FREQ_50M 0x03u
#define MCHP_ESPI_GBL_CAP1_MAX_FREQ_66M 0x04u
#define MCHP_ESPI_GBL_CAP1_ALERT_POS 3u /* Read-Only */
#define MCHP_ESPI_GBL_CAP1_ALERT_DED_PIN \
BIT(MCHP_ESPI_GBL_CAP1_ALERT_POS)
#define MCHP_ESPI_GBL_CAP1_ALERT_ON_IO1 0u
#define MCHP_ESPI_GBL_CAP1_IO_MODE_POS 4u
#define MCHP_ESPI_GBL_CAP1_IO_MODE_MASK0 0x03u
#define MCHP_ESPI_GBL_CAP1_IO_MODE_MASK SHLU32(0x03u, 4)
#define MCHP_ESPI_GBL_CAP1_IO_MODE0_1 0u
#define MCHP_ESPI_GBL_CAP1_IO_MODE0_12 1u
#define MCHP_ESPI_GBL_CAP1_IO_MODE0_14 2u
#define MCHP_ESPI_GBL_CAP1_IO_MODE0_124 3u
#define MCHP_ESPI_GBL_CAP1_IO_MODE_1 \
SHLU32(MCHP_ESPI_GBL_CAP1_IO_MODE0_1, MCHP_ESPI_GBL_CAP1_IO_MODE_POS)
#define MCHP_ESPI_GBL_CAP1_IO_MODE_12 \
SHLU32(MCHP_ESPI_GBL_CAP1_IO_MODE0_12, MCHP_ESPI_GBL_CAP1_IO_MODE_POS)
#define MCHP_ESPI_GBL_CAP1_IO_MODE_14 \
SHLU32(MCHP_ESPI_GBL_CAP1_IO_MODE0_14, MCHP_ESPI_GBL_CAP1_IO_MODE_POS)
#define MCHP_ESPI_GBL_CAP1_IO_MODE_124 \
SHLU32(MCHP_ESPI_GBL_CAP1_IO_MODE0_124, MCHP_ESPI_GBL_CAP1_IO_MODE_POS)
/*
* Support Open Drain ALERT pin configuration
* EC sets this bit if it can support open-drain ESPI_ALERT#
*/
#define MCHP_ESPI_GBL_CAP1_ALERT_ODS_POS 6u
#define MCHP_ESPI_GBL_CAP1_ALERT_ODS BIT(MCHP_ESPI_GBL_CAP1_ALERT_ODS_POS)
/*
* Read-Only ALERT Open Drain select.
* If EC has indicated it can support open-drain ESPI_ALERT# then
* the Host can enable open-drain ESPI_ALERT# by sending a configuration
* message. This read-only bit reflects the configuration selection.
*/
#define MCHP_ESPI_GBL_CAP1_ALERT_ODS_SEL_POS 7u
#define MCHP_ESPI_GBL_CAP1_ALERT_SEL_ODS \
BIT(MCHP_ESPI_GBL_CAP1_ALERT_ODS_SEL_POS)
/* Peripheral Channel(PC) Capabilities */
#define MCHP_ESPI_PC_CAP_MASK 0x07u
#define MCHP_ESPI_PC_CAP_MAX_PLD_SZ_MASK 0x07u
#define MCHP_ESPI_PC_CAP_MAX_PLD_SZ_64 0x01u
#define MCHP_ESPI_PC_CAP_MAX_PLD_SZ_128 0x02u
#define MCHP_ESPI_PC_CAP_MAX_PLD_SZ_256 0x03u
/* Virtual Wire(VW) Capabilities */
#define MCHP_ESPI_VW_CAP_MASK 0x3fu
#define MCHP_ESPI_VW_CAP_MAX_VW_CNT_MASK 0x3fu
/* Out-of-Band(OOB) Capabilities */
#define MCHP_ESPI_OOB_CAP_MASK 0x07u
#define MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_MASK 0x07u
#define MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_73 0x01u
#define MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_137 0x02u
#define MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_265 0x03u
/* Flash Channel(FC) Capabilities */
#define MCHP_ESPI_FC_CAP_MASK 0xffu
#define MCHP_ESPI_FC_CAP_MAX_PLD_SZ_MASK 0x07u
#define MCHP_ESPI_FC_CAP_MAX_PLD_SZ_64 0x01u
#define MCHP_ESPI_FC_CAP_SHARE_POS 3u
#define MCHP_ESPI_FC_CAP_SHARE_MASK0 0x03u
#define MCHP_ESPI_FC_CAP_SHARE_MASK \
SHLU32(MCHP_ESPI_FC_CAP_SHARE_MASK0, MCHP_ESPI_FC_CAP_SHARE_POS)
#define MCHP_ESPI_FC_CAP_SHARE_MAF_ONLY 0u
#define MCHP_ESPI_FC_CAP_SHARE_MAF2_ONLY \
SHLU32(1U, MCHP_ESPI_FC_CAP_SHARE_POS)
#define MCHP_ESPI_FC_CAP_SHARE_SAF_ONLY \
SHLU32(2U, MCHP_ESPI_FC_CAP_SHARE_POS)
#define MCHP_ESPI_FC_CAP_SHARE_MAF_SAF \
SHLU32(3U, MCHP_ESPI_FC_CAP_SHARE_POS)
#define MCHP_ESPI_FC_CAP_MAX_RD_SZ_POS 5u
#define MCHP_ESPI_FC_CAP_MAX_RD_SZ_MASK0 0x07u
#define MCHP_ESPI_FC_CAP_MAX_RD_SZ_MASK \
SHLU32(MCHP_ESPI_FC_CAP_MAX_RD_SZ_MASK0, \
MCHP_ESPI_FC_CAP_MAX_RD_SZ_POS)
#define MCHP_ESPI_FC_CAP_MAX_RD_SZ_64 \
BIT(MCHP_ESPI_FC_CAP_MAX_RD_SZ_POS)
/* PC Ready */
#define MCHP_ESPI_PC_READY_MASK 0x01u;
#define MCHP_ESPI_PC_READY 0x01u;
/* OOB Ready */
#define MCHP_ESPI_OOB_READY_MASK 0x01u;
#define MCHP_ESPI_OOB_READY 0x01u;
/* FC Ready */
#define MCHP_ESPI_FC_READY_MASK 0x01u;
#define MCHP_ESPI_FC_READY 0x01u;
/* ESPI_RESET# Interrupt Status */
#define MCHP_ESPI_RST_ISTS_MASK 0x03u;
#define MCHP_ESPI_RST_ISTS_POS 0u
#define MCHP_ESPI_RST_ISTS BIT(MCHP_ESPI_RST_ISTS_POS)
#define MCHP_ESPI_RST_ISTS_PIN_RO_POS 1u
#define MCHP_ESPI_RST_ISTS_PIN_RO_HI BIT(MCHP_ESPI_RST_ISTS_PIN_RO_POS)
/* ESPI_RESET# Interrupt Enable */
#define MCHP_ESPI_RST_IEN_MASK 0x01u
#define MCHP_ESPI_RST_IEN 0x01u
/* eSPI Platform Reset Source */
#define MCHP_ESPI_PLTRST_SRC_MASK 0x01u
#define MCHP_ESPI_PLTRST_SRC_POS 0u
#define MCHP_ESPI_PLTRST_SRC_IS_PIN 0x01u
#define MCHP_ESPI_PLTRST_SRC_IS_VW 0x00u
/* VW Ready */
#define MCHP_ESPI_VW_READY_MASK 0x01u
#define MCHP_ESPI_VW_READY 0x01u
/* SAF Erase Block size */
#define MCHP_ESPI_SERASE_SZ_1K_BITPOS 0
#define MCHP_ESPI_SERASE_SZ_2K_BITPOS 1
#define MCHP_ESPI_SERASE_SZ_4K_BITPOS 2
#define MCHP_ESPI_SERASE_SZ_8K_BITPOS 3
#define MCHP_ESPI_SERASE_SZ_16K_BITPOS 4
#define MCHP_ESPI_SERASE_SZ_32K_BITPOS 5
#define MCHP_ESPI_SERASE_SZ_64K_BITPOS 6
#define MCHP_ESPI_SERASE_SZ_128K_BITPOS 7
#define MCHP_ESPI_SERASE_SZ_1K BIT(0)
#define MCHP_ESPI_SERASE_SZ_2K BIT(1)
#define MCHP_ESPI_SERASE_SZ_4K BIT(2)
#define MCHP_ESPI_SERASE_SZ_8K BIT(3)
#define MCHP_ESPI_SERASE_SZ_16K BIT(4)
#define MCHP_ESPI_SERASE_SZ_32K BIT(5)
#define MCHP_ESPI_SERASE_SZ_64K BIT(6)
#define MCHP_ESPI_SERASE_SZ_128K BIT(7)
#define MCHP_ESPI_SERASE_SZ(bitpos) BIT((bitpos) + 10u)
/* VW Error Status */
#define MCHP_ESPI_VW_ERR_STS_MASK 0x33u
#define MCHP_ESPI_VW_ERR_STS_FATAL_POS 0u
#define MCHP_ESPI_VW_ERR_STS_FATAL_RO \
BIT(MCHP_ESPI_VW_ERR_STS_FATAL_POS)
#define MCHP_ESPI_VW_ERR_STS_FATAL_CLR_POS 1u
#define MCHP_ESPI_VW_ERR_STS_FATAL_CLR_WO \
BIT(MCHP_ESPI_VW_ERR_STS_FATAL_CLR_POS)
#define MCHP_ESPI_VW_ERR_STS_NON_FATAL_POS 4u
#define MCHP_ESPI_VW_ERR_STS_NON_FATAL_RO \
BIT(MCHP_ESPI_VW_ERR_STS_NON_FATAL_POS)
#define MCHP_ESPI_VW_ERR_STS_NON_FATAL_CLR_POS 5u
#define MCHP_ESPI_VW_ERR_STS_NON_FATAL_CLR_WO \
BIT(MCHP_ESPI_VW_ERR_STS_NON_FATAL_CLR_POS)
/* VW Channel Enable Status */
#define MCHP_ESPI_VW_EN_STS_MASK 0x01u
#define MCHP_ESPI_VW_EN_STS_RO 0x01u
/*
* MCHP_ESPI_IO_PC - eSPI IO Peripheral Channel registers @ 0x400F3500
*/
/* Peripheral Channel Last Cycle length, type, and tag. */
#define MCHP_ESPI_PC_LC_LEN_POS 0u
#define MCHP_ESPI_PC_LC_LEN_MASK0 0x0fffu
#define MCHP_ESPI_PC_LC_LEN_MASK 0x0fffu
#define MCHP_ESPI_PC_LC_TYPE_POS 12u
#define MCHP_ESPI_PC_LC_TYPE_MASK0 0xffu
#define MCHP_ESPI_PC_LC_TYPE_MASK (0xffu << 12)
#define MCHP_ESPI_PC_LC_TAG_POS 20u
#define MCHP_ESPI_PC_LC_TAG_MASK0 0x0fu
#define MCHP_ESPI_PC_LC_TAG_MASK (0x0fu << 20)
/*
* Peripheral Channel Status
* Bus error, Channel enable change, and Bus master enable change.
*/
#define MCHP_ESPI_PC_STS_BUS_ERR_POS 16u /* RW1C */
#define MCHP_ESPI_PC_STS_BUS_ERR BIT(MCHP_ESPI_PC_STS_BUS_ERR_POS)
#define MCHP_ESPI_PC_STS_EN_POS 24u /* RO */
#define MCHP_ESPI_PC_STS_EN BIT(MCHP_ESPI_PC_STS_EN_POS)
#define MCHP_ESPI_PC_STS_EN_CHG_POS 25u /* RW1C */
#define MCHP_ESPI_PC_STS_EN_CHG BIT(MCHP_ESPI_PC_STS_EN_CHG_POS)
#define MCHP_ESPI_PC_STS_BM_EN_POS 27u /* RO */
#define MCHP_ESPI_PC_STS_BM_EN BIT(MCHP_ESPI_PC_STS_BM_EN_POS)
#define MCHP_ESPI_PC_STS_BM_EN_CHG_POS 28u /* RW1C */
#define MCHP_ESPI_PC_STS_BM_EN_CHG BIT(MCHP_ESPI_PC_STS_BM_EN_CHG_POS)
/*
* Peripheral Channel Interrupt Enables for
* Bus error, Channel enable change, and Bus master enable change.
* PC_LC_ADDR_LSW (@ 0x0000) Periph Chan Last Cycle address LSW
* PC_LC_ADDR_MSW (@ 0x0004) Periph Chan Last Cycle address MSW
* PC_LC_LEN_TYPE_TAG (@ 0x0008) Periph Chan Last Cycle length/type/tag
* PC_ERR_ADDR_LSW (@ 0x000C) Periph Chan Error Address LSW
* PC_ERR_ADDR_MSW (@ 0x0010) Periph Chan Error Address MSW
* PC_STATUS (@ 0x0014) Periph Chan Status
* PC_IEN (@ 0x0018) Periph Chan IEN
*/
#define MCHP_ESPI_PC_IEN_BUS_ERR_POS 16u
#define MCHP_ESPI_PC_IEN_BUS_ERR BIT(MCHP_ESPI_PC_IEN_BUS_ERR_POS)
#define MCHP_ESPI_PC_IEN_EN_CHG_POS 25u
#define MCHP_ESPI_PC_IEN_EN_CHG BIT(MCHP_ESPI_PC_IEN_BUS_ERR_POS)
#define MCHP_ESPI_PC_IEN_BM_EN_CHG_POS 28u
#define MCHP_ESPI_PC_IEN_BM_EN_CHG BIT(MCHP_ESPI_PC_IEN_BUS_ERR_POS)
/*---- ESPI_IO_LTR - eSPI IO LTR registers ----*/
#define MCHP_ESPI_LTR_STS_TX_DONE_POS 0u /* RW1C */
#define MCHP_ESPI_LTR_STS_TX_DONE BIT(MCHP_ESPI_LTR_STS_TX_DONE_POS)
#define MCHP_ESPI_LTR_STS_OVRUN_POS 3u /* RW1C */
#define MCHP_ESPI_LTR_STS_OVRUN BIT(MCHP_ESPI_LTR_STS_OVRUN_POS)
#define MCHP_ESPI_LTR_STS_HDIS_POS 4u /* RW1C */
#define MCHP_ESPI_LTR_STS_HDIS BIT(MCHP_ESPI_LTR_STS_HDIS_POS)
#define MCHP_ESPI_LTR_STS_TX_BUSY_POS 8u /* RO */
#define MCHP_ESPI_LTR_STS_TX_BUSY BIT(MCHP_ESPI_LTR_STS_TX_BUSY_POS)
#define MCHP_ESPI_LTR_IEN_TX_DONE_POS 0u
#define MCHP_ESPI_LTR_IEN_TX_DONE BIT(MCHP_ESPI_LTR_IEN_TX_DONE_POS)
#define MCHP_ESPI_LTR_CTRL_START_POS 0u
#define MCHP_ESPI_LTR_CTRL_START BIT(MCHP_ESPI_LTR_CTRL_START_POS)
#define MCHP_ESPI_LTR_CTRL_TAG_POS 8u
#define MCHP_ESPI_LTR_CTRL_TAG_MASK0 0x0fu
#define MCHP_ESPI_LTR_CTRL_TAG_MASK \
SHLU32(MCHP_ESPI_LTR_CTRL_TAG_MASK0, MCHP_ESPI_LTR_CTRL_TAG_POS)
#define MCHP_ESPI_LTR_MSG_VAL_POS 0u
#define MCHP_ESPI_LTR_MSG_VAL_MASK0 0x3ffu
#define MCHP_ESPI_LTR_MSG_VAL_MASK \
SHLU32(MCHP_ESPI_LTR_MSG_VAL_MASK0, MCHP_ESPI_LTR_MSG_VAL_POS)
#define MCHP_ESPI_LTR_MSG_SC_POS 10u
#define MCHP_ESPI_LTR_MSG_SC_MASK0 0x07u
#define MCHP_ESPI_LTR_MSG_SC_MASK \
SHLU32(MCHP_ESPI_LTR_MSG_SC_MASK0, MCHP_ESPI_LTR_MSG_SC_POS)
#define MCHP_ESPI_LTR_MSG_RT_POS 13u
#define MCHP_ESPI_LTR_MSG_RT_MASK0 0x03u
#define MCHP_ESPI_LTR_MSG_RT_MASK \
SHLU32(MCHP_ESPI_LTR_MSG_RT_MASK0, MCHP_ESPI_LTR_MSG_RT_POS)
/* eSPI specification indicates RT field must be 00b */
#define MCHP_ESPI_LTR_MSG_RT_VAL 0u
#define MCHP_ESPI_LTR_MSG_REQ_POS 15u
/* infinite latency(default) */
#define MCHP_ESPI_LTR_MSG_REQ_INF 0u
/* latency computed from VAL and SC(scale) fields */
#define MCHP_ESPI_LTR_MSG_REQ_VAL BIT(MCHP_ESPI_LTR_MSG_REQ_POS)
/*---- ESPI_IO_OOB - eSPI IO OOB registers ----*/
#define MCHP_ESPI_OOB_RX_ADDR_LSW_MASK 0xfffffffcu
#define MCHP_ESPI_OOB_TX_ADDR_LSW_MASK 0xfffffffcu
/* OOB RX_LEN register */
/* Number of bytes received (RO) */
#define MCHP_ESPI_OOB_RX_LEN_POS 0u
#define MCHP_ESPI_OOB_RX_LEN_MASK 0x1fffu
/* Receive buffer length field (RW) */
#define MCHP_ESPI_OOB_RX_BUF_LEN_POS 16u
#define MCHP_ESPI_OOB_RX_BUF_LEN_MASK0 0x1fffu
#define MCHP_ESPI_OOB_RX_BUF_LEN_MASK \
SHLU32(MCHP_ESPI_OOB_RX_BUF_LEN_MASK0, MCHP_ESPI_OOB_RX_BUF_LEN_POS)
/* OOB TX_LEN register */
#define MCHP_ESPI_OOB_TX_MSG_LEN_POS 0u
#define MCHP_ESPI_OOB_TX_MSG_LEN_MASK 0x1fffu
/* OOB RX_CTRL */
/* Set AVAIL bit to indicate SRAM Buffer and size has been configured */
#define MCHP_ESPI_OOB_RX_CTRL_AVAIL_POS 0u /* WO */
#define MCHP_ESPI_OOB_RX_CTRL_AVAIL BIT(MCHP_ESPI_OOB_RX_CTRL_AVAIL_POS)
#define MCHP_ESPI_OOB_RX_CTRL_CHEN_POS 9u /* RO */
#define MCHP_ESPI_OOB_RX_CTRL_CHEN BIT(MCHP_ESPI_OOB_RX_CTRL_CHEN_POS)
/* Copy of eSPI OOB Capabilities max. payload size */
#define MCHP_ESPI_OOB_RX_CTRL_MAX_SZ_POS 16u /* RO */
#define MCHP_ESPI_OOB_RX_CTRL_MAX_SZ_MASK0 0x07u
#define MCHP_ESPI_OOB_RX_CTRL_MAX_SZ_MASK \
SHLU32(MCHP_ESPI_OOB_RX_CTRL_MAX_SZ_MASK0, \
MCHP_ESPI_OOB_RX_CTRL_MAX_SZ_POS)
/* OOB RX_IEN */
#define MCHP_ESPI_OOB_RX_IEN_POS 0u
#define MCHP_ESPI_OOB_RX_IEN BIT(MCHP_ESPI_OOB_RX_IEN_POS)
/* OOB RX_STS */
#define MCHP_ESPI_OOB_RX_STS_DONE_POS 0u /* RW1C */
#define MCHP_ESPI_OOB_RX_STS_DONE BIT(MCHP_ESPI_OOB_RX_STS_DONE_POS)
#define MCHP_ESPI_OOB_RX_STS_IBERR_POS 1u /* RW1C */
#define MCHP_ESPI_OOB_RX_STS_IBERR BIT(MCHP_ESPI_OOB_RX_STS_IBERR_POS)
#define MCHP_ESPI_OOB_RX_STS_OVRUN_POS 2u /* RW1C */
#define MCHP_ESPI_OOB_RX_STS_OVRUN BIT(MCHP_ESPI_OOB_RX_STS_OVRUN_POS)
#define MCHP_ESPI_OOB_RX_STS_RXEN_POS 3u /* RO */
#define MCHP_ESPI_OOB_RX_STS_RXEN BIT(MCHP_ESPI_OOB_RX_STS_RXEN_POS)
#define MCHP_ESPI_OOB_RX_STS_TAG_POS 8u /* RO */
#define MCHP_ESPI_OOB_RX_STS_TAG_MASK0 0x0fu
#define MCHP_ESPI_OOB_RX_STS_TAG_MASK \
SHLU32(MCHP_ESPI_OOB_RX_STS_TAG_MASK0, MCHP_ESPI_OOB_RX_STS_TAG_POS)
#define MCHP_ESPI_OOB_RX_STS_ALL_RW1C 0x07u
#define MCHP_ESPI_OOB_RX_STS_ALL 0x0fu
/* OOB TX_CTRL */
#define MCHP_ESPI_OOB_TX_CTRL_START_POS 0u /* WO */
#define MCHP_ESPI_OOB_TX_CTRL_START BIT(MCHP_ESPI_OOB_TX_CTRL_START_POS)
#define MCHP_ESPI_OOB_TX_CTRL_TAG_POS 8u /* RW */
#define MCHP_ESPI_OOB_TX_CTRL_TAG_MASK0 0x0fu
#define MCHP_ESPI_OOB_TX_CTRL_TAG_MASK \
SHLU32(MCHP_ESPI_OOB_TX_CTRL_TAG_MASK0, MCHP_ESPI_OOB_TX_CTRL_TAG_POS)
/* OOB TX_IEN */
#define MCHP_ESPI_OOB_TX_IEN_DONE_POS 0u
#define MCHP_ESPI_OOB_TX_IEN_DONE BIT(MCHP_ESPI_OOB_TX_IEN_DONE_POS)
#define MCHP_ESPI_OOB_TX_IEN_CHG_EN_POS 1u
#define MCHP_ESPI_OOB_TX_IEN_CHG_EN BIT(MCHP_ESPI_OOB_TX_IEN_CHG_EN_POS)
#define MCHP_ESPI_OOB_TX_IEN_ALL 0x03u
/* OOB TX_STS */
#define MCHP_ESPI_OOB_TX_STS_DONE_POS 0u /* RW1C */
#define MCHP_ESPI_OOB_TX_STS_DONE BIT(MCHP_ESPI_OOB_TX_STS_DONE_POS)
#define MCHP_ESPI_OOB_TX_STS_CHG_EN_POS 1u /* RW1C */
#define MCHP_ESPI_OOB_TX_STS_CHG_EN BIT(MCHP_ESPI_OOB_TX_STS_CHG_EN_POS)
#define MCHP_ESPI_OOB_TX_STS_IBERR_POS 2u /* RW1C */
#define MCHP_ESPI_OOB_TX_STS_IBERR BIT(MCHP_ESPI_OOB_TX_STS_IBERR_POS)
#define MCHP_ESPI_OOB_TX_STS_OVRUN_POS 3u /* RW1C */
#define MCHP_ESPI_OOB_TX_STS_OVRUN BIT(MCHP_ESPI_OOB_TX_STS_OVRUN_POS)
#define MCHP_ESPI_OOB_TX_STS_BADREQ_POS 5u /* RW1C */
#define MCHP_ESPI_OOB_TX_STS_BADREQ BIT(MCHP_ESPI_OOB_TX_STS_BADREQ_POS)
#define MCHP_ESPI_OOB_TX_STS_BUSY_POS 8u /* RO */
#define MCHP_ESPI_OOB_TX_STS_BUSY BIT(MCHP_ESPI_OOB_TX_STS_BUSY_POS)
/* Read-only copy of OOB Channel Enabled bit */
#define MCHP_ESPI_OOB_TX_STS_CHEN_POS 9u /* RO */
#define MCHP_ESPI_OOB_TX_STS_CHEN BIT(MCHP_ESPI_OOB_TX_STS_CHEN_POS)
#define MCHP_ESPI_OOB_TX_STS_ALL_RW1C 0x2fu
/*---- MCHP_ESPI_IO_FC - eSPI IO Flash channel registers ----*/
/* FC MEM_ADDR_LSW */
#define MCHP_ESPI_FC_MEM_ADDR_LSW_MASK 0xfffffffcu
/* FC CTRL */
#define MCHP_ESPI_FC_CTRL_START_POS 0u /* WO */
#define MCHP_ESPI_FC_CTRL_START BIT(MCHP_ESPI_FC_CTRL_START_POS)
#define MCHP_ESPI_FC_CTRL_FUNC_POS 2u /* RW */
#define MCHP_ESPI_FC_CTRL_FUNC_MASK0 0x03u
#define MCHP_ESPI_FC_CTRL_FUNC_MASK \
SHLU32(MCHP_ESPI_FC_CTRL_FUNC_MASK0, MCHP_ESPI_FC_CTRL_FUNC_POS)
#define MCHP_ESPI_FC_CTRL_RD0 0x00u
#define MCHP_ESPI_FC_CTRL_WR0 0x01u
#define MCHP_ESPI_FC_CTRL_ERS0 0x02u
#define MCHP_ESPI_FC_CTRL_ERL0 0x03u
#define MCHP_ESPI_FC_CTRL_FUNC(f) \
(SHLU32((uint32_t)(f), MCHP_ESPI_FC_CTRL_FUNC_POS) & \
MCHP_ESPI_FC_CTRL_FUNC_MASK)
#define MCHP_ESPI_FC_CTRL_TAG_POS 4u
#define MCHP_ESPI_FC_CTRL_TAG_MASK0 0x0fu
#define MCHP_ESPI_FC_CTRL_TAG_MASK \
SHLU32(MCHP_ESPI_FC_CTRL_TAG_MASK0, MCHP_ESPI_FC_CTRL_TAG_POS)
#define MCHP_ESPI_FC_CTRL_TAG(t) \
((uint32_t)(t) & MCHP_ESPI_FC_CTRL_TAG_MASK)
#define MCHP_ESPI_FC_CTRL_ABORT_POS 16u /* WO */
#define MCHP_ESPI_FC_CTRL_ABORT BIT(MCHP_ESPI_FC_CTRL_ABORT_POS)
/* FC IEN */
#define MCHP_ESPI_FC_IEN_DONE_POS 0u
#define MCHP_ESPI_FC_IEN_DONE BIT(MCHP_ESPI_FC_IEN_DONE_POS)
#define MCHP_ESPI_FC_IEN_CHG_EN_POS 1u
#define MCHP_ESPI_FC_IEN_CHG_EN BIT(MCHP_ESPI_FC_IEN_CHG_EN_POS)
/* FC CFG */
#define MCHP_ESPI_FC_CFG_BUSY_POS 0u /* RO */
#define MCHP_ESPI_FC_CFG_BUSY BIT(MCHP_ESPI_FC_CFG_BUSY_POS)
#define MCHP_ESPI_FC_CFG_ERBSZ_POS 2u /* RO */
#define MCHP_ESPI_FC_CFG_ERBSZ_MASK0 0x07u
#define MCHP_ESPI_FC_CFG_ERBSZ_MASK \
SHLU32(MCHP_ESPI_FC_CFG_ERBSZ_MASK0, MCHP_ESPI_FC_CFG_ERBSZ_POS)
#define MCHP_ESPI_FC_CFG_ERBSZ_4K \
SHLU32(0x01u, MCHP_ESPI_FC_CFG_ERBSZ_POS)
#define MCHP_ESPI_FC_CFG_ERBSZ_64K \
SHLU32(0x02u, MCHP_ESPI_FC_CFG_ERBSZ_POS)
#define MCHP_ESPI_FC_CFG_ERBSZ_4K_64K \
SHLU32(0x03u, MCHP_ESPI_FC_CFG_ERBSZ_POS)
#define MCHP_ESPI_FC_CFG_ERBSZ_128K \
SHLU32(0x04u, MCHP_ESPI_FC_CFG_ERBSZ_POS)
#define MCHP_ESPI_FC_CFG_ERBSZ_256K \
SHLU32(0x05u, MCHP_ESPI_FC_CFG_ERBSZ_POS)
#define MCHP_ESPI_FC_CFG_MAXPLD_POS 8u /* RO */
#define MCHP_ESPI_FC_CFG_MAXPLD_MASK0 0x07u
#define MCHP_ESPI_FC_CFG_MAXPLD_MASK \
SHLU32(MCHP_ESPI_FC_CFG_MAXPLD_MASK0, MCHP_ESPI_FC_CFG_MAXPLD_POS)
#define MCHP_ESPI_FC_CFG_MAXPLD_64B \
SHLU32(0x01u, MCHP_ESPI_FC_CFG_MAXPLD_POS)
#define MCHP_ESPI_FC_CFG_MAXPLD_128B \
SHLU32(0x02u, MCHP_ESPI_FC_CFG_MAXPLD_POS)
#define MCHP_ESPI_FC_CFG_MAXPLD_256B \
SHLU32(0x03u, MCHP_ESPI_FC_CFG_MAXPLD_POS)
#define MCHP_ESPI_FC_CFG_SAFS_SEL_POS 11u
#define MCHP_ESPI_FC_CFG_SAFS_SEL BIT(MCHP_ESPI_FC_CFG_SAFS_SEL_POS)
#define MCHP_ESPI_FC_CFG_MAXRD_POS 12u /* RO */
#define MCHP_ESPI_FC_CFG_MAXRD_MASK0 0x07u
#define MCHP_ESPI_FC_CFG_MAXRD_MASK \
SHLU32(MCHP_ESPI_FC_CFG_MAXRD_MASK0, MCHP_ESPI_FC_CFG_MAXRD_POS)
#define MCHP_ESPI_FC_CFG_MAXRD_64B \
SHLU32(0x01u, MCHP_ESPI_FC_CFG_MAXRD_POS)
#define MCHP_ESPI_FC_CFG_MAXRD_128B \
SHLU32(0x02u, MCHP_ESPI_FC_CFG_MAXRD_POS)
#define MCHP_ESPI_FC_CFG_MAXRD_256B \
SHLU32(0x03u, MCHP_ESPI_FC_CFG_MAXRD_POS)
#define MCHP_ESPI_FC_CFG_MAXRD_512B \
SHLU32(0x04u, MCHP_ESPI_FC_CFG_MAXRD_POS)
#define MCHP_ESPI_FC_CFG_MAXRD_1K \
SHLU32(0x05u, MCHP_ESPI_FC_CFG_MAXRD_POS)
#define MCHP_ESPI_FC_CFG_MAXRD_2K \
SHLU32(0x06u, MCHP_ESPI_FC_CFG_MAXRD_POS)
#define MCHP_ESPI_FC_CFG_MAXRD_4K \
SHLU32(0x07u, MCHP_ESPI_FC_CFG_MAXRD_POS)
#define MCHP_ESPI_FC_CFG_FORCE_MS_POS 28u /* RW */
#define MCHP_ESPI_FC_CFG_FORCE_MS_MASK0 0x03u
#define MCHP_ESPI_FC_CFG_FORCE_MS_MASK \
SHLU32(MCHP_ESPI_FC_CFG_FORCE_MS_MASK0, MCHP_ESPI_FC_CFG_FORCE_MS_POS)
/* Host (eSPI Master) can select MAFS or SAFS */
#define MCHP_ESPI_FC_CFG_FORCE_NONE 0u
/* EC forces eSPI slave HW to only allow MAFS */
#define MCHP_ESPI_FC_CFG_FORCE_MAFS \
SHLU32(0x02u, MCHP_ESPI_FC_CFG_FORCE_MS_POS)
/* EC forces eSPI slave HW to only allow SAFS */
#define MCHP_ESPI_FC_CFG_FORCE_SAFS \
SHLU32(0x03u, MCHP_ESPI_FC_CFG_FORCE_MS_POS)
/* FC STS */
#define MCHP_ESPI_FC_STS_CHAN_EN_POS 0u /* RO */
#define MCHP_ESPI_FC_STS_CHAN_EN BIT(MCHP_ESPI_FC_STS_CHAN_EN_POS)
#define MCHP_ESPI_FC_STS_CHAN_EN_CHG_POS 1u /* RW1C */
#define MCHP_ESPI_FC_STS_CHAN_EN_CHG BIT(MCHP_ESPI_FC_STS_CHAN_EN_CHG_POS)
#define MCHP_ESPI_FC_STS_DONE_POS 2u /* RW1C */
#define MCHP_ESPI_FC_STS_DONE BIT(MCHP_ESPI_FC_STS_DONE_POS)
#define MCHP_ESPI_FC_STS_MDIS_POS 3u /* RW1C */
#define MCHP_ESPI_FC_STS_MDIS BIT(MCHP_ESPI_FC_STS_MDIS_POS)
#define MCHP_ESPI_FC_STS_IBERR_POS 4u /* RW1C */
#define MCHP_ESPI_FC_STS_IBERR BIT(MCHP_ESPI_FC_STS_IBERR_POS)
#define MCHP_ESPI_FC_STS_ABS_POS 5u /* RW1C */
#define MCHP_ESPI_FC_STS_ABS BIT(MCHP_ESPI_FC_STS_ABS_POS)
#define MCHP_ESPI_FC_STS_OVRUN_POS 6u /* RW1C */
#define MCHP_ESPI_FC_STS_OVRUN BIT(MCHP_ESPI_FC_STS_OVRUN_POS)
#define MCHP_ESPI_FC_STS_INC_POS 7u /* RW1C */
#define MCHP_ESPI_FC_STS_INC BIT(MCHP_ESPI_FC_STS_INC_POS)
#define MCHP_ESPI_FC_STS_FAIL_POS 8u /* RW1C */
#define MCHP_ESPI_FC_STS_FAIL BIT(MCHP_ESPI_FC_STS_FAIL_POS)
#define MCHP_ESPI_FC_STS_OVFL_POS 9u /* RW1C */
#define MCHP_ESPI_FC_STS_OVFL BIT(MCHP_ESPI_FC_STS_OVFL_POS)
#define MCHP_ESPI_FC_STS_BADREQ_POS 11u /* RW1C */
#define MCHP_ESPI_FC_STS_BADREQ BIT(MCHP_ESPI_FC_STS_BADREQ_POS)
#define MCHP_ESPI_FC_STS_ALL_RW1C 0x0bfeu
/*---- MCHP_ESPI_IO_BAR_HOST - eSPI IO Host visible BAR registers ----*/
/*
* IOBAR_INH_LSW/MSW 64-bit register: each bit = 1 inhibits an I/O BAR
* independent of the BAR's Valid bit.
* Logical Device Number = bit position.
*/
#define MCHP_ESPI_IOBAR_LDN_MBOX 0u
#define MCHP_ESPI_IOBAR_LDN_KBC 1u
#define MCHP_ESPI_IOBAR_LDN_ACPI_EC_0 2u
#define MCHP_ESPI_IOBAR_LDN_ACPI_EC_1 3u
#define MCHP_ESPI_IOBAR_LDN_ACPI_EC_2 4u
#define MCHP_ESPI_IOBAR_LDN_ACPI_EC_3 5u
#define MCHP_ESPI_IOBAR_LDN_ACPI_EC_4 6u
#define MCHP_ESPI_IOBAR_LDN_ACPI_PM1 7u
#define MCHP_ESPI_IOBAR_LDN_PORT92 8u
#define MCHP_ESPI_IOBAR_LDN_UART_0 9u
#define MCHP_ESPI_IOBAR_LDN_UART_1 10u
#define MCHP_ESPI_IOBAR_LDN_IOC 13u
#define MCHP_ESPI_IOBAR_LDN_MEM 14u
#define MCHP_ESPI_IOBAR_LDN_GLUE_LOG 15u
#define MCHP_ESPI_IOBAR_LDN_EMI_0 16u
#define MCHP_ESPI_IOBAR_LDN_EMI_1 17u
#define MCHP_ESPI_IOBAR_LDN_EMI_2 18u
#define MCHP_ESPI_IOBAR_LDN_RTC 20u
#define MCHP_ESPI_IOBAR_LDN_P80CAP_0 32u /* BDP Port80 Capture */
#define MCHP_ESPI_IOBAR_LDN_P80CAP_1 31u /* BDP Alias Capture */
#define MCHP_ESPI_IOBAR_LDN_T32B 47u
#define MCHP_ESPI_IOBAR_LDN_LASIC 48u
/*
* IOBAR_INIT: Default address of I/O Plug and Play Super-IO index/data
* configuration registers. (Defaults to 0x2E/0x2F)
*/
#define MCHP_ESPI_IOBAR_INIT_DFLT 0x2eu
/*
* EC_IRQ: A write to bit[0] triggers EC SERIRQ. The actual
* SERIRQ slot is configured in MCHP_ESPI_IO_SIRQ.EC_SIRQ
*/
#define MCHP_ESPI_EC_IRQ_GEN (1u << 0)
/* 32-bit Host IO BAR */
#define MCHP_ESPI_IO_BAR_HOST_VALID_POS 0u
#define MCHP_ESPI_IO_BAR_HOST_VALID \
BIT(MCHP_ESPI_IO_BAR_HOST_VALID_POS)
#define MCHP_ESPI_IO_BAR_HOST_ADDR_POS 16u
#define MCHP_ESPI_IO_BAR_HOST_ADDR_MASK0 0xffffu
#define MCHP_ESPI_IO_BAR_HOST_ADDR_MASK 0xffff0000u
/* Offsets from first SIRQ */
#define MCHP_ESPI_SIRQ_MBOX_SIRQ 0u
#define MCHP_ESPI_SIRQ_MBOX_SMI 1u
#define MCHP_ESPI_SIRQ_KBC_KIRQ 2u
#define MCHP_ESPI_SIRQ_KBC_MIRQ 3u
#define MCHP_ESPI_SIRQ_ACPI_EC0 4u
#define MCHP_ESPI_SIRQ_ACPI_EC1 5u
#define MCHP_ESPI_SIRQ_ACPI_EC2 6u
#define MCHP_ESPI_SIRQ_ACPI_EC3 7u
#define MCHP_ESPI_SIRQ_ACPI_EC4 8u
#define MCHP_ESPI_SIRQ_UART0 9u
#define MCHP_ESPI_SIRQ_UART1 10u
#define MCHP_ESPI_SIRQ_EMI0_HOST 11u
#define MCHP_ESPI_SIRQ_EMI0_E2H 12u
#define MCHP_ESPI_SIRQ_EMI1_HOST 13u
#define MCHP_ESPI_SIRQ_EMI1_E2H 14u
#define MCHP_ESPI_SIRQ_EMI2_HOST 15u
#define MCHP_ESPI_SIRQ_EMI2_E2H 16u
#define MCHP_ESPI_SIRQ_RTC 17u
#define MCHP_ESPI_SIRQ_EC 18u
#define MCHP_ESPI_SIRQ_RSVD19 19u
#define MCHP_ESPI_SIRQ_MAX 20u
/*
* Values for Logical Device SIRQ registers.
* Unless disabled each logical device must have a unique value
* programmed to its SIRQ register.
* Values 0x00u through 0x7Fu are sent using VWire host index 0x00
* Values 0x80h through 0xFEh are sent using VWire host index 0x01
* All registers reset default is 0xFFu (disabled).
*/
#define MCHP_ESPI_IO_SIRQ_DIS 0xFFu
/* eSPI Memory component registers */
/* BM_STS */
#define MCHP_ESPI_BM_STS_DONE_1_POS 0u /* RW1C */
#define MCHP_ESPI_BM_STS_DONE_1 BIT(MCHP_ESPI_BM_STS_DONE_1_POS)
#define MCHP_ESPI_BM_STS_BUSY_1_POS 1u /* RO */
#define MCHP_ESPI_BM_STS_BUSY_1 BIT(MCHP_ESPI_BM_STS_BUSY_1_POS)
#define MCHP_ESPI_BM_STS_AB_EC_1_POS 2u /* RW1C */
#define MCHP_ESPI_BM_STS_AB_EC_1 BIT(MCHP_ESPI_BM_STS_AB_EC_1_POS)
#define MCHP_ESPI_BM_STS_AB_HOST_1_POS 3u /* RW1C */
#define MCHP_ESPI_BM_STS_AB_HOST_1 BIT(MCHP_ESPI_BM_STS_AB_HOST_1_POS)
#define MCHP_ESPI_BM_STS_AB_CH2_1_POS 4u /* RW1C */
#define MCHP_ESPI_BM_STS_CH2_AB_1 BIT(MCHP_ESPI_BM_STS_AB_CH2_1_POS)
#define MCHP_ESPI_BM_STS_OVFL_1_POS 5u /* RW1C */
#define MCHP_ESPI_BM_STS_OVFL_1_CH2 BIT(MCHP_ESPI_BM_STS_OVFL_1_POS)
#define MCHP_ESPI_BM_STS_OVRUN_1_POS 6u /* RW1C */
#define MCHP_ESPI_BM_STS_OVRUN_1_CH2 BIT(MCHP_ESPI_BM_STS_OVRUN_1_POS)
#define MCHP_ESPI_BM_STS_INC_1_POS 7u /* RW1C */
#define MCHP_ESPI_BM_STS_INC_1 BIT(MCHP_ESPI_BM_STS_INC_1_POS)
#define MCHP_ESPI_BM_STS_FAIL_1_POS 8u /* RW1C */
#define MCHP_ESPI_BM_STS_FAIL_1 BIT(MCHP_ESPI_BM_STS_FAIL_1_POS)
#define MCHP_ESPI_BM_STS_IBERR_1_POS 9u /* RW1C */
#define MCHP_ESPI_BM_STS_IBERR_1 BIT(MCHP_ESPI_BM_STS_IBERR_1_POS)
#define MCHP_ESPI_BM_STS_BADREQ_1_POS 11u /* RW1C */
#define MCHP_ESPI_BM_STS_BADREQ_1 BIT(MCHP_ESPI_BM_STS_BADREQ_1_POS)
#define MCHP_ESPI_BM_STS_DONE_2_POS 16u /* RW1C */
#define MCHP_ESPI_BM_STS_DONE_2 BIT(MCHP_ESPI_BM_STS_DONE_2_POS)
#define MCHP_ESPI_BM_STS_BUSY_2_POS 17u /* RO */
#define MCHP_ESPI_BM_STS_BUSY_2 BIT(MCHP_ESPI_BM_STS_BUSY_2_POS)
#define MCHP_ESPI_BM_STS_AB_EC_2_POS 18u /* RW1C */
#define MCHP_ESPI_BM_STS_AB_EC_2 BIT(MCHP_ESPI_BM_STS_AB_EC_2_POS)
#define MCHP_ESPI_BM_STS_AB_HOST_2_POS 19u /* RW1C */
#define MCHP_ESPI_BM_STS_AB_HOST_2 BIT(MCHP_ESPI_BM_STS_AB_HOST_2_POS)
#define MCHP_ESPI_BM_STS_AB_CH1_2_POS 20u /* RW1C */
#define MCHP_ESPI_BM_STS_AB_CH1_2 BIT(MCHP_ESPI_BM_STS_AB_CH1_2_POS)
#define MCHP_ESPI_BM_STS_OVFL_2_POS 21u /* RW1C */
#define MCHP_ESPI_BM_STS_OVFL_2_CH2 BIT(MCHP_ESPI_BM_STS_OVFL_2_POS)
#define MCHP_ESPI_BM_STS_OVRUN_2_POS 22u /* RW1C */
#define MCHP_ESPI_BM_STS_OVRUN_CH2_2 BIT(MCHP_ESPI_BM_STS_OVRUN_2_POS)
#define MCHP_ESPI_BM_STS_INC_2_POS 23u /* RW1C */
#define MCHP_ESPI_BM_STS_INC_2 BIT(MCHP_ESPI_BM_STS_INC_2_POS)
#define MCHP_ESPI_BM_STS_FAIL_2_POS 24u /* RW1C */
#define MCHP_ESPI_BM_STS_FAIL_2 BIT(MCHP_ESPI_BM_STS_FAIL_2_POS)
#define MCHP_ESPI_BM_STS_IBERR_2_POS 25u /* RW1C */
#define MCHP_ESPI_BM_STS_IBERR_2 BIT(MCHP_ESPI_BM_STS_IBERR_2_POS)
#define MCHP_ESPI_BM_STS_BADREQ_2_POS 27u /* RW1C */
#define MCHP_ESPI_BM_STS_BADREQ_2 BIT(MCHP_ESPI_BM_STS_BADREQ_2_POS)
#define MCHP_ESPI_BM_STS_ALL_RW1C_1 0x0bfdu
#define MCHP_ESPI_BM_STS_ALL_RW1C_2 0x0bfd0000u
/* BM_IEN */
#define MCHP_ESPI_BM1_IEN_DONE_POS 0u
#define MCHP_ESPI_BM1_IEN_DONE BIT(MCHP_ESPI_BM1_IEN_DONE_POS)
#define MCHP_ESPI_BM2_IEN_DONE_POS 16u
#define MCHP_ESPI_BM2_IEN_DONE BIT(MCHP_ESPI_BM2_IEN_DONE_POS)
/* BM_CFG */
#define MCHP_ESPI_BM1_CFG_TAG_POS 0u
#define MCHP_ESPI_BM1_CFG_TAG_MASK0 0x0fu
#define MCHP_ESPI_BM1_CFG_TAG_MASK 0x0fu
#define MCHP_ESPI_BM2_CFG_TAG_POS 16u
#define MCHP_ESPI_BM2_CFG_TAG_MASK0 0x0fu
#define MCHP_ESPI_BM2_CFG_TAG_MASK 0x0f0000u
/* BM1_CTRL */
#define MCHP_ESPI_BM1_CTRL_START_POS 0u /* WO */
#define MCHP_ESPI_BM1_CTRL_START BIT(MCHP_ESPI_BM1_CTRL_START_POS)
#define MCHP_ESPI_BM1_CTRL_ABORT_POS 1u /* WO */
#define MCHP_ESPI_BM1_CTRL_ABORT BIT(MCHP_ESPI_BM1_CTRL_ABORT_POS)
#define MCHP_ESPI_BM1_CTRL_EN_INC_POS 2u /* RW */
#define MCHP_ESPI_BM1_CTRL_EN_INC BIT(MCHP_ESPI_BM1_CTRL_EN_INC_POS)
#define MCHP_ESPI_BM1_CTRL_WAIT_NB2_POS 3u /* RW */
#define MCHP_ESPI_BM1_CTRL_WAIT_NB2 BIT(MCHP_ESPI_BM1_CTRL_WAIT_NB2_POS)
#define MCHP_ESPI_BM1_CTRL_CTYPE_POS 8u
#define MCHP_ESPI_BM1_CTRL_CTYPE_MASK0 0x03u
#define MCHP_ESPI_BM1_CTRL_CTYPE_MASK \
SHLU32(MCHP_ESPI_BM1_CTRL_CTYPE_MASK0, MCHP_ESPI_BM1_CTRL_CTYPE_POS)
#define MCHP_ESPI_BM1_CTRL_CTYPE_RD_ADDR32 0x00u
#define MCHP_ESPI_BM1_CTRL_CTYPE_WR_ADDR32 \
SHLU32(0x01u, MCHP_ESPI_BM1_CTRL_CTYPE_POS)
#define MCHP_ESPI_BM1_CTRL_CTYPE_RD_ADDR64 \
SHLU32(0x02u, MCHP_ESPI_BM1_CTRL_CTYPE_POS)
#define MCHP_ESPI_BM1_CTRL_CTYPE_WR_ADDR64 \
SHLU32(0x03u, MCHP_ESPI_BM1_CTRL_CTYPE_POS)
#define MCHP_ESPI_BM1_CTRL_LEN_POS 16u
#define MCHP_ESPI_BM1_CTRL_LEN_MASK0 0x1fffu
#define MCHP_ESPI_BM1_CTRL_LEN_MASK 0x1fff0000u
/* BM1_EC_ADDR_LSW */
#define MCHP_ESPI_BM1_EC_ADDR_LSW_MASK 0xfffffffcu
/* BM2_CTRL */
#define MCHP_ESPI_BM2_CTRL_START_POS 0u /* WO */
#define MCHP_ESPI_BM2_CTRL_START BIT(MCHP_ESPI_BM2_CTRL_START_POS)
#define MCHP_ESPI_BM2_CTRL_ABORT_POS 1u /* WO */
#define MCHP_ESPI_BM2_CTRL_ABORT BIT(MCHP_ESPI_BM2_CTRL_ABORT_POS)
#define MCHP_ESPI_BM2_CTRL_EN_INC_POS 2u /* RW */
#define MCHP_ESPI_BM2_CTRL_EN_INC BIT(MCHP_ESPI_BM2_CTRL_EN_INC_POS)
#define MCHP_ESPI_BM2_CTRL_WAIT_NB2_POS 3u /* RW */
#define MCHP_ESPI_BM2_CTRL_WAIT_NB2 BIT(MCHP_ESPI_BM2_CTRL_WAIT_NB2_POS)
#define MCHP_ESPI_BM2_CTRL_CTYPE_POS 8u
#define MCHP_ESPI_BM2_CTRL_CTYPE_MASK0 0x03u
#define MCHP_ESPI_BM2_CTRL_CTYPE_MASK 0x0300u
#define MCHP_ESPI_BM2_CTRL_CTYPE_RD_ADDR32 0x00u
#define MCHP_ESPI_BM2_CTRL_CTYPE_WR_ADDR32 0x0100u
#define MCHP_ESPI_BM2_CTRL_CTYPE_RD_ADDR64 0x0200u
#define MCHP_ESPI_BM2_CTRL_CTYPE_WR_ADDR64 0x0300u
#define MCHP_ESPI_BM2_CTRL_LEN_POS 16u
#define MCHP_ESPI_BM2_CTRL_LEN_MASK0 0x1fffu
#define MCHP_ESPI_BM2_CTRL_LEN_MASK 0x1fff0000u
/* BM2_EC_ADDR_LSW */
#define MCHP_ESPI_BM2_EC_ADDR_LSW_MASK 0xfffffffcu
/*
* MCHP_ESPI_MEM_BAR_EC @ 0x400F3930
* Half-word H0 of each EC Memory BAR contains
* Memory BAR memory address mask bits in bits[7:0]
* Logical Device Number in bits[13:8]
*/
#define MCHP_ESPI_EBAR_H0_MEM_MASK_POS 0u
#define MCHP_ESPI_EBAR_H0_MEM_MASK_MASK 0xffu
#define MCHP_ESPI_EBAR_H0_LDN_POS 8u
#define MCHP_ESPI_EBAR_H0_LDN_MASK0 0x3fu
#define MCHP_ESPI_EBAR_H0_LDN_MASK 0x3f00u
/*
* MCHP_ESPI_MEM_BAR_HOST @ 0x400F3B30
* Each Host BAR contains:
* bit[0] (RW) = Valid bit
* bits[15:1] = Reserved, read-only 0
* bits[47:16] (RW) = bits[31:0] of the Host Memory address.
*/
/* Memory BAR Host address valid */
#define MCHP_ESPI_HBAR_VALID_POS 0u
#define MCHP_ESPI_HBAR_VALID_MASK 0x01u
/*
* Host address is in bits[47:16] of the HBAR
* HBAR's are spaced every 10 bytes (80 bits) but
* only implement bits[47:0]
*/
#define MCHP_ESPI_HBAR_VALID_OFS 0x00u /* byte 0 */
/* 32-bit Host Address */
#define MCHP_ESPI_HBAR_ADDR_B0_OFS 0x02u /* byte 2 */
#define MCHP_ESPI_HBAR_ADDR_B1_OFS 0x03u /* byte 3 */
#define MCHP_ESPI_HBAR_ADDR_B2_OFS 0x04u /* byte 4 */
#define MCHP_ESPI_HBAR_ADDR_B3_OFS 0x05u /* byte 5 */
#define MCHP_EC_SRAM_BAR_H0_VALID_POS 0u
#define MCHP_EC_SRAM_BAR_H0_VALID_MASK0 0x01u
#define MCHP_EC_SRAM_BAR_H0_VALID_MASK 0x01u
#define MCHP_EC_SRAM_BAR_H0_VALID 0x01u
#define MCHP_EC_SRAM_BAR_H0_ACCESS_POS 1u
#define MCHP_EC_SRAM_BAR_H0_ACCESS_MASK0 0x03u
#define MCHP_EC_SRAM_BAR_H0_ACCESS_MASK 0x06u
#define MCHP_EC_SRAM_BAR_H0_ACCESS_NONE 0x00u
#define MCHP_EC_SRAM_BAR_H0_ACCESS_RO 0x02u
#define MCHP_EC_SRAM_BAR_H0_ACCESS_WO 0x04u
#define MCHP_EC_SRAM_BAR_H0_ACCESS_RW 0x06u
#define MCHP_EC_SRAM_BAR_H0_SIZE_POS 4u
#define MCHP_EC_SRAM_BAR_H0_SIZE_MASK0 0x0fu
#define MCHP_EC_SRAM_BAR_H0_SIZE_MASK 0xf0u
#define MCHP_EC_SRAM_BAR_H0_SIZE_1B 0x00u
#define MCHP_EC_SRAM_BAR_H0_SIZE_2B 0x10u
#define MCHP_EC_SRAM_BAR_H0_SIZE_4B 0x20u
#define MCHP_EC_SRAM_BAR_H0_SIZE_8B 0x30u
#define MCHP_EC_SRAM_BAR_H0_SIZE_16B 0x40u
#define MCHP_EC_SRAM_BAR_H0_SIZE_32B 0x50u
#define MCHP_EC_SRAM_BAR_H0_SIZE_64B 0x60u
#define MCHP_EC_SRAM_BAR_H0_SIZE_128B 0x70u
#define MCHP_EC_SRAM_BAR_H0_SIZE_256B 0x80u
#define MCHP_EC_SRAM_BAR_H0_SIZE_512B 0x90u
#define MCHP_EC_SRAM_BAR_H0_SIZE_1KB 0xa0u
#define MCHP_EC_SRAM_BAR_H0_SIZE_2KB 0xb0u
#define MCHP_EC_SRAM_BAR_H0_SIZE_4KB 0xc0u
#define MCHP_EC_SRAM_BAR_H0_SIZE_8KB 0xd0u
#define MCHP_EC_SRAM_BAR_H0_SIZE_16KB 0xe0u
#define MCHP_EC_SRAM_BAR_H0_SIZE_32KB 0xf0u
/* EC and Host SRAM BAR start offset of EC or Host memory address */
#define MCHP_EC_SRAM_BAR_MADDR_OFS1 2u
#define MCHP_EC_SRAM_BAR_MADDR_OFS2 4u
/* Interfaces to any C modules */
#ifdef __cplusplus
extern "C" {
#endif
/* Array indices for eSPI IO BAR Host and EC-only register structures */
enum espi_io_bar_idx {
IOB_IOC = 0,
IOB_MEM,
IOB_MBOX,
IOB_KBC,
IOB_ACPI_EC0,
IOB_ACPI_EC1,
IOB_ACPI_EC2,
IOB_ACPI_EC3,
IOB_ACPI_EC4,
IOB_ACPI_PM1,
IOB_PORT92,
IOB_UART0,
IOB_UART1,
IOB_EMI0,
IOB_EMI1,
IOB_EMI2,
IOB_P80BD, /* MEC152x IOB_P80_CAP0 */
IOB_P80BD_ALIAS, /* MEC152x IOB_P80_CAP1 */
IOB_RTC,
IOB_RSVD19,
IOB_T32B,
IOB_RSVD21,
IOB_GLUE,
IOB_MAX
};
/** @brief Serial IRQ byte register indices */
enum espi_io_sirq_idx {
SIRQ_MBOX = 0, SIRQ_MBOX_SMI, SIRQ_KBC_KIRQ,
SIRQ_KBC_MIRQ, SIRQ_ACPI_EC0_OBF, SIRQ_ACPI_EC1_OBF,
SIRQ_ACPI_EC2_OBF, SIRQ_ACPI_EC3_OBF, SIRQ_ACPI_EC4_OBF,
SIRQ_UART0, SIRQ_UART1, SIRQ_EMI0_HEV,
SIRQ_EMI0_E2H, SIRQ_EMI1_HEV, SIRQ_EMI1_E2H,
SIRQ_EMI2_HEV, SIRQ_EMI2_E2H, SIRQ_RTC,
SIRQ_EC, SIRQ_MAX
};
enum espi_mem_bar_idx {
MEMB_MBOX = 0,
MEMB_ACPI_EC0,
MEMB_ACPI_EC1,
MEMB_ACPI_EC2,
MEMB_ACPI_EC3,
MEMB_ACPI_EC4,
MEMB_EMI0,
MEMB_EMI1,
MEMB_EMI2,
MEMB_T32B,
MEMB_MAX
};
/* eSPI */
struct espi_io_mbar { /* 80-bit register */
volatile uint16_t LDN_MASK;
volatile uint16_t RESERVED[4];
}; /* Size = 10 (0xa) */
struct espi_mbar_host {
volatile uint16_t VALID;
volatile uint16_t HADDR_LSH;
volatile uint16_t HADDR_MSH;
volatile uint16_t RESERVED[2];
}; /* Size = 10 (0xa) */
struct espi_sram_bar {
volatile uint16_t VACCSZ;
volatile uint16_t EC_SRAM_BASE_LSH;
volatile uint16_t EC_SRAM_BASE_MSH;
volatile uint16_t RESERVED[2];
}; /* Size = 10 (0xa) */
struct espi_sram_host_bar {
volatile uint16_t ACCSZ;
volatile uint16_t HBASE_LSH;
volatile uint16_t HBASE_MSH;
volatile uint16_t RESERVED[2];
}; /* Size = 10 (0xa) */
/** @brief eSPI Capabilities, I/O and Memory components in one structure */
struct espi_iom_regs { /* @ 0x400F3400 */
volatile uint8_t RTIDX; /* @ 0x0000 */
volatile uint8_t RTDAT; /* @ 0x0001 */
volatile uint16_t RESERVED;
volatile uint32_t RESERVED1[63];
volatile uint32_t PCLC[3]; /* @ 0x0100 */
volatile uint32_t PCERR[2]; /* @ 0x010C */
volatile uint32_t PCSTS; /* @ 0x0114 */
volatile uint32_t PCIEN; /* @ 0x0118 */
volatile uint32_t RESERVED2;
volatile uint32_t PCBINH[2]; /* @ 0x0120 */
volatile uint32_t PCBINIT; /* @ 0x0128 */
volatile uint32_t PCECIRQ; /* @ 0x012C */
volatile uint32_t PCCKNP; /* @ 0x0130 */
volatile uint32_t PCBARI[29]; /* @ 0x0134 */
volatile uint32_t RESERVED3[30];
volatile uint32_t PCLTRSTS; /* @ 0x0220 */
volatile uint32_t PCLTREN; /* @ 0x0224 */
volatile uint32_t PCLTRCTL; /* @ 0x0228 */
volatile uint32_t PCLTRM; /* @ 0x022C */
volatile uint32_t RESERVED4[4];
volatile uint32_t OOBRXA[2]; /* @ 0x0240 */
volatile uint32_t OOBTXA[2]; /* @ 0x0248 */
volatile uint32_t OOBRXL; /* @ 0x0250 */
volatile uint32_t OOBTXL; /* @ 0x0254 */
volatile uint32_t OOBRXC; /* @ 0x0258 */
volatile uint32_t OOBRXIEN; /* @ 0x025C */
volatile uint32_t OOBRXSTS; /* @ 0x0260 */
volatile uint32_t OOBTXC; /* @ 0x0264 */
volatile uint32_t OOBTXIEN; /* @ 0x0268 */
volatile uint32_t OOBTXSTS; /* @ 0x026C */
volatile uint32_t RESERVED5[4];
volatile uint32_t FCFA[2]; /* @ 0x0280 */
volatile uint32_t FCBA[2]; /* @ 0x0288 */
volatile uint32_t FCLEN; /* @ 0x0290 */
volatile uint32_t FCCTL; /* @ 0x0294 */
volatile uint32_t FCIEN; /* @ 0x0298 */
volatile uint32_t FCCFG; /* @ 0x029C */
volatile uint32_t FCSTS; /* @ 0x02A0 */
volatile uint32_t RESERVED6[3];
volatile uint32_t VWSTS; /* @ 0x02B0 */
volatile uint32_t RESERVED7[11];
volatile uint8_t CAPID; /* @ 0x02E0 */
volatile uint8_t CAP0; /* @ 0x02E1 */
volatile uint8_t CAP1; /* @ 0x02E2 */
volatile uint8_t CAPPC; /* @ 0x02E3 */
volatile uint8_t CAPVW; /* @ 0x02E4 */
volatile uint8_t CAPOOB; /* @ 0x02E5 */
volatile uint8_t CAPFC; /* @ 0x02E6 */
volatile uint8_t PCRDY; /* @ 0x02E7 */
volatile uint8_t OOBRDY; /* @ 0x02E8 */
volatile uint8_t FCRDY; /* @ 0x02E9 */
volatile uint8_t ERIS; /* @ 0x02EA */
volatile uint8_t ERIE; /* @ 0x02EB */
volatile uint8_t PLTSRC; /* @ 0x02EC */
volatile uint8_t VWRDY; /* @ 0x02ED */
volatile uint8_t SAFEBS; /* @ 0x02EE */
volatile uint8_t RESERVED8;
volatile uint32_t RESERVED9[16];
volatile uint32_t ACTV; /* @ 0x0330 */
volatile uint32_t IOHBAR[29]; /* @ 0x0334 */
volatile uint32_t RESERVED10;
volatile uint8_t SIRQ[19]; /* @ 0x03ac */
volatile uint8_t RESERVED11;
volatile uint32_t RESERVED12[12];
volatile uint32_t VWERREN; /* @ 0x03f0 */
volatile uint32_t RESERVED13[79];
struct espi_io_mbar MBAR[10]; /* @ 0x0530 */
volatile uint32_t RESERVED14[6];
struct espi_sram_bar SRAMBAR[2]; /* @ 0x05AC */
volatile uint32_t RESERVED15[16];
volatile uint32_t BM_STATUS; /* @ 0x0600 */
volatile uint32_t BM_IEN; /* @ 0x0604 */
volatile uint32_t BM_CONFIG; /* @ 0x0608 */
volatile uint32_t RESERVED16;
volatile uint32_t BM_CTRL1; /* @ 0x0610 */
volatile uint32_t BM_HADDR1_LSW; /* @ 0x0614 */
volatile uint32_t BM_HADDR1_MSW; /* @ 0x0618 */
volatile uint32_t BM_EC_ADDR1_LSW; /* @ 0x061C */
volatile uint32_t BM_EC_ADDR1_MSW; /* @ 0x0620 */
volatile uint32_t BM_CTRL2; /* @ 0x0624 */
volatile uint32_t BM_HADDR2_LSW; /* @ 0x0628 */
volatile uint32_t BM_HADDR2_MSW; /* @ 0x062C */
volatile uint32_t BM_EC_ADDR2_LSW; /* @ 0x0630 */
volatile uint32_t BM_EC_ADDR2_MSW; /* @ 0x0634 */
volatile uint32_t RESERVED17[62];
struct espi_mbar_host HMBAR[10]; /* @ 0x0730 */
volatile uint32_t RESERVED18[6];
struct espi_sram_host_bar HSRAMBAR[2]; /* @ 0x07AC */
}; /* Size = 1984 (0x7c0) */
#ifdef __cplusplus
}
#endif
#endif /* #ifndef _MEC172X_ESPI_IO_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MEC172X_ESPI_SAF_H_
#define _MEC172X_ESPI_SAF_H_
#include <stdint.h>
#include <stddef.h>
#define MCHP_ESPI_SAF_BASE_ADDR 0x40008000u
#define MCHP_ESPI_SAF_COMM_BASE_ADDR 0x40071000u
/* SAF hardware supports up to 2 external SPI flash devices */
#define MCHP_ESPI_SAF_CS_MAX 2
/* Three TAG Map registers */
#define MCHP_ESPI_SAF_TAGMAP_MAX 3
/* 17 protection regions */
#define MCHP_ESPI_SAF_PR_MAX 17
#define MCHP_SAF_FL_CM_PRF_CS0_OFS 0x1b0u
#define MCHP_SAF_FL_CM_PRF_CS1_OFS 0x1b2u
#define MCHP_ESPI_SAF_BASE 0x40008000u
#define MCHP_ESPI_SAF_COMM_BASE 0x40071000u
#define MCHP_ESPI_SAF_COMM_MODE_OFS 0x2b8u
#define MCHP_ESPI_SAF_COMM_MODE_ADDR (MCHP_ESPI_SAF_COMM_BASE_ADDR + \
MCHP_ESPI_SAF_COMM_MODE_OFS)
/* SAF Protection region described by 4 32-bit registers. 17 regions */
#define MCHP_ESPI_SAF_PROT_MAX 17u
/* Register bit definitions */
/* SAF EC Portal Command register */
#define MCHP_SAF_ECP_CMD_OFS 0x18u
#define MCHP_SAF_ECP_CMD_MASK 0xff00ffffu
#define MCHP_SAF_ECP_CMD_PUT_POS 0
#define MCHP_SAF_ECP_CMD_PUT_MASK 0xffu
#define MCHP_SAF_ECP_CMD_PUT_FLASH_NP 0x0au
#define MCHP_SAF_ECP_CMD_CTYPE_POS 8
#define MCHP_SAF_ECP_CMD_CTYPE_MSK0 0xffu
#define MCHP_SAF_ECP_CMD_CTYPE_MASK 0xff00u
#define MCHP_SAF_ECP_CMD_CTYPE_READ 0x0000u
#define MCHP_SAF_ECP_CMD_CTYPE_WRITE 0x0100u
#define MCHP_SAF_ECP_CMD_CTYPE_ERASE 0x0200u
#define MCHP_SAF_ECP_CMD_CTYPE_RPMC_OP1_CS0 0x0300u
#define MCHP_SAF_ECP_CMD_CTYPE_RPMC_OP2_CS0 0x0400u
#define MCHP_SAF_ECP_CMD_CTYPE_RPMC_OP1_CS1 0x8300u
#define MCHP_SAF_ECP_CMD_CTYPE_RPMC_OP2_CS1 0x8400u
#define MCHP_SAF_ECP_CMD_LEN_POS 24
#define MCHP_SAF_ECP_CMD_LEN_MASK0 0xffu
#define MCHP_SAF_ECP_CMD_LEN_MASK 0xff000000ul
/* Read/Write request size (1 <= reqlen <= 64) bytes */
#define MCHP_SAF_ECP_CMD_RW_LEN_MIN 1u
#define MCHP_SAF_ECP_CMD_RW_LEN_MAX 64u
/* Only three erase sizes are supported encoded as */
#define MCHP_SAF_ECP_CMD_ERASE_4K 0u
#define MCHP_SAF_ECP_CMD_ERASE_32K BIT(24)
#define MCHP_SAF_ECP_CMD_ERASE_64K BIT(25)
/* Zero based command values */
#define MCHP_SAF_ECP_CMD_READ 0x00u
#define MCHP_SAF_ECP_CMD_WRITE 0x01u
#define MCHP_SAF_ECP_CMD_ERASE 0x02u
#define MCHP_SAF_ECP_CMD_RPMC_OP1_CS0 0x03u
#define MCHP_SAF_ECP_CMD_RPMC_OP2_CS0 0x04u
#define MCHP_SAF_ECP_CMD_RPMC_OP1_CS1 0x83u
#define MCHP_SAF_ECP_CMD_RPMC_OP2_CS1 0x84u
/* SAF EC Portal Flash Address register */
#define MCHP_SAF_ECP_FLAR_OFS 0x1cu
#define MCHP_SAF_ECP_FLAR_MASK 0xffffffffu
/* SAF EC Portal Start register */
#define MCHP_SAF_ECP_START_OFS 0x20u
#define MCHP_SAF_ECP_START_MASK 0x01u
#define MCHP_SAF_ECP_START_POS 0
#define MCHP_SAF_ECP_START BIT(0)
/* SAF EC Portal Buffer Address register */
#define MCHP_SAF_ECP_BFAR_OFS 0x24u
#define MCHP_SAF_ECP_BFAR_MASK 0xfffffffcu
/* SAF EC Portal Status register */
#define MCHP_SAF_ECP_STS_OFS 0x28u
#define MCHP_SAF_ECP_STS_MASK 0x1ffu
#define MCHP_SAF_ECP_STS_ERR_MASK 0x1fcu
#define MCHP_SAF_ECP_STS_DONE_POS 0
#define MCHP_SAF_ECP_STS_DONE_TST_POS 1
#define MCHP_SAF_ECP_STS_TMOUT_POS 2
#define MCHP_SAF_ECP_STS_OOR_POS 3
#define MCHP_SAF_ECP_STS_AV_POS 4
#define MCHP_SAF_ECP_STS_BND_4K_POS 5
#define MCHP_SAF_ECP_STS_ERSZ_POS 6
#define MCHP_SAF_ECP_STS_ST_OVFL_POS 7
#define MCHP_SAF_ECP_STS_BAD_REQ_POS 8
#define MCHP_SAF_ECP_STS_DONE BIT(0)
#define MCHP_SAF_ECP_STS_DONE_TST BIT(1)
#define MCHP_SAF_ECP_STS_TMOUT BIT(2)
#define MCHP_SAF_ECP_STS_OOR BIT(3)
#define MCHP_SAF_ECP_STS_AV BIT(4)
#define MCHP_SAF_ECP_STS_BND_4K BIT(5)
#define MCHP_SAF_ECP_STS_ERSZ BIT(6)
#define MCHP_SAF_ECP_STS_ST_OVFL BIT(7)
#define MCHP_SAF_ECP_STS_BAD_REQ BIT(8)
/* SAF EC Portal Interrupt Enable register */
#define MCHP_SAF_ECP_INTEN_OFS 0x2cu
#define MCHP_SAF_ECP_INTEN_MASK 0x01u
#define MCHP_SAF_ECP_INTEN_DONE_POS 0
#define MCHP_SAF_ECP_INTEN_DONE BIT(0)
/* SAF Flash Configuration Size Limit register */
#define MCHP_SAF_FL_CFG_SIZE_LIM_OFS 0x30u
#define MCHP_SAF_FL_CFG_SIZE_LIM_MASK 0xffffffffu
/* SAF Flash Configuration Threshold register */
#define MCHP_SAF_FL_CFG_THRH_OFS 0x34u
#define MCHP_SAF_FL_CFG_THRH_MASK 0xffffffffu
/* SAF Flash Configuration Miscellaneous register */
#define MCHP_SAF_FL_CFG_MISC_OFS 0x38u
#define MCHP_SAF_FL_CFG_MISC_MASK 0x000030f3u
#define MCHP_SAF_FL_CFG_MISC_PFOE_MASK 0x3u
#define MCHP_SAF_FL_CFG_MISC_PFOE_DFLT 0u
#define MCHP_SAF_FL_CFG_MISC_PFOE_EXP 0x3u
#define MCHP_SAF_FL_CFG_MISC_CS0_4BM_POS 4
#define MCHP_SAF_FL_CFG_MISC_CS1_4BM_POS 5
#define MCHP_SAF_FL_CFG_MISC_CS0_CPE_POS 6
#define MCHP_SAF_FL_CFG_MISC_CS1_CPE_POS 7
#define MCHP_SAF_FL_CFG_MISC_SAF_EN_POS 12
#define MCHP_SAF_FL_CFG_MISC_SAF_LOCK_POS 13
#define MCHP_SAF_FL_CFG_MISC_CS0_4BM BIT(4)
#define MCHP_SAF_FL_CFG_MISC_CS1_4BM BIT(5)
#define MCHP_SAF_FL_CFG_MISC_CS0_CPE BIT(6)
#define MCHP_SAF_FL_CFG_MISC_CS1_CPE BIT(7)
#define MCHP_SAF_FL_CFG_MISC_SAF_EN BIT(12)
#define MCHP_SAF_FL_CFG_MISC_SAF_LOCK BIT(13)
/* SAF eSPI Monitor Status and Interrupt enable registers */
#define MCHP_SAF_ESPI_MON_STATUS_OFS 0x3cu
#define MCHP_SAF_ESPI_MON_INTEN_OFS 0x40u
#define MCHP_SAF_ESPI_MON_STS_IEN_MSK 0x1fu
#define MCHP_SAF_ESPI_MON_STS_IEN_TMOUT_POS 0
#define MCHP_SAF_ESPI_MON_STS_IEN_OOR_POS 1
#define MCHP_SAF_ESPI_MON_STS_IEN_AV_POS 2
#define MCHP_SAF_ESPI_MON_STS_IEN_BND_4K_POS 3
#define MCHP_SAF_ESPI_MON_STS_IEN_ERSZ_POS 4
#define MCHP_SAF_ESPI_MON_STS_IEN_TMOUT BIT(0)
#define MCHP_SAF_ESPI_MON_STS_IEN_OOR BIT(1)
#define MCHP_SAF_ESPI_MON_STS_IEN_AV BIT(2)
#define MCHP_SAF_ESPI_MON_STS_IEN_BND_4K BIT(3)
#define MCHP_SAF_ESPI_MON_STS_IEN_ERSZ BIT(4)
/* SAF EC Portal Busy register */
#define MCHP_SAF_ECP_BUSY_OFS 0x44u
#define MCHP_SAF_ECP_BUSY_MASK 0x01u
#define MCHP_SAF_ECP_EC0_BUSY_POS 0
#define MCHP_SAF_ECP_EC1_BUSY_POS 1
#define MCHP_SAF_ECP_EC0_BUSY BIT(0)
#define MCHP_SAF_ECP_EC1_BUSY BIT(1)
/* SAF CS0/CS1 Opcode A registers */
#define MCHP_SAF_CS0_OPA_OFS 0x4cu
#define MCHP_SAF_CS1_OPA_OFS 0x5cu
#define MCHP_SAF_CS_OPA_MASK 0xffffffffu
#define MCHP_SAF_CS_OPA_WE_POS 0
#define MCHP_SAF_CS_OPA_WE_MASK 0xfful
#define MCHP_SAF_CS_OPA_SUS_POS 8
#define MCHP_SAF_CS_OPA_SUS_MASK 0xff00ul
#define MCHP_SAF_CS_OPA_RSM_POS 16
#define MCHP_SAF_CS_OPA_RSM_MASK 0xff0000ul
#define MCHP_SAF_CS_OPA_POLL1_POS 24
#define MCHP_SAF_CS_OPA_POLL1_MASK 0xff000000ul
/* SAF CS0/CS1 Opcode B registers */
#define MCHP_SAF_CS0_OPB_OFS 0x50u
#define MCHP_SAF_CS1_OPB_OFS 0x60u
#define MCHP_SAF_CS_OPB_OFS 0xffffffffu
#define MCHP_SAF_CS_OPB_ER0_POS 0
#define MCHP_SAF_CS_OPB_ER0_MASK 0xffu
#define MCHP_SAF_CS_OPB_ER1_POS 8
#define MCHP_SAF_CS_OPB_ER1_MASK 0xff00ul
#define MCHP_SAF_CS_OPB_ER2_POS 16
#define MCHP_SAF_CS_OPB_ER2_MASK 0xff0000ul
#define MCHP_SAF_CS_OPB_PGM_POS 24
#define MCHP_SAF_CS_OPB_PGM_MASK 0xff000000ul
/* SAF CS0/CS1 Opcode C registers */
#define MCHP_SAF_CS0_OPC_OFS 0x54u
#define MCHP_SAF_CS1_OPC_OFS 0x64u
#define MCHP_SAF_CS_OPC_MASK 0xffffffffu
#define MCHP_SAF_CS_OPC_RD_POS 0
#define MCHP_SAF_CS_OPC_RD_MASK 0xffu
#define MCHP_SAF_CS_OPC_MNC_POS 8
#define MCHP_SAF_CS_OPC_MNC_MASK 0xff00ul
#define MCHP_SAF_CS_OPC_MC_POS 16
#define MCHP_SAF_CS_OPC_MC_MASK 0xff0000ul
#define MCHP_SAF_CS_OPC_POLL2_POS 24
#define MCHP_SAF_CS_OPC_POLL2_MASK 0xff000000ul
/* SAF CS0/CS1 registers */
#define MCHP_SAF_CS0_DESCR_OFS 0x58u
#define MCHP_SAF_CS1_DESCR_OFS 0x68u
#define MCHP_SAF_CS_DESCR_MASK 0x0000ff0fu
#define MCHP_SAF_CS_DESCR_ENTC_POS 0
#define MCHP_SAF_CS_DESCR_ENTC_MASK 0x0fu
#define MCHP_SAF_CS_DESCR_RDC_POS 8
#define MCHP_SAF_CS_DESCR_RDC_MASK 0x0f00ul
#define MCHP_SAF_CS_DESCR_SZC_POS 12
#define MCHP_SAF_CS_DESCR_SZC_MASK 0xf000ul
/* SAF Flash Configuration General Descriptors register */
#define MCHP_SAF_FL_CFG_GEN_DESCR_OFS 0x6cu
#define MCHP_SAF_FL_CFG_GEN_DESCR_MASK 0x0000ff0fu
/* value for standard 16 descriptor programming */
#define MCHP_SAF_FL_CFG_GEN_DESCR_STD 0x0000ee0cu
#define MCHP_SAF_FL_CFG_GEN_DESCR_EXC_POS 0
#define MCHP_SAF_FL_CFG_GEN_DESCR_EXC_MASK 0x0fu
#define MCHP_SAF_FL_CFG_GEN_DESCR_POLL1_POS 8
#define MCHP_SAF_FL_CFG_GEN_DESCR_POLL1_MASK \
SHLU32(0x0Fu, MCHP_SAF_FL_CFG_GEN_DESCR_POLL1_POS)
#define MCHP_SAF_FL_CFG_GEN_DESCR_POLL2_POS 12
#define MCHP_SAF_FL_CFG_GEN_DESCR_POLL2_MASK \
SHLU32(0x0Fu, MCHP_SAF_FL_CFG_GEN_DESCR_POLL2_POS)
/* SAF Protection Lock register */
#define MCHP_SAF_PROT_LOCK_OFS 0x70u
#define MCHP_SAF_PROT_LOCK_MASK 0x1ffffu
#define MCHP_SAF_PROT_LOCK0 BIT(0)
#define MCHP_SAF_PROT_LOCK1 BIT(1)
#define MCHP_SAF_PROT_LOCK2 BIT(2)
#define MCHP_SAF_PROT_LOCK3 BIT(3)
#define MCHP_SAF_PROT_LOCK4 BIT(4)
#define MCHP_SAF_PROT_LOCK5 BIT(5)
#define MCHP_SAF_PROT_LOCK6 BIT(6)
#define MCHP_SAF_PROT_LOCK7 BIT(7)
#define MCHP_SAF_PROT_LOCK8 BIT(8)
#define MCHP_SAF_PROT_LOCK9 BIT(9)
#define MCHP_SAF_PROT_LOCK10 BIT(10)
#define MCHP_SAF_PROT_LOCK11 BIT(11)
#define MCHP_SAF_PROT_LOCK12 BIT(12)
#define MCHP_SAF_PROT_LOCK13 BIT(13)
#define MCHP_SAF_PROT_LOCK14 BIT(14)
#define MCHP_SAF_PROT_LOCK15 BIT(15)
#define MCHP_SAF_PROT_LOCK16 BIT(16)
/* SAF Protection Dirty register */
#define MCHP_SAF_PROT_DIRTY_OFS 0x74u
#define MCHP_SAF_PROT_DIRTY_MASK 0xfffu
#define MCHP_SAF_PROT_DIRTY0 BIT(0)
#define MCHP_SAF_PROT_DIRTY1 BIT(1)
#define MCHP_SAF_PROT_DIRTY2 BIT(2)
#define MCHP_SAF_PROT_DIRTY3 BIT(3)
#define MCHP_SAF_PROT_DIRTY4 BIT(4)
#define MCHP_SAF_PROT_DIRTY5 BIT(5)
#define MCHP_SAF_PROT_DIRTY6 BIT(6)
#define MCHP_SAF_PROT_DIRTY7 BIT(7)
#define MCHP_SAF_PROT_DIRTY8 BIT(8)
#define MCHP_SAF_PROT_DIRTY9 BIT(9)
#define MCHP_SAF_PROT_DIRTY10 BIT(10)
#define MCHP_SAF_PROT_DIRTY11 BIT(11)
/* SAF Tag Map 0 register */
#define MCHP_SAF_TAG_MAP0_OFS 0x78u
#define MCHP_SAF_TAG_MAP0_MASK 0x77777777u
#define MCHP_SAF_TAG_MAP0_DFLT_VAL 0x23221100u
#define MCHP_SAF_TAG_MAP0_STM0_POS 0
#define MCHP_SAF_TAG_MAP0_STM0_MASK 0x07u
#define MCHP_SAF_TAG_MAP0_STM1_POS 4
#define MCHP_SAF_TAG_MAP0_STM1_MASK \
SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP0_STM1_POS)
#define MCHP_SAF_TAG_MAP0_STM2_POS 8
#define MCHP_SAF_TAG_MAP0_STM2_MASK \
SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM2_POS)
#define MCHP_SAF_TAG_MAP0_STM3_POS 12
#define MCHP_SAF_TAG_MAP0_STM3_MASK \
SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM3_POS)
#define MCHP_SAF_TAG_MAP0_STM4_POS 16
#define MCHP_SAF_TAG_MAP0_STM4_MASK \
SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM4_POS)
#define MCHP_SAF_TAG_MAP0_STM5_POS 20
#define MCHP_SAF_TAG_MAP0_STM5_MASK \
SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM5_POS)
#define MCHP_SAF_TAG_MAP0_STM6_POS 24
#define MCHP_SAF_TAG_MAP0_STM6_MASK \
SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM6_POS)
#define MCHP_SAF_TAG_MAP0_STM7_POS 28
#define MCHP_SAF_TAG_MAP0_STM7_MASK \
SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM7_POS)
/* SAF Tag Map 1 register */
#define MCHP_SAF_TAG_MAP1_OFS 0x7Cu
#define MCHP_SAF_TAG_MAP1_MASK 0x77777777u
#define MCHP_SAF_TAG_MAP1_DFLT_VAL 0x77677767u
#define MCHP_SAF_TAG_MAP1_STM8_POS 0
#define MCHP_SAF_TAG_MAP1_STM8_MASK 0x07u
#define MCHP_SAF_TAG_MAP1_STM9_POS 4
#define MCHP_SAF_TAG_MAP1_STM9_MASK \
SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STM9_POS)
#define MCHP_SAF_TAG_MAP1_STMA_POS 8
#define MCHP_SAF_TAG_MAP1_STMA_MASK \
SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STMA_POS)
#define MCHP_SAF_TAG_MAP1_STMB_POS 12
#define MCHP_SAF_TAG_MAP1_STMB_MASK \
SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STMB_POS)
#define MCHP_SAF_TAG_MAP1_STMC_POS 16
#define MCHP_SAF_TAG_MAP1_STMC_MASK \
SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STMC_POS)
#define MCHP_SAF_TAG_MAP1_STMD_POS 20
#define MCHP_SAF_TAG_MAP1_STMD_MASK \
SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STMD_POS)
#define MCHP_SAF_TAG_MAP1_STME_POS 24
#define MCHP_SAF_TAG_MAP1_STME_MASK \
SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STME_POS)
#define MCHP_SAF_TAG_MAP1_STMF_POS 28
#define MCHP_SAF_TAG_MAP1_STMF_MASK \
SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STMF_POS)
/* SAF Tag Map 2 register */
#define MCHP_SAF_TAG_MAP2_OFS 0x80u
#define MCHP_SAF_TAG_MAP2_MASK 0x80000007u
#define MCHP_SAF_TAG_MAP2_DFLT_VAL 0x00000005u
#define MCHP_SAF_TAG_MAP2_SM_EC_POS 0
#define MCHP_SAF_TAG_MAP2_SM_EC_MASK 0x07u
#define MCHP_SAF_TAG_MAP2_LOCK_POS 31
#define MCHP_SAF_TAG_MAP2_LOCK BIT(MCHP_SAF_TAG_MAP2_LOCK_POS)
/* SAF Protection Region Start registers */
#define MCHP_SAF_PROT_RG0_START_OFS 0x84u
#define MCHP_SAF_PROT_RG1_START_OFS 0x94u
#define MCHP_SAF_PROT_RG2_START_OFS 0xA4u
#define MCHP_SAF_PROT_RG3_START_OFS 0xB4u
#define MCHP_SAF_PROT_RG4_START_OFS 0xC4u
#define MCHP_SAF_PROT_RG5_START_OFS 0xD4u
#define MCHP_SAF_PROT_RG6_START_OFS 0xE4u
#define MCHP_SAF_PROT_RG7_START_OFS 0xF4u
#define MCHP_SAF_PROT_RG8_START_OFS 0x104u
#define MCHP_SAF_PROT_RG9_START_OFS 0x114u
#define MCHP_SAF_PROT_RG10_START_OFS 0x124u
#define MCHP_SAF_PROT_RG11_START_OFS 0x134u
#define MCHP_SAF_PROT_RG12_START_OFS 0x144u
#define MCHP_SAF_PROT_RG13_START_OFS 0x154u
#define MCHP_SAF_PROT_RG14_START_OFS 0x164u
#define MCHP_SAF_PROT_RG15_START_OFS 0x174u
#define MCHP_SAF_PROT_RG16_START_OFS 0x184u
#define MCHP_SAF_PROT_RG_START_MASK 0xfffffu
#define MCHP_SAF_PROT_RG_START_DFLT 0x07fffu
/* SAF Protection Region Limit registers */
#define MCHP_SAF_PROT_RG0_LIMIT_OFS 0x88u
#define MCHP_SAF_PROT_RG1_LIMIT_OFS 0x98u
#define MCHP_SAF_PROT_RG2_LIMIT_OFS 0xa8u
#define MCHP_SAF_PROT_RG3_LIMIT_OFS 0xb8u
#define MCHP_SAF_PROT_RG4_LIMIT_OFS 0xc8u
#define MCHP_SAF_PROT_RG5_LIMIT_OFS 0xd8u
#define MCHP_SAF_PROT_RG6_LIMIT_OFS 0xe8u
#define MCHP_SAF_PROT_RG7_LIMIT_OFS 0xf8u
#define MCHP_SAF_PROT_RG8_LIMIT_OFS 0x108u
#define MCHP_SAF_PROT_RG9_LIMIT_OFS 0x118u
#define MCHP_SAF_PROT_RG10_LIMIT_OFS 0x128u
#define MCHP_SAF_PROT_RG11_LIMIT_OFS 0x138u
#define MCHP_SAF_PROT_RG12_LIMIT_OFS 0x148u
#define MCHP_SAF_PROT_RG13_LIMIT_OFS 0x158u
#define MCHP_SAF_PROT_RG14_LIMIT_OFS 0x168u
#define MCHP_SAF_PROT_RG15_LIMIT_OFS 0x178u
#define MCHP_SAF_PROT_RG16_LIMIT_OFS 0x188u
#define MCHP_SAF_PROT_RG_LIMIT_MASK 0xfffffu
#define MCHP_SAF_PROT_RG_LIMIT_DFLT 0
/* SAF Protection Region Write Bitmap registers */
#define MCHP_SAF_PROT_RG0_WBM_OFS 0x8cu
#define MCHP_SAF_PROT_RG1_WBM_OFS 0x9cu
#define MCHP_SAF_PROT_RG2_WBM_OFS 0xacu
#define MCHP_SAF_PROT_RG3_WBM_OFS 0xbcu
#define MCHP_SAF_PROT_RG4_WBM_OFS 0xccu
#define MCHP_SAF_PROT_RG5_WBM_OFS 0xdcu
#define MCHP_SAF_PROT_RG6_WBM_OFS 0xefu
#define MCHP_SAF_PROT_RG7_WBM_OFS 0xfcu
#define MCHP_SAF_PROT_RG8_WBM_OFS 0x10cu
#define MCHP_SAF_PROT_RG9_WBM_OFS 0x11cu
#define MCHP_SAF_PROT_RG10_WBM_OFS 0x12cu
#define MCHP_SAF_PROT_RG11_WBM_OFS 0x13cu
#define MCHP_SAF_PROT_RG12_WBM_OFS 0x14cu
#define MCHP_SAF_PROT_RG13_WBM_OFS 0x15cu
#define MCHP_SAF_PROT_RG14_WBM_OFS 0x16cu
#define MCHP_SAF_PROT_RG15_WBM_OFS 0x17cu
#define MCHP_SAF_PROT_RG16_WBM_OFS 0x18cu
#define MCHP_SAF_PROT_RG_WBM_MASK 0xffu
#define MCHP_SAF_PROT_RG_WBM0 BIT(0)
#define MCHP_SAF_PROT_RG_WBM1 BIT(1)
#define MCHP_SAF_PROT_RG_WBM2 BIT(2)
#define MCHP_SAF_PROT_RG_WBM3 BIT(3)
#define MCHP_SAF_PROT_RG_WBM4 BIT(4)
#define MCHP_SAF_PROT_RG_WBM5 BIT(5)
#define MCHP_SAF_PROT_RG_WBM6 BIT(6)
#define MCHP_SAF_PROT_RG_WBM7 BIT(7)
/* SAF Protection Region Read Bitmap registers */
#define MCHP_SAF_PROT_RG0_RBM_OFS 0x90u
#define MCHP_SAF_PROT_RG1_RBM_OFS 0xa0u
#define MCHP_SAF_PROT_RG2_RBM_OFS 0xb0u
#define MCHP_SAF_PROT_RG3_RBM_OFS 0xc0u
#define MCHP_SAF_PROT_RG4_RBM_OFS 0xd0u
#define MCHP_SAF_PROT_RG5_RBM_OFS 0xe0u
#define MCHP_SAF_PROT_RG6_RBM_OFS 0xf0u
#define MCHP_SAF_PROT_RG7_RBM_OFS 0x100u
#define MCHP_SAF_PROT_RG8_RBM_OFS 0x110u
#define MCHP_SAF_PROT_RG9_RBM_OFS 0x120u
#define MCHP_SAF_PROT_RG10_RBM_OFS 0x130u
#define MCHP_SAF_PROT_RG11_RBM_OFS 0x140u
#define MCHP_SAF_PROT_RG12_RBM_OFS 0x150u
#define MCHP_SAF_PROT_RG13_RBM_OFS 0x160u
#define MCHP_SAF_PROT_RG14_RBM_OFS 0x170u
#define MCHP_SAF_PROT_RG15_RBM_OFS 0x180u
#define MCHP_SAF_PROT_RG16_RBM_OFS 0x190u
#define MCHP_SAF_PROT_RG_RBM_MASK 0xffu
#define MCHP_SAF_PROT_RG_RBM0 BIT(0)
#define MCHP_SAF_PROT_RG_RBM1 BIT(1)
#define MCHP_SAF_PROT_RG_RBM2 BIT(2)
#define MCHP_SAF_PROT_RG_RBM3 BIT(3)
#define MCHP_SAF_PROT_RG_RBM4 BIT(4)
#define MCHP_SAF_PROT_RG_RBM5 BIT(5)
#define MCHP_SAF_PROT_RG_RBM6 BIT(6)
#define MCHP_SAF_PROT_RG_RBM7 BIT(7)
/* SAF Poll Timeout register */
#define MCHP_SAF_POLL_TMOUT_OFS 0x194u
#define MCHP_SAF_POLL_TMOUT_MASK 0x3ffffu
#define MCHP_SAF_POLL_TMOUT_5S 0x28000u
/* SAF Poll Interval register */
#define MCHP_SAF_POLL_INTRVL_OFS 0x198u
#define MCHP_SAF_POLL_INTRVL_MASK 0xffffu
/* SAF Suspend Resume Interval register */
#define MCHP_SAF_SUS_RSM_INTRVL_OFS 0x19Cu
#define MCHP_SAF_SUS_RSM_INTRVL_MASK 0xffffu
/* SAF Consecutive Read Timeout register */
#define MCHP_SAF_CRD_TMOUT_OFS 0x1a0u
#define MCHP_SAF_CRD_TMOUT_MASK 0xfffffu
/* SAF Flash CS0/CS1 Configuration Poll2 Mask registers */
#define MCHP_SAF_FL0_CFG_P2M_OFS 0x1a4u
#define MCHP_SAF_FL1_CFG_P2M_OFS 0x1a6u
#define MCHP_SAF_FL_CFG_P2M_MASK 0xffffu
/* SAF Flash Configuration Special Mode register */
#define MCHP_SAF_FL_CFG_SPM_OFS 0x1a8u
#define MCHP_SAF_FL_CFG_SPM_MASK 0x01u
#define MCHP_SAF_FL_CFG_SPM_DIS_SUSP BIT(0)
/* SAF Suspend Check Delay register */
#define MCHP_SAF_SUS_CHK_DLY_OFS 0x1acu
#define MCHP_SAF_SUS_CHK_DLY_MASK 0xfffffu
/* SAF Flash 0/1 Continuous Mode Prefix registers */
#define MCHP_SAF_FL_CM_PRF_OFS 0x1b0u
#define MCHP_SAF_FL_CM_PRF_MASK 0xffffu
#define MCHP_SAF_FL_CM_PRF_CS_OP_POS 0
#define MCHP_SAF_FL_CM_PRF_CS_OP_MASK 0xffu
#define MCHP_SAF_FL_CM_PRF_CS_DAT_POS 8
#define MCHP_SAF_FL_CM_PRF_CS_DAT_MASK \
SHLU32(MCHP_SAF_FL_CM_PRF_CS_OP_MASK, MCHP_SAF_FL_CM_PRF_CS_DAT_POS)
/* SAF DnX Protection Bypass register */
#define MCHP_SAF_DNX_PROT_BYP_OFS 0x1b4u
#define MCHP_SAF_DNX_PROT_BYP_MASK 0x1110ffffu
#define MCHP_SAF_DNX_PB_TAG_POS(n) ((uint32_t)(n) & 0xfu)
#define MCHP_SAF_DNX_PB_TAG(n) BIT(((n) & 0xfu))
#define MCHP_SAF_DNX_DS_RO_POS 20
#define MCHP_SAF_DNX_DS_RO BIT(20)
#define MCHP_SAF_DNX_DM_POS 24
#define MCHP_SAF_DNX_DM BIT(24)
#define MCHP_SAF_DNX_LK_POS 28
#define MCHP_SAF_DNX_LK BIT(28)
/* SAF Activity Count Reload Valud register */
#define MCHP_SAF_AC_RELOAD_OFS 0x1b8u
#define MCHP_SAF_AC_RELOAD_REG_MSK 0xffffu
/* SAF Power Down Control register */
#define SAF_PWRDN_CTRL_OFS 0x1bcu
#define SAF_PWRDN_CTRL_REG_MSK 0x0fu
#define SAF_PWRDN_CTRL_CS0_PD_EN_POS 0
#define SAF_PWRDN_CTRL_CS1_PD_EN_POS 1
#define SAF_PWRDN_CTRL_CS0_WPA_EN_POS 2
#define SAF_PWRDN_CTRL_CS1_WPA_EN_POS 3
/* SAF Memory Power Status register (RO) */
#define SAF_MEM_PWR_STS_OFS 0x1c0u
#define SAF_MEM_PWR_STS_REG_MSK 0x03u
/* SAF Config CS0 and CS1 Opcode registers */
#define SAF_CFG_CS0_OPC_OFS 0x1c4u
#define SAF_CFG_CS1_OPC_OFS 0x1c8u
#define SAF_CFG_CS_OPC_REG_MSK 0x00ffffffu
#define SAF_CFG_CS_OPC_ENTER_PD_POS 0
#define SAF_CFG_CS_OPC_ENTER_PD_MSK0 0xffu
#define SAF_CFG_CS_OPC_ENTER_PD_MSK 0xffu
#define SAF_CFG_CS_OPC_EXIT_PD_POS 8
#define SAF_CFG_CS_OPC_EXIT_PD_MSK0 0xffu
#define SAF_CFG_CS_OPC_EXIT_PD_MSK 0xff00u
#define SAF_CFG_CS_OPC_RPMC_OP2_POS 16
#define SAF_CFG_CS_OPC_RPMC_OP2_MSK0 0xffu
#define SAF_CFG_CS_OPC_RPMC_OP2_MSK 0xff0000u
/* SAF Flash Power Down/Up Timerout register */
#define SAF_FL_PWR_TMOUT_OFS 0x1ccu
#define SAF_FL_PWR_TMOUT_REG_MSK 0xffffu
/* SAF Clock Divider CS0 and CS1 registers */
#define SAF_CLKDIV_CS0_OFS 0x200u
#define SAF_CLKDIV_CS1_OFS 0x204u
#define SAF_CLKDIV_CS_REG_MSK 0xffffffffu
#define SAF_CLKDIV_CS_READ_POS 0
#define SAF_CLKDIV_CS_REST_POS 16
#define SAF_CLKDIV_CS_MSK0 0xffffu
/* SAF RPMC OP2 eSPI, EC0, and EC1 Result Address register */
#define SAF_RPMC_OP2_ESPI_RES_OFS 0x208u
#define SAF_RPMC_OP2_EC0_RES_OFS 0x20cu
#define SAF_RPMC_OP2_EC1_RES_OFS 0x210u
#define SAF_RPMC_OP2_RES_REG_MSK 0xffffffffu
/* SAF Communication Mode */
#define MCHP_SAF_COMM_MODE_MASK 0x01u
/* Allow pre-fetch from flash devices */
#define MCHP_SAF_COMM_MODE_PF_EN BIT(0)
/* SAF TAG numbers[0:0xF] */
#define MCHP_SAF_TAG_M0T0 0u
#define MCHP_SAF_TAG_M0T1 1u
#define MCHP_SAF_TAG_M1T0 2u
#define MCHP_SAF_TAG_M1T1 3u
#define MCHP_SAF_TAG_M2T0 4u
#define MCHP_SAF_TAG_M2T1 5u
#define MCHP_SAF_TAG_M3T0 6u
#define MCHP_SAF_TAG_M2T2 7u
#define MCHP_SAF_TAG_M6T0 9u
#define MCHP_SAF_TAG_M6T1 0x0du
#define MCHP_SAF_TAG_MAX 0x10u
/* SAF Master numbers */
#define MCHP_SAF_MSTR_CS_INIT 0u
#define MCHP_SAF_MSTR_CPU 1u
#define MCHP_SAF_MSTR_CS_ME 2u
#define MCHP_SAF_MSTR_CS_LAN 3u
#define MCHP_SAF_MSTR_UNUSED4 4u
#define MCHP_SAF_MSTR_EC_FW 5u
#define MCHP_SAF_MSTR_CS_IE 6u
#define MCHP_SAF_MSTR_UNUSED7 7u
#define MCHP_SAF_MSTR_MAX 8u
#define MCHP_SAF_MSTR_ALL 0xffu
/* eSPI SAF */
/** @brief SAF SPI Opcodes and descriptor indices */
struct mchp_espi_saf_op {
volatile uint32_t OPA;
volatile uint32_t OPB;
volatile uint32_t OPC;
volatile uint32_t OP_DESCR;
};
/** @brief SAF protection regions contain 4 32-bit registers. */
struct mchp_espi_saf_pr {
volatile uint32_t START;
volatile uint32_t LIMIT;
volatile uint32_t WEBM;
volatile uint32_t RDBM;
};
/** @brief eSPI SAF configuration and control registers at 0x40008000 */
struct mchp_espi_saf {
uint32_t RSVD1[6];
volatile uint32_t SAF_ECP_CMD; /* 0x18 */
volatile uint32_t SAF_ECP_FLAR; /* 0x1c */
volatile uint32_t SAF_ECP_START; /* 0x20 */
volatile uint32_t SAF_ECP_BFAR; /* 0x24 */
volatile uint32_t SAF_ECP_STATUS; /* 0x28 */
volatile uint32_t SAF_ECP_INTEN; /* 0x2c */
volatile uint32_t SAF_FL_CFG_SIZE_LIM; /* 0x30 */
volatile uint32_t SAF_FL_CFG_THRH; /* 0x34 */
volatile uint32_t SAF_FL_CFG_MISC; /* 0x38 */
volatile uint32_t SAF_ESPI_MON_STATUS; /* 0x3c */
volatile uint32_t SAF_ESPI_MON_INTEN; /* 0x40 */
volatile uint32_t SAF_ECP_BUSY; /* 0x44 */
uint32_t RSVD2[1];
struct mchp_espi_saf_op SAF_CS_OP[2]; /* 0x4c - 0x6b */
volatile uint32_t SAF_FL_CFG_GEN_DESCR; /* 0x6c */
volatile uint32_t SAF_PROT_LOCK; /* 0x70 */
volatile uint32_t SAF_PROT_DIRTY; /* 0x74 */
volatile uint32_t SAF_TAG_MAP[3]; /* 0x78 - 0x83 */
struct mchp_espi_saf_pr SAF_PROT_RG[17]; /* 0x84 - 0x193 */
volatile uint32_t SAF_POLL_TMOUT; /* 0x194 */
volatile uint32_t SAF_POLL_INTRVL; /* 0x198 */
volatile uint32_t SAF_SUS_RSM_INTRVL; /* 0x19c */
volatile uint32_t SAF_CONSEC_RD_TMOUT; /* 0x1a0 */
volatile uint16_t SAF_CS0_CFG_P2M; /* 0x1a4 */
volatile uint16_t SAF_CS1_CFG_P2M; /* 0x1a6 */
volatile uint32_t SAF_FL_CFG_SPM; /* 0x1a8 */
volatile uint32_t SAF_SUS_CHK_DLY; /* 0x1ac */
volatile uint16_t SAF_CS0_CM_PRF; /* 0x1b0 */
volatile uint16_t SAF_CS1_CM_PRF; /* 0x1b2 */
volatile uint32_t SAF_DNX_PROT_BYP; /* 0x1b4 */
volatile uint32_t SAF_AC_RELOAD; /* 0x1b8 */
volatile uint32_t SAF_PWRDN_CTRL; /* 0x1bc */
volatile uint32_t SAF_MEM_PWR_STS; /* 0x1c0 */
volatile uint32_t SAF_CFG_CS0_OPD; /* 0x1c4 */
volatile uint32_t SAF_CFG_CS1_OPD; /* 0x1c8 */
volatile uint32_t SAF_FL_PWR_TMOUT; /* 0x1cc */
uint32_t RSVD[12];
volatile uint32_t SAF_CLKDIV_CS0; /* 0x200 */
volatile uint32_t SAF_CLKDIV_CS1; /* 0x204 */
volatile uint32_t SAF_RPMC_OP2_ESPI_RES; /* 0x208 */
volatile uint32_t SAF_RPMC_OP2_EC0_RES; /* 0x20c */
volatile uint32_t SAF_RPMC_OP2_EC1_RES; /* 0x210 */
};
struct mchp_espi_saf_comm { /* @ 0x40071000 */
uint32_t TEST0;
uint32_t TEST1;
uint32_t TEST2;
uint32_t TEST3;
uint32_t TEST4;
uint32_t TEST5;
uint32_t TEST6;
uint32_t RSVD1[(0x2b8 - 0x01c) / 4];
uint32_t SAF_COMM_MODE; /* @ 0x400712b8 */
uint32_t TEST7;
};
#endif /* _MEC172X_ESPI_SAF_H_ */

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MEC172X_ESPI_VW_H
#define _MEC172X_ESPI_VW_H
#include <stdint.h>
#include <stddef.h>
/* Master to Slave VW register: 96-bit (3 32 bit registers) */
/* 32-bit word 0 (bits[31:0]) */
#define ESPI_M2SW0_OFS 0u
#define ESPI_M2SW0_IDX_POS 0
#define ESPI_M2SW0_IDX_MASK 0xffu
#define ESPI_M2SW0_MTOS_SRC_POS 8u
#define ESPI_M2SW0_MTOS_SRC_MASK0 0x03u
#define ESPI_M2SW0_MTOS_SRC_MASK 0x300u
#define ESPI_M2SW0_MTOS_SRC_ESPI_RST 0u
#define ESPI_M2SW0_MTOS_SRC_SYS_RST 0x100u
#define ESPI_M2SW0_MTOS_SRC_SIO_RST 0x200u
#define ESPI_M2SW0_MTOS_SRC_PLTRST 0x300u
#define ESPI_M2SW0_MTOS_STATE_POS 12u
#define ESPI_M2SW0_MTOS_STATE_MASK0 0x0fu
#define ESPI_M2SW0_MTOS_STATE_MASK 0xf000u
/* 32-bit word 1 (bits[63:32]) */
#define ESPI_M2SW1_OFS 4u
#define ESPI_M2SW1_SRC0_SEL_POS 0
#define ESPI_M2SW1_SRC_SEL_MASK0 0x0fu
#define ESPI_M2SW1_SRC0_SEL_MASK 0x0fu
#define ESPI_M2SW1_SRC1_SEL_POS 8
#define ESPI_M2SW1_SRC1_SEL_MASK 0x0f00u
#define ESPI_M2SW1_SRC2_SEL_POS 16
#define ESPI_M2SW1_SRC2_SEL_MASK 0x0f0000u
#define ESPI_M2SW1_SRC3_SEL_POS 24
#define ESPI_M2SW1_SRC3_SEL_MASK 0x0f000000u
/* 0 <= n < 4 */
#define ESPI_M2SW1_SRC_SEL_POS(n) ((n) * 8u)
#define ESPI_M2SW1_SRC_SEL_MASK(n) SHLU32(0xfu, ((n) * 8u))
#define ESPI_M2SW1_SRC_SEL_VAL(n, v) SHLU32(((v) & 0xfu), ((n) * 8u))
/* 32-bit word 2 (bits[95:64]) */
#define ESPI_M2SW2_OFS 8u
#define ESPI_M2SW2_SRC_MASK0 0x0fu
#define ESPI_M2SW2_SRC0_POS 0
#define ESPI_M2SW2_SRC0_MASK 0x0fu
#define ESPI_M2SW2_SRC1_POS 8u
#define ESPI_M2SW2_SRC1_MASK 0x0f00u
#define ESPI_M2SW2_SRC2_POS 16u
#define ESPI_M2SW2_SRC2_MASK 0x0f0000u
#define ESPI_M2SW2_SRC3_POS 24u
#define ESPI_M2SW2_SRC3_MASK 0x0f000000u
/* 0 <= n < 4 */
#define ESPI_M2SW2_SRC_POS(n) ((n) * 8u)
#define ESPI_M2SW2_SRC_MASK(n) SHLU32(0xfu, ((n) * 8u))
#define ESPI_M2SW2_SRC_VAL(n, v) SHLU32(((v) & 0xfu), ((n) * 8u))
/*
* Zero based values used for above SRC_SEL fields.
* These values select the interrupt sensitivity for the VWire.
* Example: Set SRC1 to Level High
*
* r = read MSVW1 register
* r &= ESPI_M2SW1_SRC_SEL_MASK(1)
* r |= ESPI_MSVW1_SRC_SEL_VAL(1, ESPI_IRQ_SEL_LVL_HI)
* write r to MSVW1 register
*/
#define ESPI_IRQ_SEL_LVL_LO 0
#define ESPI_IRQ_SEL_LVL_HI 1
#define ESPI_IRQ_SEL_DIS 4
/* NOTE: Edge trigger modes allow VWires to wake from deep sleep */
#define ESPI_IRQ_SEL_REDGE 0x0du
#define ESPI_IRQ_SEL_FEDGE 0x0eu
#define ESPI_IRQ_SEL_BEDGE 0x0fu
/* Slave to Master VW register: 64-bit (2 32 bit registers) */
/* 32-bit word 0 (bits[31:0]) */
#define ESPI_S2MW0_OFS 0
#define ESPI_S2MW0_IDX_POS 0
#define ESPI_S2MW0_IDX_MASK 0xffu
#define ESPI_S2MW0_STOM_POS 8u
#define ESPI_S2MW0_STOM_SRC_POS 8u
#define ESPI_S2MW0_STOM_MASK0 0xf3u
#define ESPI_S2MW0_STOM_MASK 0xf300u
#define ESPI_S2MW0_STOM_SRC_MASK0 0x03u
#define ESPI_S2MW0_STOM_SRC_MASK 0x0300u
#define ESPI_S2MW0_STOM_SRC_ESPI_RST 0u
#define ESPI_S2MW0_STOM_SRC_SYS_RST 0x0100u
#define ESPI_S2MW0_STOM_SRC_SIO_RST 0x0200u
#define ESPI_S2MW0_STOM_SRC_PLTRST 0x0300u
#define ESPI_S2MW0_STOM_STATE_POS 12u
#define ESPI_S2MW0_STOM_STATE_MASK0 0x0fu
#define ESPI_S2MW0_STOM_STATE_MASK 0x0f000u
#define ESPI_S2MW0_CHG0_POS 16u
#define ESPI_S2MW0_CHG0 BIT(ESPI_S2MW0_CHG0_POS)
#define ESPI_S2MW0_CHG1_POS 17u
#define ESPI_S2MW0_CHG1 BIT(ESPI_S2MW0_CHG1_POS)
#define ESPI_S2MW0_CHG2_POS 18u
#define ESPI_S2MW0_CHG2 BIT(ESPI_S2MW0_CHG2_POS)
#define ESPI_S2MW0_CHG3_POS 19u
#define ESPI_S2MW0_CHG3 BIT(ESPI_S2MW0_CHG3_POS)
#define ESPI_S2MW0_CHG_ALL_POS 16u
#define ESPI_S2MW0_CHG_ALL_MASK0 0x0fu
#define ESPI_S2MW0_CHG_ALL_MASK 0x0f0000u
/* 0 <= n < 4 */
#define ESPI_S2MW1_CHG_POS(n) ((n) + 16u)
#define ESPI_S2MW1_CHG(v, n) \
(((uint32_t)(v) >> ESPI_S2MW1_CHG_POS(n)) & 0x01)
/* 32-bit word 1 (bits[63:32]) */
#define ESPI_S2MW1_OFS 4u
#define ESPI_S2MW1_SRC0_POS 0u
#define ESPI_S2MW1_SRC0 BIT(ESPI_S2MW1_SRC0_POS)
#define ESPI_S2MW1_SRC1_POS 8u
#define ESPI_S2MW1_SRC1 BIT(ESPI_S2MW1_SRC1_POS)
#define ESPI_S2MW1_SRC2_POS 16u
#define ESPI_S2MW1_SRC2 BIT(ESPI_S2MW1_SRC2_POS)
#define ESPI_S2MW1_SRC3_POS 24u
#define ESPI_S2MW1_SRC3 BIT(ESPI_S2MW1_SRC3_POS)
/* 0 <= n < 4 */
#define ESPI_S2MW1_SRC_POS(n) SHLU32((n), 3)
#define ESPI_S2MW1_SRC(v, n) \
SHLU32(((uint32_t)(v) & 0x01), (ESPI_S2MW1_SRC_POS(n)))
/**
* @brief eSPI Virtual Wires (ESPI_VW)
*/
#define ESPI_MSVW_IDX_MAX 10u
#define ESPI_SMVW_IDX_MAX 10u
#define ESPI_NUM_MSVW 11u
#define ESPI_NUM_SMVW 11u
/*
* ESPI MSVW interrupts
* GIRQ24 contains MSVW 0 - 6
* GIRQ25 contains MSVW 7 - 10
*/
#define MEC_ESPI_MSVW_NUM_GIRQS 2u
/* Master-to-Slave VW byte indices(offsets) */
#define MSVW_INDEX_OFS 0u
#define MSVW_MTOS_OFS 1u
#define MSVW_SRC0_ISEL_OFS 4u
#define MSVW_SRC1_ISEL_OFS 5u
#define MSVW_SRC2_ISEL_OFS 6u
#define MSVW_SRC3_ISEL_OFS 7u
#define MSVW_SRC0_OFS 8u
#define MSVW_SRC1_OFS 9u
#define MSVW_SRC2_OFS 10u
#define MSVW_SRC3_OFS 11u
/* Slave-to-Master VW byte indices(offsets) */
#define SMVW_INDEX_OFS 0u
#define SMVW_STOM_OFS 1u
#define SMVW_CHANGED_OFS 2u
#define SMVW_SRC0_OFS 4u
#define SMVW_SRC1_OFS 5u
#define SMVW_SRC2_OFS 6u
#define SMVW_SRC3_OFS 7u
/* Master-to-Slave Virtual Wire 96-bit register */
#define MEC_MSVW_SRC0_IRQ_SEL_POS 0u
#define MEC_MSVW_SRC1_IRQ_SEL_POS 8u
#define MEC_MSVW_SRC2_IRQ_SEL_POS 16u
#define MEC_MSVW_SRC3_IRQ_SEL_POS 24u
#define MEC_MSVW_SRC_IRQ_SEL_MASK0 0x0fu
#define MEC_MSVW_SRC0_IRQ_SEL_MASK \
SHLU32(MEC_MSVW_SRC_IRQ_SEL_MASK0, MEC_MSVW_SRC0_IRQ_SEL_POS)
#define MEC_MSVW_SRC1_IRQ_SEL_MASK \
SHLU32(MEC_MSVW_SRC_IRQ_SEL_MASK0, MEC_MSVW_SRC1_IRQ_SEL_POS)
#define MEC_MSVW_SRC2_IRQ_SEL_MASK \
SHLU32(MEC_MSVW_SRC_IRQ_SEL_MASK0, MEC_MSVW_SRC2_IRQ_SEL_POS)
#define MEC_MSVW_SRC3_IRQ_SEL_MASK \
SHLU32(MEC_MSVW_SRC_IRQ_SEL_MASK0, MEC_MSVW_SRC3_IRQ_SEL_POS)
#define MEC_MSVW_SRC_IRQ_SEL_LVL_LO 0x00u
#define MEC_MSVW_SRC_IRQ_SEL_LVL_HI 0x01u
#define MEC_MSVW_SRC_IRQ_SEL_DIS 0x04u
#define MEC_MSVW_SRC_IRQ_SEL_EDGE_FALL 0x0du
#define MEC_MSVW_SRC_IRQ_SEL_EDGE_RISE 0x0eu
#define MEC_MSVW_SRC_IRQ_SEL_EDGE_BOTH 0x0fu
/*
* 0 <= src <= 3
* isel = MEC_MSVW_SRC_IRQ_SEL_LVL_LO, ...
*/
#define MEC_MSVW_SRC_IRQ_SEL_VAL(src, isel) \
((uint32_t)(isel) << ((src) * 8u))
#define MEC_MSVW_SRC0_POS 0u
#define MEC_MSVW_SRC1_POS 8u
#define MEC_MSVW_SRC2_POS 16u
#define MEC_MSVW_SRC3_POS 24u
#define MEC_MSVW_SRC_MASK0 0x01u
#define MEC_MSVW_SRC0_MASK BIT(0)
#define MEC_MSVW_SRC1_MASK BIT(8)
#define MEC_MSVW_SRC2_MASK BIT(16)
#define MEC_MSVW_SRC3_MASK BIT(24)
/*
* 0 <= src <= 3
* val = 0 or 1
*/
#define MEC_MSVW_SRC_VAL(src, val) \
((uint32_t)(val & 0x01u) << ((src) * 8u))
/* Slave-to-Master Virtual Wire 64-bit register */
/* MSVW helper inline functions */
/* Interfaces to any C modules */
#ifdef __cplusplus
extern "C" {
#endif
enum espi_msvw_src {
MSVW_SRC0 = 0u,
MSVW_SRC1,
MSVW_SRC2,
MSVW_SRC3
};
enum espi_smvw_src {
SMVW_SRC0 = 0u,
SMVW_SRC1,
SMVW_SRC2,
SMVW_SRC3
};
enum espi_msvw_irq_sel {
MSVW_IRQ_SEL_LVL_LO = 0x00u,
MSVW_IRQ_SEL_LVL_HI = 0x01u,
MSVW_IRQ_SEL_DIS = 0x04u,
MSVW_IRQ_SEL_EDGE_FALL = 0x0du,
MSVW_IRQ_SEL_EDGE_RISE = 0x0eu,
MSVW_IRQ_SEL_EDGE_BOTH = 0x0fu
};
/* Used for both MSVW MTOS and SMVW STOM fields */
enum espi_vw_rst_src {
VW_RST_SRC_ESPI_RESET = 0u,
VW_RST_SRC_SYS_RESET,
VW_RST_SRC_SIO_RESET,
VW_RST_SRC_PLTRST,
};
enum espi_msvw_byte_idx {
MSVW_BI_INDEX = 0,
MSVW_BI_MTOS,
MSVW_BI_RSVD2,
MSVW_BI_RSVD3,
MSVW_BI_IRQ_SEL0,
MSVW_BI_IRQ_SEL1,
MSVW_BI_IRQ_SEL2,
MSVW_BI_IRQ_SEL3,
MSVW_BI_SRC0,
MSVW_BI_SRC1,
MSVW_BI_SRC2,
MSVW_BI_SRC3,
MSVW_IDX_MAX
};
enum espi_smvw_byte_idx {
SMVW_BI_INDEX = 0,
SMVW_BI_STOM,
SMVW_BI_SRC_CHG,
SMVW_BI_RSVD3,
SMVW_BI_SRC0,
SMVW_BI_SRC1,
SMVW_BI_SRC2,
SMVW_BI_SRC3,
SMVW_IDX_MAX
};
/** @brief eSPI 96-bit Host-to-Target Virtual Wire register */
struct espi_msvw_reg {
volatile uint8_t INDEX;
volatile uint8_t MTOS;
uint8_t RSVD1[2];
volatile uint32_t SRC_IRQ_SEL;
volatile uint32_t SRC;
};
/** @brief eSPI 96-bit Host-to-Target Virtual Wire register as bytes */
struct espi_msvwb_reg {
volatile uint8_t HTVWB[12];
};
/** @brief HW implements 11 Host-to-Target VW registers as an array */
struct espi_msvw_ar_regs {
struct espi_msvw_reg MSVW[11];
};
/** @brief HW implements 11 Host-to-Target VW registers as named registers */
struct espi_msvw_named_regs {
struct espi_msvw_reg MSVW00;
struct espi_msvw_reg MSVW01;
struct espi_msvw_reg MSVW02;
struct espi_msvw_reg MSVW03;
struct espi_msvw_reg MSVW04;
struct espi_msvw_reg MSVW05;
struct espi_msvw_reg MSVW06;
struct espi_msvw_reg MSVW07;
struct espi_msvw_reg MSVW08;
struct espi_msvw_reg MSVW09;
struct espi_msvw_reg MSVW10;
};
/** @brief eSPI M2S VW registers as an array of words at 0x400F9C00 */
struct espi_msvw32_regs {
volatile uint32_t MSVW32[11 * 3];
};
/** @brief eSPI 64-bit Target-to-Host Virtual Wire register */
struct espi_smvw_reg {
volatile uint8_t INDEX;
volatile uint8_t STOM;
volatile uint8_t SRC_CHG;
uint8_t RSVD1[1];
volatile uint32_t SRC;
};
/** @brief eSPI 64-bit Target-to-Host Virtual Wire register as bytes */
struct espi_smvwb_reg {
volatile uint8_t THVWB[8];
};
/** @brief HW implements 11 Target-to-Host VW registers as an array */
struct espi_smvw_ar_regs {
struct espi_smvw_reg SMVW[11];
};
/** @brief HW implements 11 Target-to-Host VW registers as named registers */
struct espi_smvw_named_regs {
struct espi_smvw_reg SMVW00;
struct espi_smvw_reg SMVW01;
struct espi_smvw_reg SMVW02;
struct espi_smvw_reg SMVW03;
struct espi_smvw_reg SMVW04;
struct espi_smvw_reg SMVW05;
struct espi_smvw_reg SMVW06;
struct espi_smvw_reg SMVW07;
struct espi_smvw_reg SMVW08;
struct espi_smvw_reg SMVW09;
struct espi_smvw_reg SMVW10;
};
/** @brief eSPI S2M VW registers as an array of words at 0x400F9E00 */
struct espi_smvw32_regs {
volatile uint32_t SMVW[11 * 2];
};
#ifdef __cplusplus
}
#endif
#endif /* #ifndef _MEC172X_ESPI_VW_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MEC172X_GPIO_H
#define _MEC172X_GPIO_H
#include <stdint.h>
#include <stddef.h>
#if defined(CONFIG_SOC_MEC172X_NSZ)
#include "gpio_pkg_sz.h"
#elif defined(CONFIG_SOC_MEC172X_NLJ)
#include "gpio_pkg_lj.h"
#endif
#define NUM_MCHP_GPIO_PORTS 6u
#define MAX_NUM_MCHP_GPIO (NUM_MCHP_GPIO_PORTS * 32u)
/* GPIO Control register field definitions. */
/* bits[1:0] internal pull up/down selection */
#define MCHP_GPIO_CTRL_PUD_POS 0
#define MCHP_GPIO_CTRL_PUD_MASK0 0x03u
#define MCHP_GPIO_CTRL_PUD_MASK 0x03u
#define MCHP_GPIO_CTRL_PUD_NONE 0x00u
#define MCHP_GPIO_CTRL_PUD_PU 0x01u
#define MCHP_GPIO_CTRL_PUD_PD 0x02u
/* Repeater(keeper) mode */
#define MCHP_GPIO_CTRL_PUD_RPT 0x03u
/* bits[3:2] power gating */
#define MCHP_GPIO_CTRL_PWRG_POS 2
#define MCHP_GPIO_CTRL_PWRG_MASK0 0x03u
#define MCHP_GPIO_CTRL_PWRG_VTR_IO 0
#define MCHP_GPIO_CTRL_PWRG_VCC_IO SHLU32(1, MCHP_GPIO_CTRL_PWRG_POS)
#define MCHP_GPIO_CTRL_PWRG_OFF SHLU32(2, MCHP_GPIO_CTRL_PWRG_POS)
#define MCHP_GPIO_CTRL_PWRG_RSVD SHLU32(3, MCHP_GPIO_CTRL_PWRG_POS)
#define MCHP_GPIO_CTRL_PWRG_MASK SHLU32(3, MCHP_GPIO_CTRL_PWRG_POS)
/* bits[7:4] interrupt detection mode */
#define MCHP_GPIO_CTRL_IDET_POS 4
#define MCHP_GPIO_CTRL_IDET_MASK0 0x0fu
#define MCHP_GPIO_CTRL_IDET_LVL_LO 0
#define MCHP_GPIO_CTRL_IDET_LVL_HI SHLU32(1, MCHP_GPIO_CTRL_IDET_POS)
#define MCHP_GPIO_CTRL_IDET_DISABLE SHLU32(4, MCHP_GPIO_CTRL_IDET_POS)
#define MCHP_GPIO_CTRL_IDET_REDGE SHLU32(0xd, MCHP_GPIO_CTRL_IDET_POS)
#define MCHP_GPIO_CTRL_IDET_FEDGE SHLU32(0xe, MCHP_GPIO_CTRL_IDET_POS)
#define MCHP_GPIO_CTRL_IDET_BEDGE SHLU32(0xf, MCHP_GPIO_CTRL_IDET_POS)
#define MCHP_GPIO_CTRL_IDET_MASK SHLU32(0xf, MCHP_GPIO_CTRL_IDET_POS)
/* bit[8] output buffer type: push-pull or open-drain */
#define MCHP_GPIO_CTRL_BUFT_POS 8
#define MCHP_GPIO_CTRL_BUFT_MASK BIT(MCHP_GPIO_CTRL_BUFT_POS)
#define MCHP_GPIO_CTRL_BUFT_OPENDRAIN BIT(MCHP_GPIO_CTRL_BUFT_POS)
#define MCHP_GPIO_CTRL_BUFT_PUSHPULL 0
/* bit[9] direction */
#define MCHP_GPIO_CTRL_DIR_POS 9
#define MCHP_GPIO_CTRL_DIR_MASK BIT(MCHP_GPIO_CTRL_DIR_POS)
#define MCHP_GPIO_CTRL_DIR_OUTPUT BIT(MCHP_GPIO_CTRL_DIR_POS)
#define MCHP_GPIO_CTRL_DIR_INPUT 0
/*
* bit[10] Alternate output disable. Default==0(alternate output enabled)
* GPIO output value is controlled by bit[16] of this register.
* Set bit[10]=1 if you wish to control pin output using the parallel
* GPIO output register bit for this pin.
*/
#define MCHP_GPIO_CTRL_AOD_POS 10
#define MCHP_GPIO_CTRL_AOD_MASK BIT(MCHP_GPIO_CTRL_AOD_POS)
#define MCHP_GPIO_CTRL_AOD_DIS BIT(MCHP_GPIO_CTRL_AOD_POS)
/* bit[11] GPIO function output polarity */
#define MCHP_GPIO_CTRL_POL_POS 11
#define MCHP_GPIO_CTRL_POL_INVERT BIT(MCHP_GPIO_CTRL_POL_POS)
/* bits[14:12] pin mux (function) */
#define MCHP_GPIO_CTRL_MUX_POS 12
#define MCHP_GPIO_CTRL_MUX_MASK0 0x07u
#define MCHP_GPIO_CTRL_MUX_MASK SHLU32(7, MCHP_GPIO_CTRL_MUX_POS)
#define MCHP_GPIO_CTRL_MUX_F0 0
#define MCHP_GPIO_CTRL_MUX_GPIO MCHP_GPIO_CTRL_MUX_F0
#define MCHP_GPIO_CTRL_MUX_F1 SHLU32(1, MCHP_GPIO_CTRL_MUX_POS)
#define MCHP_GPIO_CTRL_MUX_F2 SHLU32(2, MCHP_GPIO_CTRL_MUX_POS)
#define MCHP_GPIO_CTRL_MUX_F3 SHLU32(3, MCHP_GPIO_CTRL_MUX_POS)
#define MCHP_GPIO_CTRL_MUX_F4 SHLU32(4, MCHP_GPIO_CTRL_MUX_POS)
#define MCHP_GPIO_CTRL_MUX_F5 SHLU32(5, MCHP_GPIO_CTRL_MUX_POS)
#define MCHP_GPIO_CTRL_MUX_F6 SHLU32(6, MCHP_GPIO_CTRL_MUX_POS)
#define MCHP_GPIO_CTRL_MUX_F7 SHLU32(7, MCHP_GPIO_CTRL_MUX_POS)
#define MCHP_GPIO_CTRL_MUX(n) SHLU32(((n) & 0x7u), MCHP_GPIO_CTRL_MUX_POS)
/*
* bit[15] Disables input pad leaving output pad enabled
* Useful for reducing power consumption of output only pins.
*/
#define MCHP_GPIO_CTRL_INPAD_DIS_POS 15
#define MCHP_GPIO_CTRL_INPAD_DIS_MASK BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS)
#define MCHP_GPIO_CTRL_INPAD_DIS BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS)
/* bit[16]: Alternate output pin value. Enabled when bit[10]==0(default) */
#define MCHP_GPIO_CTRL_OUTVAL_POS 16
#define MCHP_GPIO_CTRL_OUTV_HI BIT(MCHP_GPIO_CTRL_OUTVAL_POS)
/* bit[24] Input pad value. Always live unless input pad is powered down */
#define MCHP_GPIO_CTRL_INPAD_VAL_POS 24
#define MCHP_GPIO_CTRL_INPAD_VAL_HI BIT(MCHP_GPIO_CTRL_INPAD_VAL_POS)
#define MCHP_GPIO_CTRL_DRIVE_OD_HI \
(MCHP_GPIO_CTRL_BUFT_OPENDRAIN + MCHP_GPIO_CTRL_DIR_OUTPUT + \
MCHP_GPIO_CTRL_MUX_GPIO + MCHP_GPIO_CTRL_OUTV_HI)
/*
* Each GPIO pin implements a second control register.
* GPIO Control 2 register selects pin drive strength and slew rate.
* bit[0] = slew rate: 0=slow, 1=fast
* bits[5:4] = drive strength
* 00b = 2mA (default)
* 01b = 4mA
* 10b = 8mA
* 11b = 12mA
*/
#define MCHP_GPIO_CTRL2_SLEW_POS 0
#define MCHP_GPIO_CTRL2_SLEW_MASK 0x01u
#define MCHP_GPIO_CTRL2_SLEW_SLOW 0
#define MCHP_GPIO_CTRL2_SLEW_FAST BIT(MCHP_GPIO_CTRL2_SLEW_POS)
#define MCHP_GPIO_CTRL2_DRV_STR_POS 4
#define MCHP_GPIO_CTRL2_DRV_STR_MASK 0x30u
#define MCHP_GPIO_CTRL2_DRV_STR_2MA 0
#define MCHP_GPIO_CTRL2_DRV_STR_4MA 0x10u
#define MCHP_GPIO_CTRL2_DRV_STR_8MA 0x20u
#define MCHP_GPIO_CTRL2_DRV_STR_12MA 0x30u
/* Interfaces to any C modules */
#ifdef __cplusplus
extern "C" {
#endif
#define MCHP_GPIO_PIN2PORT(pin_id) ((uint32_t)(pin_id) >> 5)
/* Helper functions */
enum mchp_gpio_pud {
MCHP_GPIO_NO_PUD = 0,
MCHP_GPIO_PU_EN,
MCHP_GPIO_PD_EN,
MCHP_GPIO_RPT_EN,
};
enum mchp_gpio_pwrgate {
MCHP_GPIO_PWRGT_VTR = 0,
MCHP_GPIO_PWRGT_VCC,
MCHP_GPIO_PWRGD_OFF,
};
enum mchp_gpio_idet {
MCHP_GPIO_IDET_LO_LVL = 0u,
MCHP_GPIO_IDET_HI_LVL = 0x01u,
MCHP_GPIO_IDET_DIS = 0x04u,
MCHP_GPIO_IDET_RISING_EDGE = 0x0du,
MCHP_GPIO_IDET_FALLING_EDGE = 0x0eu,
MCHP_GPIO_IDET_BOTH_EDGES = 0x0fu
};
enum mchp_gpio_outbuf {
MCHP_GPIO_PUSH_PULL = 0,
MCHP_GPIO_OPEN_DRAIN,
};
enum mchp_gpio_dir {
MCHP_GPIO_DIR_IN = 0,
MCHP_GPIO_DIR_OUT,
};
enum mchp_gpio_parout_en {
MCHP_GPIO_PAROUT_DIS = 0,
MCHP_GPIO_PAROUT_EN,
};
enum mchp_gpio_pol {
MCHP_GPIO_POL_NORM = 0,
MCHP_GPIO_POL_INV,
};
enum mchp_gpio_mux {
MCHP_GPIO_MUX_GPIO = 0u,
MCHP_GPIO_MUX_FUNC1,
MCHP_GPIO_MUX_FUNC2,
MCHP_GPIO_MUX_FUNC3,
MCHP_GPIO_MUX_FUNC4,
MCHP_GPIO_MUX_FUNC5,
MCHP_GPIO_MUX_FUNC6,
MCHP_GPIO_MUX_FUNC7,
MCHP_GPIO_MUX_MAX
};
enum mchp_gpio_inpad_ctrl {
MCHP_GPIO_INPAD_CTRL_EN = 0,
MCHP_GPIO_INPAD_CTRL_DIS,
};
enum mchp_gpio_alt_out {
MCHP_GPIO_ALT_OUT_LO = 0,
MCHP_GPIO_ALT_OUT_HI,
};
enum mchp_gpio_slew {
MCHP_GPIO_SLEW_SLOW = 0,
MCHP_GPIO_SLEW_FAST,
};
enum mchp_gpio_drv_str {
MCHP_GPIO_DRV_STR_2MA = 0,
MCHP_GPIO_DRV_STR_4MA,
MCHP_GPIO_DRV_STR_8MA,
MCHP_GPIO_DRV_STR_12MA,
};
#ifdef __cplusplus
}
#endif
#endif /* #ifndef _MEC172X_GPIO_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MEC172X_I2C_SMB_H
#define _MEC172X_I2C_SMB_H
#include <stdint.h>
#include <stddef.h>
/* Version 3.7 MCHP I2C/SMBus Controller specification */
#define MCHP_I2C_BAUD_CLK_HZ 16000000u
#define MCHP_I2C_SMB_INST_SPACING 0x400u
#define MCHP_I2C_SMB_INST_SPACING_P2 10u
#define MCHP_I2C_SMB0_BASE_ADDR 0x40004000u
#define MCHP_I2C_SMB1_BASE_ADDR 0x40004400u
#define MCHP_I2C_SMB2_BASE_ADDR 0x40004800u
#define MCHP_I2C_SMB3_BASE_ADDR 0x40004c00u
#define MCHP_I2C_SMB4_BASE_ADDR 0x40005000u
/* 0 <= n < MCHP_I2C_SMB_MAX_INSTANCES */
#define MCHP_I2C_SMB_BASE_ADDR(n) \
((MCHP_I2C_SMB0_BASE_ADDR) + \
((uint32_t)(n) * (MCHP_I2C_SMB_INST_SPACING)))
/*
* Offset 0x00
* Control and Status register
* Write to Control
* Read from Status
* Size 8-bit
*/
#define MCHP_I2C_SMB_CTRL_OFS 0x00u
#define MCHP_I2C_SMB_CTRL_MASK 0xcfu
#define MCHP_I2C_SMB_CTRL_ACK BIT(0)
#define MCHP_I2C_SMB_CTRL_STO BIT(1)
#define MCHP_I2C_SMB_CTRL_STA BIT(2)
#define MCHP_I2C_SMB_CTRL_ENI BIT(3)
/* bits [5:4] reserved */
#define MCHP_I2C_SMB_CTRL_ESO BIT(6)
#define MCHP_I2C_SMB_CTRL_PIN BIT(7)
/* Status Read-only */
#define MCHP_I2C_SMB_STS_OFS 0x00u
#define MCHP_I2C_SMB_STS_NBB BIT(0)
#define MCHP_I2C_SMB_STS_LAB BIT(1)
#define MCHP_I2C_SMB_STS_AAS BIT(2)
#define MCHP_I2C_SMB_STS_LRB_AD0 BIT(3)
#define MCHP_I2C_SMB_STS_BER BIT(4)
#define MCHP_I2C_SMB_STS_EXT_STOP BIT(5)
#define MCHP_I2C_SMB_STS_SAD BIT(6)
#define MCHP_I2C_SMB_STS_PIN BIT(7)
/*
* Offset 0x04
* Own Address b[7:0] = Slave address 1
* b[14:8] = Slave address 2
*/
#define MCHP_I2C_SMB_OWN_ADDR_OFS 0x04u
#define MCHP_I2C_SMB_OWN_ADDR2_OFS 0x05u
#define MCHP_I2C_SMB_OWN_ADDR_MASK 0x7f7fu
/*
* Offset 0x08
* Data register, 8-bit
* Data to be shifted out or shifted in.
*/
#define MCHP_I2C_SMB_DATA_OFS 0x08u
/* Offset 0x0C Leader Command register
*/
#define MCHP_I2C_SMB_MSTR_CMD_OFS 0x0cu
#define MCHP_I2C_SMB_MSTR_CMD_RD_CNT_OFS 0x0fu /* byte 3 */
#define MCHP_I2C_SMB_MSTR_CMD_WR_CNT_OFS 0x0eu /* byte 2 */
#define MCHP_I2C_SMB_MSTR_CMD_OP_OFS 0x0du /* byte 1 */
#define MCHP_I2C_SMB_MSTR_CMD_M_OFS 0x0cu /* byte 0 */
#define MCHP_I2C_SMB_MSTR_CMD_MASK 0xffff3ff3u
/* 32-bit definitions */
#define MCHP_I2C_SMB_MSTR_CMD_MRUN BIT(0)
#define MCHP_I2C_SMB_MSTR_CMD_MPROCEED BIT(1)
#define MCHP_I2C_SMB_MSTR_CMD_START0 BIT(8)
#define MCHP_I2C_SMB_MSTR_CMD_STARTN BIT(9)
#define MCHP_I2C_SMB_MSTR_CMD_STOP BIT(10)
#define MCHP_I2C_SMB_MSTR_CMD_PEC_TERM BIT(11)
#define MCHP_I2C_SMB_MSTR_CMD_READM BIT(12)
#define MCHP_I2C_SMB_MSTR_CMD_READ_PEC BIT(13)
#define MCHP_I2C_SMB_MSTR_CMD_RD_CNT_POS 24u
#define MCHP_I2C_SMB_MSTR_CMD_WR_CNT_POS 16u
/* byte 0 definitions */
#define MCHP_I2C_SMB_MSTR_CMD_B0_MRUN BIT(0)
#define MCHP_I2C_SMB_MSTR_CMD_B0_MPROCEED BIT(1)
/* byte 1 definitions */
#define MCHP_I2C_SMB_MSTR_CMD_B1_START0 BIT((8 - 8))
#define MCHP_I2C_SMB_MSTR_CMD_B1_STARTN BIT((9 - 8))
#define MCHP_I2C_SMB_MSTR_CMD_B1_STOP BIT((10 - 8))
#define MCHP_I2C_SMB_MSTR_CMD_B1_PEC_TERM BIT((11 - 8))
#define MCHP_I2C_SMB_MSTR_CMD_B1_READM BIT((12 - 8))
#define MCHP_I2C_SMB_MSTR_CMD_B1_READ_PEC BIT((13 - 8))
/* Offset 0x10 Follower Command register */
#define MCHP_I2C_SMB_SLV_CMD_OFS 0x10u
#define MCHP_I2C_SMB_SLV_CMD_MASK 0x00ffff07u
#define MCHP_I2C_SMB_SLV_CMD_SRUN BIT(0)
#define MCHP_I2C_SMB_SLV_CMD_SPROCEED BIT(1)
#define MCHP_I2C_SMB_SLV_CMD_SEND_PEC BIT(2)
#define MCHP_I2C_SMB_SLV_WR_CNT_POS 8u
#define MCHP_I2C_SMB_SLV_RD_CNT_POS 16u
/* Offset 0x14 PEC CRC register, 8-bit read-write */
#define MCHP_I2C_SMB_PEC_CRC_OFS 0x14u
/* Offset 0x18 Repeated Start Hold Time register, 8-bit read-write */
#define MCHP_I2C_SMB_RSHT_OFS 0x18u
/* Offset 0x20 Completion register, 32-bit */
#define MCHP_I2C_SMB_CMPL_OFS 0x20u
#define MCHP_I2C_SMB_CMPL_MASK 0xe33b7f7Cu
#define MCHP_I2C_SMB_CMPL_RW1C_MASK 0xe1397f00u
#define MCHP_I2C_SMB_CMPL_DTEN BIT(2)
#define MCHP_I2C_SMB_CMPL_MCEN BIT(3)
#define MCHP_I2C_SMB_CMPL_SCEN BIT(4)
#define MCHP_I2C_SMB_CMPL_BIDEN BIT(5)
#define MCHP_I2C_SMB_CMPL_TIMERR BIT(6)
#define MCHP_I2C_SMB_CMPL_DTO_RWC BIT(8)
#define MCHP_I2C_SMB_CMPL_MCTO_RWC BIT(9)
#define MCHP_I2C_SMB_CMPL_SCTO_RWC BIT(10)
#define MCHP_I2C_SMB_CMPL_CHDL_RWC BIT(11)
#define MCHP_I2C_SMB_CMPL_CHDH_RWC BIT(12)
#define MCHP_I2C_SMB_CMPL_BER_RWC BIT(13)
#define MCHP_I2C_SMB_CMPL_LAB_RWC BIT(14)
#define MCHP_I2C_SMB_CMPL_SNAKR_RWC BIT(16)
#define MCHP_I2C_SMB_CMPL_STR_RO BIT(17)
#define MCHP_I2C_SMB_CMPL_SPROT_RWC BIT(19)
#define MCHP_I2C_SMB_CMPL_RPT_RD_RWC BIT(20)
#define MCHP_I2C_SMB_CMPL_RPT_WR_RWC BIT(21)
#define MCHP_I2C_SMB_CMPL_MNAKX_RWC BIT(24)
#define MCHP_I2C_SMB_CMPL_MTR_RO BIT(25)
#define MCHP_I2C_SMB_CMPL_IDLE_RWC BIT(29)
#define MCHP_I2C_SMB_CMPL_MDONE_RWC BIT(30)
#define MCHP_I2C_SMB_CMPL_SDONE_RWC BIT(31)
/* Offset 0x24 Idle Scaling register */
#define MCHP_I2C_SMB_IDLSC_OFS 0x24u
#define MCHP_I2C_SMB_IDLSC_DLY_OFS 0x24u
#define MCHP_I2C_SMB_IDLSC_BUS_OFS 0x26u
#define MCHP_I2C_SMB_IDLSC_MASK 0x0fff0fffu
#define MCHP_I2C_SMB_IDLSC_BUS_MIN_POS 0u
#define MCHP_I2C_SMB_IDLSC_DLY_POS 16u
/* Offset 0x28 Configuration register */
#define MCHP_I2C_SMB_CFG_OFS 0x28u
#define MCHP_I2C_SMB_CFG_MASK 0xf00f5Fbfu
#define MCHP_I2C_SMB_CFG_PORT_SEL_POS 0
#define MCHP_I2C_SMB_CFG_PORT_SEL_MASK 0x0fu
#define MCHP_I2C_SMB_CFG_TCEN BIT(4)
#define MCHP_I2C_SMB_CFG_SLOW_CLK BIT(5)
#define MCHP_I2C_SMB_CFG_PCEN BIT(7)
#define MCHP_I2C_SMB_CFG_FEN BIT(8)
#define MCHP_I2C_SMB_CFG_RESET BIT(9)
#define MCHP_I2C_SMB_CFG_ENAB BIT(10)
#define MCHP_I2C_SMB_CFG_DSA BIT(11)
#define MCHP_I2C_SMB_CFG_FAIR BIT(12)
#define MCHP_I2C_SMB_CFG_GC_DIS BIT(14)
#define MCHP_I2C_SMB_CFG_FLUSH_SXBUF_WO BIT(16)
#define MCHP_I2C_SMB_CFG_FLUSH_SRBUF_WO BIT(17)
#define MCHP_I2C_SMB_CFG_FLUSH_MXBUF_WO BIT(18)
#define MCHP_I2C_SMB_CFG_FLUSH_MRBUF_WO BIT(19)
#define MCHP_I2C_SMB_CFG_EN_AAS BIT(28)
#define MCHP_I2C_SMB_CFG_ENIDI BIT(29)
#define MCHP_I2C_SMB_CFG_ENMI BIT(30)
#define MCHP_I2C_SMB_CFG_ENSI BIT(31)
/* Offset 0x2C Bus Clock register */
#define MCHP_I2C_SMB_BUS_CLK_OFS 0x2cu
#define MCHP_I2C_SMB_BUS_CLK_MASK 0x0000ffffu
#define MCHP_I2C_SMB_BUS_CLK_LO_POS 0u
#define MCHP_I2C_SMB_BUS_CLK_HI_POS 8u
/* Offset 0x30 Block ID register, 8-bit read-only */
#define MCHP_I2C_SMB_BLOCK_ID_OFS 0x30u
#define MCHP_I2C_SMB_BLOCK_ID_MASK 0xffu
/* Offset 0x34 Block Revision register, 8-bit read-only */
#define MCHP_I2C_SMB_BLOCK_REV_OFS 0x34u
#define MCHP_I2C_SMB_BLOCK_REV_MASK 0xffu
/* Offset 0x38 Bit-Bang Control register, 8-bit read-write */
#define MCHP_I2C_SMB_BB_OFS 0x38u
#define MCHP_I2C_SMB_BB_MASK 0x7fu
#define MCHP_I2C_SMB_BB_EN BIT(0)
#define MCHP_I2C_SMB_BB_SCL_DIR_IN 0
#define MCHP_I2C_SMB_BB_SCL_DIR_OUT BIT(1)
#define MCHP_I2C_SMB_BB_SDA_DIR_IN 0
#define MCHP_I2C_SMB_BB_SDA_DIR_OUT BIT(2)
#define MCHP_I2C_SMB_BB_CL BIT(3)
#define MCHP_I2C_SMB_BB_DAT BIT(4)
#define MCHP_I2C_SMB_BB_IN_POS 5u
#define MCHP_I2C_SMB_BB_IN_MASK0 0x03u
#define MCHP_I2C_SMB_BB_IN_MASK SHLU32(0x03, 5)
#define MCHP_I2C_SMB_BB_CLKI_RO BIT(5)
#define MCHP_I2C_SMB_BB_DATI_RO BIT(6)
/* Offset 0x40 Data Timing register */
#define MCHP_I2C_SMB_DATA_TM_OFS 0x40u
#define MCHP_I2C_SMB_DATA_TM_MASK GENMASK(31, 0)
#define MCHP_I2C_SMB_DATA_TM_DATA_HOLD_POS 0u
#define MCHP_I2C_SMB_DATA_TM_DATA_HOLD_MASK 0xffu
#define MCHP_I2C_SMB_DATA_TM_DATA_HOLD_MASK0 0xffu
#define MCHP_I2C_SMB_DATA_TM_RESTART_POS 8u
#define MCHP_I2C_SMB_DATA_TM_RESTART_MASK 0xff00u
#define MCHP_I2C_SMB_DATA_TM_RESTART_MASK0 0xffu
#define MCHP_I2C_SMB_DATA_TM_STOP_POS 16u
#define MCHP_I2C_SMB_DATA_TM_STOP_MASK 0xff0000u
#define MCHP_I2C_SMB_DATA_TM_STOP_MASK0 0xffu
#define MCHP_I2C_SMB_DATA_TM_FSTART_POS 24u
#define MCHP_I2C_SMB_DATA_TM_FSTART_MASK 0xff000000u
#define MCHP_I2C_SMB_DATA_TM_FSTART_MASK0 0xffu
/* Offset 0x44 Time-out Scaling register */
#define MCHP_I2C_SMB_TMTSC_OFS 0x44u
#define MCHP_I2C_SMB_TMTSC_MASK GENMASK(31, 0)
#define MCHP_I2C_SMB_TMTSC_CLK_HI_POS 0u
#define MCHP_I2C_SMB_TMTSC_CLK_HI_MASK 0xffu
#define MCHP_I2C_SMB_TMTSC_CLK_HI_MASK0 0xffu
#define MCHP_I2C_SMB_TMTSC_SLV_POS 8u
#define MCHP_I2C_SMB_TMTSC_SLV_MASK 0xff00u
#define MCHP_I2C_SMB_TMTSC_SLV_MASK0 0xffu
#define MCHP_I2C_SMB_TMTSC_MSTR_POS 16u
#define MCHP_I2C_SMB_TMTSC_MSTR_MASK 0xff0000u
#define MCHP_I2C_SMB_TMTSC_MSTR_MASK0 0xffu
#define MCHP_I2C_SMB_TMTSC_BUS_POS 24u
#define MCHP_I2C_SMB_TMTSC_BUS_MASK 0xff000000u
#define MCHP_I2C_SMB_TMTSC_BUS_MASK0 0xffu
/* Offset 0x48 Follower Transmit Buffer register 8-bit read-write */
#define MCHP_I2C_SMB_SLV_TX_BUF_OFS 0x48u
/* Offset 0x4C Follower Receive Buffer register 8-bit read-write */
#define MCHP_I2C_SMB_SLV_RX_BUF_OFS 0x4cu
/* Offset 0x50 Leader Transmit Buffer register 8-bit read-write */
#define MCHP_I2C_SMB_MTR_TX_BUF_OFS 0x50u
/* Offset 0x54 Leader Receive Buffer register 8-bit read-write */
#define MCHP_I2C_SMB_MTR_RX_BUF_OFS 0x54u
/* Offset 0x58 I2C FSM read-only */
#define MCHP_I2C_SMB_I2C_FSM_OFS 0x58u
/* Offset 0x5C SMB Network layer FSM read-only */
#define MCHP_I2C_SMB_FSM_OFS 0x5cu
/* Offset 0x60 Wake Status register */
#define MCHP_I2C_SMB_WAKE_STS_OFS 0x60u
#define MCHP_I2C_SMB_WAKE_STS_START_RWC BIT(0)
/* Offset 0x64 Wake Enable register */
#define MCHP_I2C_SMB_WAKE_EN_OFS 0x64u
#define MCHP_I2C_SMB_WAKE_EN BIT(0)
/* Offset 0x68 */
#define MCHP_I2C_SMB_WAKE_SYNC_OFS 0x68u
#define MCHP_I2C_SMB_WAKE_FAST_RESYNC_EN BIT(0)
/** @brief I2C-SMBus with network layer registers. */
struct i2c_smb_regs {
volatile uint8_t CTRLSTS;
uint8_t RSVD1[3];
volatile uint32_t OWN_ADDR;
volatile uint8_t I2CDATA;
uint8_t RSVD2[3];
volatile uint32_t MCMD;
volatile uint32_t SCMD;
volatile uint8_t PEC;
uint8_t RSVD3[3];
volatile uint32_t RSHTM;
volatile uint32_t EXTLEN;
volatile uint32_t COMPL;
volatile uint32_t IDLSC;
volatile uint32_t CFG;
volatile uint32_t BUSCLK;
volatile uint32_t BLKID;
volatile uint32_t BLKREV;
volatile uint8_t BBCTRL;
uint8_t RSVD7[3];
volatile uint32_t CLKSYNC;
volatile uint32_t DATATM;
volatile uint32_t TMOUTSC;
volatile uint8_t SLV_TXB;
uint8_t RSVD8[3];
volatile uint8_t SLV_RXB;
uint8_t RSVD9[3];
volatile uint8_t MTR_TXB;
uint8_t RSVD10[3];
volatile uint8_t MTR_RXB;
uint8_t RSVD11[3];
volatile uint32_t FSM;
volatile uint32_t FSM_SMB;
volatile uint8_t WAKE_STS;
uint8_t RSVD12[3];
volatile uint8_t WAKE_EN;
uint32_t RSVD13[2];
volatile uint32_t PROM_ISTS;
volatile uint32_t PROM_IEN;
volatile uint32_t PROM_CTRL;
volatile uint32_t SHADOW_DATA;
}; /* Size = 128(0x80) */
#endif /* #ifndef _MEC172X_I2C_SMB_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MEC172X_P80BD_H
#define _MEC172X_P80BD_H
#include <stdint.h>
#include <stddef.h>
#define MCHP_P80BD_0_BASE_ADDR 0x400f8000u
/* HDATA - Write-Only 32-bit */
#define MCHP_P80BD_HDATA_OFS 0x00u
#define MCHP_P80BD_HDATA_MASK GENMASK(31, 0)
/*
* EC-only Data/Attributes 16-bit
* b[7:0] = data byte from capture FIFO
* b[15:8] = data attributes
*/
#define MCHP_P80BD_ECDA_OFS 0x100u
#define MCHP_P80BD_ECDA_MASK 0x7fffu
#define MCHP_P80BD_ECDA_DPOS 0
#define MCHP_P80BD_ECDA_APOS 8
#define MCHP_P80BD_ECDA_DMSK 0xffu
#define MCHP_P80BD_ECDA_AMSK 0x7f00u
#define MCHP_P80BD_ECDA_LANE_POS 8
#define MCHP_P80BD_ECDA_LANE_MSK 0x0300u
#define MCHP_P80BD_ECDA_LANE_0 0x0000u
#define MCHP_P80BD_ECDA_LANE_1 0x0100u
#define MCHP_P80BD_ECDA_LANE_2 0x0200u
#define MCHP_P80BD_ECDA_LANE_3 0x0300u
#define MCHP_P80BD_ECDA_LEN_POS 10
#define MCHP_P80BD_ECDA_LEN_MSK 0x0c00u
#define MCHP_P80BD_ECDA_LEN_1 0x0000u
#define MCHP_P80BD_ECDA_LEN_2 0x0400u
#define MCHP_P80BD_ECDA_LEN_4 0x0800u
#define MCHP_P80BD_ECDA_LEN_INVAL 0x0c00u
#define MCHP_P80BD_ECDA_NE BIT(12)
#define MCHP_P80BD_ECDA_OVR BIT(13)
#define MCHP_P80BD_ECDA_THR BIT(14)
/* Configuration */
#define MCHP_P80BD_CFG_OFS 0x104u
#define MCHP_P80BD_CFG_MASK 0x80000703u
#define MCHP_P80BD_CFG_FLUSH_FIFO BIT(0) /* WO */
#define MCHP_P80BD_CFG_SNAP_CLR BIT(1) /* WO */
#define MCHP_P80BD_CFG_FIFO_THR_POS 8
#define MCHP_P80BD_CFG_FIFO_THR_MSK 0x700u
#define MCHP_P80BD_CFG_FIFO_THR_1 0x000u
#define MCHP_P80BD_CFG_FIFO_THR_4 0x100u
#define MCHP_P80BD_CFG_FIFO_THR_8 0x200u
#define MCHP_P80BD_CFG_FIFO_THR_16 0x300u
#define MCHP_P80BD_CFG_FIFO_THR_20 0x400u
#define MCHP_P80BD_CFG_FIFO_THR_24 0x500u
#define MCHP_P80BD_CFG_FIFO_THR_28 0x600u
#define MCHP_P80BD_CFG_FIFO_THR_30 0x700u
#define MCHP_P80BD_CFG_SRST BIT(31) /* WO */
/* Status and Interrupt Enable 16-bit */
#define MCHP_P80BD_SI_OFS 0x108u
#define MCHP_P80BD_SI_MASK 0x107u
#define MCHP_P80BD_SI_STS_MASK 0x007u
#define MCHP_P80BD_SI_IEN_MASK 0x100u
#define MCHP_P80BD_SI_NE_STS BIT(0)
#define MCHP_P80BD_SI_OVR_STS BIT(1)
#define MCHP_P80BD_SI_THR_STS BIT(2)
#define MCHP_P80BD_SI_THR_IEN BIT(8)
/* Snapshot 32-bit (RO) */
#define MCHP_P80BD_SS_OFS 0x10Cu
#define MCHP_P80BD_SS_MASK 0xffffffffu
/* Capture 32-bit (RO). Current 4-byte Port 80 capture value */
#define MCHP_P80BD_CAP_OFS 0x110u
/** @brief BIOS Debug Port 80h and Alias port capture registers. */
struct p80bd_regs {
volatile uint32_t HDATA;
uint8_t RSVD1[0x100 - 0x04];
volatile uint32_t EC_DA;
volatile uint32_t CONFIG;
volatile uint32_t STS_IEN;
volatile uint32_t SNAPSHOT;
volatile uint32_t CAPTURE;
uint8_t RSVD2[0x330 - 0x114];
volatile uint32_t ACTV;
uint8_t RSVD3[0x400 - 0x334];
volatile uint8_t ALIAS_HDATA;
uint8_t RSVD4[0x730 - 0x401];
volatile uint32_t ALIAS_ACTV;
uint8_t RSVD5[0x7f0 - 0x734];
volatile uint32_t ALIAS_BLS;
};
#endif /* #ifndef _MEC172X_P80BD_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <stddef.h>
#ifndef _MEC172X_PCR_H
#define _MEC172X_PCR_H
#define MCHP_PCR_SYS_SLP_CTRL_OFS 0x00u
#define MCHP_PCR_SYS_CLK_CTRL_OFS 0x04u
#define MCHP_PCR_SLOW_CLK_CTRL_OFS 0x08u
#define MCHP_PCR_OSC_ID_OFS 0x0cu
#define MCHP_PCR_PRS_OFS 0x10u
#define MCHP_PCR_PR_CTRL_OFS 0x14u
#define MCHP_PCR_SYS_RESET_OFS 0x18u
#define MCHP_PCR_PKE_CLK_CTRL_OFS 0x1cu
#define MCHP_PCR_SLP_EN0_OFS 0x30u
#define MCHP_PCR_SLP_EN1_OFS 0x34u
#define MCHP_PCR_SLP_EN2_OFS 0x38u
#define MCHP_PCR_SLP_EN3_OFS 0x3cu
#define MCHP_PCR_SLP_EN4_OFS 0x40u
#define MCHP_PCR_CLK_REQ0_OFS 0x50u
#define MCHP_PCR_CLK_REQ1_OFS 0x54u
#define MCHP_PCR_CLK_REQ2_OFS 0x58u
#define MCHP_PCR_CLK_REQ3_OFS 0x5cu
#define MCHP_PCR_CLK_REQ4_OFS 0x60u
#define MCHP_PCR_PERIPH_RST0_OFS 0x70u
#define MCHP_PCR_PERIPH_RST1_OFS 0x74u
#define MCHP_PCR_PERIPH_RST2_OFS 0x78u
#define MCHP_PCR_PERIPH_RST3_OFS 0x7cu
#define MCHP_PCR_PERIPH_RST4_OFS 0x80u
#define MCHP_PCR_PERIPH_RST_LCK_OFS 0x84u
#define MCHP_PCR_VBAT_SRST_OFS 0x88u
#define MCHP_PCR_CLK32K_SRC_VTR_OFS 0x8cu
#define MCHP_PCR_CNT32K_PER_OFS 0xc0u
#define MCHP_PCR_CNT32K_PULSE_HI_OFS 0xc4u
#define MCHP_PCR_CNT32K_PER_MIN_OFS 0xc8u
#define MCHP_PCR_CNT32K_PER_MAX_OFS 0xccu
#define MCHP_PCR_CNT32K_DV_OFS 0xd0u
#define MCHP_PCR_CNT32K_DV_MAX_OFS 0xd4u
#define MCHP_PCR_CNT32K_VALID_OFS 0xd8u
#define MCHP_PCR_CNT32K_VALID_MIN_OFS 0xdcu
#define MCHP_PCR_CNT32K_CTRL_OFS 0xe0u
#define MCHP_PCR_CLK32K_MON_ISTS_OFS 0xe4u
#define MCHP_PCR_CLK32K_MON_IEN_OFS 0xe8u
/*
* MEC172x PCR implements multiple SLP_EN, CLR_REQ, and RST_EN registers.
* CLK_REQ bits are read-only. The peripheral sets its CLK_REQ if it requires
* clocks. CLK_REQ bits must all be zero for the PCR block to put the MEC17xx
* into light or heavy sleep.
* SLP_EN bit = 1 instructs HW to gate off clock tree to peripheral only if
* peripherals PCR CLK_REQ bit is 0.
* RST_EN bit = 1 will reset the peripheral at any time. The RST_EN registers
* must be unlocked by writing the unlock code to PCR Peripheral Reset Lock
* register.
* SLP_EN usage is:
* Initialization set all PCR SLP_EN bits = 0 except for crypto blocks as
* these IP do not implement internal clock gating.
* When firmware wants to enter light or heavy sleep.
* Configure wake up source(s)
* Write MCHP_PCR_SYS_SLP_CTR register to value based on light/heavy with
* SLEEP_ALL bit = 1.
* Execute Cortex-M4 WFI sequence. DSB(), ISB(), WFI(), NOP()
* Cortex-M4 will assert sleep signal to PCR block.
* PCR HW will spin until all CLK_REQ==0
* PCR will then turn off clocks based on light/heavy sleep.
*
* RST_EN usage is:
* Save and disable maskable interrupts
* Write unlock code to PCR Peripheral Reset Lock
* Write bit patterns to one or more of PCR RST_EN[0, 4] registers
* Selected peripherals will be reset.
* Write lock code to PCR Peripheral Reset Lock.
* Restore interrupts.
*/
#define MCHP_MAX_PCR_SCR_REGS 5u
/* VTR Powered PCR registers */
#define MCHP_PCR_SLP(bitpos) BIT(bitpos)
/* PCR System Sleep Control */
#define MCHP_PCR_SYS_SLP_CTRL_MASK 0x0109u
#define MCHP_PCR_SYS_SLP_CTRL_SLP_HEAVY BIT(0)
#define MCHP_PCR_SYS_SLP_CTRL_SLP_ALL BIT(3)
/*
* bit[8] can be used to prevent entry to heavy sleep unless the
* PLL is locked.
* bit[8]==0 (POR default) system will allow entry to light or heavy
* sleep if and only if PLL is locked.
* bit[8]==1 system will allow entry to heavy sleep before PLL is locked.
*/
#define MCHP_PCR_SYS_SLP_CTRL_ALLOW_SLP_NO_PLL_LOCK BIT(8)
/* Assert all peripheral sleep enables once CPU asserts its sleep signal */
#define MCHP_PCR_SYS_SLP_LIGHT BIT(3)
#define MCHP_PCR_SYS_SLP_HEAVY (BIT(3) | BIT(0))
/*
* PCR Process Clock Control
* Divides 96MHz clock to ARM Cortex-M4 core including
* SysTick and NVIC.
*/
#define MCHP_PCR_PROC_CLK_CTRL_MASK GENMASK(7, 0)
#define MCHP_PCR_PROC_CLK_CTRL_96MHZ 1
#define MCHP_PCR_PROC_CLK_CTRL_48MHZ 2
#define MCHP_PCR_PROC_CLK_CTRL_24MHZ 4
#define MCHP_PCR_PROC_CLK_CTRL_12MHZ 8
#define MCHP_PCR_PROC_CLK_CTRL_6MHZ 16
#define MCHP_PCR_PROC_CLK_CTRL_2MHZ 48
#define MCHP_PCR_PROC_CLK_CTRL_DFLT MCHP_PCR_PROC_CLK_CTRL_24MHZ
/* PCR Slow Clock Control. Clock divider for 100KHz clock domain */
#define MCHP_PCR_SLOW_CLK_CTRL_MASK GENMASK(9, 0)
#define MCHP_PCR_SLOW_CLK_CTRL_100KHZ 0x1e0u
/* PCR Oscillator ID register (Read-Only) */
#define MCHP_PCR_OSC_ID_MASK GENMASK(8, 0)
#define MCHP_PCR_OSC_ID_PLL_LOCK BIT(8)
/* PCR Power Reset Status Register */
#define MCHP_PCR_PRS_MASK \
(GENMASK(11, 10) | GENMASK(8, 2))
#define MCHP_PCR_PRS_VCC_PWRGD_STATE_RO BIT(2)
#define MCHP_PCR_PRS_HOST_RESET_STATE_RO BIT(3)
#define MCHP_PCR_PRS_VTR_RST_RWC BIT(4)
#define MCHP_PCR_PRS_VBAT_RST_RWC BIT(5)
#define MCHP_PCR_PRS_RST_SYS_RWC BIT(6)
#define MCHP_PCR_PRS_JTAG_RST_RO BIT(7)
#define MCHP_PCR_PRS_WDT_EVENT_RWC BIT(8)
#define MCHP_PCR_PRS_32K_ACTIVE_RO BIT(10)
#define MCHP_PCR_PRS_LPC_ESPI_CLK_ACTIVE_RO BIT(11)
/* PCR Power Reset Control Register */
#define MCHP_PCR_PR_CTRL_MASK (BIT(8) | BIT(0))
#define MCHP_PCR_PR_CTRL_PWR_INV BIT(0)
#define MCHP_PCR_PR_CTRL_USE_ESPI_PLTRST 0u
#define MCHP_PCR_PR_CTRL_USE_PCI_RST BIT(8)
/* PCR System Reset Register */
#define MCHP_PCR_SYS_RESET_MASK BIT(8)
#define MCHP_PCR_SYS_RESET_NOW BIT(8)
/* Turbo Clock Register */
#define MCHP_PCR_TURBO_CLK_MASK BIT(2)
#define MCHP_PCR_TURBO_CLK_96M BIT(2)
/*
* Sleep Enable Reg 0 (Offset +30h)
* Clock Required Reg 0 (Offset +50h)
* Reset Enable Reg 0 (Offset +70h)
*/
#define MCHP_PCR0_JTAG_STAP_POS 0
#define MCHP_PCR0_OTP_POS 1
#define MCHP_PCR0_ISPI_EMC_POS 2
/*
* Sleep Enable Reg 1 (Offset +34h)
* Clock Required Reg 1 (Offset +54h)
* Reset Enable Reg 1 (Offset +74h)
*/
#define MCHP_PCR1_ECIA_POS 0
#define MCHP_PCR1_PECI_POS 1
#define MCHP_PCR1_TACH0_POS 2
#define MCHP_PCR1_PWM0_POS 4
#define MCHP_PCR1_PMC_POS 5
#define MCHP_PCR1_DMA_POS 6
#define MCHP_PCR1_TFDP_POS 7
#define MCHP_PCR1_CPU_POS 8
#define MCHP_PCR1_WDT_POS 9
#define MCHP_PCR1_SMB0_POS 10
#define MCHP_PCR1_TACH1_POS 11
#define MCHP_PCR1_TACH2_POS 12
#define MCHP_PCR1_TACH3_POS 13
#define MCHP_PCR1_PWM1_POS 20
#define MCHP_PCR1_PWM2_POS 21
#define MCHP_PCR1_PWM3_POS 22
#define MCHP_PCR1_PWM4_POS 23
#define MCHP_PCR1_PWM5_POS 24
#define MCHP_PCR1_PWM6_POS 25
#define MCHP_PCR1_PWM7_POS 26
#define MCHP_PCR1_PWM8_POS 27
#define MCHP_PCR1_ECS_POS 29
#define MCHP_PCR1_B16TMR0_POS 30
#define MCHP_PCR1_B16TMR1_POS 31
/*
* Sleep Enable Reg 2 (Offset +38h)
* Clock Required Reg 2 (Offset +58h)
* Reset Enable Reg 2 (Offset +78h)
*/
#define MCHP_PCR2_EMI0_POS 0
#define MCHP_PCR2_UART0_POS 1
#define MCHP_PCR2_UART1_POS 2
#define MCHP_PCR2_GCFG_POS 12
#define MCHP_PCR2_ACPI_EC0_POS 13
#define MCHP_PCR2_ACPI_EC1_POS 14
#define MCHP_PCR2_ACPI_PM1_POS 15
#define MCHP_PCR2_KBC_POS 16
#define MCHP_PCR2_MBOX_POS 17
#define MCHP_PCR2_RTC_POS 18
#define MCHP_PCR2_ESPI_POS 19
#define MCHP_PCR2_SCR32_POS 20
#define MCHP_PCR2_ACPI_EC2_POS 21
#define MCHP_PCR2_ACPI_EC3_POS 22
#define MCHP_PCR2_ACPI_EC4_POS 23
#define MCHP_PCR2_P80BD_POS 25
#define MCHP_PCR2_ESPI_SAF_POS 27
#define MCHP_PCR2_GLUE_POS 29
/*
* Sleep Enable Reg 3 (Offset +3Ch)
* Clock Required Reg 3 (Offset +5Ch)
* Reset Enable Reg 3 (Offset +7Ch)
*/
#define MCHP_PCR3_ADC_POS 3
#define MCHP_PCR3_PS2_0_POS 5
#define MCHP_PCR3_GPSPI0_POS 9
#define MCHP_PCR3_HTMR0_POS 10
#define MCHP_PCR3_KEYSCAN_POS 11
#define MCHP_PCR3_RPMFAN0_POS 12
#define MCHP_PCR3_SMB1_POS 13
#define MCHP_PCR3_SMB2_POS 14
#define MCHP_PCR3_SMB3_POS 15
#define MCHP_PCR3_LED0_POS 16
#define MCHP_PCR3_LED1_POS 17
#define MCHP_PCR3_LED2_POS 18
#define MCHP_PCR3_BCL0_POS 19
#define MCHP_PCR3_SMB4_POS 20
#define MCHP_PCR3_B16TMR2_POS 21
#define MCHP_PCR3_B16TMR3_POS 22
#define MCHP_PCR3_B32TMR0_POS 23
#define MCHP_PCR3_B32TMR1_POS 24
#define MCHP_PCR3_LED3_POS 25
#define MCHP_PCR3_CRYPTO_POS 26
#define MCHP_PCR3_HTMR1_POS 29
#define MCHP_PCR3_CCT_POS 30
#define MCHP_PCR3_PWM9_POS 31
#define MCHP_PCR3_CRYPTO_MASK BIT(MCHP_PCR3_CRYPTO_POS)
/*
* Sleep Enable Reg 4 (Offset +40h)
* Clock Required Reg 4 (Offset +60h)
* Reset Enable Reg 4 (Offset +80h)
*/
#define MCHP_PCR4_PWM10_POS 0
#define MCHP_PCR4_PWM11_POS 1
#define MCHP_CTMR0_POS 2
#define MCHP_CTMR1_POS 3
#define MCHP_CTMR2_POS 4
#define MCHP_CTMR3_POS 5
#define MCHP_PCR4_RTMR_POS 6
#define MCHP_PCR4_RPMFAN1_POS 7
#define MCHP_PCR4_QMSPI_POS 8
#define MCHP_PCR4_RCID0_POS 10
#define MCHP_PCR4_RCID1_POS 11
#define MCHP_PCR4_RCID2_POS 12
#define MCHP_PCR4_PHOT_POS 13
#define MCHP_PCR4_EEPROM_POS 14
#define MCHP_PCR4_SPIP_POS 16
#define MCHP_PCR4_GPSPI1_POS 22
/* Reset Enable Lock (Offset +84h) */
#define MCHP_PCR_RSTEN_UNLOCK 0xa6382d4cu
#define MCHP_PCR_RSTEN_LOCK 0xa6382d4du
/* VBAT Soft Reset (Offset +88h) */
#define MCHP_PCR_VBSR_MASK BIT(0)
#define MCHP_PCR_VBSR_EN BIT(0) /* self clearing */
/* VTR Source 32 KHz Clock (Offset +8Ch) */
#define MCHP_PCR_VTR_32K_SRC_MASK GENMASK(1, 0)
#define MCHP_PCR_VTR_32K_SRC_SILOSC 0u
#define MCHP_PCR_VTR_32K_SRC_XTAL BIT(0)
#define MCHP_PCR_VTR_32K_SRC_PIN BIT(1)
#define MCHP_PCR_VTR_32K_SRC_NONE (BIT(0) | BIT(1))
/*
* Clock monitor 32KHz period counter (Offset +C0h, RO)
* Clock monitor 32KHz high counter (Offset +C4h, RO)
* Clock monitor 32KHz period counter minimum (Offset +C8h, RW)
* Clock monitor 32KHz period counter maximum (Offset +CCh, RW)
* Clock monitor 32KHz Duty Cycle variation counter (Offset +D0h, RO)
* Clock monitor 32KHz Duty Cycle variation counter maximum (Offset +D4h, RW)
*/
#define MCHP_PCR_CLK32M_CNT_MASK GENMASK(15, 0)
/*
* Clock monitor 32KHz Valid Count (Offset +0xD8, RO)
* Clock monitor 32KHz Valid Count minimum (Offset +0xDC, RW)
*/
#define MCHP_PCR_CLK32M_VALID_CNT_MASK GENMASK(7, 0)
/* Clock monitor control register (Offset +0xE0, RW) */
#define MCHP_PCR_CLK32M_CTRL_MASK (BIT(24) | BIT(4) | GENMASK(2, 0))
#define MCHP_PCR_CLK32M_CTRL_PER_EN BIT(0)
#define MCHP_PCR_CLK32M_CTRL_DC_EN BIT(1)
#define MCHP_PCR_CLK32M_CTRL_VAL_EN BIT(2)
#define MCHP_PCR_CLK32M_CTRL_SRC_SO BIT(4)
#define MCHP_PCR_CLK32M_CTRL_CLR_CNT BIT(24)
/* Clock monitor interrupt status (Offset +0xE4, R/W1C) */
#define MCHP_PCR_CLK32M_ISTS_MASK GENMASK(6, 0)
#define MCHP_PCR_CLK32M_ISTS_PULSE_RDY BIT(0)
#define MCHP_PCR_CLK32M_ISTS_PASS_PER BIT(1)
#define MCHP_PCR_CLK32M_ISTS_PASS_DC BIT(2)
#define MCHP_PCR_CLK32M_ISTS_FAIL BIT(3)
#define MCHP_PCR_CLK32M_ISTS_STALL BIT(4)
#define MCHP_PCR_CLK32M_ISTS_VALID BIT(5)
#define MCHP_PCR_CLK32M_ISTS_UNWELL BIT(6)
/* Clock monitor interrupt enable (Offset +0xE8, RW) */
#define MCHP_PCR_CLK32M_IEN_MASK GENMASK(6, 0)
#define MCHP_PCR_CLK32M_IEN_PULSE_RDY BIT(0)
#define MCHP_PCR_CLK32M_IEN_PASS_PER BIT(1)
#define MCHP_PCR_CLK32M_IEN_PASS_DC BIT(2)
#define MCHP_PCR_CLK32M_IEN_FAIL BIT(3)
#define MCHP_PCR_CLK32M_IEN_STALL BIT(4)
#define MCHP_PCR_CLK32M_IEN_VALID BIT(5)
#define MCHP_PCR_CLK32M_IEN_UNWELL BIT(6)
/* PCR 32KHz clock monitor uses 48 MHz for all counters */
#define MCHP_PCR_CLK32M_CLOCK 48000000u
struct pcr_regs {
volatile uint32_t SYS_SLP_CTRL;
volatile uint32_t PROC_CLK_CTRL;
volatile uint32_t SLOW_CLK_CTRL;
volatile uint32_t OSC_ID;
volatile uint32_t PWR_RST_STS;
volatile uint32_t PWR_RST_CTRL;
volatile uint32_t SYS_RST;
volatile uint32_t TURBO_CLK;
volatile uint32_t TEST20;
uint32_t RSVD1[3];
volatile uint32_t SLP_EN[5];
uint32_t RSVD2[3];
volatile uint32_t CLK_REQ[5];
uint32_t RSVD3[3];
volatile uint32_t RST_EN[5];
volatile uint32_t RST_EN_LOCK;
volatile uint32_t VBAT_SRST;
volatile uint32_t CLK32K_SRC_VTR;
volatile uint32_t TEST90;
uint32_t RSVD4[(0x00c0 - 0x0094) / 4];
volatile uint32_t CNT32K_PER;
volatile uint32_t CNT32K_PULSE_HI;
volatile uint32_t CNT32K_PER_MIN;
volatile uint32_t CNT32K_PER_MAX;
volatile uint32_t CNT32K_DV;
volatile uint32_t CNT32K_DV_MAX;
volatile uint32_t CNT32K_VALID;
volatile uint32_t CNT32K_VALID_MIN;
volatile uint32_t CNT32K_CTRL;
volatile uint32_t CLK32K_MON_ISTS;
volatile uint32_t CLK32K_MON_IEN;
};
#endif /* #ifndef _MEC172X_PCR_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MEC_QSPI_H_
#define _MEC_QSPI_H_
#include <stdint.h>
#include <stddef.h>
#define QMPSPI_HW_VER 4u
#define MCHP_QMSPI_BASE_ADDR 0x40070000u
#define MCHP_QMSPI_MAX_DESCR 16u
#define MCHP_QMSPI_INPUT_CLOCK_FREQ_HZ 96000000u
#define MCHP_QMSPI_MAX_FREQ_KHZ \
((MCHP_QMSPI_INPUT_CLOCK_FREQ_HZ) / 1000u)
#define MCHP_QMSPI_MIN_FREQ_KHZ (MCHP_QMSPI_MAX_FREQ_KHZ / 256u)
/* Mode 0: Clock idle = Low. Data change falling edge, sample rising edge */
#define MCHP_QMSPI_SPI_MODE0 0u
/* Mode 1: Clock idle = Low. Data change rising edge, sample falling edge */
#define MCHP_QMSPI_SPI_MODE1 0x06u
/* Mode 2: Clock idle = High. Data change rising edge, sample falling edge */
#define MCHP_QMSPI_SPI_MODE2 0x06u
/* Mode 3: Clock idle = High. Data change falling edge, sample rising edge */
#define MCHP_QMSPI_SPI_MODE3 0x07u
/* Device ID used in DMA channel Control.DeviceID field */
#define MCHP_QMSPI_TX_DMA_REQ_ID 10u
#define MCHP_QMSPI_RX_DMA_REQ_ID 11u
/* QMSPI transmit and receive FIFO lengths */
#define MCHP_QMSPI_TX_FIFO_LEN 8u
#define MCHP_QMSPI_RX_FIFO_LEN 8u
/* QMSPI Local DMA channels */
#define MCHP_QMSPI_LDMA_RX_CHANNELS 3u
#define MCHP_QMSPI_LDMA_TX_CHANNELS 3u
#define MCHP_QMSPI_M_ACT_SRST_OFS 0u
#define MCHP_QMSPI_M_SPI_MODE_OFS 1u
#define MCHP_QMSPI_M_CLK_DIV_OFS 2u
#define MCHP_QMSPI_CTRL_OFS 4u
#define MCHP_QMSPI_EXE_OFS 8u
#define MCHP_QMSPI_IF_CTRL_OFS 0x0cu
#define MCHP_QMSPI_STS_OFS 0x10u
#define MCHP_QMSPI_BUF_CNT_STS_OFS 0x14u
#define MCHP_QMSPI_IEN_OFS 0x18u
#define MCHP_QMSPI_BUF_CNT_TRIG_OFS 0x1cu
#define MCHP_QMSPI_TX_FIFO_OFS 0x20u
#define MCHP_QMSPI_RX_FIFO_OFS 0x24u
#define MCHP_QMSPI_CSTM_OFS 0x28u
/* 0 <= n < MCHP_QMSPI_MAX_DESCR */
#define MCHP_QMSPI_DESC0_OFS 0x30u
#define MCHP_QMSPI_DESCR_OFS(n) (0x30u + ((uint32_t)(n) * 4u))
#define MCHP_QMSPI_ALIAS_CTRL_OFS 0xb0u
#define MCHP_QMSPI_MODE_ALT1_OFS 0xc0u
#define MCHP_QMSPI_TAPS_OFS 0xd0u
#define MCHP_QMSPI_TAPS_ADJ_OFS 0xd4u
#define MCHP_QMSPI_TAPS_CTRL_OFS 0xd8u
#define MCHP_QMSPI_LDMA_RX_EN_OFS 0x100u
#define MCHP_QMSPI_LDMA_TX_EN_OFS 0x104u
#define MCHP_QMSPI_LDMA_RX_0_CTRL_OFS 0x110u
#define MCHP_QMSPI_LDMA_RX_0_START_OFS 0x114u
#define MCHP_QMSPI_LDMA_RX_0_LEN_OFS 0x118u
#define MCHP_QMSPI_LDMA_RX_1_CTRL_OFS 0x120u
#define MCHP_QMSPI_LDMA_RX_1_START_OFS 0x124u
#define MCHP_QMSPI_LDMA_RX_1_LEN_OFS 0x128u
#define MCHP_QMSPI_LDMA_RX_2_CTRL_OFS 0x130u
#define MCHP_QMSPI_LDMA_RX_2_START_OFS 0x134u
#define MCHP_QMSPI_LDMA_RX_2_LEN_OFS 0x138u
#define MCHP_QMSPI_LDMA_TX_0_CTRL_OFS 0x140u
#define MCHP_QMSPI_LDMA_TX_0_START_OFS 0x144u
#define MCHP_QMSPI_LDMA_TX_0_LEN_OFS 0x148u
#define MCHP_QMSPI_LDMA_TX_1_CTRL_OFS 0x150u
#define MCHP_QMSPI_LDMA_TX_1_START_OFS 0x154u
#define MCHP_QMSPI_LDMA_TX_1_LEN_OFS 0x158u
#define MCHP_QMSPI_LDMA_TX_2_CTRL_OFS 0x160u
#define MCHP_QMSPI_LDMA_TX_2_START_OFS 0x164u
#define MCHP_QMSPI_LDMA_TX_2_LEN_OFS 0x168u
#define MCHP_QMSPI_MODE_ADDR (MCHP_QMSPI_BASE_ADDR + 0x00)
#define MCHP_QMSPI_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0x04)
#define MCHP_QMSPI_EXE_ADDR (MCHP_QMSPI_BASE_ADDR + 0x08)
#define MCHP_QMSPI_IFC_ADDR (MCHP_QMSPI_BASE_ADDR + 0x0c)
#define MCHP_QMSPI_STS_ADDR (MCHP_QMSPI_BASE_ADDR + 0x10)
#define MCHP_QMSPI_BUFCNT_STS_ADDR (MCHP_QMSPI_BASE_ADDR + 0x14)
#define MCHP_QMSPI_TX_BCNT_STS_ADDR (MCHP_QMSPI_BASE_ADDR + 0x14)
#define MCHP_QMSPI_RX_BCNT_STS_ADDR (MCHP_QMSPI_BASE_ADDR + 0x16)
#define MCHP_QMSPI_IEN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x18)
#define MCHP_QMSPI_TXB_ADDR (MCHP_QMSPI_BASE_ADDR + 0x20)
#define MCHP_QMSPI_RXB_ADDR (MCHP_QMSPI_BASE_ADDR + 0x24)
#define MCHP_QMSPI_CSTM_ADDR (MCHP_QMSPI_BASE_ADDR + 0x28)
#define MCHP_QMSPI_DESCR_ADDR(n) \
(MCHP_QMSPI_BASE_ADDR + (0x30 + (((uint32_t)(n) & 0x0Fu) << 2)))
#define MCHP_QMSPI_ALIAS_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0xb0u)
#define MCHP_QMSPI_MODE_ALT1_ADDR (MCHP_QMSPI_BASE_ADDR + 0xc0u)
#define MCHP_QMSPI_TAPS_ADDR (MCHP_QMSPI_BASE_ADDR + 0xd0u)
#define MCHP_QMSPI_TAPS_ADJ_ADDR (MCHP_QMSPI_BASE_ADDR + 0xd4u)
#define MCHP_QMSPI_TAPS_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0xd8u)
#define MCHP_QMSPI_LDMA_RX_EN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x100u)
#define MCHP_QMSPI_LDMA_TX_EN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x104u)
#define MCHP_QMSPI_LDMA_RX_0_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0x110u)
#define MCHP_QMSPI_LDMA_RX_0_START_ADDR (MCHP_QMSPI_BASE_ADDR + 0x114u)
#define MCHP_QMSPI_LDMA_RX_0_LEN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x118u)
#define MCHP_QMSPI_LDMA_RX_1_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0x120u)
#define MCHP_QMSPI_LDMA_RX_1_START_ADDR (MCHP_QMSPI_BASE_ADDR + 0x124u)
#define MCHP_QMSPI_LDMA_RX_1_LEN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x128u)
#define MCHP_QMSPI_LDMA_RX_2_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0x130u)
#define MCHP_QMSPI_LDMA_RX_2_START_ADDR (MCHP_QMSPI_BASE_ADDR + 0x134u)
#define MCHP_QMSPI_LDMA_RX_2_LEN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x138u)
#define MCHP_QMSPI_LDMA_TX_0_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0x140u)
#define MCHP_QMSPI_LDMA_TX_0_START_ADDR (MCHP_QMSPI_BASE_ADDR + 0x144u)
#define MCHP_QMSPI_LDMA_TX_0_LEN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x148u)
#define MCHP_QMSPI_LDMA_TX_1_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0x150u)
#define MCHP_QMSPI_LDMA_TX_1_START_ADDR (MCHP_QMSPI_BASE_ADDR + 0x154u)
#define MCHP_QMSPI_LDMA_TX_1_LEN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x158u)
#define MCHP_QMSPI_LDMA_TX_2_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0x160u)
#define MCHP_QMSPI_LDMA_TX_2_START_ADDR (MCHP_QMSPI_BASE_ADDR + 0x164u)
#define MCHP_QMSPI_LDMA_TX_2_LEN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x168u)
/* Mode Register */
#define MCHP_QMSPI_M_MASK 0x00ff371fu
#define MCHP_QMSPI_M_ACTIVATE BIT(0)
#define MCHP_QMSPI_M_SRST BIT(1)
#define MCHP_QMSPI_M_SAF_DMA_MODE_EN BIT(2)
#define MCHP_QMSPI_M_LDMA_RX_EN BIT(3)
#define MCHP_QMSPI_M_LDMA_TX_EN BIT(4)
#define MCHP_QMSPI_M_CPOL_POS 8u
#define MCHP_QMSPI_M_CPOL_CLK_IDLE_LO 0
#define MCHP_QMSPI_M_CPOL_CLK_IDLE_HI BIT(8)
#define MCHP_QMSPI_M_CPHA_MOSI_POS 9u
/* MOSI data changes on first clock edge of clock pulse */
#define MCHP_QMSPI_M_CPHA_MOSI_CE1 0u
/* MOSI data changes on second clock edge of clock pulse */
#define MCHP_QMSPI_M_CPHA_MOSI_CE2 BIT(9)
#define MCHP_QMSPI_M_CPHA_MIS0_POS 10u
/* MISO data capture on first clock edge of clock pulse */
#define MCHP_QMSPI_M_CPHA_MISO_CE1 0u
/* MISO data capture on second clock edge of clock pulse */
#define MCHP_QMSPI_M_CPHA_MISO_CE2 BIT(10)
#define MCHP_QMSPI_M_SIG_POS 8u
#define MCHP_QMSPI_M_SIG_MASK0 0x07u
#define MCHP_QMSPI_M_SIG_MASK 0x0700u
#define MCHP_QMSPI_M_SIG_MODE0_VAL 0u
#define MCHP_QMSPI_M_SIG_MODE1_VAL 0x06u
#define MCHP_QMSPI_M_SIG_MODE2_VAL 0x01u
#define MCHP_QMSPI_M_SIG_MODE3_VAL 0x07u
#define MCHP_QMSPI_M_SIG_MODE0 0u
#define MCHP_QMSPI_M_SIG_MODE1 SHLU32(6u, MCHP_QMSPI_M_SIG_POS)
#define MCHP_QMSPI_M_SIG_MODE2 SHLU32(1u, MCHP_QMSPI_M_SIG_POS)
#define MCHP_QMSPI_M_SIG_MODE3 SHLU32(7u, MCHP_QMSPI_M_SIG_POS)
#define MCHP_QMSPI_M_CS_POS 12u
#define MCHP_QMSPI_M_CS_MASK0 0x03u
#define MCHP_QMSPI_M_CS_MASK SHLU32(3u, 12)
#define MCHP_QMSPI_M_CS0 SHLU32(0u, 12)
#define MCHP_QMSPI_M_CS1 SHLU32(1u, 12)
/* Two chip selects only 0 and 1 */
#define MCHP_QMSPI_M_CS(n) \
(((uint32_t)(n) & MCHP_QMSPI_M_CS_MASK0) << MCHP_QMSPI_M_CS_POS)
#define MCHP_QMSPI_M_FDIV_POS 16u
#define MCHP_QMSPI_M_FDIV_MASK0 0xffffu
#define MCHP_QMSPI_M_FDIV_MASK 0xffff0000u
/* Control/Descriptors */
#define MCHP_QMSPI_C_IFM_MASK 0x03u
#define MCHP_QMSPI_C_IFM_1X 0u
#define MCHP_QMSPI_C_IFM_2X 1u
#define MCHP_QMSPI_C_IFM_4X 2u
#define MCHP_QMSPI_C_TX_POS 2u
#define MCHP_QMSPI_C_TX_MASK SHLU32(3u, MCHP_QMSPI_C_TX_POS)
#define MCHP_QMSPI_C_TX_DIS 0u
#define MCHP_QMSPI_C_TX_DATA SHLU32(1u, MCHP_QMSPI_C_TX_POS)
#define MCHP_QMSPI_C_TX_ZEROS SHLU32(2u, MCHP_QMSPI_C_TX_POS)
#define MCHP_QMSPI_C_TX_ONES SHLU32(3u, MCHP_QMSPI_C_TX_POS)
#define MCHP_QMSPI_C_TX_DMA_POS 4u
#define MCHP_QMSPI_C_TX_DMA_MASK SHLU32(3u, MCHP_QMSPI_C_TX_DMA_POS)
#define MCHP_QMSPI_C_TX_DMA_DIS 0u
#define MCHP_QMSPI_C_TX_DMA_1B SHLU32(1u, MCHP_QMSPI_C_TX_DMA_POS)
#define MCHP_QMSPI_C_TX_DMA_2B SHLU32(2u, MCHP_QMSPI_C_TX_DMA_POS)
#define MCHP_QMSPI_C_TX_DMA_4B SHLU32(3u, MCHP_QMSPI_C_TX_DMA_POS)
#define MCHP_QMSPI_C_TX_LDMA_CH0 SHLU32(1u, MCHP_QMSPI_C_TX_DMA_POS)
#define MCHP_QMSPI_C_TX_LDMA_CH1 SHLU32(2u, MCHP_QMSPI_C_TX_DMA_POS)
#define MCHP_QMSPI_C_TX_LDMA_CH2 SHLU32(3u, MCHP_QMSPI_C_TX_DMA_POS)
#define MCHP_QMSPI_C_RX_POS 6u
#define MCHP_QMSPI_C_RX_DIS 0u
#define MCHP_QMSPI_C_RX_EN BIT(MCHP_QMSPI_C_RX_POS)
#define MCHP_QMSPI_C_RX_DMA_POS 7u
#define MCHP_QMSPI_C_RX_DMA_MASK SHLU32(3u, MCHP_QMSPI_C_RX_DMA_POS)
#define MCHP_QMSPI_C_RX_DMA_DIS 0u
#define MCHP_QMSPI_C_RX_DMA_1B SHLU32(1u, MCHP_QMSPI_C_RX_DMA_POS)
#define MCHP_QMSPI_C_RX_DMA_2B SHLU32(2u, MCHP_QMSPI_C_RX_DMA_POS)
#define MCHP_QMSPI_C_RX_DMA_4B SHLU32(3u, MCHP_QMSPI_C_RX_DMA_POS)
#define MCHP_QMSPI_C_RX_LDMA_CH0 SHLU32(1u, MCHP_QMSPI_C_RX_DMA_POS)
#define MCHP_QMSPI_C_RX_LDMA_CH1 SHLU32(2u, MCHP_QMSPI_C_RX_DMA_POS)
#define MCHP_QMSPI_C_RX_lDMA_CH2 SHLU32(3u, MCHP_QMSPI_C_RX_DMA_POS)
#define MCHP_QMSPI_C_CLOSE_POS 9u
#define MCHP_QMSPI_C_NO_CLOSE 0u
#define MCHP_QMSPI_C_CLOSE BIT(MCHP_QMSPI_C_CLOSE_POS)
#define MCHP_QMSPI_C_XFR_UNITS_POS 10u
#define MCHP_QMSPI_C_XFR_UNITS_MASK SHLU32(3u, MCHP_QMSPI_C_XFR_UNITS_POS)
#define MCHP_QMSPI_C_XFR_UNITS_BITS 0u
#define MCHP_QMSPI_C_XFR_UNITS_1 SHLU32(1u, MCHP_QMSPI_C_XFR_UNITS_POS)
#define MCHP_QMSPI_C_XFR_UNITS_4 SHLU32(2u, MCHP_QMSPI_C_XFR_UNITS_POS)
#define MCHP_QMSPI_C_XFR_UNITS_16 SHLU32(3u, MCHP_QMSPI_C_XFR_UNITS_POS)
#define MCHP_QMSPI_C_NEXT_DESCR_POS 12u
#define MCHP_QMSPI_C_NEXT_DESCR_MASK0 0x0fu
#define MCHP_QMSPI_C_NEXT_DESCR_MASK 0xf000u
#define MCHP_QMSPI_C_DESCR0 0u
#define MCHP_QMSPI_C_DESCR1 0x1000u
#define MCHP_QMSPI_C_DESCR2 0x2000u
#define MCHP_QMSPI_C_DESCR3 0x3000u
#define MCHP_QMSPI_C_DESCR4 0x4000u
/* Control register start descriptor field */
#define MCHP_QMSPI_C_DESCR(n) \
SHLU32(((n) & 0xFu), MCHP_QMSPI_C_NEXT_DESCR_POS)
/* Descriptor registers next descriptor field */
#define MCHP_QMSPI_C_NEXT_DESCR(n) \
SHLU32(((n) & 0xFu), MCHP_QMSPI_C_NEXT_DESCR_POS)
/* Control register descriptor mode enable */
#define MCHP_QMSPI_C_DESCR_EN_POS 16u
#define MCHP_QMSPI_C_DESCR_EN BIT(MCHP_QMSPI_C_DESCR_EN_POS)
/* Descriptor registers last descriptor flag */
#define MCHP_QMSPI_C_DESCR_LAST BIT(MCHP_QMSPI_C_DESCR_EN_POS)
#define MCHP_QMSPI_C_MAX_UNITS 0x7fffu
#define MCHP_QMSPI_C_MAX_UNITS_MASK 0x7fffu
#define MCHP_QMSPI_C_XFR_NUNITS_POS 17u
#define MCHP_QMSPI_C_XFR_NUNITS_MASK0 0x7fffu
#define MCHP_QMSPI_C_XFR_NUNITS_MASK 0xfffe0000u
#define MCHP_QMSPI_C_XFR_NUNITS(n) SHLU32((n), MCHP_QMSPI_C_XFR_NUNITS_POS)
#define MCHP_QMSPI_C_XFR_NUNITS_GET(descr) ((uint32_t)(descr) >> 17)
/* Exe */
#define MCHP_QMSPI_EXE_START BIT(0)
#define MCHP_QMSPI_EXE_STOP BIT(1)
#define MCHP_QMSPI_EXE_CLR_FIFOS BIT(2)
/* Interface Control */
#define MCHP_QMSPI_IFC_DFLT 0u
#define MCHP_QMSPI_IFC_WP_OUT_HI BIT(0)
#define MCHP_QMSPI_IFC_WP_OUT_EN BIT(1)
#define MCHP_QMSPI_IFC_HOLD_OUT_HI BIT(2)
#define MCHP_QMSPI_IFC_HOLD_OUT_EN BIT(3)
#define MCHP_QMSPI_IFC_PD_ON_NS BIT(4)
#define MCHP_QMSPI_IFC_PU_ON_NS BIT(5)
#define MCHP_QMSPI_IFC_PD_ON_ND BIT(6)
#define MCHP_QMSPI_IFC_PU_ON_ND BIT(7)
/* Status Register */
#define MCHP_QMSPI_STS_REG_MASK 0x0f01ff1fu
#define MCHP_QMSPI_STS_RO_MASK 0x0f013300u
#define MCHP_QMSPI_STS_RW1C_MASK 0x0000cc7fu
#define MCHP_QMSPI_STS_DONE BIT(0)
#define MCHP_QMSPI_STS_DMA_DONE BIT(1)
#define MCHP_QMSPI_STS_TXB_ERR BIT(2)
#define MCHP_QMSPI_STS_RXB_ERR BIT(3)
#define MCHP_QMSPI_STS_PROG_ERR BIT(4)
#define MCHP_QMSPI_STS_LDMA_RX_ERR BIT(5)
#define MCHP_QMSPI_STS_LDMA_TX_ERR BIT(6)
#define MCHP_QMSPI_STS_TXBF_RO BIT(8)
#define MCHP_QMSPI_STS_TXBE_RO BIT(9)
#define MCHP_QMSPI_STS_TXBR BIT(10)
#define MCHP_QMSPI_STS_TXBS BIT(11)
#define MCHP_QMSPI_STS_RXBF_RO BIT(12)
#define MCHP_QMSPI_STS_RXBE_RO BIT(13)
#define MCHP_QMSPI_STS_RXBR BIT(14)
#define MCHP_QMSPI_STS_RXBS BIT(15)
#define MCHP_QMSPI_STS_ACTIVE_RO BIT(16)
#define MCHP_QMSPI_STS_CD_POS 24u
#define MCHP_QMSPI_STS_CD_MASK0 0x0fu
#define MCHP_QMSPI_STS_CD_MASK 0x0f000000u
/* Buffer Count Status (RO) */
#define MCHP_QMSPI_TX_BUF_CNT_STS_POS 0u
#define MCHP_QMSPI_TX_BUF_CNT_STS_MASK 0xffffu
#define MCHP_QMSPI_RX_BUF_CNT_STS_POS 16u
#define MCHP_QMSPI_RX_BUF_CNT_STS_MASK 0xffff0000u
/* Interrupt Enable Register */
#define MCHP_QMSPI_IEN_XFR_DONE BIT(0)
#define MCHP_QMSPI_IEN_DMA_DONE BIT(1)
#define MCHP_QMSPI_IEN_TXB_ERR BIT(2)
#define MCHP_QMSPI_IEN_RXB_ERR BIT(3)
#define MCHP_QMSPI_IEN_PROG_ERR BIT(4)
#define MCHP_QMSPI_IEN_LDMA_RX_ERR BIT(5)
#define MCHP_QMSPI_IEN_LDMA_TX_ERR BIT(6)
#define MCHP_QMSPI_IEN_TXB_FULL BIT(8)
#define MCHP_QMSPI_IEN_TXB_EMPTY BIT(9)
#define MCHP_QMSPI_IEN_TXB_REQ BIT(10)
#define MCHP_QMSPI_IEN_RXB_FULL BIT(12)
#define MCHP_QMSPI_IEN_RXB_EMPTY BIT(13)
#define MCHP_QMSPI_IEN_RXB_REQ BIT(14)
/* Buffer Count Trigger (RW) */
#define MCHP_QMSPI_TX_BUF_CNT_TRIG_POS 0u
#define MCHP_QMSPI_RX_BUF_CNT_TRIG_POS 16u
/* Chip Select Timing (RW) */
#define MCHP_QMSPI_CSTM_MASK 0xff0f0f0fu
#define MCHP_QMSPI_CSTM_DFLT 0x06060406u
#define MCHP_QMSPI_DLY_CS_ON_CK_STR_POS 0u
#define MCHP_QMSPI_DLY_CS_ON_CK_STR_MASK 0x0fu
#define MCHP_QMSPI_DLY_CK_STP_CS_OFF_POS 8u
#define MCHP_QMSPI_DLY_CK_STP_CS_OFF_MASK 0x0f00u
#define MCHP_QMSPI_DLY_LST_DAT_HLD_POS 16u
#define MCHP_QMSPI_DLY_LST_DAT_HLD_MASK 0x0f0000u
#define MCHP_QMSPI_DLY_CS_OFF_CS_ON_POS 24u
#define MCHP_QMSPI_DLY_CS_OFF_CS_ON_MASK 0x0f000000u
/* Alias Control (WO) */
#define MCHP_QMSPI_ACTRL_MASK 0xffffff7fu
#define MCHP_QMSPI_ACTRL_ESTART BIT(0)
#define MCHP_QMSPI_ACTRL_CDE BIT(1)
#define MCHP_QMSPI_ACTRL_TXBW BIT(2)
#define MCHP_QMSPI_ACTRL_DLEN BIT(3)
#define MCHP_QMSPI_ACTRL_CS_POS 4
#define MCHP_QMSPI_ACTRL_CS0 0u
#define MCHP_QMSPI_ACTRL_CS1 0x10u
#define MCHP_QMSPI_ACTRL_LDIA BIT(6)
#define MCHP_QMSPI_ACTRL_DBP_POS 8
#define MCHP_QMSPI_ACTRL_DBP_0 0u
#define MCHP_QMSPI_ACTRL_DBP_1 0x100u
#define MCHP_QMSPI_ACTRL_DBP_N(n) SHLU32(((n) & 0xFu), 8)
#define MCHP_QMSPI_ACTRL_BSEL_POS 12
#define MCHP_QMSPI_ACTRL_BSEL_MSK 0xf000u
#define MCHP_QMSPI_ACTRL_DBLEN_POS 16
#define MCHP_QMSPI_ACTRL_DBLEN_MSK 0xff0000u
#define MCHP_QMSPI_ACTRL_TXB_DATA_POS 24
#define MCHP_QMSPI_ACTRL_TXB_DATA_MSK 0xff000000u
/* Mode Alternate 1 (RW) */
#define MCHP_QMSPI_MA1_MASK 0xffff0001u
#define MCHP_QMSPI_MA1_CS1_CDIV_EN BIT(0)
#define MCHP_QMSPI_MA1_CS1_CDIV_POS 16
#define MCHP_QMSPI_MA1_CS1_CDIV_MSK 0xffff0000u
/* TAPS select and TAPS Adjust registers */
#define MCHP_QMSPI_TAPS_MASK 0xffffu
#define MCHP_QMSPI_TAPS_SCK_MASK 0xffu
#define MCHP_QMSPI_TAPS_CTL_MASK 0xff00u
/* TAPS Control register */
#define MCHP_QMSPI_TCTRL_MASK 0x70107u
#define MCHP_QMSPI_TCTRL_AUTO_MODE_MASK 0x03u
#define MCHP_QMSPI_TCTRL_AM_OFF 0x00u
#define MCHP_QMSPI_TCTRL_AM_ON 0x01u
#define MCHP_QMSPI_TCTRL_AM_PERIODIC 0x02u
#define MCHP_QMSPI_TCTRL_UPDATE_EN BIT(2)
#define MCHP_QMSPI_TCTRL_UPDATE_NOW BIT(8)
#define MCHP_QMSPI_TCTRL_MULT_POS 16
#define MCHP_QMSPI_TCTRL_MULT_MSK 0x70000u
/* Local DMA RX Descriptor Enable bit map */
/* Local DMA TX Descriptor Enable bit map */
#define MCHP_QMSPI_LDMA_DESCR_EN_MASK 0xffffu
#define MCHP_QMSPI_LDMA_DESCR_EN(n) BIT((n) & 0xfu)
/* Each Local DMA channel implements 4 32-bit registers.
* Channels are identical for RX and TX
* offset 0x00: Control
* offset 0x04: memory start address
* offset 0x08: transfer byte length
* offset 0x0c: reserved read-only 0
*/
/* LDMA Channel Control register */
#define MCHP_QMSPI_LDC_MASK 0x7fu
/* enable channel */
#define MCHP_QMSPI_LDC_EN BIT(0)
/* re-enable channel upon done */
#define MCHP_QMSPI_LDC_RS_EN BIT(1)
/* on restart put memory start address back to its original value */
#define MCHP_QMSPI_LDC_RSA_EN BIT(2)
/* use channel length not length in descriptor */
#define MCHP_QMSPI_LDC_UCHL_EN BIT(3)
/* LDMA unit(access) size: 1, 2, or 4 bytes */
#define MCHP_QMSPI_LDC_ASZ_POS 4
#define MCHP_QMSPI_LDC_ASZ_MSK 0x30u
#define MCHP_QMSPI_LDC_ASZ_1 0u
#define MCHP_QMSPI_LDC_ASZ_2 0x10u
#define MCHP_QMSPI_LDC_ASZ_4 0x20u
/* LDMA increment memory start address by access size */
#define MCHP_QMSPI_LDC_INCR_EN BIT(6)
/* LDMA Channel (memory) Start address register */
#define MCHP_QMSPI_LDMS_MASK 0xffffffffu
/* LDMA Channel Length register */
#define MCHP_QMSPI_LDLEN_MASK 0xffffffffu
/** @brief QMSPI Local DMA channel registers */
struct qldma_chan {
volatile uint32_t CTRL;
volatile uint32_t MSTART;
volatile uint32_t LEN;
uint32_t RSVD1[1];
};
/** @brief QMSPI controller. Size = 368(0x170) */
struct qmspi_regs {
volatile uint32_t MODE;
volatile uint32_t CTRL;
volatile uint32_t EXE;
volatile uint32_t IFCTRL;
volatile uint32_t STS;
volatile uint32_t BCNT_STS;
volatile uint32_t IEN;
volatile uint32_t BCNT_TRIG;
volatile uint32_t TX_FIFO;
volatile uint32_t RX_FIFO;
volatile uint32_t CSTM;
uint32_t RSVD1[1];
volatile uint32_t DESCR[16];
uint32_t RSVD2[16];
volatile uint32_t ALIAS_CTRL;
uint32_t RSVD3[3];
volatile uint32_t MODE_ALT1;
uint32_t RSVD4[3];
volatile uint32_t TM_TAPS;
volatile uint32_t TM_TAPS_ADJ;
volatile uint32_t TM_TAPS_CTRL;
uint32_t RSVD5[9];
volatile uint32_t LDMA_RX_DESCR_BM;
volatile uint32_t LDMA_TX_DESCR_BM;
uint32_t RSVD6[2];
struct qldma_chan LDRX[3];
struct qldma_chan LDTX[3];
};
#endif /* #ifndef _MEC_QSPI_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MEC172X_VBAT_H
#define _MEC172X_VBAT_H
#include <stdint.h>
#include <stddef.h>
/* VBAT Registers Registers */
#define MCHP_VBAT_MEMORY_SIZE 128u
/* Offset 0x00 Power-Fail and Reset Status */
#define MCHP_VBATR_PFRS_OFS 0u
#define MCHP_VBATR_PFRS_MASK 0x7cu
#define MCHP_VBATR_PFRS_SYS_RST_POS 2u
#define MCHP_VBATR_PFRS_JTAG_POS 3u
#define MCHP_VBATR_PFRS_RESETI_POS 4u
#define MCHP_VBATR_PFRS_WDT_POS 5u
#define MCHP_VBATR_PFRS_SYSRESETREQ_POS 6u
#define MCHP_VBATR_PFRS_VBAT_RST_POS 7u
#define MCHP_VBATR_PFRS_SYS_RST BIT(2)
#define MCHP_VBATR_PFRS_JTAG BIT(3)
#define MCHP_VBATR_PFRS_RESETI BIT(4)
#define MCHP_VBATR_PFRS_WDT BIT(5)
#define MCHP_VBATR_PFRS_SYSRESETREQ BIT(6)
#define MCHP_VBATR_PFRS_VBAT_RST BIT(7)
/* Offset 0x08 32K Clock Source register */
#define MCHP_VBATR_CS_OFS 0x08u
#define MCHP_VBATR_CS_MASK 0x71f1u
#define MCHP_VBATR_CS_SO_EN_POS 0
#define MCHP_VBATR_CS_XTAL_EN_POS 8
#define MCHP_VBATR_CS_XTAL_SEL_POS 9
#define MCHP_VBATR_CS_XTAL_DHC_POS 10
#define MCHP_VBATR_CS_XTAL_CNTR_POS 11
#define MCHP_VBATR_CS_PCS_POS 16
#define MCHP_VBATR_CS_DI32_VTR_OFF_POS 18
/* Enable and start internal 32KHz Silicon Oscillator */
#define MCHP_VBATR_CS_SO_EN BIT(0)
/* Enable and start the external crystal */
#define MCHP_VBATR_CS_XTAL_EN BIT(8)
/* single ended crystal on XTAL2 instead of parallel across XTAL1 and XTAL2 */
#define MCHP_VBATR_CS_XTAL_SE BIT(9)
/* disable XTAL high startup current */
#define MCHP_VBATR_CS_XTAL_DHC BIT(10)
/* crystal amplifier gain control */
#define MCHP_VBATR_CS_XTAL_CNTR_MSK 0x1800u
#define MCHP_VBATR_CS_XTAL_CNTR_DG 0x0800u
#define MCHP_VBATR_CS_XTAL_CNTR_RG 0x1000u
#define MCHP_VBATR_CS_XTAL_CNTR_MG 0x1800u
/* Select source of peripheral 32KHz clock */
#define MCHP_VBATR_CS_PCS_POS 16
#define MCHP_VBATR_CS_PCS_MSK 0x30000u
#define MCHP_VBATR_CS_PCR_VTR_VBAT_SO_VAL 0
#define MCHP_VBATR_CS_PCS_VTR_VBAT_XTAL_VAL 1
#define MCHP_VBATR_CS_PCS_VTR_PIN_SO_VAL 2
#define MCHP_VBATR_CS_PCS_VTR_PIN_XTAL_VAL 3
/* 32K silicon OSC when chip powered by VBAT or VTR */
#define MCHP_VBATR_CS_PCS_VTR_VBAT_SO 0u
/* 32K external crystal when chip powered by VBAT or VTR */
#define MCHP_VBATR_CS_PCS_VTR_VBAT_XTAL 0x10000u
/* 32K input pin on VTR. Switch to Silicon OSC on VBAT */
#define MCHP_VBATR_CS_PCS_VTR_PIN_SO 0x20000u
/* 32K input pin on VTR. Switch to crystal on VBAT */
#define MCHP_VBATR_CS_PCS_VTR_PIN_XTAL 0x30000u
/* Disable internal 32K VBAT clock source when VTR is off */
#define MCHP_VBATR_CS_DI32_VTR_OFF_POS 18
#define MCHP_VBATR_CS_DI32_VTR_OFF BIT(18)
/*
* Monotonic Counter least significant word (32-bit), read-only.
* Increments by one on read.
*/
#define MCHP_VBATR_MCNT_LSW_OFS 0x20u
/* Monotonic Counter most significant word (32-bit). Read-Write */
#define MCHP_VBATR_MCNT_MSW_OFS 0x24u
/* ROM Feature register */
#define MCHP_VBATR_ROM_FEAT_OFS 0x28u
/* Embedded Reset Debounce Enable register */
#define MCHP_VBATR_EMBRD_EN_OFS 0x34u
#define MCHP_VBATR_EMBRD_EN BIT(0)
/** @brief VBAT Register Bank (VBATR) */
struct vbatr_regs {
volatile uint32_t PFRS;
uint32_t RSVD1[1];
volatile uint32_t CLK32_SRC;
uint32_t RSVD2[5];
volatile uint32_t MCNT_LO;
volatile uint32_t MCNT_HI;
uint32_t RSVD3[3];
volatile uint32_t EMBRD_EN;
};
#endif /* #ifndef _MEC172X_VBAT_H */

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/*
* Copyright (c) 2021 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/sys/__assert.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <cmsis_core.h>
/* Enable SWD and ETM debug interface and pins.
* NOTE: ETM TRACE pins exposed on MEC172x EVB J30 12,14,16,18,20.
*/
static void configure_debug_interface(void)
{
struct ecs_regs *ecs = (struct ecs_regs *)(DT_REG_ADDR(DT_NODELABEL(ecs)));
#ifdef CONFIG_SOC_MEC172X_DEBUG_DISABLED
ecs->ETM_CTRL = 0;
ecs->DEBUG_CTRL = 0;
#elif defined(CONFIG_SOC_MEC172X_DEBUG_WITHOUT_TRACING)
ecs->ETM_CTRL = 0;
ecs->DEBUG_CTRL = (MCHP_ECS_DCTRL_DBG_EN | MCHP_ECS_DCTRL_MODE_SWD);
#elif defined(CONFIG_SOC_MEC172X_DEBUG_AND_TRACING)
#if defined(CONFIG_SOC_MEC172X_DEBUG_AND_ETM_TRACING)
ecs->ETM_CTRL = 1u;
ecs->DEBUG_CTRL = (MCHP_ECS_DCTRL_DBG_EN | MCHP_ECS_DCTRL_MODE_SWD);
#elif defined(CONFIG_SOC_MEC172X_DEBUG_AND_SWV_TRACING)
ecs->ETM_CTRL = 0;
ecs->DEBUG_CTRL = (MCHP_ECS_DCTRL_DBG_EN | MCHP_ECS_DCTRL_MODE_SWD_SWV);
#endif /* CONFIG_SOC_MEC172X_DEBUG_AND_ETM_TRACING */
#endif /* CONFIG_SOC_MEC172X_DEBUG_DISABLED */
}
static int soc_init(void)
{
configure_debug_interface();
return 0;
}
SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

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/*
* Copyright (c) 2019 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __MEC_SOC_H
#define __MEC_SOC_H
#ifndef _ASMLANGUAGE
/*
* MEC172x includes the ARM single precision FPU and the ARM MPU with
* eight regions. Zephyr has an in-tree CMSIS header located in the arch
* include hierarchy that includes the correct ARM CMSIS core_xxx header
* from hal_cmsis based on the k-config CPU selection.
* The Zephyr in-tree header does not provide all the symbols ARM CMSIS
* requires. Zephyr does not define CMSIS FPU present and defaults CMSIS
* MPU present to 0. We define these two symbols here based on our k-config
* selections. NOTE: Zephyr in-tree CMSIS defines the Cortex-M4 hardware
* revision to 0. At this time ARM CMSIS does not appear to use the hardware
* revision in any macros.
*/
#define __FPU_PRESENT CONFIG_CPU_HAS_FPU
#define __MPU_PRESENT CONFIG_CPU_HAS_ARM_MPU
#define __CM4_REV 0x0201 /*!< Core Revision r2p1 */
#define __VTOR_PRESENT 1 /*!< Set to 1 if VTOR is present */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< 0 use default SysTick HW */
#define __FPU_DP 0 /*!< Set to 1 if FPU is double precision */
#define __ICACHE_PRESENT 0 /*!< Set to 1 if I-Cache is present */
#define __DCACHE_PRESENT 0 /*!< Set to 1 if D-Cache is present */
#define __DTCM_PRESENT 0 /*!< Set to 1 if DTCM is present */
/** @brief ARM Cortex-M4 NVIC Interrupt Numbers
* CM4 NVIC implements 16 internal interrupt sources. CMSIS macros use
* negative numbers [-15, -1]. Lower numerical value indicates higher
* priority.
* -15 = Reset Vector invoked on POR or any CPU reset.
* -14 = NMI
* -13 = Hard Fault. At POR or CPU reset all faults map to Hard Fault.
* -12 = Memory Management Fault. If enabled Hard Faults caused by access
* violations, no address match, or MPU mismatch.
* -11 = Bus Fault. If enabled pre-fetch, AHB access faults.
* -10 = Usage Fault. If enabled Undefined instructions, illegal state
* transition (Thumb -> ARM mode), unaligned, etc.
* -9 through -6 are not implemented (reserved).
* -5 System call via SVC instruction.
* -4 Debug Monitor.
* -3 not implemented (reserved).
* -2 PendSV for system service.
* -1 SysTick NVIC system timer.
* Numbers >= 0 are external peripheral interrupts.
*/
typedef enum {
/* ========== ARM Cortex-M4 Specific Interrupt Numbers ============ */
Reset_IRQn = -15, /*!< POR/CPU Reset Vector */
NonMaskableInt_IRQn = -14, /*!< NMI */
HardFault_IRQn = -13, /*!< Hard Faults */
MemoryManagement_IRQn = -12, /*!< Memory Management faults */
BusFault_IRQn = -11, /*!< Bus Access faults */
UsageFault_IRQn = -10, /*!< Usage/instruction faults */
SVCall_IRQn = -5, /*!< SVC */
DebugMonitor_IRQn = -4, /*!< Debug Monitor */
PendSV_IRQn = -2, /*!< PendSV */
SysTick_IRQn = -1, /*!< SysTick */
/* ============== MEC172x Specific Interrupt Numbers ============ */
GIRQ08_IRQn = 0, /*!< GPIO 0140 - 0176 */
GIRQ09_IRQn = 1, /*!< GPIO 0100 - 0136 */
GIRQ10_IRQn = 2, /*!< GPIO 0040 - 0076 */
GIRQ11_IRQn = 3, /*!< GPIO 0000 - 0036 */
GIRQ12_IRQn = 4, /*!< GPIO 0200 - 0236 */
GIRQ13_IRQn = 5, /*!< SMBus Aggregated */
GIRQ14_IRQn = 6, /*!< DMA Aggregated */
GIRQ15_IRQn = 7,
GIRQ16_IRQn = 8,
GIRQ17_IRQn = 9,
GIRQ18_IRQn = 10,
GIRQ19_IRQn = 11,
GIRQ20_IRQn = 12,
GIRQ21_IRQn = 13,
/* GIRQ22(peripheral clock wake) is not connected to NVIC */
GIRQ23_IRQn = 14,
GIRQ24_IRQn = 15,
GIRQ25_IRQn = 16,
GIRQ26_IRQn = 17, /*!< GPIO 0240 - 0276 */
/* Reserved 18-19 */
/* GIRQ's 8 - 12, 24 - 26 no direct connections */
I2C_SMB_0_IRQn = 20, /*!< GIRQ13 b[0] */
I2C_SMB_1_IRQn = 21, /*!< GIRQ13 b[1] */
I2C_SMB_2_IRQn = 22, /*!< GIRQ13 b[2] */
I2C_SMB_3_IRQn = 23, /*!< GIRQ13 b[3] */
DMA0_IRQn = 24, /*!< GIRQ14 b[0] */
DMA1_IRQn = 25, /*!< GIRQ14 b[1] */
DMA2_IRQn = 26, /*!< GIRQ14 b[2] */
DMA3_IRQn = 27, /*!< GIRQ14 b[3] */
DMA4_IRQn = 28, /*!< GIRQ14 b[4] */
DMA5_IRQn = 29, /*!< GIRQ14 b[5] */
DMA6_IRQn = 30, /*!< GIRQ14 b[6] */
DMA7_IRQn = 31, /*!< GIRQ14 b[7] */
DMA8_IRQn = 32, /*!< GIRQ14 b[8] */
DMA9_IRQn = 33, /*!< GIRQ14 b[9] */
DMA10_IRQn = 34, /*!< GIRQ14 b[10] */
DMA11_IRQn = 35, /*!< GIRQ14 b[11] */
DMA12_IRQn = 36, /*!< GIRQ14 b[12] */
DMA13_IRQn = 37, /*!< GIRQ14 b[13] */
DMA14_IRQn = 38, /*!< GIRQ14 b[14] */
DMA15_IRQn = 39, /*!< GIRQ14 b[15] */
UART0_IRQn = 40, /*!< GIRQ15 b[0] */
UART1_IRQn = 41, /*!< GIRQ15 b[1] */
EMI0_IRQn = 42, /*!< GIRQ15 b[2] */
EMI1_IRQn = 43, /*!< GIRQ15 b[3] */
EMI2_IRQn = 44, /*!< GIRQ15 b[4] */
ACPI_EC0_IBF_IRQn = 45, /*!< GIRQ15 b[5] */
ACPI_EC0_OBE_IRQn = 46, /*!< GIRQ15 b[6] */
ACPI_EC1_IBF_IRQn = 47, /*!< GIRQ15 b[7] */
ACPI_EC1_OBE_IRQn = 48, /*!< GIRQ15 b[8] */
ACPI_EC2_IBF_IRQn = 49, /*!< GIRQ15 b[9] */
ACPI_EC2_OBE_IRQn = 50, /*!< GIRQ15 b[10] */
ACPI_EC3_IBF_IRQn = 51, /*!< GIRQ15 b[11] */
ACPI_EC3_OBE_IRQn = 52, /*!< GIRQ15 b[12] */
ACPI_EC4_IBF_IRQn = 53, /*!< GIRQ15 b[13] */
ACPI_EC4_OBE_IRQn = 54, /*!< GIRQ15 b[14] */
ACPI_PM1_CTL_IRQn = 55, /*!< GIRQ15 b[15] */
ACPI_PM1_EN_IRQn = 56, /*!< GIRQ15 b[16] */
ACPI_PM1_STS_IRQn = 57, /*!< GIRQ15 b[17] */
KBC_OBE_IRQn = 58, /*!< GIRQ15 b[18] */
KBC_IBF_IRQn = 59, /*!< GIRQ15 b[19] */
MBOX_IRQn = 60, /*!< GIRQ15 b[20] */
/* reserved 61 */
P80BD_0_IRQn = 62, /*!< GIRQ15 b[22] */
/* reserved 63-64 */
PKE_IRQn = 65, /*!< GIRQ16 b[0] */
/* reserved 66 */
RNG_IRQn = 67, /*!< GIRQ16 b[2] */
AESH_IRQn = 68, /*!< GIRQ16 b[3] */
/* reserved 69 */
PECI_IRQn = 70, /*!< GIRQ17 b[0] */
TACH_0_IRQn = 71, /*!< GIRQ17 b[1] */
TACH_1_IRQn = 72, /*!< GIRQ17 b[2] */
TACH_2_IRQn = 73, /*!< GIRQ17 b[3] */
RPMFAN_0_FAIL_IRQn = 74, /*!< GIRQ17 b[20] */
RPMFAN_0_STALL_IRQn = 75, /*!< GIRQ17 b[21] */
RPMFAN_1_FAIL_IRQn = 76, /*!< GIRQ17 b[22] */
RPMFAN_1_STALL_IRQn = 77, /*!< GIRQ17 b[23] */
ADC_SNGL_IRQn = 78, /*!< GIRQ17 b[8] */
ADC_RPT_IRQn = 79, /*!< GIRQ17 b[9] */
RCID_0_IRQn = 80, /*!< GIRQ17 b[10] */
RCID_1_IRQn = 81, /*!< GIRQ17 b[11] */
RCID_2_IRQn = 82, /*!< GIRQ17 b[12] */
LED_0_IRQn = 83, /*!< GIRQ17 b[13] */
LED_1_IRQn = 84, /*!< GIRQ17 b[14] */
LED_2_IRQn = 85, /*!< GIRQ17 b[15] */
LED_3_IRQn = 86, /*!< GIRQ17 b[16] */
PHOT_IRQn = 87, /*!< GIRQ17 b[17] */
/* reserved 88-89 */
SPIP_0_IRQn = 90, /*!< GIRQ18 b[0] */
QMSPI_0_IRQn = 91, /*!< GIRQ18 b[1] */
GPSPI_0_TXBE_IRQn = 92, /*!< GIRQ18 b[2] */
GPSPI_0_RXBF_IRQn = 93, /*!< GIRQ18 b[3] */
GPSPI_1_TXBE_IRQn = 94, /*!< GIRQ18 b[4] */
GPSPI_1_RXBF_IRQn = 95, /*!< GIRQ18 b[5] */
BCL_0_ERR_IRQn = 96, /*!< GIRQ18 b[7] */
BCL_0_BCLR_IRQn = 97, /*!< GIRQ18 b[6] */
/* reserved 98-99 */
PS2_0_ACT_IRQn = 100, /*!< GIRQ18 b[10] */
/* reserved 101-102 */
ESPI_PC_IRQn = 103, /*!< GIRQ19 b[0] */
ESPI_BM1_IRQn = 104, /*!< GIRQ19 b[1] */
ESPI_BM2_IRQn = 105, /*!< GIRQ19 b[2] */
ESPI_LTR_IRQn = 106, /*!< GIRQ19 b[3] */
ESPI_OOB_UP_IRQn = 107, /*!< GIRQ19 b[4] */
ESPI_OOB_DN_IRQn = 108, /*!< GIRQ19 b[5] */
ESPI_FLASH_IRQn = 109, /*!< GIRQ19 b[6] */
ESPI_RESET_IRQn = 110, /*!< GIRQ19 b[7] */
RTMR_IRQn = 111, /*!< GIRQ23 b[10] */
HTMR_0_IRQn = 112, /*!< GIRQ23 b[16] */
HTMR_1_IRQn = 113, /*!< GIRQ23 b[17] */
WK_IRQn = 114, /*!< GIRQ21 b[3] */
WKSUB_IRQn = 115, /*!< GIRQ21 b[4] */
WKSEC_IRQn = 116, /*!< GIRQ21 b[5] */
WKSUBSEC_IRQn = 117, /*!< GIRQ21 b[6] */
WKSYSPWR_IRQn = 118, /*!< GIRQ21 b[7] */
RTC_IRQn = 119, /*!< GIRQ21 b[8] */
RTC_ALARM_IRQn = 120, /*!< GIRQ21 b[9] */
VCI_OVRD_IN_IRQn = 121, /*!< GIRQ21 b[10] */
VCI_IN0_IRQn = 122, /*!< GIRQ21 b[11] */
VCI_IN1_IRQn = 123, /*!< GIRQ21 b[12] */
VCI_IN2_IRQn = 124, /*!< GIRQ21 b[13] */
VCI_IN3_IRQn = 125, /*!< GIRQ21 b[14] */
VCI_IN4_IRQn = 126, /*!< GIRQ21 b[15] */
/* reserved 127-128 */
PS2_0A_WAKE_IRQn = 129, /*!< GIRQ21 b[18] */
PS2_0B_WAKE_IRQn = 130, /*!< GIRQ21 b[19] */
/* reserved 131-134 */
KEYSCAN_IRQn = 135, /*!< GIRQ21 b[25] */
B16TMR_0_IRQn = 136, /*!< GIRQ23 b[0] */
B16TMR_1_IRQn = 137, /*!< GIRQ23 b[1] */
B16TMR_2_IRQn = 138, /*!< GIRQ23 b[2] */
B16TMR_3_IRQn = 139, /*!< GIRQ23 b[3] */
B32TMR_0_IRQn = 140, /*!< GIRQ23 b[4] */
B32TMR_1_IRQn = 141, /*!< GIRQ23 b[5] */
CTMR_0_IRQn = 142, /*!< GIRQ23 b[6] */
CTMR_1_IRQn = 143, /*!< GIRQ23 b[7] */
CTMR_2_IRQn = 144, /*!< GIRQ23 b[8] */
CTMR_3_IRQn = 145, /*!< GIRQ23 b[9] */
CCT_IRQn = 146, /*!< GIRQ18 b[20] */
CCT_CAP0_IRQn = 147, /*!< GIRQ18 b[21] */
CCT_CAP1_IRQn = 148, /*!< GIRQ18 b[22] */
CCT_CAP2_IRQn = 149, /*!< GIRQ18 b[23] */
CCT_CAP3_IRQn = 150, /*!< GIRQ18 b[24] */
CCT_CAP4_IRQn = 151, /*!< GIRQ18 b[25] */
CCT_CAP5_IRQn = 152, /*!< GIRQ18 b[26] */
CCT_CMP0_IRQn = 153, /*!< GIRQ18 b[27] */
CCT_CMP1_IRQn = 154, /*!< GIRQ18 b[28] */
EEPROMC_IRQn = 155, /*!< GIRQ18 b[13] */
ESPI_VWIRE_IRQn = 156, /*!< GIRQ19 b[8] */
/* reserved 157 */
I2C_SMB_4_IRQn = 158, /*!< GIRQ13 b[4] */
TACH_3_IRQn = 159, /*!< GIRQ17 b[4] */
/* reserved 160-165 */
SAF_DONE_IRQn = 166, /*!< GIRQ19 b[9] */
SAF_ERR_IRQn = 167, /*!< GIRQ19 b[10] */
/* reserved 168 */
SAF_CACHE_IRQn = 169, /*!< GIRQ19 b[11] */
/* reserved 170 */
WDT_0_IRQn = 171, /*!< GIRQ21 b[2] */
GLUE_IRQn = 172, /*!< GIRQ21 b[26] */
OTP_RDY_IRQn = 173, /*!< GIRQ20 b[3] */
CLK32K_MON_IRQn = 174, /*!< GIRQ20 b[9] */
ACPI_EC0_IRQn = 175, /* ACPI EC OBE and IBF combined into one */
ACPI_EC1_IRQn = 176, /* No GIRQ connection. Status in ACPI blocks */
ACPI_EC2_IRQn = 177, /* Code uses level bits and NVIC bits */
ACPI_EC3_IRQn = 178,
ACPI_EC4_IRQn = 179,
ACPI_PM1_IRQn = 180,
MAX_IRQn
} IRQn_Type;
#include <core_cm4.h>
#include <zephyr/sys/util.h>
/* chip specific register defines */
#include "reg/mec172x_defs.h"
#include "reg/mec172x_ecia.h"
#include "reg/mec172x_ecs.h"
#include "reg/mec172x_espi_iom.h"
#include "reg/mec172x_espi_saf.h"
#include "reg/mec172x_espi_vw.h"
#include "reg/mec172x_gpio.h"
#include "reg/mec172x_i2c_smb.h"
#include "reg/mec172x_p80bd.h"
#include "reg/mec172x_pcr.h"
#include "reg/mec172x_qspi.h"
#include "reg/mec172x_vbat.h"
#include "reg/mec172x_emi.h"
/* common peripheral register defines */
#include "../common/reg/mec_acpi_ec.h"
#include "../common/reg/mec_adc.h"
#include "../common/reg/mec_global_cfg.h"
#include "../common/reg/mec_kbc.h"
#include "../common/reg/mec_keyscan.h"
#include "../common/reg/mec_peci.h"
#include "../common/reg/mec_ps2.h"
#include "../common/reg/mec_pwm.h"
#include "../common/reg/mec_tach.h"
#include "../common/reg/mec_tfdp.h"
#include "../common/reg/mec_timers.h"
#include "../common/reg/mec_uart.h"
#include "../common/reg/mec_vci.h"
#include "../common/reg/mec_wdt.h"
#include "../common/reg/mec_gpio.h"
/* common SoC API */
#include "../common/soc_dt.h"
#include "../common/soc_gpio.h"
#include "../common/soc_pcr.h"
#include "../common/soc_pins.h"
#include "../common/soc_espi_channels.h"
#include "../common/soc_i2c.h"
/* MEC172x SAF V2 */
#include "soc_espi_saf_v2.h"
#endif
#endif

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/*
* Copyright (c) 2020 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file Header containing definitions for MCHP eSPI SAF
*/
#ifndef _SOC_ESPI_SAF_H_
#define _SOC_ESPI_SAF_H_
#include <stdint.h>
#include <zephyr/sys/util.h>
#define MCHP_SAF_MAX_FLASH_DEVICES 2U
/*
* SAF hardware state machine timings
* poll timeout is in 32KHz clock periods
* poll interval is in AHB clock(48MHz) units.
* suspend resume interval is in 32KHz clock periods.
* consecutive read timeout is in AHB clock periods.
* suspend check delay is in AHB clock(48MHz) periods.
*/
#define MCHP_SAF_FLASH_POLL_TIMEOUT 0x28000u
#define MCHP_SAF_FLASH_POLL_INTERVAL 0u
#define MCHP_SAF_FLASH_SUS_RSM_INTERVAL 8u
#define MCHP_SAF_FLASH_CONSEC_READ_TIMEOUT 2u
#define MCHP_SAF_FLASH_SUS_CHK_DELAY 0u
/* Default SAF Map of eSPI TAG numbers to master numbers */
#define MCHP_SAF_TAG_MAP0_DFLT 0x23221100u
#define MCHP_SAF_TAG_MAP1_DFLT 0x77677767u
#define MCHP_SAF_TAG_MAP2_DFLT 0x00000005u
/*
* Default QMSPI clock divider and chip select timing.
* QMSPI master clock is either 96 or 48 MHz depending upon
* Boot-ROM OTP configuration.
*/
#define MCHP_SAF_QMSPI_CLK_DIV 4u
/* SAF V2 implements dynamically changing the QMSPI clock
* divider for SPI read vs all other SPI commands.
*/
#define MCHP_SAF_CS_CLK_DIV(read, other) \
(((uint32_t)(read) & 0xffffu) | (((uint32_t)(other) & 0xffffu) << 16))
#define MCHP_SAF_CS0_CLK_DIV MCHP_SAF_CS_CLK_DIV(4, 4)
#define MCHP_SAF_CS1_CLK_DIV MCHP_SAF_CS_CLK_DIV(4, 4)
#define MCHP_SAF_QMSPI_CS_TIMING 0x03000101u
/* SAF QMSPI programming */
#define MCHP_SAF_QMSPI_NUM_FLASH_DESCR 6u
#define MCHP_SAF_QMSPI_CS0_START_DESCR 0u
#define MCHP_SAF_QMSPI_CS1_START_DESCR \
(MCHP_SAF_QMSPI_CS0_START_DESCR + MCHP_SAF_QMSPI_NUM_FLASH_DESCR)
/* SAF engine requires start indices of descriptor chains */
#define MCHP_SAF_CM_EXIT_START_DESCR 12u
#define MCHP_SAF_CM_EXIT_LAST_DESCR 13u
#define MCHP_SAF_POLL_STS_START_DESCR 14u
#define MCHP_SAF_POLL_STS_END_DESCR 15u
#define MCHP_SAF_NUM_GENERIC_DESCR 4u
/* QMSPI descriptors 12-15 for all SPI flash devices */
/* QMSPI descriptors 12-13 are exit continuous mode */
#define MCHP_SAF_EXIT_CM_DESCR12 \
(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_ONES | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | \
MCHP_QMSPI_C_NEXT_DESCR(13) | \
MCHP_QMSPI_C_XFR_NUNITS(1))
#define MCHP_SAF_EXIT_CM_DESCR13 \
(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_EN | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | \
MCHP_QMSPI_C_NEXT_DESCR(0) | \
MCHP_QMSPI_C_XFR_NUNITS(9) | \
MCHP_QMSPI_C_DESCR_LAST)
#define MCHP_SAF_EXIT_CM_DUAL_DESCR12 \
(MCHP_QMSPI_C_IFM_2X | MCHP_QMSPI_C_TX_ONES | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | \
MCHP_QMSPI_C_NEXT_DESCR(13) | \
MCHP_QMSPI_C_XFR_NUNITS(1))
#define MCHP_SAF_EXIT_CM_DUAL_DESCR13 \
(MCHP_QMSPI_C_IFM_2X | MCHP_QMSPI_C_TX_DIS | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_EN | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | \
MCHP_QMSPI_C_NEXT_DESCR(0) | \
MCHP_QMSPI_C_XFR_NUNITS(5) | \
MCHP_QMSPI_C_DESCR_LAST)
/*
* QMSPI descriptors 14-15 are poll 16-bit flash status
* Transmit one byte opcode at 1X (no DMA).
* Receive two bytes at 1X (no DMA).
*/
#define MCHP_SAF_POLL_DESCR14 \
(MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DATA | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | \
MCHP_QMSPI_C_NEXT_DESCR(15) | \
MCHP_QMSPI_C_XFR_NUNITS(1))
#define MCHP_SAF_POLL_DESCR15 \
(MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DIS | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_EN | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | \
MCHP_QMSPI_C_NEXT_DESCR(0) | \
MCHP_QMSPI_C_XFR_NUNITS(2) | \
MCHP_QMSPI_C_DESCR_LAST)
/* SAF Pre-fetch optimization mode */
#define MCHP_SAF_PREFETCH_MODE MCHP_SAF_FL_CFG_MISC_PFOE_DFLT
#define MCHP_SAF_CFG_MISC_PREFETCH_EXPEDITED 0x03U
/*
* SAF Opcode 32-bit register value.
* Each byte contain a SPI flash 8-bit opcode.
* NOTE1: opcode value of 0 = flash does not support this operation
* NOTE2:
* SAF Opcode A
* op0 = SPI flash write-enable opcode
* op1 = SPI flash program/erase suspend opcode
* op2 = SPI flash program/erase resume opcode
* op3 = SPI flash read STATUS1 opcode
* SAF Opcode B
* op0 = SPI flash erase 4KB sector opcode
* op1 = SPI flash erase 32KB sector opcode
* op2 = SPI flash erase 64KB sector opcode
* op3 = SPI flash page program opcode
* SAF Opcode C
* op0 = SPI flash read 1-4-4 continuous mode opcode
* op1 = SPI flash op0 mode byte value for non-continuous mode
* op2 = SPI flash op0 mode byte value for continuous mode
* op3 = SPI flash read STATUS2 opcode
*/
#define MCHP_SAF_OPCODE_REG_VAL(op0, op1, op2, op3) \
(((uint32_t)(op0)&0xffU) | (((uint32_t)(op1)&0xffU) << 8) | \
(((uint32_t)(op2)&0xffU) << 16) | (((uint32_t)(op3)&0xffU) << 24))
/*
* SAF Flash Config CS0/CS1 QMSPI descriptor indices register value
* e = First QMSPI descriptor index for enter continuous mode chain
* r = First QMSPI descriptor index for continuous mode read chain
* s = Index of QMSPI descriptor in continuous mode read chain that
* contains the data length field.
*/
#define MCHP_SAF_CS_CFG_DESCR_IDX_REG_VAL(e, r, s) \
(((uint32_t)(e)&0xfU) | (((uint32_t)(r)&0xfU) << 8) | \
(((uint32_t)(s)&0xfU) << 12))
/* W25Q128 SPI flash device connected size in bytes */
#define MCHP_W25Q128_SIZE (16U * 1024U * 1024U)
/*
* Six QMSPI descriptors describe SPI flash opcode protocols.
* Example: W25Q128
*/
/* Continuous mode read: transmit-quad 24-bit address and mode byte */
#define MCHP_W25Q128_CM_RD_D0 \
(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DATA | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(4))
/* Continuous mode read: transmit-quad 4 dummy clocks with I/O tri-stated */
#define MCHP_W25Q128_CM_RD_D1 \
(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(2))
/* Continuous mode read: read N bytes */
#define MCHP_W25Q128_CM_RD_D2 \
(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_EN | \
MCHP_QMSPI_C_RX_LDMA_CH0 | MCHP_QMSPI_C_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | \
MCHP_QMSPI_C_XFR_NUNITS(0) | MCHP_QMSPI_C_DESCR_LAST)
/* Continuous Mode: 24-bit address plus mode byte */
#define MCHP_W25Q128_CM_RD_DUAL_D0 \
(MCHP_QMSPI_C_IFM_2X | MCHP_QMSPI_C_TX_DATA | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(4))
/* Continuous mode read: read N bytes */
#define MCHP_W25Q128_CM_RD_DUAL_D1 \
(MCHP_QMSPI_C_IFM_2X | MCHP_QMSPI_C_TX_DIS | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_EN | \
MCHP_QMSPI_C_RX_LDMA_CH0 | MCHP_QMSPI_C_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | \
MCHP_QMSPI_C_XFR_NUNITS(0) | MCHP_QMSPI_C_DESCR_LAST)
/* Continuous mode Dual D2. Not used */
#define MCHP_W25Q128_CM_RD_DUAL_D2 0
/* Enter Continuous mode: transmit-single CM quad read opcode */
#define MCHP_W25Q128_ENTER_CM_D0 \
(MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DATA | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(1))
/* Enter Continuous mode: transmit-quad 24-bit address and mode byte */
#define MCHP_W25Q128_ENTER_CM_D1 \
(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DATA | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(4))
/* Enter Continuous mode: read-quad 3 bytes */
#define MCHP_W25Q128_ENTER_CM_D2 \
(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | \
MCHP_QMSPI_C_XFR_NUNITS(3) | MCHP_QMSPI_C_DESCR_LAST)
/* Enter Continuous mode: transmit-single CM dual read opcode */
#define MCHP_W25Q128_ENTER_CM_DUAL_D0 \
(MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DATA | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(1))
/* Enter Continuous mode: transmit-dual 24-bit address and mode byte */
#define MCHP_W25Q128_ENTER_CM_DUAL_D1 \
(MCHP_QMSPI_C_IFM_2X | MCHP_QMSPI_C_TX_DATA | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(4))
/* Enter Continuous mode: read-dual 3 bytes */
#define MCHP_W25Q128_ENTER_CM_DUAL_D2 \
(MCHP_QMSPI_C_IFM_2X | MCHP_QMSPI_C_TX_DIS | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | \
MCHP_QMSPI_C_XFR_NUNITS(3) | MCHP_QMSPI_C_DESCR_LAST)
#define MCHP_W25Q128_OPA MCHP_SAF_OPCODE_REG_VAL(0x06u, 0x75u, 0x7au, 0x05u)
#define MCHP_W25Q128_OPB MCHP_SAF_OPCODE_REG_VAL(0x20u, 0x52u, 0xd8u, 0x02u)
#define MCHP_W25Q128_OPC MCHP_SAF_OPCODE_REG_VAL(0xebu, 0xffu, 0xa5u, 0x35u)
#define MCHP_W25Q128_OPD MCHP_SAF_OPCODE_REG_VAL(0xb9u, 0xabu, 0u, 0u)
#define MCHP_W25Q128_DUAL_OPC MCHP_SAF_OPCODE_REG_VAL(0xbbu, 0xffu, 0xa5u, 0x35u)
/* W25Q128 STATUS2 bit[7] == 0 part is NOT in suspend state */
#define MCHP_W25Q128_POLL2_MASK 0xff7fU
/*
* SAF Flash Continuous Mode Prefix register value
* b[7:0] = continuous mode prefix opcode
* b[15:8] = continuous mode prefix opcode data
* Some SPI flash devices require a prefix command before
* they will enter continuous mode.
* A zero value means the SPI flash does not require a prefix
* command.
*/
#define MCHP_W25Q128_CONT_MODE_PREFIX_VAL 0u
/* SAF Flash power down/up activity timeout in 32KHz units */
#define MCHP_W25Q128_PD_TIMEOUT_32K 0x10u
/* SAF Flash minimum time between power up and down events in
* 48MHz time units (~20 ns)
*/
#define MCHP_W25Q128_PD_EVENT_INTERVAL 0x4ffu
#define MCHP_SAF_PD_EVENT_INTERVAL_25US 1279u
#define MCHP_W25Q128_FLAGS 0U
/* W25Q256 SPI flash device connected size in bytes */
#define MCHP_W25Q256_SIZE (32U * 1024U * 1024U)
/*
* Six QMSPI descriptors describe SPI flash opcode protocols.
* W25Q256 device.
*/
/* Continuous Mode Read: Transmit-quad opcode plus 32-bit address */
#define MCHP_W25Q256_CM_RD_D0 \
(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DATA | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(5))
#define MCHP_W25Q256_CM_RD_D1 \
(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(2))
#define MCHP_W25Q256_CM_RD_D2 \
(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_EN | \
MCHP_QMSPI_C_RX_LDMA_CH0 | MCHP_QMSPI_C_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(0) | \
MCHP_QMSPI_C_DESCR_LAST)
/* Enter Continuous mode: transmit-single CM quad read opcode */
#define MCHP_W25Q256_ENTER_CM_D0 \
(MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DATA | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(1))
/* Enter Continuous mode: transmit-quad 32-bit address and mode byte */
#define MCHP_W25Q256_ENTER_CM_D1 \
(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DATA | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(5))
/* Enter Continuous mode: read-quad 3 bytes */
#define MCHP_W25Q256_ENTER_CM_D2 \
(MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \
MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \
MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_CLOSE | \
MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(3) | \
MCHP_QMSPI_C_DESCR_LAST)
#define MCHP_W25Q256_OPA MCHP_SAF_OPCODE_REG_VAL(0x06U, 0x75U, 0x7aU, 0x05U)
#define MCHP_W25Q256_OPB MCHP_SAF_OPCODE_REG_VAL(0x20U, 0x52U, 0xd8U, 0x02U)
#define MCHP_W25Q256_OPC MCHP_SAF_OPCODE_REG_VAL(0xebU, 0xffU, 0xa5U, 0x35U)
#define MCHP_W25Q256_OPD MCHP_SAF_OPCODE_REG_VAL(0xb9U, 0xabU, 0U, 0U)
#define MCHP_W25Q256_POLL2_MASK 0xff7fU
#define MCHP_W25Q256_CONT_MODE_PREFIX_VAL 0U
#define MCHP_W25Q256_FLAGS 0U
/* SAF Flash Config CS0 QMSPI descriptor indices */
#define MCHP_CS0_CFG_DESCR_IDX_REG_VAL \
MCHP_SAF_CS_CFG_DESCR_IDX_REG_VAL(3U, 0U, 2U)
#define MCHP_CS0_CFG_DESCR_IDX_REG_VAL_DUAL \
MCHP_SAF_CS_CFG_DESCR_IDX_REG_VAL(3U, 0U, 1U)
/* SAF Flash Config CS1 QMSPI descriptor indices */
#define MCHP_CS1_CFG_DESCR_IDX_REG_VAL \
MCHP_SAF_CS_CFG_DESCR_IDX_REG_VAL(9U, 6U, 8U)
#define MCHP_CS1_CFG_DESCR_IDX_REG_VAL_DUAL \
MCHP_SAF_CS_CFG_DESCR_IDX_REG_VAL(9U, 6U, 7U)
#define MCHP_SAF_HW_CFG_FLAG_FREQ 0x01U
#define MCHP_SAF_HW_CFG_FLAG_CSTM 0x02U
#define MCHP_SAF_HW_CFG_FLAG_CPHA 0x04U
/* enable SAF prefetch */
#define MCHP_SAF_HW_CFG_FLAG_PFEN 0x10U
/* Use expedited prefetch instead of default */
#define MCHP_SAF_HW_CFG_FLAG_PFEXP 0x20U
/*
* Override the default tag map value when this bit is set
* in a tag_map[].
*/
#define MCHP_SAF_HW_CFG_TAGMAP_USE BIT(31)
#define MCHP_SAF_VER_1 0
#define MCHP_SAF_VER_2 1
struct espi_saf_hw_cfg {
uint8_t version;
uint8_t flags;
uint8_t rsvd1;
uint8_t qmspi_cpha;
uint32_t qmspi_cs_timing;
uint16_t flash_pd_timeout;
uint16_t flash_pd_min_interval;
uint32_t generic_descr[MCHP_SAF_NUM_GENERIC_DESCR];
uint32_t tag_map[MCHP_ESPI_SAF_TAGMAP_MAX];
};
/*
* SAF local flash configuration.
* Version: 0 = V1, 1 = V2(this version)
* miscellaneous configuration flags
* SPI flash device size in bytes
* SPI opcodes for SAF Opcode A register
* SPI opcodes for SAF Opcode B register
* SPI opcodes for SAF Opcode C register
* SPI opcodes for SAF Opcode D register: power down/up and
* RPMC continuous mode read
* SAF controller Poll2 Mask value specific for this flash device
* SAF continuous mode prefix register value for those flashes requiring
* a prefix byte transmitted before the enter continuous mode command.
* Start QMSPI descriptor numbers.
* Power down timeout count in units of 32 KHz ticks.
* Minimum interval between power down/up commands in 48 MHz units.
* QMSPI descriptors describing SPI opcode transmit and data read.
*/
/* Flags */
#define MCHP_FLASH_FLAG_ADDR32 BIT(0)
#define MCHP_FLASH_FLAG_V1_MSK 0xffu
#define MCHP_FLASH_FLAG_V2_MSK 0xff00u
#define MCHP_FLASH_FLAG_V2_PD_CS0_EN BIT(8)
#define MCHP_FLASH_FLAG_V2_PD_CS1_EN BIT(9)
#define MCHP_FLASH_FLAG_V2_PD_CS0_EC_WK_EN BIT(10)
#define MCHP_FLASH_FLAG_V2_PD_CS1_EC_WK_EN BIT(11)
struct espi_saf_flash_cfg {
uint8_t version;
uint8_t rsvd1;
uint16_t flags;
uint32_t flashsz;
uint8_t rd_freq_mhz;
uint8_t freq_mhz;
uint8_t rsvd2[2];
uint32_t opa;
uint32_t opb;
uint32_t opc;
uint32_t opd;
uint16_t poll2_mask;
uint16_t cont_prefix;
uint16_t cs_cfg_descr_ids;
uint16_t rsvd3;
uint32_t descr[MCHP_SAF_QMSPI_NUM_FLASH_DESCR];
};
/*
* 17 flash protection regions
* Each region is described by:
* SPI start address. 20-bits = bits[31:12] of SPI address
* SPI limit address. 20-bits = bits[31:12] of last SPI address
* 8-bit bit map of eSPI master write-erase permission
* 8-bit bit map of eSPI maste read permission
* eSPI master numbers 0 - 7 correspond to bits 0 - 7.
*
* Protection region lock:
* One 32-bit register with bits[16:0] -> protection regions 16:0
*
* eSPI Host maps threads by a tag number to master numbers.
* Thread numbers are 4-bit
* Master numbers are 3-bit
* Master number Thread numbers Description
* 0 0h, 1h Host PCH HW init
* 1 2h, 3h Host CPU access(HW/BIOS/SMM/SW)
* 2 4h, 5h Host PCH ME
* 3 6h Host PCH LAN
* 4 N/A Not defined/used
* 5 N/A EC Firmware portal access
* 6 9h, Dh Host PCH IE
* 7 N/A Not defined/used
*
* NOTE: eSPI SAF specification allows master 0 (Host PCH HW) full
* access to all protection regions.
*
* SAF TAG Map registers 0 - 2 map eSPI TAG values 0h - Fh to
* the three bit master number. Each 32-bit register contains 3-bit
* fields aligned on nibble boundaries holding the master number
* associated with the eSPI tag (thread) number.
* A master value of 7h in a field indicates a non-existent map entry.
*
* bit map of registers to program
* b[2:0] = TAG Map[2:0]
* b[20:4] = ProtectionRegions[16:0]
* bit map of PR's to lock
* b[20:4] = ProtectionRegions[16:0]
*
*/
#define MCHP_SAF_PR_FLAG_ENABLE 0x01U
#define MCHP_SAF_PR_FLAG_LOCK 0x02U
#define MCHP_SAF_MSTR_HOST_PCH 0U
#define MCHP_SAF_MSTR_HOST_CPU 1U
#define MCHP_SAF_MSTR_HOST_PCH_ME 2U
#define MCHP_SAF_MSTR_HOST_PCH_LAN 3U
#define MCHP_SAF_MSTR_RSVD4 4U
#define MCHP_SAF_MSTR_EC 5U
#define MCHP_SAF_MSTR_HOST_PCH_IE 6U
struct espi_saf_pr {
uint32_t start;
uint32_t size;
uint8_t master_bm_we;
uint8_t master_bm_rd;
uint8_t pr_num;
uint8_t flags; /* bit[0]==1 is lock the region */
};
struct espi_saf_protection {
size_t nregions;
const struct espi_saf_pr *pregions;
};
#endif /* _SOC_ESPI_SAF_H_ */

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/*
* Copyright (c) 2021 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __SOC_POWER_DEBUG_H__
#define __SOC_POWER_DEBUG_H__
/* #define SOC_SLEEP_STATE_GPIO_MARKER_DEBUG */
#ifdef SOC_SLEEP_STATE_GPIO_MARKER_DEBUG
/* Select a gpio not used. LED4 on EVB. High = ON */
#define DP_GPIO_ID MCHP_GPIO_0241_ID
/* output drive high */
#define PM_DP_ENTER_GPIO_VAL 0x10240U
/* output drive low */
#define PM_DP_EXIT_GPIO_VAL 0x0240U
static inline void pm_dp_gpio(uint32_t gpio_ctrl_val)
{
struct gpio_regs * const regs =
(struct gpio_regs * const)(DT_REG_ADDR(DT_NODELABEL(gpio_000_036)));
regs->CTRL[DP_GPIO_ID] = gpio_ctrl_val;
}
#endif
#ifdef DP_GPIO_ID
#define PM_DP_ENTER() pm_dp_gpio(PM_DP_ENTER_GPIO_VAL)
#define PM_DP_EXIT() pm_dp_gpio(PM_DP_EXIT_GPIO_VAL)
#else
#define PM_DP_ENTER()
#define PM_DP_EXIT()
#endif
#endif /* __SOC_POWER_DEBUG_H__ */

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/*
* Copyright (c) 2020 Intel Corporation.
* Copyright (c) 2021 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/arch/arm/arch.h>
#include <zephyr/kernel.h>
#include <zephyr/sys_clock.h>
#include <zephyr/timing/timing.h>
#include <soc.h>
/*
* This code is conditionally built please refer to the SoC cmake file and
* is not built normally. If this is is not built then timer5 is available
* for other uses.
*/
#define BTMR_XEC_REG_BASE \
((struct btmr_regs *)(DT_REG_ADDR(DT_NODELABEL(timer5))))
void soc_timing_init(void)
{
struct btmr_regs *regs = BTMR_XEC_REG_BASE;
/* Setup counter */
regs->CTRL = MCHP_BTMR_CTRL_ENABLE | MCHP_BTMR_CTRL_AUTO_RESTART |
MCHP_BTMR_CTRL_COUNT_UP;
regs->PRLD = 0; /* Preload */
regs->CNT = 0; /* Counter value */
regs->IEN = 0; /* Disable interrupt */
regs->STS = 1; /* Clear interrupt */
}
void soc_timing_start(void)
{
regs->CTRL |= MCHP_BTMR_CTRL_START;
}
void soc_timing_stop(void)
{
regs->CTRL &= ~MCHP_BTMR_CTRL_START;
}
timing_t soc_timing_counter_get(void)
{
return regs->CNT;
}
uint64_t soc_timing_cycles_get(volatile timing_t *const start,
volatile timing_t *const end)
{
return *end - *start;
}
uint64_t soc_timing_freq_get(void)
{
return CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
}
uint64_t soc_timing_cycles_to_ns(uint64_t cycles)
{
return cycles * NSEC_PER_SEC / CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
}
uint64_t soc_timing_cycles_to_ns_avg(uint64_t cycles, uint32_t count)
{
return (uint32_t)soc_timing_cycles_to_ns(cycles) / count;
}
uint32_t soc_timing_freq_get_mhz(void)
{
return (uint32_t)(soc_timing_freq_get() / 1000000);
}

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family:
- name: microchip_mec
series:
- name: mec15xx
socs:
- name: mec1501_hsz
- name: mec172x
socs:
- name: mec172x_nsz
- name: mec172x_nlj

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# Copyright (c) 2024 Nordic Semiconductor
# SPDX-License-Identifier: Apache-2.0
add_subdirectory(${SOC_SERIES})

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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
if SOC_FAMILY_MICROCHIP_MIV
rsource "*/Kconfig"
endif # SOC_FAMILY_MICROCHIP_MIV

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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
if SOC_FAMILY_MICROCHIP_MIV
rsource "*/Kconfig.defconfig"
endif # SOC_FAMILY_MICROCHIP_MIV

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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
config SOC_FAMILY_MICROCHIP_MIV
bool
config SOC_FAMILY
default "microchip_miv" if SOC_FAMILY_MICROCHIP_MIV
rsource "*/Kconfig.soc"

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# SPDX-License-Identifier: Apache-2.0
# Copyright (c) 2018 Antmicro <www.antmicro.com>
zephyr_sources()
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")

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# RISCV32_MIV configuration options
# Copyright (c) 2018 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_MIV
select RISCV
select RISCV_PRIVILEGED
select RISCV_HAS_PLIC
config SOC_MIV
select ATOMIC_OPERATIONS_BUILTIN
select INCLUDE_RESET_VECTOR
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI

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soc/microchip/miv/miv/Kconfig.defconfig Normal file
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# SPDX-License-Identifier: Apache-2.0
# Copyright (c) 2018 Antmicro <www.antmicro.com>
if SOC_SERIES_MIV
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 4000000
config RISCV_SOC_INTERRUPT_INIT
default y
config RISCV_GP
default y
config 2ND_LVL_ISR_TBL_OFFSET
default 12
config 2ND_LVL_INTR_00_OFFSET
default 11
config MAX_IRQ_PER_AGGREGATOR
default 30
config NUM_IRQS
default 42
endif # SOC_SERIES_MIV

22
soc/microchip/miv/miv/Kconfig.soc Normal file
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# RISCV32_MIV configuration options
# Copyright (c) 2018 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_MIV
bool
select SOC_FAMILY_MICROCHIP_MIV
help
Microchip Mi-V implementation#
config SOC_MIV
bool
select SOC_SERIES_MIV
help
Microchip Mi-V system implementation
config SOC_SERIES
default "miv" if SOC_SERIES_MIV
config SOC
default "miv" if SOC_MIV

5
soc/microchip/miv/polarfire/CMakeLists.txt Normal file
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# SPDX-License-Identifier: Apache-2.0
zephyr_sources()
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")

28
soc/microchip/miv/polarfire/Kconfig Normal file
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# RISCV64_MIV Microchip Polarfire SOC configuration options
# Copyright (c) 2020-2021 Microchip Technology Inc
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_POLARFIRE
select RISCV
select RISCV_PRIVILEGED
select RISCV_HAS_PLIC
config SOC_POLARFIRE
select ATOMIC_OPERATIONS_BUILTIN
select RISCV_GP
select USE_SWITCH_SUPPORTED
select USE_SWITCH
select CPU_HAS_FPU
select SCHED_IPI_SUPPORTED
select RISCV_ISA_RV64I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_C
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
config MPFS_HAL
depends on SOC_POLARFIRE
bool "Microchip Polarfire SOC hardware abstracton layer"
select HAS_MPFS_HAL

29
soc/microchip/miv/polarfire/Kconfig.defconfig Normal file
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# Copyright (c) 2020-2021 Microchip Technology Inc
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_POLARFIRE
# MPFS should be configured so that the mtimer clock is 1MHz independent of the CPU clock...
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 1000000
config RISCV_SOC_INTERRUPT_INIT
default y
config RISCV_GP
default y
config 2ND_LVL_ISR_TBL_OFFSET
default 13
config 2ND_LVL_INTR_00_OFFSET
default 11
config MAX_IRQ_PER_AGGREGATOR
default 186
config NUM_IRQS
default 186
endif # SOC_SERIES_POLARFIRE

22
soc/microchip/miv/polarfire/Kconfig.soc Normal file
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# RISCV64_MIV Microchip Polarfire SOC configuration options
# Copyright (c) 2020-2021 Microchip Technology Inc
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_POLARFIRE
bool
select SOC_FAMILY_MICROCHIP_MIV
help
Microchip RV64 implementation
config SOC_POLARFIRE
bool
select SOC_SERIES_POLARFIRE
help
Microchip MPFS system implementation
config SOC_SERIES
default "polarfire" if SOC_SERIES_POLARFIRE
config SOC
default "polarfire" if SOC_POLARFIRE

9
soc/microchip/miv/soc.yml Normal file
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family:
- name: microchip_miv
series:
- name: miv
socs:
- name: miv
- name: polarfire
socs:
- name: polarfire