hwmv2: Introduce Hardware model version 2 and convert devices
This is a squash of the ``collab-hwm`` branch which converts all
in-tree boards to hardware model version 2 including build system
changes, board updates and soc conversions.
This squash is a combination of the following commits:
ca214745a1 soc: Remove soc_legacy folder and move ARM Kconfig
f12cb0979f scripts: ci: check_compliance: remove HWMv1 checks
1807bcf4d4 boards: mimx8mq_evk: port to HWMv2
3ec2299c62 soc: nxp: port imx8mq SOC to HWMv2
8ea02f4e63 boards: verdin_imx8mp: convert to HVMv2
f2eb7652ce boards: phyboard_pollux: move to HVMv2
ab509a5ee0 boards: nxp: mimx8mp_evk: port M7 core to HWMv2
06ad037f99 soc: nxp: imx8mp: port M7 core to HWMv2
3f9e706859 boards: mimx8mm_phyboard: convert to HVMv2
204372d264 boards: imx8mm_evk: port CM4 core to HWMv2
f82c961a46 soc: nxp: imx8mm: port iMX8MM M4 core to HVMv2
6987b2e305 boards: pico_pi: convert to HVMv2
84484e6707 boards: warp7: convert to HWMv2
ae443d1e3c boards: meerkat96: port to HWMv2
e3629c64e6 boards: colibri_imx7d: port to HWMv2
fc835d893d soc: nxp: convert iMX7 Dual core to HWMv2
29ef2f23eb boards: udoo_neo_full: convert to HWMv2
fd49b1749e soc: nxp: convert iMX6 SoloX core to HWMv2
1e59b7a3fd soc: nxp: imxrt11xx: only set
CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION for M7
69bb0eb258 hwmv2: MAINTAINERS: Fix NXP maintainer yaml
1c4458890f boards: firefly: roc_rk3568_pc: Fix SMP configuration
651a4370ad boards: Fix variants and revisions
196cfda66d tests/samples: Drop default revision identifiers
6ec6b1d75a boards: Drop revision from twister identifiers for
default revisions
b774cdd59f scripts: utils: board_v1_to_v2: drop board_legacy prefix
7aa36e6640 boards: riscv: esp32c3_luatos_core: make usb variant
fe25709a9c twister: add unit_testing soc and board
f88f211b4e scripts: ci: check_compliance: improve the "not sorted"
command
b21a455dfb bluetooth: controller: Fix openisa checks
fdc76c48a7 workflow: compliance: Add rename limit
14ecafc67d dts: bindings: vendor-prefixes: Sort entries
dbc366c3c7 soc: nxp: lpc: Move wrong configurations
8e02c08f96 maintainers: Fix invalid paths
b1b85e2495 boards: up: Fix spaces
58cc4013b3 maintainers: Fix xen path
66ce5c0b09 boards/soc: Add missing copyright headers
bb47243254 boards: qemu: x86: Remove pointless file
2e816a8a3a samples: tests: update esp32-based board naming
9aeab17139 samples: tests: remove platform_exclude of esp32 boards
a4fe97b9de boards: shields: m5stack_core2_ext: update board name
615fcab94a samples: ipm_esp32: fix board labels and skip testing
7752f69b7f boards: legacy: remove index entry for xtensa/riscv
boards.
3eba827956 MAINTAINERS: update Espressif entries
914362bbd5 boards: xtensa: yd_esp32: Convert to v2
a62278fd23 boards: xtensa: xiao_esp32s3: Convert to v2
b6a11ccec4 boards: xtensa: olimex_esp32_evb: Convert to v2
c1067c16d2 boards: xtensa: odroid_go: Convert to v2
b8340b0109 boards: xtensa: m5stickc_plus: Convert to v2
9d81e417be boards: xtensa: m5stack_stamps3: Convert to v2
c296672720 boards: xtensa: m5stack_core2: Convert to v2
fada12aa9d boards: xtensa: m5stack_atoms3_lite: Convert to v2
fe37ebac1e boards: xtensa: m5stack_atoms3: Convert to v2
d32828fe6a boards: xtensa: kincony_kc868_a32: Convert to v2
5afba7855b boards: xtensa: heltec_wireless_stick_lite_v3: Convert to
v2
ca48c17723 boards: xtensa: heltec_wifi_lora32_v2: Convert to v2
db1fd4d229 boards: xtensa: esp32s3_luatos_core: Convert to v2
a78b2552eb boards: xtensa: esp32s3_devkitm: Convert to v2
cc96061d96 boards: xtensa: esp32s2_saola: Convert to v2
ed854e05d1 boards: xtensa: esp32s2_lolin_mini: Convert to v2
4fa1ae8110 boards: xtensa: esp32s2_franzininho: Convert to v2
5543040a18 boards: xtensa: esp_wrover_kit: Convert to v2
2335ae79b3 boards: xtensa: esp32_ethernet_kit: Convert to v2
f910b7ad4f boards: xtensa: esp32_devkitc_wrover: Convert to v2
32104db555 boards: xtensa: esp32_devkitc_wroom: Convert to v2
e23a41200d boards: riscv: icev_wireless: Convert to v2
3c670e4e53 boards: riscv: xiao_esp32c3: Convert to v2
fc7c6a060b boards: riscv: stamp_c3: Convert to v2
22c2edb89c boards: riscv: esp32c3_luatos_core: Convert to v2
0a96dcb778 boards: riscv: esp32c3_devkitm: Convert to v2
be1ee1c446 vendors: update vendors lists
5e6c62137f soc: espressif_esp32: Port to HWMv2
037a3b52a4 boards: Raspberry Pi pico pwm led adjustment
7277cae6fa samples: blinky_pwm: enable pwm_leds in rpi_pico overlay
da3e49d34e boards: nxp: update selection of
FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
bc8424dd3b soc: nxp: imxrt: move FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
to SOC level
041cb52939 soc: brcm: bcm_vk: Rename to bcnvk
576b43a95c soc: Fix SOC_FAMILY name mismatches
e8f3e6494d hwmv2: boards: intel: adsp: Fix runner after paths
renamed
550399e927 boards: weact: stm32g431_core: Add wrongly deleted file
back
08708c909e tests: drivers: flash: Renamed missed board rename
06dac41e68 hwmv2: Convert Seagate Faze board to hwmv2
dd8f842b40 hwmv2: nxp: update MAINTAINER paths for hwmv2
b4d1c04978 hwmv2: lpc: updated overlay and conf files in samples and
tests
067c69089e boards: nxp: convert lpcxpresso55s69 to hwmv2
097205b40a hwmv2: Global fix of lpc54114_m4 overlay and conf files
d8cfa6fb29 boards: nxp: convert lpcxpresso54114 to hwmv2
c29ed228c6 boards: nxp: convert lpcxpresso55s36 to hwmv2
88cfd3d6ac boards: nxp: convert lpcxpresso55s28 to hwmv2
ad30c940ee boards: nxp: convert lpcxpresso55s16 to hwmv2
9e5a10ec80 boards: nxp: convert lpcxpresso55s06 to hwmv2
5650c83268 boards: nxp: convert lpcxpresso51u68 to hwmv2
82cf44be45 boards: nxp: convert lpcxpresso11u68 to hwmv2
1a9c405a6f soc: nxp: convert LPC SOC family to hardware model V2
f2b536d253 boards: intel: doc: hwmv2: Fix some renamed paths
5ee6058710 samples/tests: Use board revisions
b76687602f boards: Add yaml files for boards missing revisions
32ae4918d0 boards: nordic: Fix board names
cc1dabca65 MAINTAINERS: Update for renamed folders
a37ddce659 soc: xilinx: Rename to xlnx
a1393a07f6 soc: xenvm: Rename to xen
813ed00f67 soc: raspberry_pi: Rename to raspberrypi
71317d6798 soc: cadence: Rename to cdns
8cb0c51ec6 soc: broadcom: Rename to brcm
2b9db15c69 soc: andes: Rename to andestech
0101216ce1 soc: altera: Rename to altr
4b4c3ca65d boards: wurth_elektronik: Rename to we
cdc3ef499f boards: ublox: Rename to u-blox
cabdd4ad05 boards: space_cubics: Rename to sc
4b5bd7ae8a boards: seeed_studio: Rename to seeed
a992785ceb boards: raspberry_pi: Rename to raspberrypi
3c1cdc20fe boards: laird_connect: Rename to lairdconnect
291c7cde2b boards: cadence: Rename to cdns
95db897526 boards: broadcom: Rename to brcm
0a47b94879 boards: beagleboard: Change to beagle
9f9f221c24 boards: andes: Rename to andestech
e7869ca38a boards: altera: Rename to altr
bf2fb5eca3 various: Change SOC_FAMILY_NRF to SOC_FAMILY_NORDIC_NRF
e25730ba56 modules: tf-m: Rename from nordic_nrf to nordic
9e3466606a boards: nordic_nrf: Rename to nordic
09a398dcc8 soc: nordic_nrf: Rename to nordic
cb8ffc74f8 boards: renode: Add documentation index
2291ff4b55 boards: arm: riscv32_virtual: Convert to v2
484b7f1996 soc: riscv_renode_virtual: Port to HWMv2
cc5c2fb0c7 soc: raspberry_pi: Fix SOC_SERIES and SOC mismatch
59cb580513 soc: arm: designstart: Fix SOC_SERIES and SOC mismatch
aa9e0de7af samples: Fix invalid links
a1480cf1cf maintainers: Fix paths
0d719e004b boards: Update documentation links
eb5c3e6f79 boards: wurth_elektronik: Drop duplicate prefix
a34a3640b7 boards: waveshare: Drop duplicate prefix
cf50e950e7 boards: weact: Drop duplicate prefix
737cfb548f boards: sparkfun: Drop duplicate prefix
505494c97a boards: segger: Drop duplicate prefix
4eaf69f37a boards: ruuvi: Drop duplicate prefix
a1335caeae boards: ronoth: Drop duplicate prefix
a9f7f30bf6 boards: raytac: Drop duplicate prefix
80db4c81b3 boards: qemu: Drop duplicate prefix
433d7e9976 boards: particle: Drop duplicate prefix
4ea79d19e7 boards: olimex: Drop duplicate prefix
fd4ae6f6a8 boards: mikroe: Drop duplicate prefix
36080549bd boards: khados: Drop duplicate prefix
169bf8ae1d boards: intel: Drop duplicate prefix
25f04d5222 boards: holyiot: Drop duplicate prefix
11c2af0de8 boards: google: Drop duplicate prefix
d5128f4016 boards: ebyte: Drop duplicate prefix
44fbc68cad boards: dragino: Drop duplicate prefix
f7fe431b44 boards: contextual_electronics: Drop duplicate prefix
9094fea63b boards: circuit_dojo: Drop duplicate prefix
b632acc1fc boards: blue_clover: Drop duplicate prefix
1a3316ebdc boards: bbc: Drop duplicate prefix
71c0344f8c boards: arduino: Drop duplicate prefix
f0176fc25f boards: altera: Drop duplicate prefix
36b920ed0f boards: adi: Drop duplicate prefix
22520368d9 boards: adafruit: Drop duplicate prefix
296acfb2bc boards: actinius: Drop duplicate prefix
55063380b7 boards: 96boards: Drop duplicate prefix
1f93394b55 boards: nxp: convert mimxrt595_evk to hardware model v2
e7a4fd2ec1 soc: nxp: rt5xx: convert RT5xx SOC to HWMv2
01942f1d11 twister: normalize platform name when storing files/data
477c8b84dd twister: tests: test with slashes in platform names
64e3e816c4 soc: Add include guards
3a7aa2fa49 gitignore: update the compliance file list
84e1c17ad9 scripts: ci: check_compliance: add a check for board yml
file
a90f53ad57 boards: sync up the vendor tags and vendor-list
af9aa65299 dts: vendor-prefixes: add keep-sorted markers
50f0bf05a3 dts: vendor-prefixes: sort the vendor list
a10b614aa4 dts: vendor-prefixes: ensure all prefixes are lowercase
5abe735e93 manifest: update SOF sha for NXP HWMv2
9ab8f64ca9 modules: rename SOC_FAMILY_IMX
483ff8dd4d modules: mcux: remove SOC_FAMILY_NXP_ADSP
f113dd5342 samples: update board name
39b31287d9 boards: nxp: Convert i.MX ADSP boards to hardware model
v2
1511e356a2 soc: nxp: Port i.MX ADSP family to hardware model v2
c91e25ab47 soc: mec: rename all mec1501x reference to mec15xx
1c231fd939 hwmv2: boards: Convert IMXRT boards
417cff1e60 hwmv2: soc: Port IMXRT family to HWMV2
28d4e41b1b hwmv2: clean up arm64 soc and board empty directory
2b520f83cb hwmv2: port NXP SoC LS1046A to V2
bf7899c645 hwmv2: port nxp_ls1046ardb board to V2
33f7b61866 samples/tests: Rename numaker boards
8f20ea6e93 boards: nuvoton: numaker_pfm: Split into 2 boards
7cf4ff43a1 drivers: pinctrl: imx: align with hwm v2
c68e1fea4e drivers: clock_control: ccm_rev2: align with hwm v2
update
3b49014a0f hwmv2: move imx8mn EVK board to V2
14f344eeab hwmv2: move imx8mp EVK board to V2
40f3f8f22d hwmv2: move imx8mm EVK board to V2
10bf79ea51 hwmv2: move imx8m soc for a-core to V2
8727d5ca80 hwmv2: move imx93 EVK board to V2
c81ef01563 hwmv2: move imx93 soc to V2
5836c1b699 modules: mcux: introduce CONFIG_MCUX_CORE_SUFFIX
338f6f2bf1 doc: update board porting guide to match new hardware
model
9639a1b5dc soc: silabs: drop useless defconfigs
981807444e soc: silabs: introduce SOC_GECKO_SDID
5d07e82485 soc: silabs: SOC_FAMILY_* replace SOC_GECKO_SERIES*
2fd081ac86 soc: silabs: align comments with soc tree
66d425f571 soc: silabs: split in families
5bd38f47a9 arch: arch: kconfig: Fix wrong placement of endmenu
00c6ef25be tests/samples: Rename overlay files for renamed boards
0c639b8378 boards: Fix bools and selections
c2ef907d1d drivers: flash: it8xxx2: Add missing Kconfigs
553de2ebc9 soc: ite: ec: it8xxx2: Fix SOC_SERIES being in wrong file
b8ec0080c2 boards: Documentation link fixes
eb7025e50f tests: Update board names for hwmv2
10ef3d4bd2 boards: silab: Add documentation index file
ba9fdaa1d6 boards: arm: efr32_radio: Convert to v2
86c8d4a0ca boards: arm: efm32pg_stk3402a: Convert to v2
575ac5cafb manifest: Update hal_silabs
87b2907304 boards: arm: efr32_thunderboard: Convert to v2
14b30055ab boards: arm: efr32mg_sltb004a: Convert to v2
0012bfc15d boards: arm: efr32xg24_dk2601b: Convert to v2
f526225ead boards: arm: efm32wg_stk3800: Convert to v2
19e7df29df boards: arm: efm32pg_stk3401a: Convert to v2
0bd7d963d6 boards: arm: efm32hg_slstk3400a: Convert to v2
795a90f9bf boards: arm: efm32gg_stk3701a: Convert to v2
43d5540be7 boards: arm: efm32gg_slwstk6121a: Convert to v2
065148d856 boards: arm: efm32gg_sltb009a: Convert to v2
1dc9a8aa17 soc: silabs_exx32: Port to HWMv2
763571e878 tests: Expand names
dae301b8a3 boards: xen: xenvm: Expand name
19e60eef36 boards: qemu: qemu_cortex_a53: Expand names
a0a7c30f28 soc: intel: intel_adsp: Fix issues
df9a4223fe scripts: ci: introduce soc name check in check_compliance
ed401abaff soc: emsdsp: align SoC name defined in soc.yml to Kconfig
SOC setting
fc78e5eaa4 MAINTAINERS: update RISC-V arch area paths
4e586958ff boards: convert QEMU RISC-V 64 bit board to Zephyr HWMv2
f4c31a2b86 boards: convert QEMU RV32E board to Zephyr HWMv2
5b2ffc652b boards: convert QEMU RISC-V 32 bit board to Zephyr HWMv2
5db061a4c6 soc/riscv: convert the QEMU virt RISCV-32 SoC to HWMv2
6547845e9d boards: convert SparkFun RED-V Things Plus to Zephyr
HWMv2
95a1f96399 boards: convert SiFive HiFive Unmatched to Zephyr HWMv2
e563eb0a62 soc/sifive/sifive_freedom: add SiFive Freedom FU740 SoC
8914bc58b6 boards: convert SiFive HiFive Unleashed to Zephyr HWMv2
7e8de1e781 soc/sifive/sifive_freedom: add SiFive Freedom U540 SoC
bfcc2ed18f boards: convert SiFive HiFive1 Rev. B to Zephyr HWMv2
330fc38f9f boards: convert SiFive HiFive1 to Zephyr HWMv2
b9e06f4c38 soc/sifive/sifive_freedom: add SiFive Freedom E310 SoC
4b90b30b9d scripts: west_commands: completion: Add hwmv2 complete to
fish
0f6842e2fa scripts: west_commands: completion: Add hwmv2 complete to
zsh
b2af1e1737 scripts: west: list_boards: Fix hwmv2 output
686a4b78b8 scripts: west_commands: completion: Add hwmv2 complete to
bash
396b6bb856 soc: nxp: fix typo in SoC name
765299c627 soc: broadcom: align SoC names defined in soc.yml to
Kconfig SOC setting
7efd46eb41 soc: arm: align SoC names defined in soc.yml to Kconfig
SOC setting
505cbc5c42 soc: mec: align SoC names defined in soc.yml to Kconfig
SOC setting
951a140701 soc: ti: define SOC name in Kconfig
a795d28810 snippets: Initial HWMv2 support
f9a957e6f6 boards: nordic: nrf9160dk: Fix missing nrf52840 config
df994e7ee8 soc: xilinx: zync7000: Remove xilinx from soc series name
8dfabd56ca soc: cypress: Add protection guard to file
447b951593 tests: kernel: tickless: Remove old board name
bad5dfa71f boards: nordic: nrf5340dk: Fix board names
ad2e863f39 soc: atmel: Use new family prefix
3f08e714b2 soc: intel_adsp: hwmv2: Align SOC_SERIES_INTEL_ACE name
and value
6734597a76 soc: intel_adsp_cavs: hwmv2: Align SOC_SERIES name and
value
2908af0bcc boards: nrf51dk/dongle: change SoC to nRF51822
d1ceb29fca soc: align CONFIG_SOC values to match soc.yml names
4768ccaf70 tests: drivers: gpio: gpio_api_1pin: exclude hifive1
ebdb0879ad boards: nxp: s32z2xxdc2: convert to hwmv2
ae82580d08 boards: nxp: mr_canhubk3: convert to hwmv2
c5f0defbae boards: nxp: ucans32k1sic: convert to hwmv2
1e46cabce6 soc: nxp: convert NXP S32 family to hwmv2
f2f85133f2 soc: stm32: Rename series path
86642f4e78 soc: stm32: Rename Kconfig SOC_SERIES symbols
c61e807896 soc: stm32: Cleanup Kconfig.defconfig files
ca46c8abc9 tests: Fix board names
fbfed5f48f maintainers: Update synopsys entries
8cd8b1cc47 boards: synopsys: Add documentation index
6f6cc57a04 boards: arc: hsdk4xd: Convert to v2
c4c14a54ca soc: snps_arc_hsdk4xd: Port to HWMv2
06c2054e5c boards: arc: iotdk: Convert to v2
ff0e0fce1b soc: snps_arc_iot: Port to HWMv2
334264c46a boards: arc: emsdp: Convert to v2
8b947a0e91 soc: snps_emsdp: Port to HWMv2
990417bbde tests: Update board names for hwmv2
e12719154a boards: arc: em_starterkit: Convert to v2
437a430fbe soc: snps_emsk: Port to HWMv2
f93387f968 boards: arc: hsdk: Convert to v2
1cf2498b13 soc: snps_arc_hsdk: Port to HWMv2
47abe81256 boards: arc: nsim: Convert to v2
1e33786dc4 soc: snps_nsim: Port to HWMv2
7f081914db boards: arc: qemu_arc: Convert to v2
bc97349dbd soc: snps_qemu: Port to HWMv2
a9902ff58e boards: Use zephyr_file for file links
126e1a4e72 boards: Fix invalid documentation links
899f0257c3 boards: stm32wb: Restore missing .defconfig files
790c10b1ee soc: x86/atom: imply mmu, do not select it
faee62088d boards: x86: remove qemu_x86_tiny_768
c34d186a57 x86: atom: remove soc.h with unused content
1be3a9e9d3 x86: remove legacy ia32, use atom instead
60e6b400f9 boards: qemu: move qemu_x86 -> x86
c4fbac27e8 boards: infineon: Add documentation index
b4dd29a9c4 maintainers: Update paths for hwmv2
380f5fdb2b boards: cypress: Add documentation index
9de981be05 boards: arm: xmc47_relax_kit: Convert to v2
6394e8a348 boards: arm: xmc45_relax_kit: Convert to v2
04dbf17e19 soc: xmc_4xxx: Port to HWMv2
c9731f1bce boards: arm: cy8cproto_063_ble: Convert to v2
53d41869d1 boards: arm: cy8cproto_062_4343w: Convert to v2
46c4f01427 boards: arm: cy8ckit_062s4: Convert to v2
d285e19cf2 boards: arm: cy8ckit_062_wifi_bt: Convert to v2
2bebd7298c boards: arm: cy8ckit_062_ble: Convert to v2
af243274c2 soc: psoc6 and psoc_6: Port to HWMv2
105a2bae84 cmake: modules: boards: Fix board deprecation for HWMv2
dca54e000a cmake: modules: boards: Enhance board aliases for HWMv2
fc314e8e3f cmake: modules: boards: Fix BOARD_ALIAS
9a7c2ce6d5 soc: gaisler: Move Kconfig file
1ac56d0501 soc: soc_legacy: mips: Remove out file
c054381a7a boards: adjust few boards/ paths
4d93b8d9fd boards: convert all microchip MEC boards to hwmv2
ab2fcb1245 soc: convert microchip_mec to hwmv2
ead4b57a7b soc: arm64: intel_socfpga: hwmv2: Rename SoCs
d4c143d306 MAINTAINERS: intel_socfpga: Adjust to HWMv2 move
70a66ac03a boards: arm64: intel_socfpga: Move boards to
subdirectories
8a85c07799 boards: arm64: intel_socfpga_agilex5_socdk: move to HWMv2
8c253a99fc boards: arm64: intel_socfpga_agilex_socdk: move to HWMv2
ab883b8019 soc: arm64: intel_socfpga: Move and convert to HWMv2
7c8b7a153b soc: arm: intel_socfpga_std: Rename with HWMv2
8dc2b911f6 soc: board: intel_socfpga_std: Align names to 'Cyclone V'
402366117a soc: arm: intel_socfpga_std: Align board subdirectory
f0a8d12745 boards: arm: cyclonev_socdk: Move to HWMv2
2271f17a86 soc: arm: intel_socfpga_std: Move and convert to HWMv2
841c2a9d99 boards: riscv: beaglev_fire: Convert to v2
3b314531ab boards: riscv: mpfs_icicle: Convert to v2
d4ea2bf70b boards: riscv: m2gl025_miv: Convert to v2
5256e9fcc3 soc: microchip_miv: Port to HWMv2
18e5cf1d51 maintainers: Update path for hwmv2
eab8628f98 boards: arm: qemu_cortex_m3: Convert to v2
1532f2fee1 soc: ti_lm3s6965: Port to HWMv2
430ca6a475 maintainers: Update ambiq paths
a9b9b41b91 boards: ambiq: Add index
db0271ecbb boards: arm: apollo4p_blue_kxr_evb: Convert to v2
957e2b2061 boards: arm: apollo4p_evb: Convert to v2
5a90a44454 soc: ambiq: Port to HWMv2
a20c113fbd boards: nxp: convert ip_k66f to hwmv2
34e3852a54 boards: nxp: convert usb_kw24d512 to hwmv2
20ad604de6 boards: nxp: convert twr_kv58f220m to hwmv2
2e2a7b7656 boards: nxp: twr_ke18f: convert to hwmv2
f7dcc2eb5e boards: nxp: convert rddrone_fmuk66 to hwmv2
b58e90a2e9 boards: nxp: convert hexiwear to hwmv2
aae6e9e454 boards: nxp: frdm_kw41z: convert to hwmv2
1d3baac2d6 boards: nxp: convert frdm_kl25z to hwmv2
3b1d21483f boards: nxp: frdm_k82f: port to hwmv2
6046e6ded9 boards: nxp: port frdm_k64f to hwmv2
0a7bf9fd79 boards: nxp: port frdm_k22f to hwmv2
dce697c823 boards: nxp: add toctree placeholder
666a353409 soc: nxp: kinetis: convert kinetis SOC family to hardware
model V2
89f0a6034b maintainers: Update paths for renesas boards/socs
004bd43c48 tests/samples/snippets: Update board names for hwmv2
a6d756923d boards: arm and arm64: rcar_h3ulcb: Convert to v2
3801216b8d boards: arm64: rcar_salvator_xs_m3: Convert to v2
b7cc30aaea boards: arm: rcar_h3_salvatorx_cr7: Convert to v2
866427ea29 boards: arm: arduino_uno_r4: Convert to v2
2689b3f0ee soc: ra: Port to HWMv2
e7ebc727c8 boards: arm: da1469x_dk_pro: Convert to v2
903265b2bb boards: arm: da14695_dk_usb: Convert to v2
529a78ed51 soc: smartbond: Port to HWMv2
97cf636ae0 boards: arm: rcar_spider_cr52: Convert to v2
6d0c53f3a1 soc: rcar: Port to HWMv2
44e0aa0668 soc: renesas: rzt2m: Move folder structure for more SoCs
85238fc205 boards: misc: Fixed STM32 based boards doc links
dffc08af56 boards: riscv: niosv_m: move and convert to HWMv2
545093abe4 boards: riscv: niosv_g: move and convert to HWMv2
ecfa192f1b soc: riscv: intel_niosv: move and convert to HWMv2
fd1e8cdc30 hwmv2: sof: intel_adsp: submanifest provisional link
8bf067e625 doc: boards: intel_adsp: Re-order pages
4833275ccd MAINTAINERS: intel_adsp: Adjust to HWMv2 move
b9a70e5ea2 soc: intel_adsp: tools: pylint compliance workaround
18c70cc4bf hwmv2: tests: boards: intel_adsp: Adjust board names
ca52baf9de hwmv2: boards: intel_adsp: Overhaul board configurations
d1b3bcce64 soc: boards: xtensa: intel_adsp_ace: Rename with HWMv2
f362a8ae2c doc: soc: boards: intel_adsp_cavs25: Rename with HWMv2
51dee5da92 tests: samples: boards: intel_adsp_cavs25: Rename with
HWMv2
e66c35e0d0 boards: xtensa: intel_adsp_cavs25: Rename board with
HWMv2
d1491a4810 soc: boards: xtensa: intel_adsp_cavs25: Rename with HWMv2
fa0fca79c4 scripts: west: runners: intel_adsp: Adjust path to HWMv2
acd18bfaf7 boards: xtensa: intel_adsp_ace20_lnl: move and convert to
HWMv2
546c94b958 boards: xtensa: intel_adsp_ace15_mtpm: move and convert
to HWMv2
8aab718c3e boards: xtensa: intel_adsp_cavs25_tgph: change to board
variant
30f17424a4 boards: xtensa: intel_adsp_cavs25: move and convert to
HWMv2
35a97cb524 soc: xtensa: intel_adsp: HWMv2 workaround for SOF config
fdc20fdff6 soc: xtensa: intel_adsp: move and convert to HWMv2
22dc2b6391 cmake: improved board handling for revisions
2f1e33a2e6 cmake: improve arch error message for invalid arch
selection
c47c37d3db sample: basic: blinky_pwm: Exclude rpi_pico w variant
7a788b9a18 boards: raspberry_pi: rpi_pico: Use full name for w
variant
7046b92d41 tests: atmel_sam: adc: Fix sam4e_xpro adc build
253ee9638c tests: atmel_sam0: Update platform name
ccb4c63324 samples: atmel_sam0: Update platform name
2d4acf9230 boards: arduino_nano_33_iot: Convert to HWMv2
a60d28969a boards: arduino_mkrzero: Convert to HWMv2
0409e51d3f boards: arduino_zero: Convert to HWMv2
1b2528df1b boards: wio_terminal: Convert to HWMv2
af1096e7ca boards: ev11l78a: Convert to HWMv2
0b1db9c53d boards: adafruit_trinket_m0: Convert to HWMv2
e9874671e2 boards: adafruit_itsybitsy_m4_express: Convert to HWMv2
ba6c014071 boards: adafruit_grand_central_m4_express: Convert to
HWMv2
33ad4a51ca boards: adafruit_feather_m0_lora: Convert to HWMv2
9812f3d54e boards: adafruit_feather_m0_basic_proto: Convert to HWMv2
c76b1fbeca boards: serpente: Convert to HWMv2
649789e433 boards: seeeduino_xiao: Convert to HWMv2
6b3bdb7364 boards: same54_xpro: Convert to HWMv2
93dda5ee4b boards: samr34_xpro: Convert to HWMv2
e48e1f5d5b boards: samc21n_xpro: Convert to HWMv2
f11cf73df1 boards: saml21_xpro: Convert to HWMv2
ac73ed6dcd boards: samd20_xpro: Convert to HWMv2
0fdbe3552e boards: samd21_xpro: Convert to HWMv2
854cff3905 boards: samr21_xpro: Convert to HWMv2
a87ea5bc0a soc: atmel: sam0: Port to HWMv2
706e5d27cd boards: riscv: neorv32: Convert to v2
d1edcdd088 soc: neorv32: Port to HWMv2
0f7add89ca boards: native_sim/posix: Add 64bit versions as variants
b6edad8d68 soc: soc_legacy: remove the arm/st_stm32 folder
c58e0822a6 boards: Convert nucleo_f207zg to HWM v2
b987093a80 soc: v2: stm32: Migrate STM32F2 series
2096fd4652 samples: bluetooth: hci_uart: Fix wrongly converted board
names
830f9c5a82 MAINTAINERS: Update Atmel entries
527cd9d8cd CODEOWNERS: Update Atmel entries
83af7d0c1c samples: atmel_sam: Update platform name
fd9b84d457 tests: atmel_sam: Update platform name
3c72fe863c boards: arduino_due: Convert to HWMv2
37dfacbf9e boards: RoboKit1: Convert to HWMv2
1108d7b0ed boards: sam_v71_xult: Convert to HWMv2
bed44a5c28 boards: sam_e70_xplained: Convert to HWMv2
40448c5a9f boards: sam4s_xplained: Convert to HWMv2
31273692c0 boards: sam4l_ek: Convert to HWMv2
35b5d33ef0 boards: sam4e_xpro: Convert to HWMv2
3b84b9910a soc: atmel: Port SAM family to HWMv2
da00d0e7b9 boards: Convert nucleo_wba55cg to HWM v2
fb2103f89e boards: Convert nucleo_wba52cg to HWM v2
1f9a533fbc soc: st: stm32: Migrate STM32WBA series
3f92f65b28 boards: fix documentation for alientek and blues boards
7646b74aaf boards: stm32l4: doc: add zephyr_file to defconfig path
fea54ddcd9 boards: Convert adi_eval_adin2111ebz to HWM v2
d47f1878b1 boards: Convert adi_eval_adin1110ebz to HWM v2
ae42be236b boards: Convert swan_r5 to HWM v2
83bd1a9ecc boards: Convert stm32l4r9i_disco to HWM v2
39c26f09ed boards: Convert stm32l496g_disco to HWM v2
29d03c970b boards: Convert stm32l476g_disco to HWM v2
74acec315c boards: Convert sensortile_box to HWM v2
fee6d8676e boards: Convert pandora_stm32l475 to HWM v2
008b5d9392 boards: Convert nucleo_l4r5zi to HWM v2
24e357d623 boards: Convert nucleo_l4a6zg to HWM v2
2c5f9dcce0 boards: Convert nucleo_l496zg to HWM v2
4da061646f boards: Convert nucleo_l476rg to HWM v2
15956a69b8 tests: drivers: flash: stm32: update platform name
80324f7707 boards: Convert nucleo_l452re_p to HWM v2
9893e0d111 boards: Convert nucleo_l452re to HWM v2
46f92b227b boards: Convert nucleo_l433rc_p to HWM v2
ed5d1bb4cd boards: Convert nucleo_l432kc to HWM v2
325f95ec20 boards: Convert nucleo_l412rb_p to HWM v2
d055676307 boards: Convert disco_l475_iot1 to HWM v2
c7a415d92c boards: Convert b_l4s5i_iot01a to HWM v2
d15144f582 soc: st: stm32: Migrate STM32L4 series
a63ff71bcb boards: nrf_bsim: Add new nrf5340 board definitions
b53c6f412c boards: nrf_bsim: Remove redundant option setting
83eb4fc069 MAINTAINERS: intel_ish: Adjust to HWMv2 move
715685b19f boards: x86: intel_ish: move and convert intel_ish boards
to HWMv2
5b9ef94106 soc: x86: intel_ish: move and convert to HWMv2
12b297707a boards: Convert stm32wb5mmg to HWM v2
cdcea932bc boards: Convert stm32wb5mm_dk to HWM v2
0a3ae2b223 boards: Convert nucleo_wb55rg to HWM v2
20b4ce17d5 soc: st: stm32: Migrate STM32WB series
47c65400d6 soc: st: stm32: fix stm32l0 family
59ec56f9e6 boards: Convert stm32h573i_dk to HWM v2
dc5977dbba boards: Convert nucleo_h563zi to HWM v2
a6e4928543 soc: st: stm32: Migrate STM32H5 series
99f248e048 soc: stm32u5: Fix references after conversion to hw
modelv2
15f16834e6 boards: Convert stm32u5a9j_dk to HWM v2
c1ee449ef1 boards: Convert sensortile_box_pro to HWM v2
db4deddf9d boards: Convert nucleo_u5a5zj_q to HWM v2
2fd3ed43d2 boards: Convert nucleo_u575zi_q to HWM v2
902fceb173 boards: Convert b_u585i_iot02a to HWM v2
d716ca1a10 soc: st: Migrate stm32u5 series to new hw model
b7abc89428 hwmv2: boards: x86: doc: Adjust common docs to new
locations
69b334f54b MAINTAINERS: Change paths to native and nrf*bsim boards
614611a528 boards: nrf*_bsim: Convert to HW model v2
5821b9ec2e board: native_sim/posix: Convert to hwmv2
04cbad174e soc: native: Convert to HWMv2
24ca0febfc boards: nrf_bsim: Fix path to pinctrl_soc.h
9a32559a2d cmake: FindHostTools: Fix for hwmv2 for host based
targets
c4b11e0251 boards: longan_nano: port to HWMv2
97edd05be3 boards: gd32vf103c_starter: port to HWMv2
9cf624c410 boards: gd32vf103v_eval: port to HWMv2
b40bf25e5e soc: gd_gd32: reorganize folders
71600d7e95 soc: gd_gd32: move pinctrl_soc.h content back to soc
folder
2bd84a1bc5 soc: gd_gd32: port gd32vf103 series to HWMv2
9dc342143b boards: doc: fix a bunch of broken reference
10392d693d doc: boards: split out shields
b2def8ed3a boards: acrn: fix title
bf7d3efe78 boards: riscv: tlsr9518adk80d: Convert to v2
c579770e1d soc: telink_tlsr: Port to HWMv2
9131540109 soc: stm32h7: Couple of tests fixes following migration
2efcefc089 boards: Convert stm32h7b3i_dk to HWM v2
d9b295a85b boards: Convert stm32h750b_dk to HWM v2
a2f56bdcd5 boards: Convert stm32h747i_disco to HWM v2
00314155df boards: Convert stm32h735g_disco to HWM v2
b08819dff7 boards: Convert nucleo_h7a3zi_q to HWM v2
56456c16e5 boards: Convert nucleo_h753zi to HWM v2
91f9198dc4 boards: Convert nucleo_h745zi_q to HWM v2
96f1bafbf9 boards: Convert nucleo_h743zi to HWM v2
b290f25baa boards: Convert nucleo_h723zg to HWM v2
9fbe6bf191 boards: Convert fk7b0m1_vbt6 to HWM v2
44bcfe57c7 boards: Convert arduino_portenta_h7 to HWM v2
4c86af7eae boards: Convert arduino_opta_m4 to HWM v2
b4f852f738 boards: Convert arduino_giga_r1 to HWM v2
bac9789264 soc: st: Migrate stm32h7 series to new hw model
a954e1722d boards: stm32l0: Cleanup board _defconfig files after
migration
7e8515b241 boards: Convert ronoth_lodev to HWM v2
25246c21ef boards: Convert nucleo_l073rz to HWM v2
09396eb2e6 boards: Convert nucleo_l053r8 to HWM v2
70c004fd83 boards: Convert nucleo_l031k6 to HWM v2
e3daa98e79 boards: Convert nucleo_l011k4 to HWM v2
a2de60c6da boards: Convert dragino_nbsn95 to HWM v2
e877ce9cec boards: Convert dragino_lsn50 to HWM v2
2b50218c23 boards: Convert b_l072z_lrwan1 to HWM v2
4a65f55916 soc: st: Migrate stm32l0 series to new hw model
cc6e6be01f boards: fix few leftover ITE board references
a837303268 soc: stm32: Protect Kconfig symbols by SOC_FAMILY_STM32
88e5959f17 hwm2: Fix unit_testing: it is also a legacy board by now
95e06e8663 cmake: Fix uses of old SOC path
d517d3cc24 soc: set linker script for ra4m1
68f9aeddab soc: ite: add SOC_SERIES_ITE_IT8XXX2 guards around ITE
options
ccf4f48f01 boards: convert ite boards to hwmv2
4a6e286a3b soc: convert ite_ec to hwmv2
12e375f826 doc: handle arch / soc / board docs in new hardware model
b4db917de9 boards: Add documentation index files
d6e0d27efe samples: bluetooth: hci_uart: Fix wrong named files
bc16a7a727 tests: Update board names for hwmv2
2834883843 boards: riscv: rv32m1_vega: Convert to v2
9c68231ba9 soc: openisa_rv32m1: Port to HWMv2
986e9619fd soc: starfive_jh71xx: Port to HWMv2
e82932e787 boards: riscv: litex_vexriscv: Convert to v2
cb9339f88f soc: litex_vexriscv: Port to HWMv2
1cd4c34654 boards: riscv: opentitan_earlgrey: Convert to v2
92eadf06b8 soc: opentitan: Port to HWMv2
a8659e170b boards: riscv: titanium_ti60_f225: Convert to v2
359133d725 soc: efinix_sapphire: Port to HWMv2
6d466429ed soc: soc_legacy: riscv: litex_vexriscv: Add updated paths
a1ff441eb3 boards: riscv: adp_xc7k_ae350: Convert to v2
ef82a8255c soc: ae350: Port to HWMv2
282204758a samples: boards: stm32: ccm: fix include path
8ca9341195 samples: basic: threads: fix broken reference
8a947f446d boards: nrf52840dk: fix rst syntax
324cb41153 boards: nordic_nrf: fix broken references
963c74df1c boards: intel_(ish|adl|ehl|rpl), up_squared: fix include
paths
8d518ce504 boards: legacy: drop empty folders
0fef0cef5b boards: mps2: fix table formatting
e52ccc244f boards: add HWMv2 board index
c7426eca5e boards: arm: add legacy tag
1eba9d8a8f boards: acrn: create vendor folder
8d92edc727 tests: kernel: Adjust qemu_x86_tiny_768 configuration
HWMv2
75117d1b2d scripts: ensure posix path is used with --cmakeformat
0b0384b56a maintainers: update paths after HWMv2 changes
c1b77b223d boards: arm: pan1783: Convert to v2
91a077b2ab boards: posix: nrf_bsim: Update paths
413b6c2a40 cmake: modules: configuration_files: Add board identifier
overlay file
4f572ba24f treewide: Update board names for hwmv2
cb348c7edf boards: arm: nrf54l15pdk_nrf54l15: Convert to v2
811ad90566 boards: arm: nrf54h20pdk_nrf54h20: Convert to v2
d44ef90cf8 soc: nordic_nrf: Migrate nRF54H/nRF54L to v2 and fix nrf
c860f205de boards: arm: nrf9151dk_nrf9151: Convert to v2
fba98a1763 soc: nordic_nrf: Migrate nRF9151 to v2
5c156a2d35 boards: arm: 96b_carbon_nrf51: Convert to v2
cfc47a3a4b boards: arm: nrf9161dk_nrf9161: Convert to v2
37129b4e44 boards: arm: nrf9131ek_nrf9131: Convert to v2
a923beba5d boards: arm: bl5340_dvk: Convert to v2
d242b2703b boards: arm: raytac_mdbt53v_db_40_nrf5340: Convert to v2
9c80d4e644 boards: arm: raytac_mdbt53_db_40: Convert to v2
28268c4938 boards: arm: nrf5340_audio_dk_nrf5340: Convert to v2
33ad2b5bc6 boards: arm: thingy53_nrf5340: Convert to v2
40daa94f2d boards: arm: nrf9160_innblue22: Convert to v2
2b0dbb9d51 boards: arm: nrf9160_innblue21: Convert to v2
ee6f7697ac boards: arm: sparkfun_thing_plus_nrf9160: Convert to v2
594e4bad6b boards: arm: circuitdojo_feather_nrf9160: Convert to v2
a5803ba099 boards: arm: actinius_icarus: Convert to v2
db8c275456 boards: arm: actinius_icarus_bee: Convert to v2
30177cf53d boards: arm: actinius_icarus_som: Convert to v2
486504cf24 boards: arm: actinius_icarus_som_dk: Convert to v2
dd0672a64c boards: arm: nrf9160dk_*: Convert to v2
c1565b3d14 boards: arm: xiao_ble: Convert to v2
6dd2723314 boards: arm: qemu_cortex_m0: Convert to v2
ee1ce24a42 boards: arm: bbc_microbit: Convert to v2
1952d559f2 boards: arm: rm1xx_dvk: Convert to v2
9e12c3d8bd boards: arm: nrf51dongle_nrf51422: Convert to v2
0ffbc1da33 boards: arm: nrf51_blenano: Convert to v2
be52dfb7b6 boards: arm: nrf51_vbluno51: Convert to v2
4c29d1827f boards: arm: nrf51_ble400: Convert to v2
5b4a9556fd boards: arm: raytac_mdbt53_db_40_nrf5340: Fix typo
69e5d87a15 boards: arm: contextualelectronics_abc: Convert to v2
5e4ace1bbe boards: arm: degu_evk: Convert to v2
2762460a64 boards: arm: pan1781_evb: Convert to v2
fdc3913e76 boards: arm: ubx_evkninab1_nrf52832: Convert to v2
9c9c3a09a1 boards: arm: holyiot_yj16019: Convert to v2
109edc296f boards: arm: blueclover_plt_demo_v2_nrf52832: Convert to
v2
7bfcdbbe8f boards: arm: decawave_dwm1001_dev: Convert to v2
0fbb543983 boards: arm: acn52832: Convert to v2
073e0f8080 boards: arm: we_proteus2ev_nrf52832: Convert to v2
197a19f396 boards: arm: ebyte_e73_tbb_nrf52832: Convert to v2
1616fc8ae5 boards: arm: nrf52_vbluno52: Convert to v2
5622077738 boards: arm: nrf52_sparkfun: Convert to v2
a6289516e4 boards: arm: 96b_nitrogen: Convert to v2
439d836883 boards: arm: nrf52_blenano2: Convert to v2
16e65f09c4 boards: arm: arduino_nicla_sense_me: Convert to v2
862efd5a21 boards: arm: thingy52_nrf52832: Convert to v2
dede0f6cd3 boards: arm: nrf52_adafruit_feather: Convert to v2
91e864ea29 boards: arm: nrf52832_mdk: Convert to v2
47ec3e416b boards: arm: ruuvi_ruuvitag: Convert to v2
52f797a227 boards: arm: pinetime_devkit0: Convert to v2
433db339f9 boards: arm: ubx_evkannab1_nrf52832: Convert to v2
a646d3f2d5 boards: arm: ubx_bmd300eval_nrf52832: Convert to v2
d0d434bf86 cmake: print identifier instead of variant
c3f5ed8157 boards: arm: we_proteus3ev_nrf52840: Convert to v2
eecff8ee7a boards: arm: nrf52840_mdk_usb_dongle: Convert to v2
34507614f6 boards: arm: nrf52840_mdk: Convert to v2
f02b56cb96 boards: arm: nrf52840_blip: Convert to v2
600c55c92a boards: arm: nrf52840_papyr: Convert to v2
f294bfc5e4 boards: arm: reel_board: Convert to v2
882524d2a0 boards: arm: nrf21540dk_nrf52840: Convert to v2
4bce0e9b39 boards: arm: nrf52840dongle_nrf52840: Convert to v2
d0229c771f boards: arm: particle_argon: Convert to v2
23a0570e64 boards: arm: particle_boron: Convert to v2
b6d3e1764f boards: arm: particle_xenon: Convert to v2
499f3e7902 boards: arm: rak5010_nrf52840: Convert to v2
9ae6b1804d boards: arm: rak4631_nrf52840: Convert to v2
fe2c90da5c boards: arm: pinnacle_100_dvk: Convert to v2
3d4d46698c boards: arm: ubx_evkninab3_nrf52840: Convert to v2
b1afbf0158 boards: arm: ubx_bmd380eval_nrf52840: Convert to v2
9f9897c872 boards: arm: ubx_bmd345eval_nrf52840: Convert to v2
f7fb2030c7 boards: arm: ubx_bmd340eval_nrf52840: Convert to v2
7186432662 boards: arm: raytac_mdbt50q_db_40_nrf52840: Convert to v2
32c4bdc0c4 boards: arm: pan1780_evb: Convert to v2
7b64c638a8 boards: arm: pan1770_evb: Convert to v2
156ee8ad8a boards: arm: mg100: Convert to v2
3d33dadeb0 boards: arm: arduino_nano_33_ble: Convert to v2
4fee7371d2 boards: arm: adafruit_itsybitsy_nrf52840: Convert to v2
ad37a0c222 boards: arm: adafruit_feather_nrf52840: Convert to v2
cf85b7169f boards: arm: bt510: Convert to v2
44b67ac430 boards: arm: bt610: Convert to v2
7dbb65d371 boards: arm: ubx_evkninab4_nrf52833: Convert to v2
5e79cb957d boards: arm: raytac_mdbt50q_db_33_nrf52833: Convert to v2
12bd83a218 boards: arm: pan1782_evb: Convert to v2
1a135ec352 boards: arm: bbc_microbit_v2: Convert to v2
4dbe97e5ea boards: arm: nrf52833dk: Convert to v2
d632b90043 boards: arm: ubx_bmd360eval_nrf52811: Convert to v2
cc1a30f24b boards: arm: we_ophelia1ev_nrf52805: Convert to v2
df0df9000b boards: arm: ubx_bmd330eval_nrf52810: Convert to v2
d2c7972a9a boards: arm: nrf52dk: Convert to v2
202c2bf447 boards: arm: bl654_sensor_board: Convert to v2
c3e36f2042 boards: arm: bl654_usb: Convert to v2
b9dd58aea1 boards: arm: bl654_dvk: Convert to v2
0e1898b093 boards: arm: bl653_dvk: Convert to v2
286f4a7524 boards: arm: bl652_dvk: Convert to v2
d1709cdb37 boards: update nRF51dk board to board scheme v2.
8f040cff2c boards: Update nrf5340dk_nrf5340 to HWMv2 scheme
8c90fae8e0 boards: update nRF52840dk_nrf52840/nrf52811 board to
board scheme v2.
c828dcc60e boards: common: openocd-nrf5: Add HWMv2 support
c79f1b0d94 kconfig: soc: adopt Nordic SoC series to support hw model
v2 scheme
3584b30fc1 tests: Update board names for hwmv2
94024d940e boards: arm: arty_a7: Convert to v2
8053c3a8df boards: arm: scobc_module1: Convert to v2
d5473b76fe soc: designstart: Port to HWMv2
f5792b05e7 boards: arm: fvp_baser_aemv8r_aarch32: Convert to v2
ff202daa8e soc: fvp_aemv8r_aarch32: Port to HWMv2
e66cbc2945 boards: arm: v2m_musca_s1: Convert to v2
33b47b2edb boards: arm: v2m_musca_b1: Convert to v2
baeebd31d2 soc: musca: Port to HWMv2
73b257a3f9 boards: arm: v2m_beetle: Convert to v2
85de0888ec soc: beetle: Port to HWMv2
867960a891 manifest: Update modules
6ca677ed3a boards: arm: mps2: Convert to v2
bcf4ad19d4 twister: build_dir: convert / to _ to support hwmv2
0ac386683f soc: Kconfig.v2: Add SOC_PART_NUMBER
9242c3c78f soc: stm32: soc.yml: reorder series
248d17f160 boards: stm32: cleanup
0a67265e99 boards: stm32: fix for boards with revisions
f8d44317ee soc: stm32l5: Rename overlays for nucleo_l552ze_q ns
target.
400343d17e soc: stm32: Set default on USE_DT_CODE_PARTITION
d783ef549a soc: stm32l5: Update stm32l5 non secure targets in
various places
643aeac552 boards: Convert stm32l562e_dk to HWM v2
e601d64344 boards: Convert nucleo_l552ze_q to HWM v2
2f7a387b32 soc: st: Migrate stm32l5 series to new hw model
519752efcd boards: xenvm: doc: Remove reference to deleted file
06263dd717 boards: xenvm: Unset HEAP_MEM_POOL_SIZE in gicv3 variant
66b0df5526 boards: qemu_cortex_a53: Fix Kconfig warnings in SMP
variant
fa07bd9419 boards: mps3: Fix non-secure variant
8f6f0726dd boards: Move xenvm under xen
7b155a7031 boards: Raspberry Pi vendor fix
804697afa5 boards: Move 96b_aerocore to 96boards
d2f001e320 boards: x86: acrn: move and convert to HWMv2
ec7f7b3c30 tests: kernel: qemu_x86: adjust to the HWMv2
89dfcddc7e boards: x86: qemu_x86_tiny@768: change to board variant
eb724eb6a7 boards: x86: qemu_x86: optimize default HWMv2
configurations
6f1043cde6 boards: x86: qemu_x86: move and convert to HWMv2
cab924cbfb soc: x86: ia32: move and convert to HWMv2
237fdff918 soc: x86: lakemont: move and convert to HWMv2
03042b7704 boards: move 96b_carbon to 96boards folder
767b94414e boards: rename vendor seeed to seeed_studio
07fa3a3d79 boards: Convert olimex_lora_stm32wl_devkit to HWM v2
ba01d3beca boards: Convert nucleo_wl55jc to HWM v2
7ce84f4041 boards: Convert lora_e5_mini to HWM v2
b988bae576 boards: Convert lora_e5_dev_board to HWM v2
6fbf39c726 soc: v2: stm32: Migrate STM32WL series
4a41878442 soc: st: stm32g4: add missing include
1e79ba15f6 boards: Convert weact_stm32g431_core to HWM v2
ffdcb60185 boards: Convert nucleo_g474re to HWM v2
d6acb08d3e boards: Convert nucleo_g431rb to HWM v2
90e592ffd1 boards: Convert b_g474e_dpow1 to HWM v2
eb8a7e3441 soc: st: stm32: Migrate STM32G4 series
ada469f237 tests: Update board names for hwmv2
0342433187 boards: arm: npcx9m6f_evb: Convert to v2
c10248d964 boards: arm: npcx7m6fb_evb: Convert to v2
21ddc5e6a6 boards: arm: npcx4m8f_evb: Convert to v2
5500f3ef21 soc: npcx*: Port to HWMv2
e7baf09ede soc: m48x: Port to HWMv2
5bae4a6480 boards: arm: numaker_pfm_m467: Convert to v2
3b0bd70c8c soc: m46x: Port to HWMv2
d52eab9e83 boards: Convert stm32g081b_eval to HWM v2
6f2835cb11 boards: Convert stm32g071b_disco to HWM v2
ca36d331d2 boards: Convert stm32g0316_disco to HWM v2
662cc4e09b boards: Convert nucleo_g0b1re to HWM v2
dd9bc29769 boards: Convert nucleo_g071rb to HWM v2
353da23ffb boards: Convert nucleo_g070rb to HWM v2
acc932b424 boards: Convert nucleo_g031k8 to HWM v2
cea9b140fd boards: Convert google_twinkie_v2 to HWM v2
52e025943a soc: st: stm32: Migrate STM32G0 series
1c7347686a ci: update check_compliance to not create duplicate lines
in Kconfig
9debd98799 hwmv2: boards: up_squared_pro_700: Add missed intel_adl
changes
adab07c42f boards: Convert msp_exp432p401r_launchxl to HWM v2
642aacdcdf soc: ti_simplelink: Add missing SoC
48637066d3 boards: Fix file paths in documentation
e983bc2a23 samples/tests: Fix mps3 board name
61e0f32716 boards: Convert stm32f3_seco_d23 to HWM v2
a1688ff641 boards: Convert stm32f3_disco to HWM v2
35fb228599 boards: Convert stm32373c_eval to HWM v2
10e5d1122b boards: Convert nucleo_f334r8 to HWM v2
c319cb19f0 boards: Convert nucleo_f303re to HWM v2
11725ccac1 boards: Convert nucleo_f303k8 to HWM v2
400f7f6a4f boards: Convert nucleo_f302r8 to HWM v2
8d84861390 soc: v2: stm32: Migrate STM32F3 series
85b9eee7e8 boards: arm: kv260_r5: Convert to v2
dafbd638e4 boards: arm: mercury_xu: Convert to v2
3ecd12f415 boards: arm: qemu_cortex_r5: Convert to v2
5db2390e9d soc: xilinx_zyncmp: Port to HWMv2
9ba8195cdc boards: arm: qemu_cortex_a9: Convert to v2
8e94b85361 boards: arm: zybo: Convert to v2
c970127fc2 soc: xilinx_zynq7000: Port to HWMv2
394c75373c boards: arm: ast1030_evb: Convert to v2
f2a1cc8714 soc: ast10x0: Port to HWMv2
28f3f25945 boards: arm: cc3235sf_launchxl: Convert to v2
c3e480f740 boards: arm: cc3220sf_launchxl: Convert to v2
fd5847123f boards: arm: beagleconnect_freedom: Convert to v2
76ba9a0587 boards: arm: cc1352p1_launchxl: Convert to v2
719baa8850 boards: arm: cc1352r1_launchxl: Convert to v2
5060a61ae1 boards: arm: cc1352r_sensortag: Convert to v2
99584be1c5 boards: arm: cc26x2r1_launchxl: Convert to v2
2dc8933942 soc: ti_simplelink: Port to HWMv2
a5b004663b scripts/utils/board_v1_to_v2.py: couple of fixes
77c2c333e5 boards: move 96b_stm32_sensor_mez to 96boards
c14ff98650 boards: stm32f411e_disco: delete obsolete file
bcdc268ccf boards: Convert stm32mp157c_dk2 to HWM v2
0c8ba92e1f boards: Convert 96b_avenger96 to HWM v2
b54fe33077 soc: v2: stm32: Migrate STM32MP1 series
2ba3639b2a boards: Convert nucleo_c031c6 to HWM v2
dbc5ed79f5 soc: st: stm32: Migrate STM32C0 series
ce6d493aa3 boards: Convert stm32l1_disco to HWM v2
a28086a9ca boards: Convert nucleo_l152re to HWM v2
1b2a511d06 boards: Convert 96b_wistrio to HWM v2
ce281f09ab soc: v2: stm32: Migrate STM32L1 series
cdb5364fd7 boards: Convert stm32f769i_disco to HWM v2
768f173dcb boards: Convert stm32f7508_dk to HWM v2
21bbbbd9cb boards: Convert stm32f746g_disco to HWM v2
bab4265693 boards: Convert stm32f723e_disco to HWM v2
58f8fe82ba boards: Convert nucleo_f767zi to HWM v2
37e9084070 boards: Convert nucleo_f756zg to HWM v2
d467e7053a boards: Convert nucleo_f746zg to HWM v2
5f2808d7cc boards: Convert nucleo_f722ze to HWM v2
bbb73e7550 soc: st: Migrate stm32f7 series to new hw model
e9094afc4d soc: st: stm32: stm32f4: change SOC_STM32F405XG to
SOC_STM32F405XX
a1712cdd53 boards: Convert stm32f4_disco to HWM v2
5be404b365 boards: Convert stm32f469i_disco to HWM v2
baaa697ab2 boards: Convert stm32f429i_disc1 to HWM v2
69ecab3c90 boards: Convert stm32f412g_disco to HWM v2
2a572e3fb0 boards: Convert stm32f411e_disco to HWM v2
ecfbf42757 boards: Convert stm32f401_mini to HWM v2
e0191d03bb boards: Convert steval_fcu001v1 to HWM v2
4454648976 boards: Convert segger_trb_stm32f407 to HWM v2
f0ad6ee6b8 boards: Convert olimex_stm32_p405 to HWM v2
1f5e228ec8 boards: Convert olimex_stm32_h407 to HWM v2
834bdb615e boards: Convert olimex_stm32_h405 to HWM v2
8f27fa8de2 boards: Convert olimex_stm32_e407 to HWM v2
f8633a9038 boards: Convert nucleo_f446ze to HWM v2
07e0bd2c07 boards: Convert nucleo_f446re to HWM v2
24d7f625dc boards: Convert nucleo_f429zi to HWM v2
157a8cde53 boards: Convert nucleo_f413zh to HWM v2
4ec99c31b0 boards: Convert nucleo_f412zg to HWM v2
a21546140a boards: Convert nucleo_f411re to HWM v2
43f01ab6de boards: Convert nucleo_f410rb to HWM v2
60c16bcb8b boards: Convert nucleo_f401re to HWM v2
2db228d730 boards: Convert mikroe_mini_m4_for_stm32 to HWM v2
73fc26225c boards: Convert mikroe_clicker_2 to HWM v2
6b62d90114 boards: Convert google_dragonclaw to HWM v2
fa845af309 boards: Convert blackpill_f411ce to HWM v2
5c8c3c3be0 boards: Convert blackpill_f401ce to HWM v2
3c02db1290 boards: Convert blackpill_f401cc to HWM v2
7eeb723cb7 boards: Convert black_f407zg_pro to HWM v2
4f9461d068 boards: Convert black_f407ve to HWM v2
a821de8532 boards: Convert az3166_iotdevkit to HWM v2
ba580c7236 boards: Convert adi_sdp_k1 to HWM v2
eb272ddf19 boards: Convert adafruit_feather_stm32f405 to HWM v2
58ed121c3a boards: Convert 96b_stm32_sensor_mez to HWM v2
b0d70959d3 boards: Convert 96b_neonkey to HWM v2
b1088baadc boards: Convert 96b_carbon to HWM v2
18d867b0a9 boards: Convert 96b_argonkey to HWM v2
ee6ede7119 boards: Convert 96b_aerocore2 to HWM v2
b48e70ead9 soc: v2: stm32: Migrate STM32F4 series
14d2b955da cmake: convert path to CMake style before writing Kconfig
files
9c4ac6a202 boards: posix: bsim: Update paths
14b57f56d7 tests: drivers: gpio: gpio_ite_it8xxx2_v2: Temp fix
f3b173be18 scripts: board_v1_to_v2: Update following move to
boards_legacy
05b50f6691 cmake: CMake soc dir variable improvements for HWMv2
a188e01a12 hwmv2: move all ported boards and socs to their final
location
22c53e97b5 hwmv2: move all non-ported legacy boards and socs to
legacy folders
53f3b181b0 soc: ti_k3: Port to HWMv2
9f19a2075a soc: rk3568: Port to HWMv2
b8928b1628 soc: rk3399: Port to HWMv2
cda3a74868 boards: arm64: qemu_kvm_arm64: Convert to v2
70d704bd20 soc: x86: atom: move and convert to HWMv2
4789e1068e boards: x86: intel_rpl: move and convert raptor_lake
boards to HWMv2
384307e3dc soc: x86: raptor_lake: move and convert to HWMv2
ed025df674 boards: x86: intel_ehl: move and convert elkhart_lake
boards to HWMv2
994b6e1731 soc: x86: elkhart_lake: move and convert to HWMv2
73b30a04cf boards: x86: up_squared_pro_7000: move and convert to
HWMv2
83b133c207 boards: x86: intel_adl: move and convert alder_lake
boards to HWMv2
847a12f1e4 soc: alder_lake: move and convert to HWMv2
67f4c8d2a1 samples: up_squared: adjust gpio_counter to HWMv2
5326b5bfc0 boards: x86: up_squared: move and convert to HWMv2
cfd5e691b4 soc: apollo_lake: move and convert to HWMv2
ac9c235741 boards: xtensa: qemu_xtensa: Convert to v2
f198c3a761 ci: update to osource for soc/Kconfig.defconfig files
e438e6cad4 ci: add SOC_SERIES_ as false positive in
check_compliance.py
95e34da7c1 soc: v2: Convert st_stm32 to st/stm32
313717df76 soc: mps3: Fix missing family
392c3969ed boards: arm: am62x_m4: Convert to v2
8f245d764d tests: Update board names for hwmv2
8f71bb7b4f boards: arm64: khadas_edgev: Convert to v2
e27d23aad0 soc: rk3399: Port to HWMv2
80823b860e boards: arm64: roc_rk3568_pc: Convert to v2
72e4483dec soc: rk3568: Port to HWMv2
bed94669e3 boards: arm64: phycore_am62x_a53: Convert to v2
c01af5a7b8 soc: ti_k3: Port to HWMv2
1e563b4ca3 boards: arm64: xenvm: Convert to v2
76e484adae soc: xenvm: Port to HWMv2
34412f7fe2 boards: arm64: rpi_4b: Convert to v2
9be50e2ca9 soc: bcm2711: Port to HWMv2
bbbed12c2f boards: arm64: qemu_kvm_arm64: Convert to v2
4f5ec7ff8f soc: qemu_virt_arm64: Port to HWMv2
d8d1b9f200 boards: arm64: qemu_cortex_a53: Convert to v2
30bd34b31e soc: qemu_cortex_a53: Port to HWMv2
c20d0dcbb6 boards: arm64: fvp_baser_aemv8r: Convert to v2
02ed6af463 boards: arm64: fvp_base_revc_2xaemv8a: Convert to v2
1b175003a4 soc: fvp_aemv8*: Port to HWMv2
de231b911d boards: v2: Clean up obsolete comments
aa9597f6d9 boards: Convert waveshare_open103z to HWM v2
9644828c81 boards: Convert stm32vl_disco to HWM v2
86ab2bd430 boards: Convert stm32_min_dev to HWM v2
d88d3ddcc4 boards: Convert stm32f103_mini to HWM v2
0ccc0204e1 boards: Convert stm3210c_eval to HWM v2
dd9972d782 boards: Convert olimex_stm32_h103 to HWM v2
a2c2e1406d boards: Convert olimexino_stm32 to HWM v2
2d9c62e118 boards: Convert nucleo_f103rb to HWM v2
e8ba99dc59 soc: v2: stm32: Migrate STM32F1 series
9a93916604 tests: Update board names for hwmv2
9c4d94844d boards: arm: bcm958401m2: Convert to v2
feaf4ffba1 boards: arm: bcm958402m2: Convert to v2
87f0827121 soc: bcm_vk: Port to HWMv2
4526be24a5 boards: arm: quick_feather: Convert to v2
cd921d2b97 boards: arm: qomu: Convert to v2
b3c04051fc soc: quicklogic_eos_s3: Port to HWMv2
a73a9e7533 boards: v2: Clean up obsolete comments
8d87bcc167 boards: Convert stm32f0_disco to HWM v2
1933585785 boards: Convert stm32f072_eval to HWM v2
6f9fe5429d boards: Convert stm32f072b_disco to HWM v2
9dc78e4025 boards: Convert stm32f030_demo to HWM v2
35113e8923 boards: Convert nucleo_f091rc to HWM v2
b276aee9a4 boards: Convert nucleo_f070rb to HWM v2
795f8d611b boards: Convert nucleo_f042k6 to HWM v2
2d82646443 boards: Convert nucleo_f031k6 to HWM v2
959786f12d boards: Convert nucleo_f030r8 to HWM v2
81670db2e9 boards: Convert legend to HWM v2
8980430aad boards: Convert google_kukui to HWM v2
ac020f66e0 dts: stm32f0: fix few warnings
5140e4551a boards: v2: doc: Add vendors
77d640e0c9 soc: v2: stm32: Migrate STM32F0 series
0131e1c159 soc: v2: Add st_stm32 structure and common folder
36b63787a7 boards: v2: Add documentation index for converted boards
ae02fc5047 boards: sparc: qemu_leon3: Convert to v2
f38f7bb223 boards: sparc: gr716a: Convert to v2
d3cca3580e soc: gr716a: Port to HWMv2
6a8a0c1647 boards: sparc: generic_leon3: Convert to v2
faf22185ce soc: leon3: Port to HWMv2
e94762ecdc tests: Update board names for hwmv2
9afcc27e05 boards: xtensa: qemu_xtensa: Convert to v2
3e4a17018f soc: dc233c: Port to HWMv2
9188fdcd78 boards: xtensa: xt-sim: Convert to v2
fcaa41cb5d soc: xtensa_sample_controller: Port to HWMv2
dbc413f7f7 scripts: board_v1_to_v2: Fix CONFIG_SOC_SERIES_ exclusion
6be3d4bc80 kconfig: remove Kconfig BOARD_RPI_PICO_W safe guard.
f4442fa698 boards: v2: Add documentation index for converted boards
ec5fbd67f7 boards: nios2: qemu_nios2: Convert to v2
d3ef220460 soc: nios2-qemu: Port to HWMv2
a223f284b5 boards: nios2: altera_max10: Convert to v2
c381edcb73 soc: nios2f-zephyr: Port to HWMv2
97401c7d2a boards: mips: qemu_malta: Convert to v2
e7a3243a24 soc: qemu_malta: Port to HWMv2
bec82c690d boards: v2: Add documentation index for converted boards
94f6f9b636 boards: arm: w5500_evb_pico: Convert to v2
209235ab6e boards: arm: sparkfun_pro_micro_rp2040: Convert to v2
e5b1885907 boards: arm: adafruit_qt_py_rp2040: Convert to v2
4c750818f9 boards: arm: adafruit_kb2040: Convert to v2
8d3896caa4 boards: arm: rpi_pico: Convert to v2
42cff42c42 soc: rpi_pico: Port to HWMv2
c2df4ca9cb scripts: improve yaml schema and board.yml validation for
revisions
3970f90f71 cmake: clear BOARD_CACHE when invalid board identifier is
given
3a70ee9ccd cmake: improve board revision handling
3cda715fae scripts: board_v1_to_v2: Don't add select
CONFIG_SOC_SERIES_FOO
dc56a543f3 scripts: board_v1_to_v2: Add License + copyright
87147f88c4 cmake: prefer cache BOARD_IDENTIFIER over extracting from
BOARD
65f5dc5b8c cmake: fail when board identifier is applied in legacy hw
model
7db2b6efd8 cmake: cache BOARD_IDENTIFIER to preserve it between
CMake invocations
85dddac5a2 scripts: using extend in list_boards for variant list
6ae5c4e7fd scripts: utils: add board v1->v2 conversion utility
ef834a12d0 maintainers: update Renesas RZT2M path
3ab7830625 boards: renesas: add documentation entry
a0c2ca0491 boards: arm: add documentation entry
27ff3654b7 boards: gigadevice: add documentation entry
6e02f43c0a maintainers: update GD32 paths
1bfcf1d974 boards: gd32l233r_eval: convert to HWMv2
6e621ee43f boards: gd32f470i_eval: convert to HWMv2
219b149768 boards: gd32f450z_eval: convert to HWMv2
91c52b0d39 boards: gd32f450v_start: convert to HWMv2
f0e0a973f6 boards: gd32f407v_start: convert to HWMv2
6f592b64c9 boards: gd32f403z_eval: convert to HWMv2
4bcb4b2ac8 boards: gd32f350r_eval: convert to HWMv2
fdc7ed6eb0 boards: gd32e507z_eval: convert to HWMv2
770376250d boards: gd32e507v_start: convert to HWMv2
a6d8b92e86 boards: gd32e103v_eval: convert to HWMv2
a5f8e5daa1 boards: gd32a503v_eval: convert to HWMv2
5ee799cc5f boards: gd32f450i_eval: convert to HWMv2
8aa8ce4ac8 soc: gigadevice: port to HWMv2
4e203c14c7 cmake: enhanced board entry file handling
312265ee04 scripts: make SoC field mandatory in board.yml
c12ae3bcbc boards: update Renesas rzt2m board.yml to contain SoC
information
c5321c1dbe cmake: make SoC optional for boards containing a single
SoC
bcc06c60ae scripts: support SoC list output for boards
db9e46010c twister: update testcase.yaml and sample.yaml to
mps3/an547 identifier
a988adee7d boards: update arm mps3 an547 board to HWMv2 scheme
7dc2c9db0c soc: use HWMv2 for arm mps3 SoC
c506675b7c boards: update Renesas Starter Kit+ for RZ/T2M board to
HWMv2 scheme
3abb792073 soc: use HWMv2 for renesas_rzt2m SoC
4f52bc646e cmake: support hw model v2 in arch/Kconfig tree
a712b5005b scripts: extend kconfig compliance to verify board / SoC
scheme v2
baa55141a1 twister: update twister testplan.py to handle HWMv2
boards
1f026f70eb boards: extend list_boards.py and update boards CMake
module
bd854a3af8 cmake: introduce arch and soc cmake modules for hw model
v2
c9edefa8fd arch: add existing archs to archs.yml for HWMv2 support
61bbfb5ba2 scripts: introduce list_hardware.py for listing of
architectures and SoCs
a4d1980c35 build: board/ soc: introduce hw model v2 scheme
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
Signed-off-by: David Leach <david.leach@nxp.com>
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This commit is contained in:
Torsten Rasmussen
Anas Nashif
parent
418b0a1e65
commit
8dc3f85622
13315 changed files with 159282 additions and 157416 deletions
5
soc/espressif/CMakeLists.txt
Normal file
5
soc/espressif/CMakeLists.txt
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# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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add_subdirectory(common)
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add_subdirectory(${SOC_SERIES})
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8
soc/espressif/Kconfig
Normal file
8
soc/espressif/Kconfig
Normal file
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# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_FAMILY_ESPRESSIF_ESP32
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rsource "*/Kconfig"
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endif # SOC_FAMILY_ESPRESSIF_ESP32
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8
soc/espressif/Kconfig.defconfig
Normal file
8
soc/espressif/Kconfig.defconfig
Normal file
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# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_FAMILY_ESPRESSIF_ESP32
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rsource "*/Kconfig.defconfig"
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endif # SOC_FAMILY_ESPRESSIF_ESP32
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10
soc/espressif/Kconfig.soc
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10
soc/espressif/Kconfig.soc
Normal file
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# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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config SOC_FAMILY_ESPRESSIF_ESP32
|
||||
bool
|
||||
|
||||
config SOC_FAMILY
|
||||
default "espressif_esp32" if SOC_FAMILY_ESPRESSIF_ESP32
|
||||
|
||||
rsource "*/Kconfig.soc"
|
||||
6
soc/espressif/common/CMakeLists.txt
Normal file
6
soc/espressif/common/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if(CONFIG_SOC_SERIES_ESP32 OR CONFIG_SOC_SERIES_ESP32S2 OR CONFIG_SOC_SERIES_ESP32S3)
|
||||
zephyr_include_directories(include)
|
||||
endif()
|
||||
215
soc/espressif/common/Kconfig
Normal file
215
soc/espressif/common/Kconfig
Normal file
|
|
@ -0,0 +1,215 @@
|
|||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config ESPTOOLPY_FLASHFREQ_80M
|
||||
bool
|
||||
|
||||
config FLASH_SIZE
|
||||
int
|
||||
|
||||
config FLASH_BASE_ADDRESS
|
||||
hex
|
||||
|
||||
if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
|
||||
|
||||
config ESP_SPIRAM
|
||||
bool "Support for external, SPI-connected RAM"
|
||||
help
|
||||
This enables support for an external SPI RAM chip, connected in
|
||||
parallel with the main SPI flash chip.
|
||||
|
||||
config ESP_HEAP_MIN_EXTRAM_THRESHOLD
|
||||
int "Minimum threshold for external RAM allocation"
|
||||
default 8192
|
||||
range 1024 131072
|
||||
depends on ESP_SPIRAM
|
||||
help
|
||||
Threshold to decide if memory will be allocated from DRAM
|
||||
or SPIRAM. If value of allocation size is less than this value,
|
||||
memory will be allocated from internal RAM.
|
||||
|
||||
config ESP_HEAP_SEARCH_ALL_REGIONS
|
||||
bool "Search for all available heap regions"
|
||||
depends on ESP_SPIRAM
|
||||
default y
|
||||
help
|
||||
This configuration enables searching all available heap
|
||||
regions. If the region of desired capability is exhausted,
|
||||
memory will be allocated from other available region.
|
||||
|
||||
config ESP_SPIRAM_HEAP_SIZE
|
||||
int "Size of SPIRAM heap"
|
||||
default 262134 if SYS_HEAP_SMALL_ONLY
|
||||
default 1048576 if !SYS_HEAP_SMALL_ONLY
|
||||
depends on ESP_SPIRAM
|
||||
help
|
||||
Specify size of SPIRAM heap.
|
||||
|
||||
menu "SPI RAM config"
|
||||
depends on ESP_SPIRAM
|
||||
|
||||
choice SPIRAM_MODE
|
||||
prompt "Mode (QUAD/OCT) of SPI RAM chip in use"
|
||||
default SPIRAM_MODE_QUAD
|
||||
|
||||
config SPIRAM_MODE_QUAD
|
||||
bool "Quad Mode PSRAM"
|
||||
|
||||
endchoice # SPIRAM_MODE
|
||||
|
||||
choice SPIRAM_TYPE
|
||||
prompt "Type of SPI RAM chip in use"
|
||||
depends on ESP_SPIRAM
|
||||
default SPIRAM_TYPE_ESPPSRAM16
|
||||
|
||||
config SPIRAM_TYPE_ESPPSRAM16
|
||||
bool "ESP-PSRAM16 or APS1604"
|
||||
|
||||
config SPIRAM_TYPE_ESPPSRAM32
|
||||
bool "ESP-PSRAM32 or IS25WP032"
|
||||
|
||||
config SPIRAM_TYPE_ESPPSRAM64
|
||||
bool "ESP-PSRAM64 or LY68L6400"
|
||||
|
||||
endchoice # SPIRAM_TYPE
|
||||
|
||||
config ESP_SPIRAM_SIZE
|
||||
int "Size of SPIRAM part"
|
||||
default 2097152 if SPIRAM_TYPE_ESPPSRAM16
|
||||
default 4194304 if SPIRAM_TYPE_ESPPSRAM32
|
||||
default 8388608 if SPIRAM_TYPE_ESPPSRAM64
|
||||
help
|
||||
Specify size of SPIRAM part.
|
||||
NOTE: If SPIRAM size is greater than 4MB, only
|
||||
lower 4MB can be allocated using k_malloc().
|
||||
|
||||
choice SPIRAM_SPEED
|
||||
prompt "Set RAM clock speed"
|
||||
default SPIRAM_SPEED_40M
|
||||
help
|
||||
Select the speed for the SPI RAM chip.
|
||||
If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now:
|
||||
|
||||
1. Flash SPI running at 40MHz and RAM SPI running at 40MHz
|
||||
2. Flash SPI running at 80MHz and RAM SPI running at 40MHz
|
||||
3. Flash SPI running at 80MHz and RAM SPI running at 80MHz
|
||||
|
||||
Note: If the third mode(80MHz+80MHz) is enabled for SPI RAM of type 32MBit, one of the HSPI/VSPI host
|
||||
will be occupied by the system. Which SPI host to use can be selected by the config item
|
||||
SPIRAM_OCCUPY_SPI_HOST. Application code should never touch HSPI/VSPI hardware in this case. The
|
||||
option to select 80MHz will only be visible if the flash SPI speed is also 80MHz.
|
||||
(ESPTOOLPY_FLASHFREQ_79M is true)
|
||||
|
||||
config SPIRAM_SPEED_26M
|
||||
bool "26MHz clock speed"
|
||||
depends on SOC_SERIES_ESP32S2
|
||||
|
||||
config SPIRAM_SPEED_20M
|
||||
bool "20MHz clock speed"
|
||||
depends on SOC_SERIES_ESP32S2
|
||||
|
||||
config SPIRAM_SPEED_40M
|
||||
bool "40MHz clock speed"
|
||||
|
||||
config SPIRAM_SPEED_80M
|
||||
depends on ESPTOOLPY_FLASHFREQ_80M
|
||||
bool "80MHz clock speed"
|
||||
|
||||
config SPIRAM_SPEED_120M
|
||||
depends on SPIRAM_MODE_QUAD && SOC_SERIES_ESP32S3
|
||||
bool "120MHz clock speed"
|
||||
|
||||
endchoice # SPIRAM_SPEED
|
||||
|
||||
menu "PSRAM clock and cs IO for ESP32-DOWD"
|
||||
|
||||
config D0WD_PSRAM_CLK_IO
|
||||
int "PSRAM CLK IO number"
|
||||
range 0 33
|
||||
default 17
|
||||
help
|
||||
The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use
|
||||
1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
|
||||
|
||||
config D0WD_PSRAM_CS_IO
|
||||
int "PSRAM CS IO number"
|
||||
range 0 33
|
||||
default 16
|
||||
help
|
||||
The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use
|
||||
1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
|
||||
|
||||
endmenu # PSRAM clock and cs IO for ESP32-DOWD
|
||||
|
||||
menu "PSRAM clock and cs IO for ESP32-D2WD"
|
||||
|
||||
config D2WD_PSRAM_CLK_IO
|
||||
int "PSRAM CLK IO number"
|
||||
range 0 33
|
||||
default 9
|
||||
help
|
||||
User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
|
||||
so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
|
||||
|
||||
config D2WD_PSRAM_CS_IO
|
||||
int "PSRAM CS IO number"
|
||||
range 0 33
|
||||
default 10
|
||||
help
|
||||
User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
|
||||
so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
|
||||
|
||||
endmenu # PSRAM clock and cs IO for ESP32-D2WD
|
||||
|
||||
menu "PSRAM clock and cs IO for ESP32-PICO"
|
||||
|
||||
config PICO_PSRAM_CS_IO
|
||||
int "PSRAM CS IO number"
|
||||
range 0 33
|
||||
default 10
|
||||
help
|
||||
The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
|
||||
|
||||
For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock
|
||||
IO.
|
||||
For the reference hardware design, please refer to
|
||||
https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf
|
||||
|
||||
endmenu # PSRAM clock and cs IO for ESP32-PICO
|
||||
|
||||
config SPIRAM_CUSTOM_SPIWP_SD3_PIN
|
||||
bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)"
|
||||
default y if SPIRAM_SPIWP_SD3_PIN != 7 # backwards compatibility, can remove in IDF 5
|
||||
default n
|
||||
help
|
||||
This setting is only used if the SPI flash pins have been overridden by setting the eFuses
|
||||
SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT.
|
||||
|
||||
When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
|
||||
ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI
|
||||
mode, so a WP pin setting is necessary.
|
||||
|
||||
If this config item is set to N (default), the correct WP pin will be automatically used for any
|
||||
Espressif chip or module with integrated flash. If a custom setting is needed, set this config item
|
||||
to Y and specify the GPIO number connected to the WP pin.
|
||||
|
||||
When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin
|
||||
configured in the bootloader.
|
||||
|
||||
config SPIRAM_SPIWP_SD3_PIN
|
||||
int "Custom SPI PSRAM WP(SD3) Pin"
|
||||
range 0 33
|
||||
default 7
|
||||
help
|
||||
The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored
|
||||
|
||||
If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this
|
||||
value to the GPIO number of the SPIRAM WP pin.
|
||||
|
||||
config SPIRAM
|
||||
bool
|
||||
default y
|
||||
|
||||
endmenu # SPI RAM config
|
||||
|
||||
endif # SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
|
||||
103
soc/espressif/common/Kconfig.defconfig
Normal file
103
soc/espressif/common/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_ESP32C3
|
||||
|
||||
config GEN_ISR_TABLES
|
||||
default y
|
||||
|
||||
config GEN_SW_ISR_TABLE
|
||||
default y
|
||||
|
||||
config GEN_IRQ_VECTOR_TABLE
|
||||
default n
|
||||
|
||||
config DYNAMIC_INTERRUPTS
|
||||
default y
|
||||
|
||||
config ISR_STACK_SIZE
|
||||
default 2048
|
||||
|
||||
config ATOMIC_OPERATIONS_C
|
||||
default y
|
||||
|
||||
config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
|
||||
default n
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default 16000000
|
||||
|
||||
config SYS_CLOCK_TICKS_PER_SEC
|
||||
default 1000
|
||||
|
||||
config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
|
||||
default n
|
||||
|
||||
config CLOCK_CONTROL
|
||||
default y
|
||||
|
||||
if BOOTLOADER_MCUBOOT
|
||||
|
||||
config HAS_FLASH_LOAD_OFFSET
|
||||
default y
|
||||
|
||||
config MCUBOOT_GENERATE_UNSIGNED_IMAGE
|
||||
default y
|
||||
|
||||
config MCUBOOT_GENERATE_CONFIRMED_IMAGE
|
||||
default y
|
||||
|
||||
config ROM_START_OFFSET
|
||||
default 0x20
|
||||
|
||||
endif # BOOTLOADER_MCUBOOT
|
||||
|
||||
endif # SOC_SERIES_ESP32C3
|
||||
|
||||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
|
||||
|
||||
# Xtensa default options for ESP32 family
|
||||
config XTENSA_RESET_VECTOR
|
||||
default n
|
||||
|
||||
config XTENSA_USE_CORE_CRT1
|
||||
default n
|
||||
|
||||
config GEN_ISR_TABLES
|
||||
default y
|
||||
|
||||
config GEN_IRQ_VECTOR_TABLE
|
||||
default n
|
||||
|
||||
config CLOCK_CONTROL
|
||||
default y
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
|
||||
|
||||
config XTENSA_CCOUNT_HZ
|
||||
default SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
|
||||
config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
|
||||
default n
|
||||
|
||||
if BOOTLOADER_MCUBOOT
|
||||
|
||||
config HAS_FLASH_LOAD_OFFSET
|
||||
default y
|
||||
|
||||
config MCUBOOT_GENERATE_UNSIGNED_IMAGE
|
||||
default y
|
||||
|
||||
config MCUBOOT_GENERATE_CONFIRMED_IMAGE
|
||||
default y
|
||||
|
||||
config ROM_START_OFFSET
|
||||
default 0x20
|
||||
|
||||
endif # BOOTLOADER_MCUBOOT
|
||||
|
||||
endif # SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
|
||||
371
soc/espressif/common/include/_soc_inthandlers.h
Normal file
371
soc/espressif/common/include/_soc_inthandlers.h
Normal file
|
|
@ -0,0 +1,371 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/*
|
||||
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*
|
||||
* Functions here are designed to produce efficient code to
|
||||
* search an Xtensa bitmask of interrupts, inspecting only those bits
|
||||
* declared to be associated with a given interrupt level. Each
|
||||
* dispatcher will handle exactly one flagged interrupt, in numerical
|
||||
* order (low bits first) and will return a mask of that bit that can
|
||||
* then be cleared by the calling code. Unrecognized bits for the
|
||||
* level will invoke an error handler.
|
||||
*/
|
||||
|
||||
#include <xtensa/config/core-isa.h>
|
||||
#include <zephyr/sys/util.h>
|
||||
#include <zephyr/sw_isr_table.h>
|
||||
|
||||
#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT22_LEVEL) || XCHAL_INT22_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT23_LEVEL) || XCHAL_INT23_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT27_LEVEL) || XCHAL_INT27_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT29_LEVEL) || XCHAL_INT29_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 7
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 5
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT26_LEVEL) || XCHAL_INT26_LEVEL != 5
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT31_LEVEL) || XCHAL_INT31_LEVEL != 5
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT21_LEVEL) || XCHAL_INT21_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT24_LEVEL) || XCHAL_INT24_LEVEL != 4
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT25_LEVEL) || XCHAL_INT25_LEVEL != 4
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT28_LEVEL) || XCHAL_INT28_LEVEL != 4
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT30_LEVEL) || XCHAL_INT30_LEVEL != 4
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
|
||||
static inline int _xtensa_handle_one_int1(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (mask & 0x7f) {
|
||||
if (mask & 0x7) {
|
||||
if (mask & BIT(0)) {
|
||||
mask = BIT(0);
|
||||
irq = 0;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(1)) {
|
||||
mask = BIT(1);
|
||||
irq = 1;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(2)) {
|
||||
mask = BIT(2);
|
||||
irq = 2;
|
||||
goto handle_irq;
|
||||
}
|
||||
} else {
|
||||
if (mask & 0x18) {
|
||||
if (mask & BIT(3)) {
|
||||
mask = BIT(3);
|
||||
irq = 3;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(4)) {
|
||||
mask = BIT(4);
|
||||
irq = 4;
|
||||
goto handle_irq;
|
||||
}
|
||||
} else {
|
||||
if (mask & BIT(5)) {
|
||||
mask = BIT(5);
|
||||
irq = 5;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(6)) {
|
||||
mask = BIT(6);
|
||||
irq = 6;
|
||||
goto handle_irq;
|
||||
}
|
||||
}
|
||||
}
|
||||
} else {
|
||||
if (mask & 0x780) {
|
||||
if (mask & 0x180) {
|
||||
if (mask & BIT(7)) {
|
||||
mask = BIT(7);
|
||||
irq = 7;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(8)) {
|
||||
mask = BIT(8);
|
||||
irq = 8;
|
||||
goto handle_irq;
|
||||
}
|
||||
} else {
|
||||
if (mask & BIT(9)) {
|
||||
mask = BIT(9);
|
||||
irq = 9;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(10)) {
|
||||
mask = BIT(10);
|
||||
irq = 10;
|
||||
goto handle_irq;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
if (mask & 0x3000) {
|
||||
if (mask & BIT(12)) {
|
||||
mask = BIT(12);
|
||||
irq = 12;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(13)) {
|
||||
mask = BIT(13);
|
||||
irq = 13;
|
||||
goto handle_irq;
|
||||
}
|
||||
} else {
|
||||
if (mask & BIT(17)) {
|
||||
mask = BIT(17);
|
||||
irq = 17;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(18)) {
|
||||
mask = BIT(18);
|
||||
irq = 18;
|
||||
goto handle_irq;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int3(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (mask & 0x408800) {
|
||||
if (mask & BIT(11)) {
|
||||
mask = BIT(11);
|
||||
irq = 11;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(15)) {
|
||||
mask = BIT(15);
|
||||
irq = 15;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(22)) {
|
||||
mask = BIT(22);
|
||||
irq = 22;
|
||||
goto handle_irq;
|
||||
}
|
||||
} else {
|
||||
if (mask & BIT(23)) {
|
||||
mask = BIT(23);
|
||||
irq = 23;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(27)) {
|
||||
mask = BIT(27);
|
||||
irq = 27;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(29)) {
|
||||
mask = BIT(29);
|
||||
irq = 29;
|
||||
goto handle_irq;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int7(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (mask & BIT(14)) {
|
||||
mask = BIT(14);
|
||||
irq = 14;
|
||||
goto handle_irq;
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int5(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (mask & BIT(16)) {
|
||||
mask = BIT(16);
|
||||
irq = 16;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(26)) {
|
||||
mask = BIT(26);
|
||||
irq = 26;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(31)) {
|
||||
mask = BIT(31);
|
||||
irq = 31;
|
||||
goto handle_irq;
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int2(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (mask & BIT(19)) {
|
||||
mask = BIT(19);
|
||||
irq = 19;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(20)) {
|
||||
mask = BIT(20);
|
||||
irq = 20;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(21)) {
|
||||
mask = BIT(21);
|
||||
irq = 21;
|
||||
goto handle_irq;
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int4(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (mask & 0x3000000) {
|
||||
if (mask & BIT(24)) {
|
||||
mask = BIT(24);
|
||||
irq = 24;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(25)) {
|
||||
mask = BIT(25);
|
||||
irq = 25;
|
||||
goto handle_irq;
|
||||
}
|
||||
} else {
|
||||
if (mask & BIT(28)) {
|
||||
mask = BIT(28);
|
||||
irq = 28;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(30)) {
|
||||
mask = BIT(30);
|
||||
irq = 30;
|
||||
goto handle_irq;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int0(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int _xtensa_handle_one_int6(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
21
soc/espressif/common/include/gdbstub/soc.h
Normal file
21
soc/espressif/common/include/gdbstub/soc.h
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <inttypes.h>
|
||||
|
||||
#ifndef SOC_XTENSA_ESP32_GDBSTUB_H_
|
||||
#define SOC_XTENSA_ESP32_GDBSTUB_H_
|
||||
|
||||
#ifndef ZEPHYR_INCLUDE_ARCH_XTENSA_GDBSTUB_SYS_H_
|
||||
#error "Must be included after arch/xtensa/gdbstub.h"
|
||||
#endif /* ZEPHYR_INCLUDE_ARCH_XTENSA_GDBSTUB_SYS_H_ */
|
||||
|
||||
#define SOC_GDB_GPKT_BIN_SIZE 420
|
||||
#define SOC_GDB_GPKT_HEX_SIZE (SOC_GDB_GPKT_BIN_SIZE * 2)
|
||||
|
||||
#define SOC_GDB_REGNO_A1 0x0001
|
||||
|
||||
#endif /* SOC_XTENSA_ESP32_GDBSTUB_H_ */
|
||||
120
soc/espressif/esp32/CMakeLists.txt
Normal file
120
soc/espressif/esp32/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,120 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if(CONFIG_SOC_ESP32_APPCPU)
|
||||
zephyr_sources(soc_appcpu.c)
|
||||
else()
|
||||
zephyr_sources(
|
||||
soc.c
|
||||
loader.c
|
||||
esp32-mp.c
|
||||
)
|
||||
endif()
|
||||
|
||||
zephyr_include_directories(.)
|
||||
|
||||
zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fix.c)
|
||||
|
||||
zephyr_library_sources_ifdef(CONFIG_GDBSTUB gdbstub.c)
|
||||
|
||||
zephyr_library_sources_ifdef(CONFIG_PM power.c)
|
||||
zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c)
|
||||
|
||||
# get flash size to use in esptool as string
|
||||
math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000")
|
||||
|
||||
if(CONFIG_BOOTLOADER_ESP_IDF)
|
||||
include(ExternalProject)
|
||||
|
||||
## we use hello-world project, but I think any can be used.
|
||||
set(espidf_components_dir ${ESP_IDF_PATH}/components)
|
||||
set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf)
|
||||
set(espidf_build_dir ${espidf_prefix}/build)
|
||||
|
||||
ExternalProject_Add(
|
||||
EspIdfBootloader
|
||||
PREFIX ${espidf_prefix}
|
||||
SOURCE_DIR ${espidf_components_dir}/bootloader/subproject
|
||||
BINARY_DIR ${espidf_build_dir}/bootloader
|
||||
CONFIGURE_COMMAND
|
||||
${CMAKE_COMMAND} -G${CMAKE_GENERATOR}
|
||||
-S ${espidf_components_dir}/bootloader/subproject
|
||||
-B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig
|
||||
-DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES}
|
||||
-DPYTHON_DEPS_CHECKED=1
|
||||
-DCMAKE_C_COMPILER=${CMAKE_C_COMPILER}
|
||||
-DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER}
|
||||
-DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER}
|
||||
-DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME}
|
||||
-DPYTHON=${PYTHON_EXECUTABLE}
|
||||
BUILD_COMMAND
|
||||
${CMAKE_COMMAND} --build .
|
||||
INSTALL_COMMAND "" # This particular build system has no install command
|
||||
)
|
||||
|
||||
ExternalProject_Add(
|
||||
EspPartitionTable
|
||||
SOURCE_DIR ${espidf_components_dir}/partition_table
|
||||
BINARY_DIR ${espidf_build_dir}
|
||||
CONFIGURE_COMMAND ""
|
||||
BUILD_COMMAND
|
||||
${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q
|
||||
--offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin
|
||||
INSTALL_COMMAND ""
|
||||
)
|
||||
|
||||
set_property(TARGET bintools PROPERTY disassembly_flag_inline_source)
|
||||
|
||||
add_dependencies(app EspIdfBootloader EspPartitionTable)
|
||||
|
||||
board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin")
|
||||
|
||||
board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin")
|
||||
|
||||
board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000")
|
||||
endif()
|
||||
|
||||
if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF)
|
||||
if(CONFIG_BUILD_OUTPUT_BIN)
|
||||
set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
|
||||
COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py
|
||||
ARGS --chip esp32 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB
|
||||
-o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin
|
||||
${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf)
|
||||
endif()
|
||||
|
||||
if(CONFIG_MCUBOOT)
|
||||
board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin")
|
||||
endif()
|
||||
endif()
|
||||
|
||||
## When building for APPCPU
|
||||
if(CONFIG_SOC_ESP32_APPCPU)
|
||||
if(CONFIG_BUILD_OUTPUT_BIN)
|
||||
set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
|
||||
COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esp_bin2c_array.py
|
||||
ARGS -i ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin
|
||||
-o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.c
|
||||
-a "esp32_appcpu_fw_array")
|
||||
endif()
|
||||
else()
|
||||
set_property(TARGET bintools PROPERTY disassembly_flag_inline_source)
|
||||
|
||||
# get code-partition slot0 address
|
||||
dt_nodelabel(dts_partition_path NODELABEL "slot0_partition")
|
||||
dt_reg_addr(img_0_off PATH ${dts_partition_path})
|
||||
|
||||
# get code-partition boot address
|
||||
dt_nodelabel(dts_partition_path NODELABEL "boot_partition")
|
||||
dt_reg_addr(boot_off PATH ${dts_partition_path})
|
||||
|
||||
board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}")
|
||||
board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}")
|
||||
endif()
|
||||
|
||||
if(CONFIG_MCUBOOT)
|
||||
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "")
|
||||
elseif(CONFIG_SOC_ESP32_APPCPU)
|
||||
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default_appcpu.ld CACHE INTERNAL "")
|
||||
else()
|
||||
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "")
|
||||
endif()
|
||||
263
soc/espressif/esp32/Kconfig
Normal file
263
soc/espressif/esp32/Kconfig
Normal file
|
|
@ -0,0 +1,263 @@
|
|||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_ESP32
|
||||
select XTENSA
|
||||
select CLOCK_CONTROL
|
||||
select DYNAMIC_INTERRUPTS
|
||||
select ARCH_HAS_GDBSTUB
|
||||
select ARCH_SUPPORTS_COREDUMP
|
||||
select PINCTRL
|
||||
select XIP if !MCUBOOT
|
||||
select HAS_ESPRESSIF_HAL
|
||||
select CPU_HAS_FPU
|
||||
select HAS_PM
|
||||
select HAS_POWEROFF
|
||||
|
||||
if SOC_SERIES_ESP32
|
||||
|
||||
config IDF_TARGET_ESP32
|
||||
bool "ESP32 as target board"
|
||||
default y
|
||||
|
||||
config ESP32_APPCPU_IRAM
|
||||
hex "ESP32 APPCPU IRAM size"
|
||||
depends on SOC_ESP32_PROCPU || SOC_ESP32_APPCPU
|
||||
default 0x20000
|
||||
help
|
||||
Defines APPCPU IRAM area in bytes.
|
||||
|
||||
config ESP32_APPCPU_DRAM
|
||||
hex "ESP32 APPCPU DRAM size"
|
||||
depends on SOC_ESP32_PROCPU || SOC_ESP32_APPCPU
|
||||
default 0x10000
|
||||
help
|
||||
Defines APPCPU DRAM area in bytes.
|
||||
|
||||
config SOC_ESP32_PROCPU
|
||||
bool
|
||||
help
|
||||
This hidden configuration defines that build is targeted for PROCPU (core 0).
|
||||
|
||||
config SOC_ESP32_APPCPU
|
||||
bool
|
||||
help
|
||||
This hidden configuration defines that build is targeted for APPCPU (core 1).
|
||||
|
||||
config SOC_ENABLE_APPCPU
|
||||
bool
|
||||
default y
|
||||
depends on IPM && SOC_ESP32_PROCPU
|
||||
help
|
||||
This hidden configuration lets PROCPU core to map and start APPCPU whenever IPM is enabled.
|
||||
|
||||
config ESP_SYSTEM_RTC_EXT_XTAL
|
||||
bool
|
||||
|
||||
config ESP_SYSTEM_RTC_EXT_OSC
|
||||
bool
|
||||
|
||||
config ESP32_BT_RESERVE_DRAM
|
||||
hex "Bluetooth controller reserved RAM region"
|
||||
default 0xdb5c if BT
|
||||
default 0
|
||||
|
||||
config ESP_HEAP_MEM_POOL_REGION_1_SIZE
|
||||
int "Internal DRAM region 1 mempool size"
|
||||
default 0 if MCUBOOT
|
||||
default 1024 if SOC_ESP32_PROCPU
|
||||
default 49152
|
||||
help
|
||||
ESP32 has two banks of size 192K and 128K which can be used
|
||||
as DRAM, system heap allocates area from region 0.
|
||||
This configuration can be used to add memory from region 1
|
||||
to heap and can be allocated using k_malloc.
|
||||
|
||||
choice ESP32_RTC_CLK_SRC
|
||||
prompt "RTC clock source"
|
||||
default ESP32_RTC_CLK_SRC_INT_RC
|
||||
help
|
||||
Choose which clock is used as RTC clock source.
|
||||
|
||||
- "Internal 150kHz oscillator" option provides lowest deep sleep current
|
||||
consumption, and does not require extra external components. However
|
||||
frequency stability with respect to temperature is poor, so time may
|
||||
drift in deep/light sleep modes.
|
||||
- "External 32kHz crystal" provides better frequency stability, at the
|
||||
expense of slightly higher (1uA) deep sleep current consumption.
|
||||
- "External 32kHz oscillator" allows using 32kHz clock generated by an
|
||||
external circuit. In this case, external clock signal must be connected
|
||||
to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal,
|
||||
and <1V in case of square wave signal. Common mode voltage should be
|
||||
0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude.
|
||||
Additionally, 1nF capacitor must be connected between 32K_XP pin and
|
||||
ground. 32K_XP pin can not be used as a GPIO in this case.
|
||||
- "Internal 8.5MHz oscillator divided by 256" option results in higher
|
||||
deep sleep current (by 5uA) but has better frequency stability than
|
||||
the internal 150kHz oscillator. It does not require external components.
|
||||
|
||||
config ESP32_RTC_CLK_SRC_INT_RC
|
||||
bool "Internal 150kHz RC oscillator"
|
||||
|
||||
config ESP32_RTC_CLK_SRC_EXT_CRYS
|
||||
bool "External 32kHz crystal"
|
||||
select ESP_SYSTEM_RTC_EXT_XTAL
|
||||
|
||||
config ESP32_RTC_CLK_SRC_EXT_OSC
|
||||
bool "External 32kHz oscillator at 32K_XN pin"
|
||||
select ESP_SYSTEM_RTC_EXT_OSC
|
||||
|
||||
config ESP32_RTC_CLK_SRC_INT_8MD256
|
||||
bool "Internal 8.5MHz oscillator, divided by 256 (~33kHz)"
|
||||
|
||||
endchoice # ESP32_RTC_CLK_SRC
|
||||
|
||||
config ESP32_RTC_CLK_CAL_CYCLES
|
||||
int "Number of cycles for RTC_SLOW_CLK calibration"
|
||||
default 3000 if ESP32_RTC_CLK_SRC_EXT_CRYS || ESP32_RTC_CLK_SRC_EXT_OSC || ESP32_RTC_CLK_SRC_INT_8MD256
|
||||
default 1024 if ESP32_RTC_CLK_SRC_INT_RC
|
||||
range 0 27000 if ESP32_RTC_CLK_SRC_EXT_CRYS || ESP32_RTC_CLK_SRC_EXT_OSC || ESP32_RTC_CLK_SRC_INT_8MD256
|
||||
range 0 32766 if ESP32_RTC_CLK_SRC_INT_RC
|
||||
help
|
||||
When the startup code initializes RTC_SLOW_CLK, it can perform
|
||||
calibration by comparing the RTC_SLOW_CLK frequency with main XTAL
|
||||
frequency. This option sets the number of RTC_SLOW_CLK cycles measured
|
||||
by the calibration routine. Higher numbers increase calibration
|
||||
precision, which may be important for applications which spend a lot of
|
||||
time in deep sleep. Lower numbers reduce startup time.
|
||||
|
||||
When this option is set to 0, clock calibration will not be performed at
|
||||
startup, and approximate clock frequencies will be assumed:
|
||||
|
||||
- 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024.
|
||||
- 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
|
||||
In case more value will help improve the definition of the launch of the crystal.
|
||||
If the crystal could not start, it will be switched to internal RC.
|
||||
|
||||
config ESP32_RTC_XTAL_CAL_RETRY
|
||||
int "Number of attempts to repeat 32k XTAL calibration"
|
||||
default 1
|
||||
depends on ESP32_RTC_CLK_SRC_EXT_CRYS
|
||||
help
|
||||
Number of attempts to repeat 32k XTAL calibration
|
||||
before giving up and switching to the internal RC.
|
||||
Increase this option if the 32k crystal oscillator
|
||||
does not start and switches to internal RC.
|
||||
|
||||
config ESP32_DEEP_SLEEP_WAKEUP_DELAY
|
||||
int "Extra delay in deep sleep wake stub (in us)"
|
||||
default 2000
|
||||
range 0 5000
|
||||
help
|
||||
When ESP32 exits deep sleep, the CPU and the flash chip are powered on
|
||||
at the same time. CPU will run deep sleep stub first, and then
|
||||
proceed to load code from flash. Some flash chips need sufficient
|
||||
time to pass between power on and first read operation. By default,
|
||||
without any extra delay, this time is approximately 900us, although
|
||||
some flash chip types need more than that.
|
||||
|
||||
By default extra delay is set to 2000us. When optimizing startup time
|
||||
for applications which require it, this value may be reduced.
|
||||
|
||||
If you are seeing "flash read err, 1000" message printed to the
|
||||
console after deep sleep reset, try increasing this value.
|
||||
|
||||
choice ESP32_UNIVERSAL_MAC_ADDRESSES
|
||||
bool "Number of universally administered (by IEEE) MAC address"
|
||||
default ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
|
||||
help
|
||||
Configure the number of universally administered (by IEEE) MAC addresses.
|
||||
During initialization, MAC addresses for each network interface are generated or
|
||||
derived from a single base MAC address. If the number of universal MAC addresses is four,
|
||||
all four interfaces (WiFi station, WiFi softap, Bluetooth and Ethernet) receive a universally
|
||||
administered MAC address. These are generated sequentially by adding 0, 1, 2 and 3 (respectively)
|
||||
to the final octet of the base MAC address. If the number of universal MAC addresses is two,
|
||||
only two interfaces (WiFi station and Bluetooth) receive a universally administered MAC address.
|
||||
These are generated sequentially by adding 0 and 1 (respectively) to the base MAC address.
|
||||
The remaining two interfaces (WiFi softap and Ethernet) receive local MAC addresses.
|
||||
These are derived from the universal WiFi station and Bluetooth MAC addresses, respectively.
|
||||
When using the default (Espressif-assigned) base MAC address, either setting can be used.
|
||||
When using a custom universal MAC address range, the correct setting will depend on the
|
||||
allocation of MAC addresses in this range (either 2 or 4 per device.)
|
||||
|
||||
config ESP32_UNIVERSAL_MAC_ADDRESSES_TWO
|
||||
bool "Two"
|
||||
select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
|
||||
select ESP_MAC_ADDR_UNIVERSE_BT
|
||||
|
||||
config ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
|
||||
bool "Four"
|
||||
select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
|
||||
select ESP_MAC_ADDR_UNIVERSE_WIFI_AP
|
||||
select ESP_MAC_ADDR_UNIVERSE_BT
|
||||
select ESP_MAC_ADDR_UNIVERSE_ETH
|
||||
|
||||
endchoice # ESP32_UNIVERSAL_MAC_ADDRESSES
|
||||
|
||||
config ESP_MAC_ADDR_UNIVERSE_WIFI_AP
|
||||
bool
|
||||
|
||||
config ESP_MAC_ADDR_UNIVERSE_WIFI_STA
|
||||
bool
|
||||
|
||||
config ESP_MAC_ADDR_UNIVERSE_BT
|
||||
bool
|
||||
|
||||
config ESP_MAC_ADDR_UNIVERSE_ETH
|
||||
bool
|
||||
|
||||
config ESP32_UNIVERSAL_MAC_ADDRESSES
|
||||
int
|
||||
default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO
|
||||
default 4 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
|
||||
|
||||
config ESP32_PHY_MAX_WIFI_TX_POWER
|
||||
int "Max WiFi/BLE TX power (dBm)"
|
||||
range 10 20
|
||||
default 20
|
||||
help
|
||||
Set maximum transmit power for WiFi radio. Actual transmit power for high
|
||||
data rates may be lower than this setting.
|
||||
|
||||
config ESP32_PHY_MAX_TX_POWER
|
||||
int
|
||||
default ESP32_PHY_MAX_WIFI_TX_POWER
|
||||
|
||||
config ESP32_EMAC
|
||||
bool
|
||||
default y if ETH_ESP32
|
||||
default y if MDIO_ESP32
|
||||
default n
|
||||
help
|
||||
Hidden option to enable the ESP32 Ethernet MAC driver.
|
||||
Both Ethernet and MDIO depend on this driver.
|
||||
This option allows enabling MDIO independently of Ethernet.
|
||||
|
||||
if ESP32_EMAC
|
||||
|
||||
config ETH_DMA_BUFFER_SIZE
|
||||
int "Ethernet DMA buffer size (Byte)"
|
||||
range 256 1600
|
||||
default 512
|
||||
help
|
||||
Set the size of each buffer used by Ethernet MAC DMA.
|
||||
|
||||
config ETH_DMA_RX_BUFFER_NUM
|
||||
int "Amount of Ethernet DMA Rx buffers"
|
||||
range 3 30
|
||||
default 10
|
||||
help
|
||||
Number of DMA receive buffers. Each buffer's size is ETH_DMA_BUFFER_SIZE.
|
||||
Larger number of buffers could increase throughput somehow.
|
||||
|
||||
config ETH_DMA_TX_BUFFER_NUM
|
||||
int "Amount of Ethernet DMA Tx buffers"
|
||||
range 3 30
|
||||
default 10
|
||||
help
|
||||
Number of DMA transmit buffers. Each buffer's size is ETH_DMA_BUFFER_SIZE.
|
||||
Larger number of buffers could increase throughput somehow.
|
||||
|
||||
endif # ESP32_EMAC config
|
||||
|
||||
endif # SOC_SERIES_ESP32
|
||||
46
soc/espressif/esp32/Kconfig.defconfig
Normal file
46
soc/espressif/esp32/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_ESP32
|
||||
|
||||
config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
|
||||
default n
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
|
||||
|
||||
config XTENSA_CCOUNT_HZ
|
||||
default SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
|
||||
config ESPTOOLPY_FLASHFREQ_80M
|
||||
default y
|
||||
|
||||
config FLASH_SIZE
|
||||
default $(dt_node_reg_size_int,/soc/flash-controller@3ff42000/flash@0,0)
|
||||
|
||||
config FLASH_BASE_ADDRESS
|
||||
default $(dt_node_reg_addr_hex,/soc/flash-controller@3ff42000/flash@0)
|
||||
|
||||
if SMP
|
||||
|
||||
config SCHED_IPI_SUPPORTED
|
||||
default y
|
||||
|
||||
config SCHED_CPU_MASK
|
||||
default y
|
||||
|
||||
config MP_MAX_NUM_CPUS
|
||||
default 2
|
||||
|
||||
endif # SMP config
|
||||
|
||||
if GDBSTUB
|
||||
|
||||
# ESP32 GDB expects 420 bytes G-packet.
|
||||
# So double for hexadecimal digits.
|
||||
config GDBSTUB_BUF_SZ
|
||||
default 840 if GDBSTUB
|
||||
|
||||
endif # GDBSTUB config
|
||||
|
||||
endif # SOC_SERIES_ESP32 config
|
||||
153
soc/espressif/esp32/Kconfig.soc
Normal file
153
soc/espressif/esp32/Kconfig.soc
Normal file
|
|
@ -0,0 +1,153 @@
|
|||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_ESP32
|
||||
bool
|
||||
select SOC_FAMILY_ESPRESSIF_ESP32
|
||||
help
|
||||
ESP32 Series
|
||||
|
||||
config SOC_ESP32_D0WD_V3
|
||||
bool
|
||||
select SOC_ESP32
|
||||
help
|
||||
ESP32_D0WD_V3
|
||||
|
||||
config SOC_ESP32_D0WDR2_V3
|
||||
bool
|
||||
select SOC_ESP32
|
||||
help
|
||||
ESP32_D0WDR2_V3
|
||||
|
||||
config SOC_ESP32_U4WDH
|
||||
bool
|
||||
select SOC_ESP32
|
||||
help
|
||||
ESP32_U4WDH
|
||||
|
||||
config SOC_ESP32_PICO_V3
|
||||
bool
|
||||
select SOC_ESP32
|
||||
help
|
||||
ESP32_PICO_V3
|
||||
|
||||
config SOC_ESP32_PICO_V3_02
|
||||
bool
|
||||
select SOC_ESP32
|
||||
help
|
||||
ESP32_PICO_V3_02
|
||||
|
||||
config SOC_ESP32_PICO_D4
|
||||
bool
|
||||
select SOC_ESP32
|
||||
help
|
||||
ESP32_PICO_D4
|
||||
|
||||
# SiP with external flash / psram
|
||||
config SOC_ESP32_WROOM_DA_N4
|
||||
bool
|
||||
select SOC_ESP32
|
||||
help
|
||||
ESP32_WROOM_DA_N4
|
||||
|
||||
config SOC_ESP32_WROOM_DA_N8
|
||||
bool
|
||||
select SOC_ESP32
|
||||
help
|
||||
ESP32_WROOM_DA_N8
|
||||
|
||||
config SOC_ESP32_WROOM_DA_N16
|
||||
bool
|
||||
select SOC_ESP32
|
||||
help
|
||||
ESP32_WROOM_DA_N16
|
||||
|
||||
config SOC_ESP32_WROOM_32UE_N4
|
||||
bool
|
||||
select SOC_ESP32
|
||||
help
|
||||
ESP32_WROOM_32UE_N4
|
||||
|
||||
config SOC_ESP32_WROOM_32UE_N8
|
||||
bool
|
||||
select SOC_ESP32
|
||||
help
|
||||
ESP32_WROOM_32UE_N8
|
||||
|
||||
config SOC_ESP32_WROOM_32UE_N16
|
||||
bool
|
||||
select SOC_ESP32
|
||||
help
|
||||
ESP32_WROOM_32UE_N16
|
||||
|
||||
config SOC_ESP32_WROVER_E_N4R2
|
||||
bool
|
||||
select SOC_ESP32
|
||||
help
|
||||
ESP32_WROVER_E_N4R2
|
||||
|
||||
config SOC_ESP32_WROVER_E_N8R2
|
||||
bool
|
||||
select SOC_ESP32
|
||||
help
|
||||
ESP32_WROVER_E_N8R2
|
||||
|
||||
config SOC_ESP32_WROVER_E_N16R2
|
||||
bool
|
||||
select SOC_ESP32
|
||||
help
|
||||
ESP32_WROVER_E_N16R2
|
||||
|
||||
config SOC_ESP32_WROVER_E_N4R8
|
||||
bool
|
||||
select SOC_ESP32
|
||||
help
|
||||
ESP32_WROVER_E_N4R8
|
||||
|
||||
config SOC_ESP32_WROVER_E_N8R8
|
||||
bool
|
||||
select SOC_ESP32
|
||||
help
|
||||
ESP32_WROVER_E_N8R8
|
||||
|
||||
config SOC_ESP32_WROVER_E_N16R8
|
||||
bool
|
||||
select SOC_ESP32
|
||||
help
|
||||
ESP32_WROVER_E_N16R8
|
||||
|
||||
config SOC_ESP32
|
||||
bool
|
||||
select SOC_SERIES_ESP32
|
||||
help
|
||||
ESP32
|
||||
|
||||
config SOC_SERIES
|
||||
default "esp32" if SOC_SERIES_ESP32
|
||||
|
||||
config SOC
|
||||
default "esp32" if SOC_SERIES_ESP32
|
||||
|
||||
config SOC_PART_NUMBER
|
||||
default "ESP32_D0WD_V3" if SOC_ESP32_D0WD_V3
|
||||
default "ESP32_D0WDR2_V3" if SOC_ESP32_D0WDR2_V3
|
||||
default "ESP32_U4WDH" if SOC_ESP32_U4WDH
|
||||
default "ESP32_PICO_V3" if SOC_ESP32_PICO_V3
|
||||
default "ESP32_PICO_V3_02" if SOC_ESP32_PICO_V3_02
|
||||
default "ESP32_PICO_D4" if SOC_ESP32_PICO_D4
|
||||
default "ESP32_WROOM_DA_N4" if SOC_ESP32_WROOM_DA_N4
|
||||
default "ESP32_WROOM_DA_N8" if SOC_ESP32_WROOM_DA_N8
|
||||
default "ESP32_WROOM_DA_N16" if SOC_ESP32_WROOM_DA_N16
|
||||
default "ESP32_WROOM_32UE_N4" if SOC_ESP32_WROOM_32UE_N4
|
||||
default "ESP32_WROOM_32UE_N8" if SOC_ESP32_WROOM_32UE_N8
|
||||
default "ESP32_WROOM_32UE_N16" if SOC_ESP32_WROOM_32UE_N16
|
||||
default "ESP32_WROVER_E_N4R2" if SOC_ESP32_WROVER_E_N4R2
|
||||
default "ESP32_WROVER_E_N8R2" if SOC_ESP32_WROVER_E_N8R2
|
||||
default "ESP32_WROVER_E_N16R2" if SOC_ESP32_WROVER_E_N16R2
|
||||
default "ESP32_WROVER_E_N4R8" if SOC_ESP32_WROVER_E_N4R8
|
||||
default "ESP32_WROVER_E_N8R8" if SOC_ESP32_WROVER_E_N8R8
|
||||
default "ESP32_WROVER_E_N16R8" if SOC_ESP32_WROVER_E_N16R8
|
||||
|
||||
config SOC_TOOLCHAIN_NAME
|
||||
string
|
||||
default "espressif_esp32" if SOC_SERIES_ESP32
|
||||
583
soc/espressif/esp32/default.ld
Normal file
583
soc/espressif/esp32/default.ld
Normal file
|
|
@ -0,0 +1,583 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Cadence Design Systems, Inc.
|
||||
* Copyright (c) 2017 Intel Corporation
|
||||
* Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Linker command/script file
|
||||
*
|
||||
* Linker script for the Xtensa platform.
|
||||
*/
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/linker/sections.h>
|
||||
#include <zephyr/linker/linker-defs.h>
|
||||
#include <zephyr/linker/linker-tool.h>
|
||||
|
||||
#define RAMABLE_REGION dram0_0_seg
|
||||
#ifndef CONFIG_SOC_ENABLE_APPCPU
|
||||
#define RAMABLE_REGION_1 dram0_1_seg
|
||||
#else
|
||||
#define RAMABLE_REGION_1 dram0_0_seg
|
||||
#endif
|
||||
#define RODATA_REGION drom0_0_seg
|
||||
#define IRAM_REGION iram0_0_seg
|
||||
#define FLASH_CODE_REGION irom0_0_seg
|
||||
|
||||
#define ROMABLE_REGION ROM
|
||||
|
||||
#ifdef CONFIG_FLASH_SIZE
|
||||
#define FLASH_SIZE CONFIG_FLASH_SIZE
|
||||
#else
|
||||
#define FLASH_SIZE 0x400000
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BOOTLOADER_ESP_IDF
|
||||
#define IROM_SEG_ORG 0x400D0020
|
||||
#define IROM_SEG_LEN FLASH_SIZE-0x20
|
||||
#define IROM_SEG_ALIGN 0x4
|
||||
#else
|
||||
#define IROM_SEG_ORG 0x400D0000
|
||||
#define IROM_SEG_LEN FLASH_SIZE
|
||||
#define IROM_SEG_ALIGN 0x10000
|
||||
#endif
|
||||
#define IRAM_SEG_LEN 0x20000
|
||||
|
||||
/* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA.
|
||||
* Executing directly from LMA is not possible. */
|
||||
#undef GROUP_ROM_LINK_IN
|
||||
#define GROUP_ROM_LINK_IN(vregion, lregion) > RODATA_REGION AT > lregion
|
||||
|
||||
MEMORY
|
||||
{
|
||||
mcuboot_hdr (RX): org = 0x0, len = 0x20
|
||||
metadata (RX): org = 0x20, len = 0x20
|
||||
ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40
|
||||
|
||||
#ifdef CONFIG_SOC_ENABLE_APPCPU
|
||||
iram0_0_seg(RX): org = 0x40080000, len = 0x08000
|
||||
#else
|
||||
iram0_0_seg(RX): org = 0x40080000, len = IRAM_SEG_LEN
|
||||
#endif
|
||||
|
||||
irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN
|
||||
/*
|
||||
* Following is DRAM memory split with reserved address ranges in ESP32:
|
||||
*
|
||||
* 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions)
|
||||
* 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage)
|
||||
* 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU)
|
||||
* 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU)
|
||||
* 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage)
|
||||
*
|
||||
* FIXME:
|
||||
* - Utilize available memory regions to full capacity
|
||||
*/
|
||||
dram0_0_seg(RW): org = 0x3FFB0000 + CONFIG_ESP32_BT_RESERVE_DRAM, len = 0x2c200 - CONFIG_ESP32_BT_RESERVE_DRAM
|
||||
|
||||
#ifdef CONFIG_SOC_ENABLE_APPCPU
|
||||
dram0_shm0_seg(RW): org = 0x3FFE5230, len = 2K /* shared RAM reserved for IPM */
|
||||
dram0_sem0_seg(RW): org = 0x3FFE5A30, len = 8 /* shared data reserved for IPM data header */
|
||||
dram0_1_seg(RW): org = 0x3FFE5A38, len = 0K /* for AMP builds dram0_1 is reserved for network core */
|
||||
#else
|
||||
dram0_1_seg(RW): org = 0x3FFE5230, len = 0x1BCB0 - 0xEE0 /* skip data for APP CPU initialization usage */
|
||||
#endif
|
||||
|
||||
/* DROM is the first segment placed in generated binary.
|
||||
* MCUboot binary for ESP32 has image header of 0x20 bytes.
|
||||
* Additional load header of 0x20 bytes are appended to the image.
|
||||
* Hence, an offset of 0x40 is added to DROM segment origin.
|
||||
*/
|
||||
drom0_0_seg(R): org = 0x3F400040, len = 0x400000 - 0x40
|
||||
rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000
|
||||
rtc_slow_seg(RW): org = 0x50000000, len = 0x1000
|
||||
#if defined(CONFIG_ESP_SPIRAM)
|
||||
ext_ram_seg(RW): org = 0x3F800000, len = CONFIG_ESP_SPIRAM_SIZE
|
||||
#endif
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Default entry point: */
|
||||
PROVIDE ( _ResetVector = 0x40000400 );
|
||||
ENTRY(CONFIG_KERNEL_ENTRY)
|
||||
|
||||
_rom_store_table = 0;
|
||||
|
||||
PROVIDE(_memmap_vecbase_reset = 0x40000450);
|
||||
PROVIDE(_memmap_reset_vector = 0x40000400);
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Reserve space for MCUboot header in the binary */
|
||||
.mcuboot_header :
|
||||
{
|
||||
QUAD(0x0)
|
||||
QUAD(0x0)
|
||||
QUAD(0x0)
|
||||
QUAD(0x0)
|
||||
} > mcuboot_hdr
|
||||
.metadata :
|
||||
{
|
||||
/* Magic byte for load header */
|
||||
LONG(0xace637d3)
|
||||
|
||||
/* Application entry point address */
|
||||
KEEP(*(.entry_addr))
|
||||
|
||||
/* IRAM metadata:
|
||||
* - Destination address (VMA) for IRAM region
|
||||
* - Flash offset (LMA) for start of IRAM region
|
||||
* - Size of IRAM region
|
||||
*/
|
||||
|
||||
LONG(ADDR(.iram0.vectors))
|
||||
LONG(LOADADDR(.iram0.vectors))
|
||||
LONG(LOADADDR(_TEXT_SECTION_NAME) + SIZEOF(_TEXT_SECTION_NAME) - LOADADDR(.iram0.vectors))
|
||||
|
||||
/* DRAM metadata:
|
||||
* - Destination address (VMA) for DRAM region
|
||||
* - Flash offset (LMA) for start of DRAM region
|
||||
* - Size of DRAM region
|
||||
*/
|
||||
|
||||
LONG(ADDR(.dram0.data))
|
||||
LONG(LOADADDR(.dram0.data))
|
||||
LONG(LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - LOADADDR(.dram0.data))
|
||||
} > metadata
|
||||
|
||||
#include <zephyr/linker/rel-sections.ld>
|
||||
|
||||
_image_drom_start = LOADADDR(_RODATA_SECTION_NAME);
|
||||
_image_drom_size = LOADADDR(_RODATA_SECTION_END) + SIZEOF(_RODATA_SECTION_END) - _image_drom_start;
|
||||
_image_drom_vaddr = ADDR(_RODATA_SECTION_NAME);
|
||||
|
||||
/* NOTE: .rodata section should be the first section in the linker script and no
|
||||
* other section should appear before .rodata section. This is the requirement
|
||||
* to align ROM section to 64K page offset.
|
||||
* Adding .rodata as first section helps to reduce size of generated binary by
|
||||
* few kBs.
|
||||
*/
|
||||
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
|
||||
{
|
||||
__rodata_region_start = ABSOLUTE(.);
|
||||
|
||||
. = ALIGN(4);
|
||||
#include <snippets-rodata.ld>
|
||||
|
||||
. = ALIGN(4);
|
||||
*(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata)
|
||||
*(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata.*)
|
||||
|
||||
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
|
||||
*(.xt_except_table)
|
||||
*(.gcc_except_table .gcc_except_table.*)
|
||||
*(.gnu.linkonce.e.*)
|
||||
*(.gnu.version_r)
|
||||
. = (. + 3) & ~ 3;
|
||||
__eh_frame = ABSOLUTE(.);
|
||||
KEEP(*(.eh_frame))
|
||||
. = (. + 7) & ~ 3;
|
||||
|
||||
/* C++ exception handlers table: */
|
||||
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
|
||||
*(.xt_except_desc)
|
||||
*(.gnu.linkonce.h.*)
|
||||
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc_end)
|
||||
*(.dynamic)
|
||||
*(.gnu.version_d)
|
||||
. = ALIGN(4);
|
||||
__rodata_region_end = ABSOLUTE(.);
|
||||
/* Literals are also RO data. */
|
||||
_lit4_start = ABSOLUTE(.);
|
||||
*(*.lit4)
|
||||
*(.lit4.*)
|
||||
*(.gnu.linkonce.lit4.*)
|
||||
_lit4_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
*(.rodata_wlog)
|
||||
*(.rodata_wlog*)
|
||||
. = ALIGN(4);
|
||||
} GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)
|
||||
|
||||
#include <zephyr/linker/common-rom/common-rom-cpp.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-kernel-devices.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-ztest.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-net.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-bt.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-debug.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-misc.ld>
|
||||
#include <zephyr/linker/thread-local-storage.ld>
|
||||
#include <snippets-sections.ld>
|
||||
|
||||
/* Create an explicit section at the end of all the data that shall be mapped into drom.
|
||||
* This is used to calculate the size of the _image_drom_size variable */
|
||||
SECTION_PROLOGUE(_RODATA_SECTION_END,,)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_image_rodata_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)
|
||||
|
||||
_image_dram_start = LOADADDR(.dram0.data);
|
||||
_image_dram_size = LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - _image_dram_start;
|
||||
_image_dram_vaddr = ADDR(.dram0.data);
|
||||
|
||||
.dram0.data :
|
||||
{
|
||||
__data_start = ABSOLUTE(.);
|
||||
|
||||
_btdm_data_start = ABSOLUTE(.);
|
||||
*libbtdm_app.a:(.data .data.*)
|
||||
. = ALIGN (4);
|
||||
_btdm_data_end = ABSOLUTE(.);
|
||||
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
/* rodata for panic handler(libarch__xtensa__core.a) and all
|
||||
* dependent functions should be placed in DRAM to avoid issue
|
||||
* when flash cache is disabled */
|
||||
*libarch__xtensa__core.a:(.rodata .rodata.*)
|
||||
*libkernel.a:fatal.*(.rodata .rodata.*)
|
||||
*libkernel.a:init.*(.rodata .rodata.*)
|
||||
*libzephyr.a:cbprintf_complete*(.rodata .rodata.*)
|
||||
*libzephyr.a:log_core.*(.rodata .rodata.*)
|
||||
*libzephyr.a:log_backend_uart.*(.rodata .rodata.*)
|
||||
*libzephyr.a:log_output.*(.rodata .rodata.*)
|
||||
*libzephyr.a:loader.*(.rodata .rodata.*)
|
||||
*libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*)
|
||||
*libzephyr.a:spi_flash_rom_patch.*(.rodata .rodata.*)
|
||||
*libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)
|
||||
|
||||
KEEP(*(.jcr))
|
||||
*(.dram1 .dram1.*)
|
||||
. = ALIGN(4);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
|
||||
|
||||
#include <zephyr/linker/cplusplus-rom.ld>
|
||||
#include <snippets-data-sections.ld>
|
||||
#include <zephyr/linker/common-ram.ld>
|
||||
#include <snippets-ram-sections.ld>
|
||||
#include <zephyr/linker/cplusplus-ram.ld>
|
||||
|
||||
/* logging sections should be placed in RAM area to avoid flash cache disabled issues */
|
||||
#pragma push_macro("GROUP_ROM_LINK_IN")
|
||||
#undef GROUP_ROM_LINK_IN
|
||||
#define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN
|
||||
#include <zephyr/linker/common-rom/common-rom-logging.ld>
|
||||
#pragma pop_macro("GROUP_ROM_LINK_IN")
|
||||
|
||||
.dram0.end :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
#include <snippets-rwdata.ld>
|
||||
. = ALIGN(4);
|
||||
_end = ABSOLUTE(.);
|
||||
__data_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
|
||||
|
||||
_image_iram_start = LOADADDR(.iram0.vectors);
|
||||
_image_iram_size = LOADADDR(_TEXT_SECTION_NAME) + SIZEOF(_TEXT_SECTION_NAME) - _image_iram_start;
|
||||
_image_iram_vaddr = ADDR(.iram0.vectors);
|
||||
|
||||
/* Send .iram0 code to iram */
|
||||
.iram0.vectors : ALIGN(4)
|
||||
{
|
||||
/* Vectors go to IRAM */
|
||||
_init_start = ABSOLUTE(.);
|
||||
/* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
|
||||
. = 0x0;
|
||||
KEEP(*(.WindowVectors.text));
|
||||
. = 0x180;
|
||||
KEEP(*(.Level2InterruptVector.text));
|
||||
. = 0x1c0;
|
||||
KEEP(*(.Level3InterruptVector.text));
|
||||
. = 0x200;
|
||||
KEEP(*(.Level4InterruptVector.text));
|
||||
. = 0x240;
|
||||
KEEP(*(.Level5InterruptVector.text));
|
||||
. = 0x280;
|
||||
KEEP(*(.DebugExceptionVector.text));
|
||||
. = 0x2c0;
|
||||
KEEP(*(.NMIExceptionVector.text));
|
||||
. = 0x300;
|
||||
KEEP(*(.KernelExceptionVector.text));
|
||||
. = 0x340;
|
||||
KEEP(*(.UserExceptionVector.text));
|
||||
. = 0x3C0;
|
||||
KEEP(*(.DoubleExceptionVector.text));
|
||||
. = 0x400;
|
||||
*(.*Vector.literal)
|
||||
|
||||
*(.UserEnter.literal);
|
||||
*(.UserEnter.text);
|
||||
. = ALIGN (16);
|
||||
*(.entry.text)
|
||||
*(.init.literal)
|
||||
*(.init)
|
||||
_init_end = ABSOLUTE(.);
|
||||
|
||||
/* This goes here, not at top of linker script, so addr2line finds it last,
|
||||
and uses it in preference to the first symbol in IRAM */
|
||||
_iram_start = ABSOLUTE(0);
|
||||
} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
|
||||
|
||||
SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))
|
||||
{
|
||||
/* Code marked as running out of IRAM */
|
||||
_iram_text_start = ABSOLUTE(.);
|
||||
*(.iram1 .iram1.*)
|
||||
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
|
||||
*libesp32.a:panic.*(.literal .text .literal.* .text.*)
|
||||
*librtc.a:(.literal .text .literal.* .text.*)
|
||||
*libarch__xtensa__core.a:(.literal .text .literal.* .text.*)
|
||||
*libkernel.a:(.literal .text .literal.* .text.*)
|
||||
*libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)
|
||||
*libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)
|
||||
*libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)
|
||||
*libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)
|
||||
*libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:log_core.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)
|
||||
*libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:log_list.*(.literal .text .literal.* .text.*)
|
||||
*libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out)
|
||||
*libzephyr.a:log_output.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:loader.*(.literal .text .literal.* .text.*)
|
||||
*liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)
|
||||
*liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*)
|
||||
*libc.a:*(.literal .text .literal.* .text.*)
|
||||
*libphy.a:( .phyiram .phyiram.*)
|
||||
*libgcov.a:(.literal .text .literal.* .text.*)
|
||||
|
||||
#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)
|
||||
*libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*)
|
||||
*libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)
|
||||
*libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
|
||||
*libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
|
||||
#endif
|
||||
|
||||
_iram_text_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
_iram_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
|
||||
|
||||
/* RTC fast memory holds RTC wake stub code,
|
||||
including from any source file named rtc_wake_stub*.c
|
||||
*/
|
||||
.rtc.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rtc.literal .rtc.text)
|
||||
*rtc_wake_stub*.o(.literal .text .literal.* .text.*)
|
||||
} GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION)
|
||||
|
||||
/* RTC slow memory holds RTC wake stub
|
||||
data/rodata, including from any source file
|
||||
named rtc_wake_stub*.c
|
||||
*/
|
||||
.rtc.data :
|
||||
{
|
||||
_rtc_data_start = ABSOLUTE(.);
|
||||
*(.rtc.data)
|
||||
*(.rtc.rodata)
|
||||
*rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)
|
||||
_rtc_data_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION)
|
||||
|
||||
/* RTC bss, from any source file named rtc_wake_stub*.c */
|
||||
.rtc.bss (NOLOAD) :
|
||||
{
|
||||
_rtc_bss_start = ABSOLUTE(.);
|
||||
*rtc_wake_stub*.o(.bss .bss.*)
|
||||
*rtc_wake_stub*.o(COMMON)
|
||||
_rtc_bss_end = ABSOLUTE(.);
|
||||
} GROUP_LINK_IN(rtc_slow_seg)
|
||||
|
||||
/* This section located in RTC SLOW Memory area.
|
||||
It holds data marked with RTC_SLOW_ATTR attribute.
|
||||
See the file "esp_attr.h" for more information.
|
||||
*/
|
||||
.rtc.force_slow :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_rtc_force_slow_start = ABSOLUTE(.);
|
||||
*(.rtc.force_slow .rtc.force_slow.*)
|
||||
. = ALIGN(4) ;
|
||||
_rtc_force_slow_end = ABSOLUTE(.);
|
||||
} > rtc_slow_seg
|
||||
|
||||
/* Get size of rtc slow data */
|
||||
_rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start);
|
||||
|
||||
#if defined(CONFIG_ESP_SPIRAM)
|
||||
.ext_ram.bss (NOLOAD):
|
||||
{
|
||||
_ext_ram_data_start = ABSOLUTE(.);
|
||||
|
||||
#if defined(CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM)
|
||||
*libdrivers__wifi.a:(.noinit .noinit.*)
|
||||
*libsubsys__net__l2__ethernet.a:(.noinit .noinit.*)
|
||||
*libsubsys__net__lib__config.a:(.noinit .noinit.*)
|
||||
*libsubsys__net__ip.a:(.noinit .noinit.*)
|
||||
*libsubsys__net.a:(.noinit .noinit.*)
|
||||
#endif
|
||||
_spiram_heap_start = ABSOLUTE(.);
|
||||
. = . + CONFIG_ESP_SPIRAM_HEAP_SIZE;
|
||||
|
||||
*(.ext_ram.bss*)
|
||||
|
||||
_ext_ram_data_end = ABSOLUTE(.);
|
||||
} GROUP_LINK_IN(ext_ram_seg)
|
||||
#endif
|
||||
|
||||
/* Shared RAM */
|
||||
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_bss_start = ABSOLUTE(.); /* required by bluetooth library */
|
||||
__bss_start = ABSOLUTE(.);
|
||||
|
||||
_btdm_bss_start = ABSOLUTE(.);
|
||||
*libbtdm_app.a:(.bss .bss.* COMMON)
|
||||
. = ALIGN (4);
|
||||
_btdm_bss_end = ABSOLUTE(.);
|
||||
|
||||
/* Buffer for system heap should be placed in dram0_0_seg */
|
||||
*libkernel.a:mempool.*(.noinit.kheap_buf__system_heap .noinit.*.kheap_buf__system_heap)
|
||||
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.share.mem)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN (8);
|
||||
__bss_end = ABSOLUTE(.);
|
||||
_end = ABSOLUTE(.);
|
||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
||||
|
||||
ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),
|
||||
"DRAM segment data does not fit.")
|
||||
|
||||
SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
*(.noinit)
|
||||
*(.noinit.*)
|
||||
. = ALIGN (8);
|
||||
} GROUP_LINK_IN(RAMABLE_REGION_1)
|
||||
|
||||
_image_irom_start = LOADADDR(.flash.text);
|
||||
_image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start;
|
||||
_image_irom_vaddr = ADDR(.flash.text);
|
||||
|
||||
.flash.text : ALIGN(IROM_SEG_ALIGN)
|
||||
{
|
||||
_stext = .;
|
||||
_text_start = ABSOLUTE(.);
|
||||
|
||||
#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)
|
||||
*libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*)
|
||||
*libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*)
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)
|
||||
*libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
|
||||
*libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
|
||||
#endif
|
||||
|
||||
*(.literal .text .literal.* .text.*)
|
||||
. = ALIGN(4);
|
||||
_text_end = ABSOLUTE(.);
|
||||
_etext = .;
|
||||
|
||||
/* Similar to _iram_start, this symbol goes here so it is
|
||||
resolved by addr2line in preference to the first symbol in
|
||||
the flash.text segment.
|
||||
*/
|
||||
_flash_cache_start = ABSOLUTE(0);
|
||||
} GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION)
|
||||
|
||||
_heap_sentry = 0x3ffe3f20;
|
||||
|
||||
#include <zephyr/linker/debug-sections.ld>
|
||||
|
||||
.xtensa.info 0 : { *(.xtensa.info) }
|
||||
.xt.insn 0 :
|
||||
{
|
||||
KEEP (*(.xt.insn))
|
||||
KEEP (*(.gnu.linkonce.x.*))
|
||||
}
|
||||
.xt.prop 0 :
|
||||
{
|
||||
KEEP (*(.xt.prop))
|
||||
KEEP (*(.xt.prop.*))
|
||||
KEEP (*(.gnu.linkonce.prop.*))
|
||||
}
|
||||
.xt.lit 0 :
|
||||
{
|
||||
KEEP (*(.xt.lit))
|
||||
KEEP (*(.xt.lit.*))
|
||||
KEEP (*(.gnu.linkonce.p.*))
|
||||
}
|
||||
.xt.profile_range 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_range))
|
||||
KEEP (*(.gnu.linkonce.profile_range.*))
|
||||
}
|
||||
.xt.profile_ranges 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_ranges))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
|
||||
}
|
||||
.xt.profile_files 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_files))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_files.*))
|
||||
}
|
||||
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
#include <zephyr/linker/intlist.ld>
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
|
||||
"IRAM0 segment data does not fit.")
|
||||
|
||||
#if defined(CONFIG_ESP_SPIRAM)
|
||||
ASSERT(((_ext_ram_data_end - _ext_ram_data_start) <= CONFIG_ESP_SPIRAM_SIZE),
|
||||
"External SPIRAM overflowed.")
|
||||
#endif /* CONFIG_ESP_SPIRAM */
|
||||
401
soc/espressif/esp32/default_appcpu.ld
Normal file
401
soc/espressif/esp32/default_appcpu.ld
Normal file
|
|
@ -0,0 +1,401 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Cadence Design Systems, Inc.
|
||||
* Copyright (c) 2017 Intel Corporation
|
||||
* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Linker command/script file
|
||||
*
|
||||
* Linker script for the Xtensa platform.
|
||||
*/
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/linker/sections.h>
|
||||
#include <zephyr/linker/linker-defs.h>
|
||||
#include <zephyr/linker/linker-tool.h>
|
||||
|
||||
#define RAMABLE_REGION dram0_1_seg
|
||||
#define RAMABLE_REGION_1 dram0_1_seg
|
||||
#define RODATA_REGION dram0_1_seg
|
||||
#define IRAM_REGION iram0_0_seg
|
||||
#define FLASH_CODE_REGION iram0_0_seg
|
||||
#define ROMABLE_REGION iram0_0_seg
|
||||
#define ROMABLE_DATA_REGION dram0_1_seg
|
||||
#define dram0_0_seg dram0_1_seg
|
||||
|
||||
/* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA.
|
||||
* Executing directly from LMA is not possible. */
|
||||
#undef GROUP_ROM_LINK_IN
|
||||
#define GROUP_ROM_LINK_IN(vregion, lregion) > RODATA_REGION AT > lregion
|
||||
|
||||
MEMORY
|
||||
{
|
||||
iram0_0_seg(RX): org = 0x40080000 + 0x08000, len = 0x18000
|
||||
dram0_shm0_seg(RW): org = 0x3FFE5230, len = 16K /* shared RAM reserved for IPM */
|
||||
dram0_sem0_seg(RW): org = 0x3FFED238, len = 8 /*shared data reserved for IPM data header */
|
||||
dram0_1_seg(RW): org = 0x3FFE9238 + CONFIG_ESP32_BT_RESERVE_DRAM, len = 0x17CB0 - 0xEE0 - CONFIG_ESP32_BT_RESERVE_DRAM
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Default entry point: */
|
||||
PROVIDE ( _ResetVector = 0x40000400 );
|
||||
ENTRY(__app_cpu_start)
|
||||
|
||||
_rom_store_table = 0;
|
||||
|
||||
PROVIDE(_memmap_vecbase_reset = 0x40000450);
|
||||
PROVIDE(_memmap_reset_vector = 0x40000400);
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
#include <zephyr/linker/rel-sections.ld>
|
||||
|
||||
_image_iram_start = LOADADDR(.iram0.vectors);
|
||||
_image_iram_size = LOADADDR(_TEXT_SECTION_NAME) + SIZEOF(_TEXT_SECTION_NAME) - _image_iram_start;
|
||||
_image_iram_vaddr = ADDR(.iram0.vectors);
|
||||
|
||||
/* Send .iram0 code to iram */
|
||||
.iram0.vectors : ALIGN(4)
|
||||
{
|
||||
/* Vectors go to IRAM */
|
||||
_init_start = ABSOLUTE(.);
|
||||
/* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
|
||||
. = 0x0;
|
||||
KEEP(*(.WindowVectors.text));
|
||||
. = 0x180;
|
||||
KEEP(*(.Level2InterruptVector.text));
|
||||
. = 0x1c0;
|
||||
KEEP(*(.Level3InterruptVector.text));
|
||||
. = 0x200;
|
||||
KEEP(*(.Level4InterruptVector.text));
|
||||
. = 0x240;
|
||||
KEEP(*(.Level5InterruptVector.text));
|
||||
. = 0x280;
|
||||
KEEP(*(.DebugExceptionVector.text));
|
||||
. = 0x2c0;
|
||||
KEEP(*(.NMIExceptionVector.text));
|
||||
. = 0x300;
|
||||
KEEP(*(.KernelExceptionVector.text));
|
||||
. = 0x340;
|
||||
KEEP(*(.UserExceptionVector.text));
|
||||
. = 0x3C0;
|
||||
KEEP(*(.DoubleExceptionVector.text));
|
||||
. = 0x400;
|
||||
*(.*Vector.literal)
|
||||
|
||||
*(.UserEnter.literal);
|
||||
*(.UserEnter.text);
|
||||
. = ALIGN (16);
|
||||
*(.entry.text)
|
||||
*(.init.literal)
|
||||
*(.init)
|
||||
_init_end = ABSOLUTE(.);
|
||||
|
||||
/* This goes here, not at top of linker script, so addr2line finds it last,
|
||||
and uses it in preference to the first symbol in IRAM */
|
||||
_iram_start = ABSOLUTE(0);
|
||||
} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
|
||||
|
||||
SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))
|
||||
{
|
||||
/* Code marked as running out of IRAM */
|
||||
_iram_text_start = ABSOLUTE(.);
|
||||
*(.iram1 .iram1.*)
|
||||
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
|
||||
*libesp32.a:panic.*(.literal .text .literal.* .text.*)
|
||||
*librtc.a:(.literal .text .literal.* .text.*)
|
||||
*libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)
|
||||
*libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)
|
||||
*libsubsys__net__ip.a:(.literal .text .literal.* .text.*)
|
||||
*libsubsys__net.a:(.literal .text .literal.* .text.*)
|
||||
*libarch__xtensa__core.a:(.literal .text .literal.* .text.*)
|
||||
*libkernel.a:(.literal .text .literal.* .text.*)
|
||||
*libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)
|
||||
*libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)
|
||||
*libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)
|
||||
*libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)
|
||||
*libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:log_core.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)
|
||||
*libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:log_list.*(.literal .text .literal.* .text.*)
|
||||
*libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out)
|
||||
*libzephyr.a:log_output.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:loader.*(.literal .text .literal.* .text.*)
|
||||
*liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)
|
||||
*liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*)
|
||||
*libc.a:*(.literal .text .literal.* .text.*)
|
||||
*libphy.a:( .phyiram .phyiram.*)
|
||||
*libgcov.a:(.literal .text .literal.* .text.*)
|
||||
|
||||
*libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*)
|
||||
*libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*)
|
||||
|
||||
*libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
|
||||
*libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
|
||||
|
||||
_iram_text_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
_iram_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
|
||||
|
||||
_image_drom_start = LOADADDR(_RODATA_SECTION_NAME);
|
||||
_image_drom_size = LOADADDR(_RODATA_SECTION_END) + SIZEOF(_RODATA_SECTION_END) - _image_drom_start;
|
||||
_image_drom_vaddr = ADDR(_RODATA_SECTION_NAME);
|
||||
|
||||
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
|
||||
{
|
||||
__rodata_region_start = ABSOLUTE(.);
|
||||
|
||||
. = ALIGN(4);
|
||||
#include <snippets-rodata.ld>
|
||||
|
||||
. = ALIGN(4);
|
||||
*(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata)
|
||||
*(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata.*)
|
||||
|
||||
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
|
||||
*(.xt_except_table)
|
||||
*(.gcc_except_table .gcc_except_table.*)
|
||||
*(.gnu.linkonce.e.*)
|
||||
*(.gnu.version_r)
|
||||
. = (. + 3) & ~ 3;
|
||||
__eh_frame = ABSOLUTE(.);
|
||||
KEEP(*(.eh_frame))
|
||||
. = (. + 7) & ~ 3;
|
||||
|
||||
/* C++ exception handlers table: */
|
||||
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
|
||||
*(.xt_except_desc)
|
||||
*(.gnu.linkonce.h.*)
|
||||
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc_end)
|
||||
*(.dynamic)
|
||||
*(.gnu.version_d)
|
||||
. = ALIGN(4);
|
||||
__rodata_region_end = ABSOLUTE(.);
|
||||
/* Literals are also RO data. */
|
||||
_lit4_start = ABSOLUTE(.);
|
||||
*(*.lit4)
|
||||
*(.lit4.*)
|
||||
*(.gnu.linkonce.lit4.*)
|
||||
_lit4_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
_thread_local_start = ABSOLUTE(.);
|
||||
*(.tdata)
|
||||
*(.tdata.*)
|
||||
*(.tbss)
|
||||
*(.tbss.*)
|
||||
*(.rodata_wlog)
|
||||
*(.rodata_wlog*)
|
||||
_thread_local_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
} GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_DATA_REGION)
|
||||
|
||||
#include <zephyr/linker/common-rom/common-rom-cpp.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-kernel-devices.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-ztest.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-net.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-bt.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-debug.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-misc.ld>
|
||||
#include <snippets-sections.ld>
|
||||
|
||||
/* Create an explicit section at the end of all the data that shall be mapped into drom.
|
||||
* This is used to calculate the size of the _image_drom_size variable */
|
||||
SECTION_PROLOGUE(_RODATA_SECTION_END,,)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_image_rodata_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)
|
||||
|
||||
_image_dram_start = LOADADDR(.dram0.data);
|
||||
_image_dram_size = LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - _image_dram_start;
|
||||
_image_dram_vaddr = ADDR(.dram0.data);
|
||||
|
||||
.dram0.data :
|
||||
{
|
||||
__data_start = ABSOLUTE(.);
|
||||
|
||||
_btdm_data_start = ABSOLUTE(.);
|
||||
*libbtdm_app.a:(.data .data.*)
|
||||
. = ALIGN (4);
|
||||
_btdm_data_end = ABSOLUTE(.);
|
||||
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
/* rodata for panic handler(libarch__xtensa__core.a) and all
|
||||
* dependent functions should be placed in DRAM to avoid issue
|
||||
* when flash cache is disabled */
|
||||
*libarch__xtensa__core.a:(.rodata .rodata.*)
|
||||
*libkernel.a:fatal.*(.rodata .rodata.*)
|
||||
*libkernel.a:init.*(.rodata .rodata.*)
|
||||
*libzephyr.a:cbprintf_complete*(.rodata .rodata.*)
|
||||
*libzephyr.a:log_core.*(.rodata .rodata.*)
|
||||
*libzephyr.a:log_backend_uart.*(.rodata .rodata.*)
|
||||
*libzephyr.a:log_output.*(.rodata .rodata.*)
|
||||
*libzephyr.a:loader.*(.rodata .rodata.*)
|
||||
*libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*)
|
||||
*libzephyr.a:spi_flash_rom_patch.*(.rodata .rodata.*)
|
||||
*libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)
|
||||
|
||||
KEEP(*(.jcr))
|
||||
*(.dram1 .dram1.*)
|
||||
. = ALIGN(4);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_DATA_REGION)
|
||||
|
||||
#include <zephyr/linker/cplusplus-rom.ld>
|
||||
#include <snippets-data-sections.ld>
|
||||
#include <zephyr/linker/common-ram.ld>
|
||||
#include <snippets-ram-sections.ld>
|
||||
#include <zephyr/linker/cplusplus-ram.ld>
|
||||
|
||||
/* logging sections should be placed in RAM area to avoid flash cache disabled issues */
|
||||
#pragma push_macro("GROUP_ROM_LINK_IN")
|
||||
#undef GROUP_ROM_LINK_IN
|
||||
#define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN
|
||||
#include <zephyr/linker/common-rom/common-rom-logging.ld>
|
||||
#pragma pop_macro("GROUP_ROM_LINK_IN")
|
||||
|
||||
.dram0.end :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
#include <snippets-rwdata.ld>
|
||||
. = ALIGN(4);
|
||||
_end = ABSOLUTE(.);
|
||||
__data_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_DATA_REGION)
|
||||
|
||||
/* Shared RAM */
|
||||
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_bss_start = ABSOLUTE(.); /* required by bluetooth library */
|
||||
__bss_start = ABSOLUTE(.);
|
||||
|
||||
_btdm_bss_start = ABSOLUTE(.);
|
||||
*libbtdm_app.a:(.bss .bss.* COMMON)
|
||||
. = ALIGN (4);
|
||||
_btdm_bss_end = ABSOLUTE(.);
|
||||
|
||||
/* Buffer for system heap should be placed in dram0_0_seg */
|
||||
*libkernel.a:mempool.*(.noinit.kheap_buf__system_heap .noinit.*.kheap_buf__system_heap)
|
||||
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.share.mem)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN (8);
|
||||
__bss_end = ABSOLUTE(.);
|
||||
_end = ABSOLUTE(.);
|
||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
||||
|
||||
ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),
|
||||
"DRAM segment data does not fit.")
|
||||
|
||||
SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
*(.noinit)
|
||||
*(.noinit.*)
|
||||
. = ALIGN (8);
|
||||
} GROUP_LINK_IN(RAMABLE_REGION_1)
|
||||
|
||||
_image_irom_start = LOADADDR(.flash.text);
|
||||
_image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start;
|
||||
_image_irom_vaddr = ADDR(.flash.text);
|
||||
|
||||
.flash.text : ALIGN(4)
|
||||
{
|
||||
_stext = .;
|
||||
_text_start = ABSOLUTE(.);
|
||||
|
||||
*(.literal .text .literal.* .text.*)
|
||||
. = ALIGN(4);
|
||||
_text_end = ABSOLUTE(.);
|
||||
_etext = .;
|
||||
|
||||
/* Similar to _iram_start, this symbol goes here so it is
|
||||
resolved by addr2line in preference to the first symbol in
|
||||
the flash.text segment.
|
||||
*/
|
||||
_flash_cache_start = ABSOLUTE(0);
|
||||
} GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION)
|
||||
|
||||
_heap_sentry = 0x3ffe3f20;
|
||||
|
||||
#include <zephyr/linker/debug-sections.ld>
|
||||
|
||||
.xtensa.info 0 : { *(.xtensa.info) }
|
||||
.xt.insn 0 :
|
||||
{
|
||||
KEEP (*(.xt.insn))
|
||||
KEEP (*(.gnu.linkonce.x.*))
|
||||
}
|
||||
.xt.prop 0 :
|
||||
{
|
||||
KEEP (*(.xt.prop))
|
||||
KEEP (*(.xt.prop.*))
|
||||
KEEP (*(.gnu.linkonce.prop.*))
|
||||
}
|
||||
.xt.lit 0 :
|
||||
{
|
||||
KEEP (*(.xt.lit))
|
||||
KEEP (*(.xt.lit.*))
|
||||
KEEP (*(.gnu.linkonce.p.*))
|
||||
}
|
||||
.xt.profile_range 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_range))
|
||||
KEEP (*(.gnu.linkonce.profile_range.*))
|
||||
}
|
||||
.xt.profile_ranges 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_ranges))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
|
||||
}
|
||||
.xt.profile_files 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_files))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_files.*))
|
||||
}
|
||||
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
#include <zephyr/linker/intlist.ld>
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
|
||||
"IRAM0 segment data does not fit.")
|
||||
308
soc/espressif/esp32/esp32-mp.c
Normal file
308
soc/espressif/esp32/esp32-mp.c
Normal file
|
|
@ -0,0 +1,308 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Intel Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* Include esp-idf headers first to avoid redefining BIT() macro */
|
||||
#include <soc/dport_reg.h>
|
||||
#include <soc/gpio_periph.h>
|
||||
#include <soc/rtc_periph.h>
|
||||
|
||||
#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
|
||||
#include <soc.h>
|
||||
#include <ksched.h>
|
||||
#include <zephyr/device.h>
|
||||
#include <zephyr/kernel.h>
|
||||
#include <zephyr/spinlock.h>
|
||||
#include <zephyr/kernel_structs.h>
|
||||
|
||||
#define Z_REG(base, off) (*(volatile uint32_t *)((base) + (off)))
|
||||
|
||||
#define RTC_CNTL_BASE 0x3ff48000
|
||||
#define RTC_CNTL_OPTIONS0 Z_REG(RTC_CNTL_BASE, 0x0)
|
||||
#define RTC_CNTL_SW_CPU_STALL Z_REG(RTC_CNTL_BASE, 0xac)
|
||||
|
||||
#define DPORT_BASE 0x3ff00000
|
||||
#define DPORT_APPCPU_CTRL_A Z_REG(DPORT_BASE, 0x02C)
|
||||
#define DPORT_APPCPU_CTRL_B Z_REG(DPORT_BASE, 0x030)
|
||||
#define DPORT_APPCPU_CTRL_C Z_REG(DPORT_BASE, 0x034)
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
struct cpustart_rec {
|
||||
int cpu;
|
||||
arch_cpustart_t fn;
|
||||
char *stack_top;
|
||||
void *arg;
|
||||
int vecbase;
|
||||
volatile int *alive;
|
||||
};
|
||||
|
||||
volatile struct cpustart_rec *start_rec;
|
||||
static void *appcpu_top;
|
||||
static bool cpus_active[CONFIG_MP_MAX_NUM_CPUS];
|
||||
#endif
|
||||
static struct k_spinlock loglock;
|
||||
|
||||
|
||||
/* Note that the logging done here is ACTUALLY REQUIRED FOR RELIABLE
|
||||
* OPERATION! At least one particular board will experience spurious
|
||||
* hangs during initialization (usually the APPCPU fails to start at
|
||||
* all) without these calls present. It's not just time -- careful
|
||||
* use of k_busy_wait() (and even hand-crafted timer loops using the
|
||||
* Xtensa timer SRs directly) that duplicates the timing exactly still
|
||||
* sees hangs. Something is happening inside the ROM UART code that
|
||||
* magically makes the startup sequence reliable.
|
||||
*
|
||||
* Leave this in place until the sequence is understood better.
|
||||
*
|
||||
* (Note that the use of the spinlock is cosmetic only -- if you take
|
||||
* it out the messages will interleave across the two CPUs but startup
|
||||
* will still be reliable.)
|
||||
*/
|
||||
void smp_log(const char *msg)
|
||||
{
|
||||
#ifndef CONFIG_SOC_ESP32_PROCPU
|
||||
k_spinlock_key_t key = k_spin_lock(&loglock);
|
||||
|
||||
while (*msg) {
|
||||
esp_rom_uart_tx_one_char(*msg++);
|
||||
}
|
||||
esp_rom_uart_tx_one_char('\r');
|
||||
esp_rom_uart_tx_one_char('\n');
|
||||
|
||||
k_spin_unlock(&loglock, key);
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
static void appcpu_entry2(void)
|
||||
{
|
||||
volatile int ps, ie;
|
||||
|
||||
/* Copy over VECBASE from the main CPU for an initial value
|
||||
* (will need to revisit this if we ever allow a user API to
|
||||
* change interrupt vectors at runtime). Make sure interrupts
|
||||
* are locally disabled, then synthesize a PS value that will
|
||||
* enable them for the user code to pass to irq_unlock()
|
||||
* later.
|
||||
*/
|
||||
__asm__ volatile("rsr.PS %0" : "=r"(ps));
|
||||
ps &= ~(PS_EXCM_MASK | PS_INTLEVEL_MASK);
|
||||
__asm__ volatile("wsr.PS %0" : : "r"(ps));
|
||||
|
||||
ie = 0;
|
||||
__asm__ volatile("wsr.INTENABLE %0" : : "r"(ie));
|
||||
__asm__ volatile("wsr.VECBASE %0" : : "r"(start_rec->vecbase));
|
||||
__asm__ volatile("rsync");
|
||||
|
||||
/* Set up the CPU pointer. Really this should be xtensa arch
|
||||
* code, not in the ESP-32 layer
|
||||
*/
|
||||
_cpu_t *cpu = &_kernel.cpus[1];
|
||||
|
||||
__asm__ volatile("wsr.MISC0 %0" : : "r"(cpu));
|
||||
|
||||
smp_log("ESP32: APPCPU running");
|
||||
|
||||
*start_rec->alive = 1;
|
||||
start_rec->fn(start_rec->arg);
|
||||
}
|
||||
|
||||
/* Defines a locally callable "function" named _stack-switch(). The
|
||||
* first argument (in register a2 post-ENTRY) is the new stack pointer
|
||||
* to go into register a1. The second (a3) is the entry point.
|
||||
* Because this never returns, a0 is used as a scratch register then
|
||||
* set to zero for the called function (a null return value is the
|
||||
* signal for "top of stack" to the debugger).
|
||||
*/
|
||||
void z_appcpu_stack_switch(void *stack, void *entry);
|
||||
__asm__("\n"
|
||||
".align 4" "\n"
|
||||
"z_appcpu_stack_switch:" "\n\t"
|
||||
|
||||
"entry a1, 16" "\n\t"
|
||||
|
||||
/* Subtle: we want the stack to be 16 bytes higher than the
|
||||
* top on entry to the called function, because the ABI forces
|
||||
* it to assume that those bytes are for its caller's A0-A3
|
||||
* spill area. (In fact ENTRY instructions with stack
|
||||
* adjustments less than 16 are a warning condition in the
|
||||
* assembler). But we aren't a caller, have no bit set in
|
||||
* WINDOWSTART and will never be asked to spill anything.
|
||||
* Those 16 bytes would otherwise be wasted on the stack, so
|
||||
* adjust
|
||||
*/
|
||||
"addi a1, a2, 16" "\n\t"
|
||||
|
||||
/* Clear WINDOWSTART so called functions never try to spill
|
||||
* our callers' registers into the now-garbage stack pointers
|
||||
* they contain. No need to set the bit corresponding to
|
||||
* WINDOWBASE, our C callee will do that when it does an
|
||||
* ENTRY.
|
||||
*/
|
||||
"movi a0, 0" "\n\t"
|
||||
"wsr.WINDOWSTART a0" "\n\t"
|
||||
|
||||
/* Clear CALLINC field of PS (you would think it would, but
|
||||
* our ENTRY doesn't actually do that) so the callee's ENTRY
|
||||
* doesn't shift the registers
|
||||
*/
|
||||
"rsr.PS a0" "\n\t"
|
||||
"movi a2, 0xfffcffff" "\n\t"
|
||||
"and a0, a0, a2" "\n\t"
|
||||
"wsr.PS a0" "\n\t"
|
||||
|
||||
"rsync" "\n\t"
|
||||
"movi a0, 0" "\n\t"
|
||||
|
||||
"jx a3" "\n\t");
|
||||
|
||||
/* Carefully constructed to use no stack beyond compiler-generated ABI
|
||||
* instructions. WE DO NOT KNOW WHERE THE STACK FOR THIS FUNCTION IS.
|
||||
* The ROM library just picks a spot on its own with no input from our
|
||||
* app linkage and tells us nothing about it until we're already
|
||||
* running.
|
||||
*/
|
||||
static void appcpu_entry1(void)
|
||||
{
|
||||
z_appcpu_stack_switch(appcpu_top, appcpu_entry2);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* The calls and sequencing here were extracted from the ESP-32
|
||||
* FreeRTOS integration with just a tiny bit of cleanup. None of the
|
||||
* calls or registers shown are documented, so treat this code with
|
||||
* extreme caution.
|
||||
*/
|
||||
void esp_appcpu_start(void *entry_point)
|
||||
{
|
||||
smp_log("ESP32: starting APPCPU");
|
||||
|
||||
/* These two calls are wrapped in a "stall_other_cpu" API in
|
||||
* esp-idf. But in this context the appcpu is stalled by
|
||||
* definition, so we can skip that complexity and just call
|
||||
* the ROM directly.
|
||||
*/
|
||||
esp_rom_Cache_Flush(1);
|
||||
esp_rom_Cache_Read_Enable(1);
|
||||
|
||||
esp_rom_ets_set_appcpu_boot_addr((void *)0);
|
||||
|
||||
RTC_CNTL_SW_CPU_STALL &= ~RTC_CNTL_SW_STALL_APPCPU_C1;
|
||||
RTC_CNTL_OPTIONS0 &= ~RTC_CNTL_SW_STALL_APPCPU_C0;
|
||||
DPORT_APPCPU_CTRL_B |= DPORT_APPCPU_CLKGATE_EN;
|
||||
DPORT_APPCPU_CTRL_C &= ~DPORT_APPCPU_RUNSTALL;
|
||||
|
||||
/* Pulse the RESETTING bit */
|
||||
DPORT_APPCPU_CTRL_A |= DPORT_APPCPU_RESETTING;
|
||||
DPORT_APPCPU_CTRL_A &= ~DPORT_APPCPU_RESETTING;
|
||||
|
||||
|
||||
/* extracted from SMP LOG above, THIS IS REQUIRED FOR AMP RELIABLE
|
||||
* OPERATION AS WELL, PLEASE DON'T touch on the dummy write below!
|
||||
*
|
||||
* Note that the logging done here is ACTUALLY REQUIRED FOR RELIABLE
|
||||
* OPERATION! At least one particular board will experience spurious
|
||||
* hangs during initialization (usually the APPCPU fails to start at
|
||||
* all) without these calls present. It's not just time -- careful
|
||||
* use of k_busy_wait() (and even hand-crafted timer loops using the
|
||||
* Xtensa timer SRs directly) that duplicates the timing exactly still
|
||||
* sees hangs. Something is happening inside the ROM UART code that
|
||||
* magically makes the startup sequence reliable.
|
||||
*
|
||||
* Leave this in place until the sequence is understood better.
|
||||
*
|
||||
*/
|
||||
esp_rom_uart_tx_one_char('\r');
|
||||
esp_rom_uart_tx_one_char('\r');
|
||||
esp_rom_uart_tx_one_char('\n');
|
||||
|
||||
/* Seems weird that you set the boot address AFTER starting
|
||||
* the CPU, but this is how they do it...
|
||||
*/
|
||||
esp_rom_ets_set_appcpu_boot_addr((void *)entry_point);
|
||||
|
||||
smp_log("ESP32: APPCPU start sequence complete");
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
IRAM_ATTR static void esp_crosscore_isr(void *arg)
|
||||
{
|
||||
ARG_UNUSED(arg);
|
||||
|
||||
/* Right now this interrupt is only used for IPIs */
|
||||
z_sched_ipi();
|
||||
|
||||
const int core_id = esp_core_id();
|
||||
|
||||
if (core_id == 0) {
|
||||
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
|
||||
} else {
|
||||
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, 0);
|
||||
}
|
||||
}
|
||||
|
||||
void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
|
||||
arch_cpustart_t fn, void *arg)
|
||||
{
|
||||
volatile struct cpustart_rec sr;
|
||||
int vb;
|
||||
volatile int alive_flag;
|
||||
|
||||
__ASSERT(cpu_num == 1, "ESP-32 supports only two CPUs");
|
||||
|
||||
__asm__ volatile("rsr.VECBASE %0\n\t" : "=r"(vb));
|
||||
|
||||
alive_flag = 0;
|
||||
|
||||
sr.cpu = cpu_num;
|
||||
sr.fn = fn;
|
||||
sr.stack_top = Z_KERNEL_STACK_BUFFER(stack) + sz;
|
||||
sr.arg = arg;
|
||||
sr.vecbase = vb;
|
||||
sr.alive = &alive_flag;
|
||||
|
||||
appcpu_top = Z_KERNEL_STACK_BUFFER(stack) + sz;
|
||||
|
||||
start_rec = &sr;
|
||||
|
||||
esp_appcpu_start(appcpu_entry1);
|
||||
|
||||
while (!alive_flag) {
|
||||
}
|
||||
|
||||
cpus_active[0] = true;
|
||||
cpus_active[cpu_num] = true;
|
||||
|
||||
esp_intr_alloc(DT_IRQN(DT_NODELABEL(ipi0)),
|
||||
ESP_INTR_FLAG_IRAM,
|
||||
esp_crosscore_isr,
|
||||
NULL,
|
||||
NULL);
|
||||
|
||||
esp_intr_alloc(DT_IRQN(DT_NODELABEL(ipi1)),
|
||||
ESP_INTR_FLAG_IRAM,
|
||||
esp_crosscore_isr,
|
||||
NULL,
|
||||
NULL);
|
||||
|
||||
smp_log("ESP32: APPCPU initialized");
|
||||
}
|
||||
|
||||
void arch_sched_ipi(void)
|
||||
{
|
||||
const int core_id = esp_core_id();
|
||||
|
||||
if (core_id == 0) {
|
||||
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);
|
||||
} else {
|
||||
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, DPORT_CPU_INTR_FROM_CPU_1);
|
||||
}
|
||||
}
|
||||
|
||||
IRAM_ATTR bool arch_cpu_active(int cpu_num)
|
||||
{
|
||||
return cpus_active[cpu_num];
|
||||
}
|
||||
#endif /* CONFIG_SMP */
|
||||
794
soc/espressif/esp32/gdbstub.c
Normal file
794
soc/espressif/esp32/gdbstub.c
Normal file
|
|
@ -0,0 +1,794 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/kernel.h>
|
||||
#include <xtensa_asm2_context.h>
|
||||
#include <zephyr/debug/gdbstub.h>
|
||||
#include <offsets.h>
|
||||
|
||||
/*
|
||||
* Address Mappings From ESP32 Technical Reference Manual Version 4.5
|
||||
* https://www.espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf
|
||||
*/
|
||||
const struct gdb_mem_region gdb_mem_region_array[] = {
|
||||
{
|
||||
/* External Memory (Data Bus) */
|
||||
.start = 0x3F400000,
|
||||
.end = 0x3FBFFFFF,
|
||||
.attributes = GDB_MEM_REGION_RW,
|
||||
.alignment = 4,
|
||||
},
|
||||
{
|
||||
/* Peripheral (Data Bus) */
|
||||
.start = 0x3FF00000,
|
||||
.end = 0x3FF7FFFF,
|
||||
.attributes = GDB_MEM_REGION_RW,
|
||||
.alignment = 4,
|
||||
},
|
||||
{
|
||||
/* RTC FAST Memory (Data Bus) */
|
||||
.start = 0x3FF80000,
|
||||
.end = 0x3FF81FFF,
|
||||
.attributes = GDB_MEM_REGION_RW,
|
||||
.alignment = 4,
|
||||
},
|
||||
{
|
||||
/* Internal ROM 1 (Data Bus) */
|
||||
.start = 0x3FF90000,
|
||||
.end = 0x3FF9FFFF,
|
||||
.attributes = GDB_MEM_REGION_RO,
|
||||
.alignment = 4,
|
||||
},
|
||||
{
|
||||
/* Internal SRAM 1 and 2 (Data Bus) */
|
||||
.start = 0x3FFAE000,
|
||||
.end = 0x3FFFFFFF,
|
||||
.attributes = GDB_MEM_REGION_RW,
|
||||
.alignment = 4,
|
||||
},
|
||||
{
|
||||
/* Internal ROM 0 (Instruction Bus) */
|
||||
.start = 0x40000000,
|
||||
.end = 0x4005FFFF,
|
||||
.attributes = GDB_MEM_REGION_RO,
|
||||
.alignment = 4,
|
||||
},
|
||||
{
|
||||
/* Internal SRAM 0 and 1 (Instruction Bus) */
|
||||
.start = 0x40070000,
|
||||
.end = 0x400BFFFF,
|
||||
.attributes = GDB_MEM_REGION_RW,
|
||||
.alignment = 4,
|
||||
},
|
||||
{
|
||||
/* RTC FAST Memory (Instruction Bus) */
|
||||
.start = 0x400C0000,
|
||||
.end = 0x400C1FFF,
|
||||
.attributes = GDB_MEM_REGION_RW,
|
||||
.alignment = 4,
|
||||
},
|
||||
{
|
||||
/* External Memory (Instruction Bus) */
|
||||
.start = 0x400C2000,
|
||||
.end = 0x400CFFFF,
|
||||
.attributes = GDB_MEM_REGION_RW,
|
||||
.alignment = 4,
|
||||
},
|
||||
{
|
||||
/*
|
||||
* Flash memory obtained via GDB memory map
|
||||
* with ESP32's OpenOCD
|
||||
*/
|
||||
.start = 0x400D0000,
|
||||
.end = 0x400D5FFF,
|
||||
.attributes = GDB_MEM_REGION_RO,
|
||||
.alignment = 4,
|
||||
},
|
||||
{
|
||||
/* External Memory (Instruction Bus) */
|
||||
.start = 0x400D6000,
|
||||
.end = 0x40BFFFFF,
|
||||
.attributes = GDB_MEM_REGION_RW,
|
||||
.alignment = 4,
|
||||
},
|
||||
{
|
||||
/* RTC SLOW Memory (Data/Instruction Bus) */
|
||||
.start = 0x50000000,
|
||||
.end = 0x50001FFF,
|
||||
.attributes = GDB_MEM_REGION_RW,
|
||||
.alignment = 4,
|
||||
},
|
||||
};
|
||||
|
||||
const size_t gdb_mem_num_regions = ARRAY_SIZE(gdb_mem_region_array);
|
||||
|
||||
static struct xtensa_register gdb_reg_list[] = {
|
||||
{
|
||||
/* PC */
|
||||
.idx = 0,
|
||||
.regno = 0x0020,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 0,
|
||||
.stack_offset = ___xtensa_irq_bsa_t_pc_OFFSET,
|
||||
},
|
||||
{
|
||||
/* AR0 */
|
||||
.idx = 1,
|
||||
.regno = 0x100,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 4,
|
||||
},
|
||||
{
|
||||
/* AR1 */
|
||||
.idx = 2,
|
||||
.regno = 0x101,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 8,
|
||||
},
|
||||
{
|
||||
/* AR2 */
|
||||
.idx = 3,
|
||||
.regno = 0x102,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 12,
|
||||
},
|
||||
{
|
||||
/* AR3 */
|
||||
.idx = 4,
|
||||
.regno = 0x103,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 16,
|
||||
},
|
||||
{
|
||||
/* AR4 */
|
||||
.idx = 5,
|
||||
.regno = 0x104,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 20,
|
||||
},
|
||||
{
|
||||
/* AR5 */
|
||||
.idx = 6,
|
||||
.regno = 0x105,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 24,
|
||||
},
|
||||
{
|
||||
/* AR6 */
|
||||
.idx = 7,
|
||||
.regno = 0x106,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 28,
|
||||
},
|
||||
{
|
||||
/* AR7 */
|
||||
.idx = 8,
|
||||
.regno = 0x107,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 32,
|
||||
},
|
||||
{
|
||||
/* AR8 */
|
||||
.idx = 9,
|
||||
.regno = 0x108,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 36,
|
||||
},
|
||||
{
|
||||
/* AR9 */
|
||||
.idx = 10,
|
||||
.regno = 0x109,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 40,
|
||||
},
|
||||
{
|
||||
/* AR10 */
|
||||
.idx = 11,
|
||||
.regno = 0x10a,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 44,
|
||||
},
|
||||
{
|
||||
/* AR11 */
|
||||
.idx = 12,
|
||||
.regno = 0x10b,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 48,
|
||||
},
|
||||
{
|
||||
/* AR12 */
|
||||
.idx = 13,
|
||||
.regno = 0x10c,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 52,
|
||||
},
|
||||
{
|
||||
/* AR13 */
|
||||
.idx = 14,
|
||||
.regno = 0x10d,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 56,
|
||||
},
|
||||
{
|
||||
/* AR14 */
|
||||
.idx = 15,
|
||||
.regno = 0x10e,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 60,
|
||||
},
|
||||
{
|
||||
/* AR15 */
|
||||
.idx = 16,
|
||||
.regno = 0x10f,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 64,
|
||||
},
|
||||
{
|
||||
/* AR16 */
|
||||
.idx = 17,
|
||||
.regno = 0x110,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 68,
|
||||
},
|
||||
{
|
||||
/* AR17 */
|
||||
.idx = 18,
|
||||
.regno = 0x111,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 72,
|
||||
},
|
||||
{
|
||||
/* AR18 */
|
||||
.idx = 19,
|
||||
.regno = 0x112,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 76,
|
||||
},
|
||||
{
|
||||
/* AR19 */
|
||||
.idx = 20,
|
||||
.regno = 0x113,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 80,
|
||||
},
|
||||
{
|
||||
/* AR20 */
|
||||
.idx = 21,
|
||||
.regno = 0x114,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 84,
|
||||
},
|
||||
{
|
||||
/* AR21 */
|
||||
.idx = 22,
|
||||
.regno = 0x115,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 88,
|
||||
},
|
||||
{
|
||||
/* AR22 */
|
||||
.idx = 23,
|
||||
.regno = 0x116,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 92,
|
||||
},
|
||||
{
|
||||
/* AR23 */
|
||||
.idx = 24,
|
||||
.regno = 0x117,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 96,
|
||||
},
|
||||
{
|
||||
/* AR24 */
|
||||
.idx = 25,
|
||||
.regno = 0x118,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 100,
|
||||
},
|
||||
{
|
||||
/* AR25 */
|
||||
.idx = 26,
|
||||
.regno = 0x119,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 104,
|
||||
},
|
||||
{
|
||||
/* AR26 */
|
||||
.idx = 27,
|
||||
.regno = 0x11a,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 108,
|
||||
},
|
||||
{
|
||||
/* AR27 */
|
||||
.idx = 28,
|
||||
.regno = 0x11b,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 112,
|
||||
},
|
||||
{
|
||||
/* AR28 */
|
||||
.idx = 29,
|
||||
.regno = 0x11c,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 116,
|
||||
},
|
||||
{
|
||||
/* AR29 */
|
||||
.idx = 30,
|
||||
.regno = 0x11d,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 120,
|
||||
},
|
||||
{
|
||||
/* AR30 */
|
||||
.idx = 31,
|
||||
.regno = 0x11e,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 124,
|
||||
},
|
||||
{
|
||||
/* AR31 */
|
||||
.idx = 32,
|
||||
.regno = 0x11f,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 128,
|
||||
},
|
||||
{
|
||||
/* AR32 */
|
||||
.idx = 33,
|
||||
.regno = 0x120,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 132,
|
||||
},
|
||||
{
|
||||
/* AR33 */
|
||||
.idx = 34,
|
||||
.regno = 0x121,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 136,
|
||||
},
|
||||
{
|
||||
/* AR34 */
|
||||
.idx = 35,
|
||||
.regno = 0x122,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 140,
|
||||
},
|
||||
{
|
||||
/* AR35 */
|
||||
.idx = 36,
|
||||
.regno = 0x123,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 144,
|
||||
},
|
||||
{
|
||||
/* AR36 */
|
||||
.idx = 37,
|
||||
.regno = 0x124,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 148,
|
||||
},
|
||||
{
|
||||
/* AR37 */
|
||||
.idx = 38,
|
||||
.regno = 0x125,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 152,
|
||||
},
|
||||
{
|
||||
/* AR38 */
|
||||
.idx = 39,
|
||||
.regno = 0x126,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 156,
|
||||
},
|
||||
{
|
||||
/* AR39 */
|
||||
.idx = 40,
|
||||
.regno = 0x127,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 160,
|
||||
},
|
||||
{
|
||||
/* AR40 */
|
||||
.idx = 41,
|
||||
.regno = 0x128,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 164,
|
||||
},
|
||||
{
|
||||
/* AR41 */
|
||||
.idx = 42,
|
||||
.regno = 0x129,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 168,
|
||||
},
|
||||
{
|
||||
/* AR42 */
|
||||
.idx = 43,
|
||||
.regno = 0x12a,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 172,
|
||||
},
|
||||
{
|
||||
/* AR43 */
|
||||
.idx = 44,
|
||||
.regno = 0x12b,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 176,
|
||||
},
|
||||
{
|
||||
/* AR44 */
|
||||
.idx = 45,
|
||||
.regno = 0x12c,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 180,
|
||||
},
|
||||
{
|
||||
/* AR45 */
|
||||
.idx = 46,
|
||||
.regno = 0x12d,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 184,
|
||||
},
|
||||
{
|
||||
/* AR46 */
|
||||
.idx = 47,
|
||||
.regno = 0x12e,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 188,
|
||||
},
|
||||
{
|
||||
/* AR47 */
|
||||
.idx = 48,
|
||||
.regno = 0x12f,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 192,
|
||||
},
|
||||
{
|
||||
/* AR48 */
|
||||
.idx = 49,
|
||||
.regno = 0x130,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 196,
|
||||
},
|
||||
{
|
||||
/* AR49 */
|
||||
.idx = 50,
|
||||
.regno = 0x131,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 200,
|
||||
},
|
||||
{
|
||||
/* AR50 */
|
||||
.idx = 51,
|
||||
.regno = 0x132,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 204,
|
||||
},
|
||||
{
|
||||
/* AR51 */
|
||||
.idx = 52,
|
||||
.regno = 0x133,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 208,
|
||||
},
|
||||
{
|
||||
/* AR52 */
|
||||
.idx = 53,
|
||||
.regno = 0x134,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 212,
|
||||
},
|
||||
{
|
||||
/* AR53 */
|
||||
.idx = 54,
|
||||
.regno = 0x135,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 216,
|
||||
},
|
||||
{
|
||||
/* AR54 */
|
||||
.idx = 55,
|
||||
.regno = 0x136,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 220,
|
||||
},
|
||||
{
|
||||
/* AR55 */
|
||||
.idx = 56,
|
||||
.regno = 0x137,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 224,
|
||||
},
|
||||
{
|
||||
/* AR56 */
|
||||
.idx = 57,
|
||||
.regno = 0x138,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 228,
|
||||
},
|
||||
{
|
||||
/* AR57 */
|
||||
.idx = 58,
|
||||
.regno = 0x139,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 232,
|
||||
},
|
||||
{
|
||||
/* AR58 */
|
||||
.idx = 59,
|
||||
.regno = 0x13a,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 236,
|
||||
},
|
||||
{
|
||||
/* AR59 */
|
||||
.idx = 60,
|
||||
.regno = 0x13b,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 240,
|
||||
},
|
||||
{
|
||||
/* AR60 */
|
||||
.idx = 61,
|
||||
.regno = 0x13c,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 244,
|
||||
},
|
||||
{
|
||||
/* AR61 */
|
||||
.idx = 62,
|
||||
.regno = 0x13d,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 248,
|
||||
},
|
||||
{
|
||||
/* AR62 */
|
||||
.idx = 63,
|
||||
.regno = 0x13e,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 252,
|
||||
},
|
||||
{
|
||||
/* AR63 */
|
||||
.idx = 64,
|
||||
.regno = 0x13f,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 256,
|
||||
},
|
||||
{
|
||||
/* LBEG */
|
||||
.idx = 65,
|
||||
.regno = 0x0200,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 260,
|
||||
.stack_offset = ___xtensa_irq_bsa_t_lbeg_OFFSET,
|
||||
},
|
||||
{
|
||||
/* LEND */
|
||||
.idx = 66,
|
||||
.regno = 0x0201,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 264,
|
||||
.stack_offset = ___xtensa_irq_bsa_t_lend_OFFSET,
|
||||
},
|
||||
{
|
||||
/* LCOUNT */
|
||||
.idx = 67,
|
||||
.regno = 0x0202,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 268,
|
||||
.stack_offset = ___xtensa_irq_bsa_t_lcount_OFFSET,
|
||||
},
|
||||
{
|
||||
/* SAR */
|
||||
.idx = 68,
|
||||
.regno = 0x0203,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 272,
|
||||
.stack_offset = ___xtensa_irq_bsa_t_sar_OFFSET,
|
||||
},
|
||||
{
|
||||
/* WINDOWBASE */
|
||||
.idx = 69,
|
||||
.regno = 0x0248,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 276,
|
||||
.is_read_only = 1,
|
||||
},
|
||||
{
|
||||
/* WINDOWSTART */
|
||||
.idx = 70,
|
||||
.regno = 0x0249,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 280,
|
||||
.is_read_only = 1,
|
||||
},
|
||||
{
|
||||
/* PS */
|
||||
.idx = 73,
|
||||
.regno = 0x02E6,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 292,
|
||||
.stack_offset = ___xtensa_irq_bsa_t_ps_OFFSET,
|
||||
},
|
||||
{
|
||||
/* THREADPTR */
|
||||
.idx = 74,
|
||||
.regno = 0x02E7,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 296,
|
||||
#ifdef CONFIG_THREAD_LOCAL_STORAGE
|
||||
/* Only saved in stack if TLS is enabled */
|
||||
.stack_offset = ___xtensa_irq_bsa_t_threadptr_OFFSET,
|
||||
#endif
|
||||
},
|
||||
{
|
||||
/* SCOMPARE1 */
|
||||
.idx = 76,
|
||||
.regno = 0x020C,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 304,
|
||||
.stack_offset = ___xtensa_irq_bsa_t_scompare1_OFFSET,
|
||||
},
|
||||
{
|
||||
/* EXCCAUSE */
|
||||
.idx = 143,
|
||||
.regno = 0x02E8,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 572,
|
||||
.stack_offset = ___xtensa_irq_bsa_t_exccause_OFFSET,
|
||||
},
|
||||
{
|
||||
/* DEBUGCAUSE */
|
||||
.idx = 144,
|
||||
.regno = 0x02E9,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 576,
|
||||
},
|
||||
{
|
||||
/* EXCVADDR */
|
||||
.idx = 149,
|
||||
.regno = 0x02EE,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 596,
|
||||
},
|
||||
{
|
||||
/* A0 */
|
||||
.idx = 157,
|
||||
.regno = 0x0000,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 628,
|
||||
.stack_offset = ___xtensa_irq_bsa_t_a0_OFFSET,
|
||||
},
|
||||
{
|
||||
/* A1 */
|
||||
.idx = 158,
|
||||
.regno = 0x0001,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 632,
|
||||
},
|
||||
{
|
||||
/* A2 */
|
||||
.idx = 159,
|
||||
.regno = 0x0002,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 636,
|
||||
.stack_offset = ___xtensa_irq_bsa_t_a2_OFFSET,
|
||||
},
|
||||
{
|
||||
/* A3 */
|
||||
.idx = 160,
|
||||
.regno = 0x0003,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 640,
|
||||
.stack_offset = ___xtensa_irq_bsa_t_a3_OFFSET,
|
||||
},
|
||||
{
|
||||
/* A4 */
|
||||
.idx = 161,
|
||||
.regno = 0x0004,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 644,
|
||||
.stack_offset = -16,
|
||||
},
|
||||
{
|
||||
/* A5 */
|
||||
.idx = 162,
|
||||
.regno = 0x0005,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 648,
|
||||
.stack_offset = -12,
|
||||
},
|
||||
{
|
||||
/* A6 */
|
||||
.idx = 163,
|
||||
.regno = 0x0006,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 652,
|
||||
.stack_offset = -8,
|
||||
},
|
||||
{
|
||||
/* A7 */
|
||||
.idx = 164,
|
||||
.regno = 0x0007,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 656,
|
||||
.stack_offset = -4,
|
||||
},
|
||||
{
|
||||
/* A8 */
|
||||
.idx = 165,
|
||||
.regno = 0x0008,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 660,
|
||||
.stack_offset = -32,
|
||||
},
|
||||
{
|
||||
/* A9 */
|
||||
.idx = 166,
|
||||
.regno = 0x0009,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 664,
|
||||
.stack_offset = -28,
|
||||
},
|
||||
{
|
||||
/* A10 */
|
||||
.idx = 167,
|
||||
.regno = 0x000A,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 668,
|
||||
.stack_offset = -24,
|
||||
},
|
||||
{
|
||||
/* A11 */
|
||||
.idx = 168,
|
||||
.regno = 0x000B,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 672,
|
||||
.stack_offset = -20,
|
||||
},
|
||||
{
|
||||
/* A12 */
|
||||
.idx = 169,
|
||||
.regno = 0x000C,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 676,
|
||||
.stack_offset = -48,
|
||||
},
|
||||
{
|
||||
/* A13 */
|
||||
.idx = 170,
|
||||
.regno = 0x000D,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 680,
|
||||
.stack_offset = -44,
|
||||
},
|
||||
{
|
||||
/* A14 */
|
||||
.idx = 171,
|
||||
.regno = 0x000E,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 684,
|
||||
.stack_offset = -40,
|
||||
},
|
||||
{
|
||||
/* A15 */
|
||||
.idx = 172,
|
||||
.regno = 0x000F,
|
||||
.byte_size = 4,
|
||||
.gpkt_offset = 688,
|
||||
.stack_offset = -36,
|
||||
},
|
||||
};
|
||||
|
||||
struct gdb_ctx xtensa_gdb_ctx = {
|
||||
.regs = gdb_reg_list,
|
||||
.num_regs = ARRAY_SIZE(gdb_reg_list),
|
||||
};
|
||||
108
soc/espressif/esp32/loader.c
Normal file
108
soc/espressif/esp32/loader.c
Normal file
|
|
@ -0,0 +1,108 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/kernel.h>
|
||||
#include <soc.h>
|
||||
#include <zephyr/storage/flash_map.h>
|
||||
#include <esp_log.h>
|
||||
|
||||
#include <esp32/rom/cache.h>
|
||||
#include <soc/dport_reg.h>
|
||||
#include <bootloader_flash_priv.h>
|
||||
|
||||
#ifdef CONFIG_BOOTLOADER_MCUBOOT
|
||||
|
||||
#define BOOT_LOG_INF(_fmt, ...) \
|
||||
ets_printf("[" CONFIG_SOC_SERIES "] [INF] " _fmt "\n\r", ##__VA_ARGS__)
|
||||
|
||||
#define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used))
|
||||
|
||||
extern uint32_t _image_irom_start, _image_irom_size, _image_irom_vaddr;
|
||||
extern uint32_t _image_drom_start, _image_drom_size, _image_drom_vaddr;
|
||||
|
||||
void __start(void);
|
||||
|
||||
static HDR_ATTR void (*_entry_point)(void) = &__start;
|
||||
|
||||
static int map_rom_segments(void)
|
||||
{
|
||||
int rc = 0;
|
||||
size_t _partition_offset = FIXED_PARTITION_OFFSET(slot0_partition);
|
||||
uint32_t _app_irom_start = _partition_offset +
|
||||
(uint32_t)&_image_irom_start;
|
||||
uint32_t _app_irom_size = (uint32_t)&_image_irom_size;
|
||||
uint32_t _app_irom_vaddr = (uint32_t)&_image_irom_vaddr;
|
||||
|
||||
uint32_t _app_drom_start = _partition_offset +
|
||||
(uint32_t)&_image_drom_start;
|
||||
uint32_t _app_drom_size = (uint32_t)&_image_drom_size;
|
||||
uint32_t _app_drom_vaddr = (uint32_t)&_image_drom_vaddr;
|
||||
|
||||
Cache_Read_Disable(0);
|
||||
Cache_Flush(0);
|
||||
/* Clear the MMU entries that are already set up,
|
||||
* so the new app only has the mappings it creates.
|
||||
*/
|
||||
for (int i = 0; i < DPORT_FLASH_MMU_TABLE_SIZE; i++) {
|
||||
DPORT_PRO_FLASH_MMU_TABLE[i] =
|
||||
DPORT_FLASH_MMU_TABLE_INVALID_VAL;
|
||||
}
|
||||
|
||||
uint32_t drom_vaddr_addr_aligned = _app_drom_vaddr & MMU_FLASH_MASK;
|
||||
uint32_t drom_page_count = bootloader_cache_pages_to_map(_app_drom_size,
|
||||
_app_drom_vaddr);
|
||||
rc = cache_flash_mmu_set(0, 0, drom_vaddr_addr_aligned, _app_drom_start
|
||||
& MMU_FLASH_MASK, 64, drom_page_count);
|
||||
rc |= cache_flash_mmu_set(1, 0, drom_vaddr_addr_aligned, _app_drom_start
|
||||
& MMU_FLASH_MASK, 64, drom_page_count);
|
||||
|
||||
uint32_t irom_vaddr_addr_aligned = _app_irom_vaddr & MMU_FLASH_MASK;
|
||||
uint32_t irom_page_count = bootloader_cache_pages_to_map(_app_irom_size,
|
||||
_app_irom_vaddr);
|
||||
rc |= cache_flash_mmu_set(0, 0, irom_vaddr_addr_aligned, _app_irom_start
|
||||
& MMU_FLASH_MASK, 64, irom_page_count);
|
||||
rc |= cache_flash_mmu_set(1, 0, irom_vaddr_addr_aligned, _app_irom_start
|
||||
& MMU_FLASH_MASK, 64, irom_page_count);
|
||||
|
||||
DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG,
|
||||
(DPORT_PRO_CACHE_MASK_IRAM0) |
|
||||
(DPORT_PRO_CACHE_MASK_IRAM1 & 0) |
|
||||
(DPORT_PRO_CACHE_MASK_IROM0 & 0) |
|
||||
DPORT_PRO_CACHE_MASK_DROM0 |
|
||||
DPORT_PRO_CACHE_MASK_DRAM1);
|
||||
|
||||
DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG,
|
||||
(DPORT_APP_CACHE_MASK_IRAM0) |
|
||||
(DPORT_APP_CACHE_MASK_IRAM1 & 0) |
|
||||
(DPORT_APP_CACHE_MASK_IROM0 & 0) |
|
||||
DPORT_APP_CACHE_MASK_DROM0 |
|
||||
DPORT_APP_CACHE_MASK_DRAM1);
|
||||
|
||||
esp_rom_Cache_Read_Enable(0);
|
||||
|
||||
/* Show map segments continue using same log format as during MCUboot phase */
|
||||
BOOT_LOG_INF("DROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map",
|
||||
_app_drom_start, _app_drom_vaddr, _app_drom_size, _app_drom_size);
|
||||
BOOT_LOG_INF("IROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map\r\n",
|
||||
_app_irom_start, _app_irom_vaddr, _app_irom_size, _app_irom_size);
|
||||
esp_rom_uart_tx_wait_idle(0);
|
||||
|
||||
return rc;
|
||||
}
|
||||
#endif
|
||||
|
||||
void __start(void)
|
||||
{
|
||||
#ifdef CONFIG_BOOTLOADER_MCUBOOT
|
||||
int err = map_rom_segments();
|
||||
|
||||
if (err != 0) {
|
||||
ets_printf("Failed to setup XIP, aborting\n");
|
||||
abort();
|
||||
}
|
||||
#endif
|
||||
__esp_platform_start();
|
||||
}
|
||||
362
soc/espressif/esp32/mcuboot.ld
Normal file
362
soc/espressif/esp32/mcuboot.ld
Normal file
|
|
@ -0,0 +1,362 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Linker command/script file
|
||||
*
|
||||
* Linker script for the MCUboot on Xtensa platform.
|
||||
*/
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/linker/sections.h>
|
||||
#include <zephyr/linker/linker-defs.h>
|
||||
#include <zephyr/linker/linker-tool.h>
|
||||
|
||||
#ifdef CONFIG_XIP
|
||||
#error "Xtensa bootloader cannot use XIP"
|
||||
#endif /* CONFIG_XIP */
|
||||
|
||||
/* Disable all romable LMA */
|
||||
#undef GROUP_DATA_LINK_IN
|
||||
#define GROUP_DATA_LINK_IN(vregion, lregion) > vregion
|
||||
|
||||
#define RAMABLE_REGION dram_seg
|
||||
#define RAMABLE_REGION_1 dram_seg
|
||||
|
||||
#define RODATA_REGION dram_seg
|
||||
#define ROMABLE_REGION dram_seg
|
||||
|
||||
#define IRAM_REGION iram_seg
|
||||
#define FLASH_CODE_REGION iram_seg
|
||||
|
||||
#define IROM_SEG_ALIGN 16
|
||||
|
||||
MEMORY
|
||||
{
|
||||
iram_loader_seg (RWX) : org = 0x40078000, len = 0x4000
|
||||
iram_seg (RWX) : org = 0x4009C000, len = 0x8000
|
||||
dram_seg (RW) : org = 0x3FFF0000, len = 0x6000
|
||||
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000
|
||||
#endif
|
||||
}
|
||||
|
||||
ENTRY(CONFIG_KERNEL_ENTRY)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* NOTE: .rodata section should be the first section in the linker script and no
|
||||
* other section should appear before .rodata section. This is the requirement
|
||||
* to align ROM section to 64K page offset.
|
||||
* Adding .rodata as first section helps to reduce size of generated binary by
|
||||
* few kBs.
|
||||
*/
|
||||
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
|
||||
{
|
||||
__rodata_region_start = ABSOLUTE(.);
|
||||
|
||||
. = ALIGN(4);
|
||||
#include <snippets-rodata.ld>
|
||||
|
||||
. = ALIGN(4);
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
|
||||
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
|
||||
*(.xt_except_table)
|
||||
*(.gcc_except_table .gcc_except_table.*)
|
||||
*(.gnu.linkonce.e.*)
|
||||
*(.gnu.version_r)
|
||||
. = (. + 3) & ~ 3;
|
||||
__eh_frame = ABSOLUTE(.);
|
||||
KEEP(*(.eh_frame))
|
||||
. = (. + 7) & ~ 3;
|
||||
|
||||
/* C++ exception handlers table: */
|
||||
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
|
||||
*(.xt_except_desc)
|
||||
*(.gnu.linkonce.h.*)
|
||||
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc_end)
|
||||
*(.dynamic)
|
||||
*(.gnu.version_d)
|
||||
. = ALIGN(4);
|
||||
__rodata_region_end = ABSOLUTE(.);
|
||||
/* Literals are also RO data. */
|
||||
_lit4_start = ABSOLUTE(.);
|
||||
*(*.lit4)
|
||||
*(.lit4.*)
|
||||
*(.gnu.linkonce.lit4.*)
|
||||
_lit4_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
_thread_local_start = ABSOLUTE(.);
|
||||
*(.tdata)
|
||||
*(.tdata.*)
|
||||
*(.tbss)
|
||||
*(.tbss.*)
|
||||
*(.rodata_wlog)
|
||||
*(.rodata_wlog*)
|
||||
_thread_local_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
} GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)
|
||||
|
||||
#include <zephyr/linker/common-rom/common-rom-cpp.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-kernel-devices.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-debug.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-misc.ld>
|
||||
#include <snippets-sections.ld>
|
||||
|
||||
.dram0.data :
|
||||
{
|
||||
__data_start = ABSOLUTE(.);
|
||||
|
||||
_btdm_data_start = ABSOLUTE(.);
|
||||
*libbtdm_app.a:(.data .data.*)
|
||||
. = ALIGN (4);
|
||||
_btdm_data_end = ABSOLUTE(.);
|
||||
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
|
||||
KEEP(*(.jcr))
|
||||
*(.dram1 .dram1.*)
|
||||
. = ALIGN(4);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
|
||||
|
||||
#include <zephyr/linker/cplusplus-rom.ld>
|
||||
#include <snippets-data-sections.ld>
|
||||
#include <zephyr/linker/common-ram.ld>
|
||||
#include <snippets-ram-sections.ld>
|
||||
#include <zephyr/linker/cplusplus-ram.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-logging.ld>
|
||||
|
||||
.dram0.end :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
#include <snippets-rwdata.ld>
|
||||
. = ALIGN(4);
|
||||
_end = ABSOLUTE(.);
|
||||
__data_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
|
||||
|
||||
/* Send .iram0 code to iram */
|
||||
.iram0.vectors : ALIGN(4)
|
||||
{
|
||||
/* Vectors go to IRAM */
|
||||
_init_start = ABSOLUTE(.);
|
||||
/* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
|
||||
. = 0x0;
|
||||
KEEP(*(.WindowVectors.text));
|
||||
. = 0x180;
|
||||
KEEP(*(.Level2InterruptVector.text));
|
||||
. = 0x1c0;
|
||||
KEEP(*(.Level3InterruptVector.text));
|
||||
. = 0x200;
|
||||
KEEP(*(.Level4InterruptVector.text));
|
||||
. = 0x240;
|
||||
KEEP(*(.Level5InterruptVector.text));
|
||||
. = 0x280;
|
||||
KEEP(*(.DebugExceptionVector.text));
|
||||
. = 0x2c0;
|
||||
KEEP(*(.NMIExceptionVector.text));
|
||||
. = 0x300;
|
||||
KEEP(*(.KernelExceptionVector.text));
|
||||
. = 0x340;
|
||||
KEEP(*(.UserExceptionVector.text));
|
||||
. = 0x3C0;
|
||||
KEEP(*(.DoubleExceptionVector.text));
|
||||
. = 0x400;
|
||||
*(.*Vector.literal)
|
||||
|
||||
*(.UserEnter.literal);
|
||||
*(.UserEnter.text);
|
||||
. = ALIGN (16);
|
||||
*(.entry.text)
|
||||
*(.init.literal)
|
||||
*(.init)
|
||||
_init_end = ABSOLUTE(.);
|
||||
|
||||
/* This goes here, not at top of linker script, so addr2line finds it last,
|
||||
* and uses it in preference to the first symbol in IRAM
|
||||
*/
|
||||
_iram_start = ABSOLUTE(0);
|
||||
} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
|
||||
|
||||
.iram_loader.text :
|
||||
{
|
||||
. = ALIGN (16);
|
||||
_loader_text_start = ABSOLUTE(.);
|
||||
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||||
*(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
|
||||
*libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_flash_config_esp32.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_init_common.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_random.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
|
||||
*libzephyr.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
|
||||
*libzephyr.a:bootloader_efuse_esp32.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_utility.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_sha.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_console.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_panic.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_soc.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:esp_image_format.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:flash_encrypt.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:flash_partitions.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:secure_boot.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:esp_efuse_table.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:esp_efuse_fields.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:esp_efuse_api.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:esp_efuse_utility.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:esp_efuse_api_key_esp32.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:app_cpu_start.*(.literal .text .literal.* .text.*)
|
||||
*esp_mcuboot.*(.literal .text .literal.* .text.*)
|
||||
*esp_loader.*(.literal .text .literal.* .text.*)
|
||||
*(.fini.literal)
|
||||
*(.fini)
|
||||
*(.gnu.version)
|
||||
_loader_text_end = ABSOLUTE(.);
|
||||
} > iram_loader_seg
|
||||
|
||||
SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))
|
||||
{
|
||||
/* Code marked as running out of IRAM */
|
||||
_iram_text_start = ABSOLUTE(.);
|
||||
*(.iram1 .iram1.*)
|
||||
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
|
||||
|
||||
. = ALIGN(4);
|
||||
_iram_text_end = ABSOLUTE(.);
|
||||
_iram_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
|
||||
|
||||
/* Shared RAM */
|
||||
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_bss_start = ABSOLUTE(.); /* required by bluetooth library */
|
||||
__bss_start = ABSOLUTE(.);
|
||||
|
||||
_btdm_bss_start = ABSOLUTE(.);
|
||||
*libbtdm_app.a:(.bss .bss.* COMMON)
|
||||
. = ALIGN (4);
|
||||
_btdm_bss_end = ABSOLUTE(.);
|
||||
|
||||
/* Buffer for system heap should be placed in dram_seg */
|
||||
*libkernel.a:mempool.*(.noinit.kheap_buf__system_heap .noinit.*.kheap_buf__system_heap)
|
||||
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.share.mem)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN (8);
|
||||
__bss_end = ABSOLUTE(.);
|
||||
_bss_end = ABSOLUTE(.);
|
||||
_end = ABSOLUTE(.);
|
||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
||||
|
||||
ASSERT(((__bss_end - ORIGIN(RAMABLE_REGION)) <= LENGTH(RAMABLE_REGION)),
|
||||
"DRAM segment data does not fit.")
|
||||
|
||||
SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
*(.noinit)
|
||||
*(.noinit.*)
|
||||
. = ALIGN (8);
|
||||
} GROUP_LINK_IN(RAMABLE_REGION_1)
|
||||
|
||||
.flash.text : ALIGN(IROM_SEG_ALIGN)
|
||||
{
|
||||
_stext = .;
|
||||
_text_start = ABSOLUTE(.);
|
||||
|
||||
*(.literal .text .literal.* .text.*)
|
||||
. = ALIGN(4);
|
||||
_text_end = ABSOLUTE(.);
|
||||
_etext = .;
|
||||
|
||||
/* Similar to _iram_start, this symbol goes here so it is
|
||||
* resolved by addr2line in preference to the first symbol in
|
||||
* the flash.text segment.
|
||||
*/
|
||||
_flash_cache_start = ABSOLUTE(0);
|
||||
} GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION)
|
||||
|
||||
#include <zephyr/linker/debug-sections.ld>
|
||||
|
||||
.xtensa.info 0 : { *(.xtensa.info) }
|
||||
.xt.insn 0 :
|
||||
{
|
||||
KEEP (*(.xt.insn))
|
||||
KEEP (*(.gnu.linkonce.x.*))
|
||||
}
|
||||
.xt.prop 0 :
|
||||
{
|
||||
KEEP (*(.xt.prop))
|
||||
KEEP (*(.xt.prop.*))
|
||||
KEEP (*(.gnu.linkonce.prop.*))
|
||||
}
|
||||
.xt.lit 0 :
|
||||
{
|
||||
KEEP (*(.xt.lit))
|
||||
KEEP (*(.xt.lit.*))
|
||||
KEEP (*(.gnu.linkonce.p.*))
|
||||
}
|
||||
.xt.profile_range 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_range))
|
||||
KEEP (*(.gnu.linkonce.profile_range.*))
|
||||
}
|
||||
.xt.profile_ranges 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_ranges))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
|
||||
}
|
||||
.xt.profile_files 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_files))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_files.*))
|
||||
}
|
||||
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
#include <zephyr/linker/intlist.ld>
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
ASSERT(((_iram_end - ORIGIN(IRAM_REGION)) <= LENGTH(IRAM_REGION)),
|
||||
"IRAM0 segment data does not fit.")
|
||||
22
soc/espressif/esp32/newlib_fix.c
Normal file
22
soc/espressif/esp32/newlib_fix.c
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* Copyright (c) 2019, Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/toolchain.h>
|
||||
#include <stdio.h>
|
||||
#include <stddef.h>
|
||||
#include <unistd.h>
|
||||
#include <sys/stat.h>
|
||||
|
||||
#include <reent.h>
|
||||
|
||||
int __weak _gettimeofday_r(struct _reent *r, struct timeval *__tp, void *__tzp)
|
||||
{
|
||||
ARG_UNUSED(r);
|
||||
ARG_UNUSED(__tp);
|
||||
ARG_UNUSED(__tzp);
|
||||
|
||||
return -1;
|
||||
}
|
||||
78
soc/espressif/esp32/pinctrl_soc.h
Normal file
78
soc/espressif/esp32/pinctrl_soc.h
Normal file
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* ESP32 SoC specific helpers for pinctrl driver
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_XTENSA_ESP32_PINCTRL_SOC_H_
|
||||
#define ZEPHYR_SOC_XTENSA_ESP32_PINCTRL_SOC_H_
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/types.h>
|
||||
|
||||
#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
|
||||
|
||||
/** @cond INTERNAL_HIDDEN */
|
||||
|
||||
/** Type for ESP32 pin. */
|
||||
typedef struct pinctrl_soc_pin {
|
||||
/** Pinmux settings (pin, direction and signal). */
|
||||
uint32_t pinmux;
|
||||
/** Pincfg settings (bias). */
|
||||
uint32_t pincfg;
|
||||
} pinctrl_soc_pin_t;
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize pinmux field in #pinctrl_pin_t.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
*/
|
||||
#define Z_PINCTRL_ESP32_PINMUX_INIT(node_id, prop, idx) DT_PROP_BY_IDX(node_id, prop, idx)
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
*/
|
||||
#define Z_PINCTRL_ESP32_PINCFG_INIT(node_id) \
|
||||
(((ESP32_NO_PULL * DT_PROP(node_id, bias_disable)) << ESP32_PIN_BIAS_SHIFT) | \
|
||||
((ESP32_PULL_UP * DT_PROP(node_id, bias_pull_up)) << ESP32_PIN_BIAS_SHIFT) | \
|
||||
((ESP32_PULL_DOWN * DT_PROP(node_id, bias_pull_down)) << ESP32_PIN_BIAS_SHIFT) | \
|
||||
((ESP32_PUSH_PULL * DT_PROP(node_id, drive_push_pull)) << ESP32_PIN_DRV_SHIFT) | \
|
||||
((ESP32_OPEN_DRAIN * DT_PROP(node_id, drive_open_drain)) << ESP32_PIN_DRV_SHIFT) | \
|
||||
((ESP32_PIN_OUT_HIGH * DT_PROP(node_id, output_high)) << ESP32_PIN_OUT_SHIFT) | \
|
||||
((ESP32_PIN_OUT_LOW * DT_PROP(node_id, output_low)) << ESP32_PIN_OUT_SHIFT) | \
|
||||
((ESP32_PIN_OUT_EN * DT_PROP(node_id, output_enable)) << ESP32_PIN_EN_DIR_SHIFT) | \
|
||||
((ESP32_PIN_IN_EN * DT_PROP(node_id, input_enable)) << ESP32_PIN_EN_DIR_SHIFT))
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize each pin.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param prop Property name.
|
||||
* @param idx Property entry index.
|
||||
*/
|
||||
#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
|
||||
{.pinmux = Z_PINCTRL_ESP32_PINMUX_INIT(node_id, prop, idx), \
|
||||
.pincfg = Z_PINCTRL_ESP32_PINCFG_INIT(node_id)},
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize state pins contained in a given property.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param prop Property name describing state pins.
|
||||
*/
|
||||
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||
{ \
|
||||
DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \
|
||||
Z_PINCTRL_STATE_PIN_INIT) \
|
||||
}
|
||||
|
||||
/** @endcond */
|
||||
|
||||
#endif /* ZEPHYR_SOC_XTENSA_ESP32_PINCTRL_SOC_H_ */
|
||||
48
soc/espressif/esp32/power.c
Normal file
48
soc/espressif/esp32/power.c
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/kernel.h>
|
||||
#include <zephyr/pm/pm.h>
|
||||
#include <esp_sleep.h>
|
||||
#include <soc/rtc_io_channel.h>
|
||||
#include <hal/rtc_io_hal.h>
|
||||
|
||||
#include <zephyr/logging/log.h>
|
||||
LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
|
||||
|
||||
static uint32_t intenable;
|
||||
|
||||
/* Invoke Low Power/System Off specific Tasks */
|
||||
void pm_state_set(enum pm_state state, uint8_t substate_id)
|
||||
{
|
||||
ARG_UNUSED(substate_id);
|
||||
|
||||
switch (state) {
|
||||
case PM_STATE_STANDBY:
|
||||
intenable = XTENSA_RSR("INTENABLE");
|
||||
__asm__ volatile ("waiti 0");
|
||||
break;
|
||||
default:
|
||||
LOG_DBG("Unsupported power state %u", state);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Handle SOC specific activity after Low Power Mode Exit */
|
||||
void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
|
||||
{
|
||||
ARG_UNUSED(substate_id);
|
||||
|
||||
switch (state) {
|
||||
case PM_STATE_STANDBY:
|
||||
z_xt_ints_on(intenable);
|
||||
esp_light_sleep_start();
|
||||
break;
|
||||
default:
|
||||
LOG_DBG("Unsupported power state %u", state);
|
||||
break;
|
||||
}
|
||||
}
|
||||
23
soc/espressif/esp32/poweroff.c
Normal file
23
soc/espressif/esp32/poweroff.c
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/sys/poweroff.h>
|
||||
|
||||
#include <esp_sleep.h>
|
||||
#include <hal/rtc_io_hal.h>
|
||||
#include <soc/rtc_io_channel.h>
|
||||
|
||||
void z_sys_poweroff(void)
|
||||
{
|
||||
/*
|
||||
* Isolate GPIO12 pin from external circuits. This is needed for modules
|
||||
* which have an external pull-up resistor on GPIO12 (such as ESP32-WROVER)
|
||||
* to minimize current consumption.
|
||||
*/
|
||||
rtcio_hal_isolate(RTCIO_GPIO12_CHANNEL);
|
||||
/* Forces RTC domain to be always on */
|
||||
esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
|
||||
esp_deep_sleep_start();
|
||||
}
|
||||
266
soc/espressif/esp32/soc.c
Normal file
266
soc/espressif/esp32/soc.c
Normal file
|
|
@ -0,0 +1,266 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Intel Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* Include esp-idf headers first to avoid redefining BIT() macro */
|
||||
#include <soc.h>
|
||||
#include <soc/rtc_cntl_reg.h>
|
||||
#include <soc/timer_group_reg.h>
|
||||
#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
|
||||
#include <xtensa/config/core-isa.h>
|
||||
#include <xtensa/corebits.h>
|
||||
|
||||
#include <zephyr/kernel_structs.h>
|
||||
#include <string.h>
|
||||
#include <zephyr/toolchain.h>
|
||||
#include <zephyr/types.h>
|
||||
#include <zephyr/linker/linker-defs.h>
|
||||
#include <kernel_internal.h>
|
||||
|
||||
#include "esp_private/system_internal.h"
|
||||
#include "esp32/rom/cache.h"
|
||||
#include "hal/soc_ll.h"
|
||||
#include "soc/cpu.h"
|
||||
#include "soc/gpio_periph.h"
|
||||
#include "esp_spi_flash.h"
|
||||
#include "esp_err.h"
|
||||
#include "esp_timer.h"
|
||||
#include "esp32/spiram.h"
|
||||
#include "esp_app_format.h"
|
||||
#include "hal/wdt_hal.h"
|
||||
|
||||
#ifndef CONFIG_SOC_ENABLE_APPCPU
|
||||
#include "esp_clk_internal.h"
|
||||
#endif /* CONFIG_SOC_ENABLE_APPCPU */
|
||||
|
||||
#ifdef CONFIG_MCUBOOT
|
||||
#include "bootloader_init.h"
|
||||
#endif /* CONFIG_MCUBOOT */
|
||||
#include <zephyr/sys/printk.h>
|
||||
|
||||
extern void z_cstart(void);
|
||||
extern void esp_reset_reason_init(void);
|
||||
|
||||
#ifdef CONFIG_SOC_ENABLE_APPCPU
|
||||
extern const unsigned char esp32_appcpu_fw_array[];
|
||||
|
||||
void IRAM_ATTR esp_start_appcpu(void)
|
||||
{
|
||||
esp_image_header_t *header = (esp_image_header_t *)&esp32_appcpu_fw_array[0];
|
||||
esp_image_segment_header_t *segment =
|
||||
(esp_image_segment_header_t *)&esp32_appcpu_fw_array[sizeof(esp_image_header_t)];
|
||||
uint8_t *segment_payload;
|
||||
uint32_t entry_addr = header->entry_addr;
|
||||
uint32_t idx = sizeof(esp_image_header_t) + sizeof(esp_image_segment_header_t);
|
||||
|
||||
for (int i = 0; i < header->segment_count; i++) {
|
||||
segment_payload = (uint8_t *)&esp32_appcpu_fw_array[idx];
|
||||
|
||||
if (segment->load_addr >= SOC_IRAM_LOW && segment->load_addr < SOC_IRAM_HIGH) {
|
||||
/* IRAM segment only accepts 4 byte access, avoid memcpy usage here */
|
||||
volatile uint32_t *src = (volatile uint32_t *)segment_payload;
|
||||
volatile uint32_t *dst = (volatile uint32_t *)segment->load_addr;
|
||||
|
||||
for (int j = 0; j < segment->data_len / 4; j++) {
|
||||
dst[j] = src[j];
|
||||
}
|
||||
} else if (segment->load_addr >= SOC_DRAM_LOW &&
|
||||
segment->load_addr < SOC_DRAM_HIGH) {
|
||||
|
||||
memcpy((void *)segment->load_addr, (const void *)segment_payload,
|
||||
segment->data_len);
|
||||
}
|
||||
|
||||
idx += segment->data_len;
|
||||
segment = (esp_image_segment_header_t *)&esp32_appcpu_fw_array[idx];
|
||||
idx += sizeof(esp_image_segment_header_t);
|
||||
}
|
||||
|
||||
esp_appcpu_start((void *)entry_addr);
|
||||
}
|
||||
#endif /* CONFIG_SOC_ENABLE_APPCPU */
|
||||
|
||||
/*
|
||||
* This is written in C rather than assembly since, during the port bring up,
|
||||
* Zephyr is being booted by the Espressif bootloader. With it, the C stack
|
||||
* is already set up.
|
||||
*/
|
||||
void __attribute__((section(".iram1"))) __esp_platform_start(void)
|
||||
{
|
||||
extern uint32_t _init_start;
|
||||
|
||||
/* Move the exception vector table to IRAM. */
|
||||
__asm__ __volatile__ (
|
||||
"wsr %0, vecbase"
|
||||
:
|
||||
: "r"(&_init_start));
|
||||
|
||||
z_bss_zero();
|
||||
|
||||
__asm__ __volatile__ (
|
||||
""
|
||||
:
|
||||
: "g"(&__bss_start)
|
||||
: "memory");
|
||||
|
||||
/* Disable normal interrupts. */
|
||||
__asm__ __volatile__ (
|
||||
"wsr %0, PS"
|
||||
:
|
||||
: "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE));
|
||||
|
||||
/* Initialize the architecture CPU pointer. Some of the
|
||||
* initialization code wants a valid _current before
|
||||
* arch_kernel_init() is invoked.
|
||||
*/
|
||||
__asm__ volatile("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0]));
|
||||
|
||||
esp_reset_reason_init();
|
||||
|
||||
#ifdef CONFIG_MCUBOOT
|
||||
/* MCUboot early initialisation. */
|
||||
if (bootloader_init()) {
|
||||
abort();
|
||||
}
|
||||
#else
|
||||
/* ESP-IDF/MCUboot 2nd stage bootloader enables RTC WDT to check
|
||||
* on startup sequence related issues in application. Hence disable that
|
||||
* as we are about to start Zephyr environment.
|
||||
*/
|
||||
wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
|
||||
|
||||
wdt_hal_write_protect_disable(&rtc_wdt_ctx);
|
||||
wdt_hal_disable(&rtc_wdt_ctx);
|
||||
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
|
||||
|
||||
#ifdef CONFIG_SOC_ESP32_APPCPU
|
||||
/* Configures the CPU clock, RTC slow and fast clocks, and performs
|
||||
* RTC slow clock calibration.
|
||||
*/
|
||||
esp_clk_init();
|
||||
#endif
|
||||
|
||||
esp_timer_early_init();
|
||||
|
||||
#if CONFIG_SOC_ENABLE_APPCPU
|
||||
/* start the ESP32 APP CPU */
|
||||
esp_start_appcpu();
|
||||
#endif
|
||||
|
||||
#if CONFIG_ESP_SPIRAM
|
||||
esp_err_t err = esp_spiram_init();
|
||||
|
||||
if (err != ESP_OK) {
|
||||
printk("Failed to Initialize SPIRAM, aborting.\n");
|
||||
abort();
|
||||
}
|
||||
esp_spiram_init_cache();
|
||||
if (esp_spiram_get_size() < CONFIG_ESP_SPIRAM_SIZE) {
|
||||
printk("SPIRAM size is less than configured size, aborting.\n");
|
||||
abort();
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Scheduler is not started at this point. Hence, guard functions
|
||||
* must be initialized after esp_spiram_init_cache which internally
|
||||
* uses guard functions. Setting guard functions before SPIRAM
|
||||
* cache initialization will result in a crash.
|
||||
*/
|
||||
#if CONFIG_SOC_FLASH_ESP32 || CONFIG_ESP_SPIRAM
|
||||
spi_flash_guard_set(&g_flash_guard_default_ops);
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_MCUBOOT */
|
||||
|
||||
esp_intr_initialize();
|
||||
|
||||
/* Start Zephyr */
|
||||
z_cstart();
|
||||
|
||||
CODE_UNREACHABLE;
|
||||
}
|
||||
|
||||
/* Boot-time static default printk handler, possibly to be overridden later. */
|
||||
int IRAM_ATTR arch_printk_char_out(int c)
|
||||
{
|
||||
if (c == '\n') {
|
||||
esp_rom_uart_tx_one_char('\r');
|
||||
}
|
||||
esp_rom_uart_tx_one_char(c);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void sys_arch_reboot(int type)
|
||||
{
|
||||
esp_restart_noos();
|
||||
}
|
||||
|
||||
void IRAM_ATTR esp_restart_noos(void)
|
||||
{
|
||||
/* Disable interrupts */
|
||||
z_xt_ints_off(0xFFFFFFFF);
|
||||
|
||||
const uint32_t core_id = cpu_hal_get_core_id();
|
||||
const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
|
||||
|
||||
soc_ll_reset_core(other_core_id);
|
||||
soc_ll_stall_core(other_core_id);
|
||||
|
||||
/* Flush any data left in UART FIFOs */
|
||||
esp_rom_uart_tx_wait_idle(0);
|
||||
esp_rom_uart_tx_wait_idle(1);
|
||||
esp_rom_uart_tx_wait_idle(2);
|
||||
|
||||
/* Disable cache */
|
||||
Cache_Read_Disable(0);
|
||||
Cache_Read_Disable(1);
|
||||
|
||||
/* 2nd stage bootloader reconfigures SPI flash signals. */
|
||||
/* Reset them to the defaults expected by ROM */
|
||||
WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
|
||||
|
||||
/* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */
|
||||
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,
|
||||
DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST |
|
||||
DPORT_BT_RST | DPORT_BTMAC_RST |
|
||||
DPORT_SDIO_RST | DPORT_SDIO_HOST_RST |
|
||||
DPORT_EMAC_RST | DPORT_MACPWR_RST |
|
||||
DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST);
|
||||
DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0);
|
||||
|
||||
/* Reset timer/spi/uart */
|
||||
DPORT_SET_PERI_REG_MASK(
|
||||
DPORT_PERIP_RST_EN_REG,
|
||||
/* UART TX FIFO cannot be reset correctly on ESP32, */
|
||||
/* so reset the UART memory by DPORT here. */
|
||||
DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST |
|
||||
DPORT_UART1_RST | DPORT_UART2_RST | DPORT_UART_MEM_RST);
|
||||
DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
|
||||
|
||||
/* Clear entry point for APP CPU */
|
||||
DPORT_REG_WRITE(DPORT_APPCPU_CTRL_D_REG, 0);
|
||||
|
||||
/* Reset CPUs */
|
||||
if (core_id == 0) {
|
||||
/* Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. */
|
||||
soc_ll_reset_core(1);
|
||||
soc_ll_reset_core(0);
|
||||
} else {
|
||||
/* Running on APP CPU: need to reset PRO CPU and unstall it, */
|
||||
/* then reset APP CPU */
|
||||
soc_ll_reset_core(0);
|
||||
soc_ll_stall_core(0);
|
||||
soc_ll_reset_core(1);
|
||||
}
|
||||
|
||||
while (true) {
|
||||
;
|
||||
}
|
||||
}
|
||||
71
soc/espressif/esp32/soc.h
Normal file
71
soc/espressif/esp32/soc.h
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Intel Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __SOC_H__
|
||||
#define __SOC_H__
|
||||
#include <soc/dport_reg.h>
|
||||
#include <soc/rtc_cntl_reg.h>
|
||||
#include <soc/soc_caps.h>
|
||||
#include <esp32/rom/ets_sys.h>
|
||||
#include <esp32/rom/spi_flash.h>
|
||||
#include <esp_rom_sys.h>
|
||||
|
||||
#include <zephyr/types.h>
|
||||
#include <stdbool.h>
|
||||
#include <zephyr/arch/xtensa/arch.h>
|
||||
|
||||
#include <xtensa/core-macros.h>
|
||||
#include <esp32/clk.h>
|
||||
|
||||
void __esp_platform_start(void);
|
||||
|
||||
static inline void esp32_set_mask32(uint32_t v, uint32_t mem_addr)
|
||||
{
|
||||
sys_write32(sys_read32(mem_addr) | v, mem_addr);
|
||||
}
|
||||
|
||||
static inline void esp32_clear_mask32(uint32_t v, uint32_t mem_addr)
|
||||
{
|
||||
sys_write32(sys_read32(mem_addr) & ~v, mem_addr);
|
||||
}
|
||||
|
||||
static inline uint32_t esp_core_id(void)
|
||||
{
|
||||
uint32_t id;
|
||||
|
||||
__asm__ volatile (
|
||||
"rsr.prid %0\n"
|
||||
"extui %0,%0,13,1" : "=r" (id));
|
||||
return id;
|
||||
}
|
||||
|
||||
extern void esp_rom_intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
|
||||
|
||||
extern int esp_rom_gpio_matrix_in(uint32_t gpio, uint32_t signal_index,
|
||||
bool inverted);
|
||||
extern int esp_rom_gpio_matrix_out(uint32_t gpio, uint32_t signal_index,
|
||||
bool out_inverted,
|
||||
bool out_enabled_inverted);
|
||||
|
||||
extern void esp_rom_uart_attach(void);
|
||||
extern void esp_rom_uart_tx_wait_idle(uint8_t uart_no);
|
||||
extern int esp_rom_uart_tx_one_char(uint8_t chr);
|
||||
extern int esp_rom_uart_rx_one_char(uint8_t *chr);
|
||||
|
||||
extern void esp_rom_Cache_Flush(int cpu);
|
||||
extern void esp_rom_Cache_Read_Enable(int cpu);
|
||||
extern void esp_rom_ets_set_appcpu_boot_addr(void *addr);
|
||||
void esp_appcpu_start(void *entry_point);
|
||||
|
||||
/* ROM functions which read/write internal i2c control bus for PLL, APLL */
|
||||
extern uint8_t esp_rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add);
|
||||
extern void esp_rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
|
||||
|
||||
/* ROM information related to SPI Flash chip timing and device */
|
||||
extern esp_rom_spiflash_chip_t g_rom_flashchip;
|
||||
extern uint8_t g_rom_spiflash_dummy_len_plus[];
|
||||
|
||||
#endif /* __SOC_H__ */
|
||||
158
soc/espressif/esp32/soc_appcpu.c
Normal file
158
soc/espressif/esp32/soc_appcpu.c
Normal file
|
|
@ -0,0 +1,158 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* Include esp-idf headers first to avoid redefining BIT() macro */
|
||||
#include <soc.h>
|
||||
#include <soc/rtc_cntl_reg.h>
|
||||
#include <soc/timer_group_reg.h>
|
||||
#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
|
||||
#include <xtensa/config/core-isa.h>
|
||||
#include <xtensa/corebits.h>
|
||||
|
||||
#include <zephyr/kernel_structs.h>
|
||||
#include <string.h>
|
||||
#include <zephyr/toolchain.h>
|
||||
#include <zephyr/types.h>
|
||||
#include <zephyr/linker/linker-defs.h>
|
||||
#include <kernel_internal.h>
|
||||
|
||||
#include <esp_private/system_internal.h>
|
||||
#include <esp32/rom/cache.h>
|
||||
#include <hal/soc_ll.h>
|
||||
#include <soc/cpu.h>
|
||||
#include <soc/gpio_periph.h>
|
||||
#include <esp_spi_flash.h>
|
||||
#include <esp_err.h>
|
||||
#include <esp32/spiram.h>
|
||||
#include <esp_app_format.h>
|
||||
#include <zephyr/sys/printk.h>
|
||||
|
||||
extern void z_cstart(void);
|
||||
|
||||
/*
|
||||
* This is written in C rather than assembly since, during the port bring up,
|
||||
* Zephyr is being booted by the Espressif bootloader. With it, the C stack
|
||||
* is already set up.
|
||||
*/
|
||||
void __app_cpu_start(void)
|
||||
{
|
||||
extern uint32_t _init_start;
|
||||
extern uint32_t _bss_start;
|
||||
extern uint32_t _bss_end;
|
||||
|
||||
/* Move the exception vector table to IRAM. */
|
||||
__asm__ __volatile__ (
|
||||
"wsr %0, vecbase"
|
||||
:
|
||||
: "r"(&_init_start));
|
||||
|
||||
/* Zero out BSS. Clobber _bss_start to avoid memset() elision. */
|
||||
z_bss_zero();
|
||||
|
||||
__asm__ __volatile__ (
|
||||
""
|
||||
:
|
||||
: "g"(&__bss_start)
|
||||
: "memory");
|
||||
|
||||
/* Disable normal interrupts. */
|
||||
__asm__ __volatile__ (
|
||||
"wsr %0, PS"
|
||||
:
|
||||
: "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE));
|
||||
|
||||
/* Initialize the architecture CPU pointer. Some of the
|
||||
* initialization code wants a valid _current before
|
||||
* arch_kernel_init() is invoked.
|
||||
*/
|
||||
__asm__ volatile("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0]));
|
||||
|
||||
esp_intr_initialize();
|
||||
/* Start Zephyr */
|
||||
z_cstart();
|
||||
|
||||
CODE_UNREACHABLE;
|
||||
}
|
||||
|
||||
/* Boot-time static default printk handler, possibly to be overridden later. */
|
||||
int IRAM_ATTR arch_printk_char_out(int c)
|
||||
{
|
||||
ARG_UNUSED(c);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void sys_arch_reboot(int type)
|
||||
{
|
||||
esp_restart_noos();
|
||||
}
|
||||
|
||||
void IRAM_ATTR esp_restart_noos(void)
|
||||
{
|
||||
/* Disable interrupts */
|
||||
z_xt_ints_off(0xFFFFFFFF);
|
||||
|
||||
const uint32_t core_id = cpu_hal_get_core_id();
|
||||
const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
|
||||
|
||||
soc_ll_reset_core(other_core_id);
|
||||
soc_ll_stall_core(other_core_id);
|
||||
|
||||
/* Flush any data left in UART FIFOs */
|
||||
esp_rom_uart_tx_wait_idle(0);
|
||||
esp_rom_uart_tx_wait_idle(1);
|
||||
esp_rom_uart_tx_wait_idle(2);
|
||||
|
||||
/* Disable cache */
|
||||
Cache_Read_Disable(0);
|
||||
Cache_Read_Disable(1);
|
||||
|
||||
/* 2nd stage bootloader reconfigures SPI flash signals. */
|
||||
/* Reset them to the defaults expected by ROM */
|
||||
WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
|
||||
|
||||
/* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */
|
||||
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,
|
||||
DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST |
|
||||
DPORT_BT_RST | DPORT_BTMAC_RST |
|
||||
DPORT_SDIO_RST | DPORT_SDIO_HOST_RST |
|
||||
DPORT_EMAC_RST | DPORT_MACPWR_RST |
|
||||
DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST);
|
||||
DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0);
|
||||
|
||||
/* Reset timer/spi/uart */
|
||||
DPORT_SET_PERI_REG_MASK(
|
||||
DPORT_PERIP_RST_EN_REG,
|
||||
/* UART TX FIFO cannot be reset correctly on ESP32, */
|
||||
/* so reset the UART memory by DPORT here. */
|
||||
DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST |
|
||||
DPORT_UART1_RST | DPORT_UART2_RST | DPORT_UART_MEM_RST);
|
||||
DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
|
||||
|
||||
/* Clear entry point for APP CPU */
|
||||
DPORT_REG_WRITE(DPORT_APPCPU_CTRL_D_REG, 0);
|
||||
|
||||
/* Reset CPUs */
|
||||
if (core_id == 0) {
|
||||
/* Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. */
|
||||
soc_ll_reset_core(1);
|
||||
soc_ll_reset_core(0);
|
||||
} else {
|
||||
/* Running on APP CPU: need to reset PRO CPU and unstall it, */
|
||||
/* then reset APP CPU */
|
||||
soc_ll_reset_core(0);
|
||||
soc_ll_stall_core(0);
|
||||
soc_ll_reset_core(1);
|
||||
}
|
||||
|
||||
while (true) {
|
||||
;
|
||||
}
|
||||
}
|
||||
103
soc/espressif/esp32c3/CMakeLists.txt
Normal file
103
soc/espressif/esp32c3/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_sources(
|
||||
vectors.S
|
||||
soc_irq.S
|
||||
soc_irq.c
|
||||
soc.c
|
||||
loader.c
|
||||
)
|
||||
|
||||
zephyr_include_directories(.)
|
||||
|
||||
zephyr_library_sources_ifdef(CONFIG_PM power.c)
|
||||
zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c)
|
||||
|
||||
# get code-partition slot0 address
|
||||
dt_nodelabel(dts_partition_path NODELABEL "slot0_partition")
|
||||
dt_reg_addr(img_0_off PATH ${dts_partition_path})
|
||||
|
||||
# get code-partition boot address
|
||||
dt_nodelabel(dts_partition_path NODELABEL "boot_partition")
|
||||
dt_reg_addr(boot_off PATH ${dts_partition_path})
|
||||
|
||||
# get flash size to use in esptool as string
|
||||
math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000")
|
||||
|
||||
if(CONFIG_BOOTLOADER_ESP_IDF)
|
||||
include(ExternalProject)
|
||||
|
||||
## we use hello-world project, but I think any can be used.
|
||||
set(espidf_components_dir ${ESP_IDF_PATH}/components)
|
||||
set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf)
|
||||
set(espidf_build_dir ${espidf_prefix}/build)
|
||||
|
||||
ExternalProject_Add(
|
||||
EspIdfBootloader
|
||||
PREFIX ${espidf_prefix}
|
||||
SOURCE_DIR ${espidf_components_dir}/bootloader/subproject
|
||||
BINARY_DIR ${espidf_build_dir}/bootloader
|
||||
CONFIGURE_COMMAND
|
||||
${CMAKE_COMMAND} -G${CMAKE_GENERATOR}
|
||||
-S ${espidf_components_dir}/bootloader/subproject
|
||||
-B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig
|
||||
-DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES}
|
||||
-DPYTHON_DEPS_CHECKED=1
|
||||
-DCMAKE_C_COMPILER=${CMAKE_C_COMPILER}
|
||||
-DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER}
|
||||
-DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER}
|
||||
-DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME}
|
||||
-DPYTHON=${PYTHON_EXECUTABLE}
|
||||
BUILD_COMMAND
|
||||
${CMAKE_COMMAND} --build .
|
||||
INSTALL_COMMAND "" # This particular build system has no install command
|
||||
)
|
||||
|
||||
ExternalProject_Add(
|
||||
EspPartitionTable
|
||||
SOURCE_DIR ${espidf_components_dir}/partition_table
|
||||
BINARY_DIR ${espidf_build_dir}
|
||||
CONFIGURE_COMMAND ""
|
||||
BUILD_COMMAND
|
||||
${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q
|
||||
--offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin
|
||||
INSTALL_COMMAND ""
|
||||
)
|
||||
|
||||
set_property(TARGET bintools PROPERTY disassembly_flag_inline_source)
|
||||
|
||||
add_dependencies(app EspIdfBootloader EspPartitionTable)
|
||||
|
||||
board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin")
|
||||
|
||||
board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin")
|
||||
|
||||
board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000")
|
||||
|
||||
endif()
|
||||
|
||||
if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF)
|
||||
|
||||
if(CONFIG_BUILD_OUTPUT_BIN)
|
||||
set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
|
||||
COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py
|
||||
ARGS --chip esp32c3 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB
|
||||
-o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin
|
||||
${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf)
|
||||
endif()
|
||||
|
||||
if(CONFIG_MCUBOOT)
|
||||
board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin")
|
||||
endif()
|
||||
|
||||
endif()
|
||||
|
||||
board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}")
|
||||
|
||||
board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}")
|
||||
|
||||
if(CONFIG_MCUBOOT)
|
||||
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "")
|
||||
else()
|
||||
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "")
|
||||
endif()
|
||||
97
soc/espressif/esp32c3/Kconfig
Normal file
97
soc/espressif/esp32c3/Kconfig
Normal file
|
|
@ -0,0 +1,97 @@
|
|||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_ESP32C3
|
||||
select RISCV
|
||||
select RISCV_GP
|
||||
select DYNAMIC_INTERRUPTS
|
||||
select CLOCK_CONTROL
|
||||
select PINCTRL
|
||||
select RISCV_ISA_RV32I
|
||||
select RISCV_ISA_EXT_M
|
||||
select RISCV_ISA_EXT_C
|
||||
select RISCV_ISA_EXT_ZICSR
|
||||
select HAS_ESPRESSIF_HAL
|
||||
select XIP if !MCUBOOT
|
||||
select HAS_PM
|
||||
select HAS_POWEROFF
|
||||
|
||||
if SOC_SERIES_ESP32C3
|
||||
|
||||
config IDF_TARGET_ESP32C3
|
||||
bool "ESP32C3 as target board"
|
||||
default y
|
||||
|
||||
config ESP_SYSTEM_RTC_EXT_XTAL
|
||||
bool
|
||||
|
||||
config ESP_SYSTEM_RTC_EXT_OSC
|
||||
bool
|
||||
|
||||
choice ESP32C3_RTC_CLK_SRC
|
||||
prompt "RTC clock source"
|
||||
default ESP32C3_RTC_CLK_SRC_INT_RC
|
||||
help
|
||||
Choose which clock is used as RTC clock source.
|
||||
|
||||
config ESP32C3_RTC_CLK_SRC_INT_RC
|
||||
bool "Internal 150kHz RC oscillator"
|
||||
|
||||
config ESP32C3_RTC_CLK_SRC_EXT_CRYS
|
||||
bool "External 32kHz crystal"
|
||||
select ESP_SYSTEM_RTC_EXT_XTAL
|
||||
|
||||
config ESP32C3_RTC_CLK_SRC_EXT_OSC
|
||||
bool "External 32kHz oscillator at 32K_XP pin"
|
||||
select ESP_SYSTEM_RTC_EXT_OSC
|
||||
|
||||
config ESP32C3_RTC_CLK_SRC_INT_8MD256
|
||||
bool "Internal 8MHz oscillator, divided by 256 (~32kHz)"
|
||||
|
||||
endchoice # ESP32C3_RTC_CLK_SRC
|
||||
|
||||
config ESP32C3_RTC_CLK_CAL_CYCLES
|
||||
int "Number of cycles for RTC_SLOW_CLK calibration"
|
||||
default 3000 if ESP32C3_RTC_CLK_SRC_EXT_CRYS || ESP32C3_RTC_CLK_SRC_EXT_OSC || ESP32C3_RTC_CLK_SRC_INT_8MD256
|
||||
default 1024 if ESP32C3_RTC_CLK_SRC_INT_RC
|
||||
range 0 27000 if ESP32C3_RTC_CLK_SRC_EXT_CRYS || ESP32C3_RTC_CLK_SRC_EXT_OSC || ESP32C3_RTC_CLK_SRC_INT_8MD256
|
||||
range 0 32766 if ESP32C3_RTC_CLK_SRC_INT_RC
|
||||
help
|
||||
When the startup code initializes RTC_SLOW_CLK, it can perform
|
||||
calibration by comparing the RTC_SLOW_CLK frequency with main XTAL
|
||||
frequency. This option sets the number of RTC_SLOW_CLK cycles measured
|
||||
by the calibration routine. Higher numbers increase calibration
|
||||
precision, which may be important for applications which spend a lot of
|
||||
time in deep sleep. Lower numbers reduce startup time.
|
||||
|
||||
When this option is set to 0, clock calibration will not be performed at
|
||||
startup, and approximate clock frequencies will be assumed:
|
||||
|
||||
- 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024.
|
||||
- 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
|
||||
In case more value will help improve the definition of the launch of the crystal.
|
||||
If the crystal could not start, it will be switched to internal RC.
|
||||
|
||||
config ESP32_PHY_MAX_WIFI_TX_POWER
|
||||
int "Max WiFi TX power (dBm)"
|
||||
range 10 20
|
||||
default 20
|
||||
help
|
||||
Set maximum transmit power for WiFi radio. Actual transmit power for high
|
||||
data rates may be lower than this setting.
|
||||
|
||||
config ESP32_PHY_MAX_TX_POWER
|
||||
int
|
||||
default ESP32_PHY_MAX_WIFI_TX_POWER
|
||||
|
||||
config MAC_BB_PD
|
||||
bool "Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled"
|
||||
depends on SOC_SERIES_ESP32C3 && TICKLESS_KERNEL
|
||||
default n
|
||||
help
|
||||
If enabled, the MAC and baseband of Wi-Fi and Bluetooth will be powered
|
||||
down when PHY is disabled. Enabling this setting reduces power consumption
|
||||
by a small amount but increases RAM use by approximately 4 KB(Wi-Fi only),
|
||||
2 KB(Bluetooth only) or 5.3 KB(Wi-Fi + Bluetooth).
|
||||
|
||||
endif # SOC_SERIES_ESP32C3
|
||||
18
soc/espressif/esp32c3/Kconfig.defconfig
Normal file
18
soc/espressif/esp32c3/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_ESP32C3
|
||||
|
||||
config NUM_IRQS
|
||||
default 62
|
||||
|
||||
config ESPTOOLPY_FLASHFREQ_80M
|
||||
default y
|
||||
|
||||
config FLASH_SIZE
|
||||
default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0)
|
||||
|
||||
config FLASH_BASE_ADDRESS
|
||||
default $(dt_node_reg_addr_hex,/soc/flash-controller@60002000/flash@0)
|
||||
|
||||
endif # SOC_SERIES_ESP32C3
|
||||
51
soc/espressif/esp32c3/Kconfig.soc
Normal file
51
soc/espressif/esp32c3/Kconfig.soc
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_ESP32C3
|
||||
bool
|
||||
select SOC_FAMILY_ESPRESSIF_ESP32
|
||||
help
|
||||
ESP32C3
|
||||
|
||||
config SOC_ESP32C3_FX4
|
||||
bool
|
||||
select SOC_ESP32C3
|
||||
help
|
||||
ESP32C3_FX4
|
||||
|
||||
config SOC_ESP32C3_MINI_N4
|
||||
bool
|
||||
select SOC_ESP32C3
|
||||
help
|
||||
ESP32C3_MINI_N4
|
||||
|
||||
config SOC_ESP32C3_WROOM_02_N4
|
||||
bool
|
||||
select SOC_ESP32C3
|
||||
help
|
||||
ESP32C3_WROOM_02_N4
|
||||
|
||||
config SOC_ESP32C3_WROOM_02_N8
|
||||
bool
|
||||
select SOC_ESP32C3
|
||||
help
|
||||
ESP32C3_WROOM_02_N8
|
||||
|
||||
config SOC_ESP32C3
|
||||
bool
|
||||
select SOC_SERIES_ESP32C3
|
||||
help
|
||||
ESP32C3
|
||||
|
||||
config SOC_SERIES
|
||||
default "esp32c3" if SOC_SERIES_ESP32C3
|
||||
|
||||
config SOC
|
||||
default "esp32c3" if SOC_SERIES_ESP32C3
|
||||
|
||||
config SOC_PART_NUMBER
|
||||
default "ESP32C3_FX4" if SOC_ESP32C3_FX4
|
||||
default "ESP32C3_MINI_N4" if SOC_ESP32C3_MINI_N4
|
||||
default "ESP32C3_WROOM_02_N4" if SOC_ESP32C3_WROOM_02_N4
|
||||
default "ESP32C3_WROOM_02_N8" if SOC_ESP32C3_WROOM_02_N8
|
||||
default "ESP32C3" if SOC_ESP32C3
|
||||
505
soc/espressif/esp32c3/default.ld
Normal file
505
soc/espressif/esp32c3/default.ld
Normal file
|
|
@ -0,0 +1,505 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Linker command/script file
|
||||
*
|
||||
* Linker script for the esp32c3 platform.
|
||||
*/
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/linker/sections.h>
|
||||
#include <zephyr/linker/linker-defs.h>
|
||||
#include <zephyr/linker/linker-tool.h>
|
||||
|
||||
#define RAMABLE_REGION dram0_0_seg
|
||||
#define RODATA_REGION drom0_0_seg
|
||||
#define IRAM_REGION iram0_0_seg
|
||||
#define FLASH_CODE_REGION irom0_0_seg
|
||||
|
||||
#define ROMABLE_REGION ROM
|
||||
|
||||
#define SRAM_IRAM_START 0x4037C000
|
||||
#define SRAM_DRAM_START 0x3FC7C000
|
||||
#define ICACHE_SIZE 0x4000 /* ICache size is fixed to 16KB on ESP32-C3 */
|
||||
#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START)
|
||||
/* SRAM_DRAM_END is equivalent 2nd stage bootloader iram_loader_seg
|
||||
start address (that should not be overlapped) */
|
||||
#define SRAM_DRAM_END 0x403D0000 - I_D_SRAM_OFFSET
|
||||
#define SRAM_IRAM_ORG (SRAM_IRAM_START + ICACHE_SIZE)
|
||||
#define SRAM_DRAM_ORG (SRAM_DRAM_START + ICACHE_SIZE)
|
||||
#define I_D_SRAM_SIZE SRAM_DRAM_END - SRAM_DRAM_ORG
|
||||
|
||||
#ifdef CONFIG_FLASH_SIZE
|
||||
#define FLASH_SIZE CONFIG_FLASH_SIZE
|
||||
#else
|
||||
#define FLASH_SIZE 0x400000
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BOOTLOADER_ESP_IDF
|
||||
#define IROM_SEG_ORG 0x42000020
|
||||
#define IROM_SEG_LEN (FLASH_SIZE-0x20)
|
||||
#define IROM_SEG_ALIGN 0x4
|
||||
#else
|
||||
#define IROM_SEG_ORG 0x42000000
|
||||
#define IROM_SEG_LEN FLASH_SIZE
|
||||
#define IROM_SEG_ALIGN 0x10000
|
||||
#endif
|
||||
|
||||
/* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA.
|
||||
* Executing directly from LMA is not possible. */
|
||||
#undef GROUP_ROM_LINK_IN
|
||||
#define GROUP_ROM_LINK_IN(vregion, lregion) > RODATA_REGION AT > lregion
|
||||
|
||||
/* Global symbols required for espressif hal build */
|
||||
MEMORY
|
||||
{
|
||||
mcuboot_hdr (RX): org = 0x0, len = 0x20
|
||||
metadata (RX): org = 0x20, len = 0x20
|
||||
ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40
|
||||
|
||||
iram0_0_seg(RX): org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE
|
||||
irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN
|
||||
|
||||
drom0_0_seg (R) : org = 0x3C000040, len = FLASH_SIZE - 0x40
|
||||
dram0_0_seg(RW): org = SRAM_DRAM_ORG, len = I_D_SRAM_SIZE
|
||||
|
||||
rtc_iram_seg(RWX): org = 0x50000000, len = 0x2000
|
||||
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/* The line below defines location alias for .rtc.data section
|
||||
* As C3 only has RTC fast memory, this is not configurable like
|
||||
* on other targets.
|
||||
*/
|
||||
REGION_ALIAS("rtc_slow_seg", rtc_iram_seg);
|
||||
|
||||
/* Default entry point: */
|
||||
ENTRY(CONFIG_KERNEL_ENTRY)
|
||||
|
||||
_rom_store_table = 0;
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Reserve space for MCUboot header in the binary */
|
||||
.mcuboot_header :
|
||||
{
|
||||
QUAD(0x0)
|
||||
QUAD(0x0)
|
||||
QUAD(0x0)
|
||||
QUAD(0x0)
|
||||
} > mcuboot_hdr
|
||||
.metadata :
|
||||
{
|
||||
/* Magic byte for load header */
|
||||
LONG(0xace637d3)
|
||||
|
||||
/* Application entry point address */
|
||||
KEEP(*(.entry_addr))
|
||||
|
||||
/* IRAM metadata:
|
||||
* - Destination address (VMA) for IRAM region
|
||||
* - Flash offset (LMA) for start of IRAM region
|
||||
* - Size of IRAM region
|
||||
*/
|
||||
LONG(ADDR(.iram0.text))
|
||||
LONG(LOADADDR(.iram0.text))
|
||||
LONG(SIZEOF(.iram0.text))
|
||||
|
||||
/* DRAM metadata:
|
||||
* - Destination address (VMA) for DRAM region
|
||||
* - Flash offset (LMA) for start of DRAM region
|
||||
* - Size of DRAM region
|
||||
*/
|
||||
LONG(ADDR(.dram0.data))
|
||||
LONG(LOADADDR(.dram0.data))
|
||||
LONG(LOADADDR(.dummy.dram.data) + SIZEOF(.dummy.dram.data) - LOADADDR(.dram0.data))
|
||||
} > metadata
|
||||
|
||||
#include <zephyr/linker/rel-sections.ld>
|
||||
_image_drom_start = LOADADDR(_RODATA_SECTION_NAME);
|
||||
_image_drom_size = LOADADDR(_RODATA_SECTION_END) + SIZEOF(_RODATA_SECTION_END) - _image_drom_start;
|
||||
_image_drom_vaddr = ADDR(_RODATA_SECTION_NAME);
|
||||
|
||||
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
|
||||
{
|
||||
_rodata_reserved_start = ABSOLUTE(.);
|
||||
_rodata_start = ABSOLUTE(.);
|
||||
|
||||
*(.rodata_desc .rodata_desc.*)
|
||||
*(.rodata_custom_desc .rodata_custom_desc.*)
|
||||
|
||||
__rodata_region_start = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
#include <snippets-rodata.ld>
|
||||
|
||||
. = ALIGN(4);
|
||||
*(EXCLUDE_FILE (*libarch__riscv__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata)
|
||||
*(EXCLUDE_FILE (*libarch__riscv__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata.*)
|
||||
|
||||
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
|
||||
*(.xt_except_table)
|
||||
*(.gcc_except_table .gcc_except_table.*)
|
||||
*(.gnu.linkonce.e.*)
|
||||
*(.gnu.version_r)
|
||||
. = (. + 3) & ~ 3;
|
||||
__eh_frame = ABSOLUTE(.);
|
||||
KEEP(*(.eh_frame))
|
||||
. = (. + 7) & ~ 3;
|
||||
|
||||
/* C++ exception handlers table: */
|
||||
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
|
||||
*(.xt_except_desc)
|
||||
*(.gnu.linkonce.h.*)
|
||||
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc_end)
|
||||
*(.dynamic)
|
||||
*(.gnu.version_d)
|
||||
__rodata_region_end = .;
|
||||
_rodata_end = ABSOLUTE(.);
|
||||
/* Literals are also RO data. */
|
||||
_lit4_start = ABSOLUTE(.);
|
||||
*(*.lit4)
|
||||
*(.lit4.*)
|
||||
*(.gnu.linkonce.lit4.*)
|
||||
_lit4_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
*(.srodata)
|
||||
*(.srodata.*)
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.rodata_wlog)
|
||||
*(.rodata_wlog*)
|
||||
. = ALIGN(4);
|
||||
} GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)
|
||||
|
||||
#include <zephyr/linker/common-rom/common-rom-cpp.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-kernel-devices.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-ztest.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-net.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-bt.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-debug.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-misc.ld>
|
||||
#include <zephyr/linker/thread-local-storage.ld>
|
||||
#include <snippets-sections.ld>
|
||||
|
||||
/* Create an explicit section at the end of all the data that shall be mapped into drom.
|
||||
* This is used to calculate the size of the _image_drom_size variable */
|
||||
SECTION_PROLOGUE(_RODATA_SECTION_END,,)
|
||||
{
|
||||
_rodata_reserved_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
_image_rodata_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)
|
||||
|
||||
.iram0.text : ALIGN(4)
|
||||
{
|
||||
/* Vectors go to IRAM */
|
||||
_iram_start = ABSOLUTE(.);
|
||||
_init_start = ABSOLUTE(.);
|
||||
|
||||
KEEP(*(.exception_vectors.text));
|
||||
. = ALIGN(256);
|
||||
|
||||
_invalid_pc_placeholder = ABSOLUTE(.);
|
||||
|
||||
_iram_text_start = ABSOLUTE(.);
|
||||
|
||||
KEEP(*(.exception.entry*)); /* contains _isr_wrapper */
|
||||
*(.exception.other*)
|
||||
. = ALIGN(4);
|
||||
|
||||
*(.entry.text)
|
||||
*(.init.literal)
|
||||
*(.init)
|
||||
. = ALIGN(4);
|
||||
*(.iram1 .iram1.*)
|
||||
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
|
||||
*libesp32.a:panic.*(.literal .text .literal.* .text.*)
|
||||
*librtc.a:(.literal .text .literal.* .text.*)
|
||||
*libarch__riscv__core.a:(.literal .text .literal.* .text.*)
|
||||
*libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)
|
||||
*libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)
|
||||
*libsubsys__net__ip.a:(.literal .text .literal.* .text.*)
|
||||
*libsubsys__net.a:(.literal .text .literal.* .text.*)
|
||||
*libkernel.a:(.literal .text .literal.* .text.*)
|
||||
*libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)
|
||||
*libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)
|
||||
*libdrivers__timer.a:esp32c3_sys_timer.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:log_core.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)
|
||||
*libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:log_list.*(.literal .text .literal.* .text.*)
|
||||
*libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out)
|
||||
*libzephyr.a:log_output.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:loader.*(.literal .text .literal.* .text.*)
|
||||
*libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)
|
||||
*libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)
|
||||
*liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*)
|
||||
*liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)
|
||||
*libc.a:*(.literal .text .literal.* .text.*)
|
||||
*libphy.a:( .phyiram .phyiram.*)
|
||||
*libgcov.a:(.literal .text .literal.* .text.*)
|
||||
|
||||
#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)
|
||||
*libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*)
|
||||
*libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)
|
||||
*libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
|
||||
*libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
|
||||
#endif
|
||||
. = ALIGN(4);
|
||||
_init_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
|
||||
|
||||
.dram0.dummy (NOLOAD):
|
||||
{
|
||||
/**
|
||||
* This section is required to skip .iram0.text area because iram0_0_seg and
|
||||
* dram0_0_seg reflect the same address space on different buses.
|
||||
*/
|
||||
. = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
|
||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
||||
|
||||
/* Shared RAM */
|
||||
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
__bss_start = ABSOLUTE(.);
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.share.mem)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN (8);
|
||||
__bss_end = ABSOLUTE(.);
|
||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
||||
|
||||
SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.noinit)
|
||||
*(.noinit.*)
|
||||
. = ALIGN(4);
|
||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
||||
|
||||
.dram0.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_data_start = ABSOLUTE(.);
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
*(.data1)
|
||||
#ifdef CONFIG_RISCV_GP
|
||||
__global_pointer$ = . + 0x800;
|
||||
#endif /* CONFIG_RISCV_GP */
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
|
||||
/* All dependent functions should be placed in DRAM to avoid issue
|
||||
* when flash cache is disabled */
|
||||
*libkernel.a:fatal.*(.rodata .rodata.*)
|
||||
*libkernel.a:init.*(.rodata .rodata.*)
|
||||
*libzephyr.a:cbprintf_complete*(.rodata .rodata.*)
|
||||
*libzephyr.a:log_core.*(.rodata .rodata.*)
|
||||
*libzephyr.a:log_backend_uart.*(.rodata .rodata.*)
|
||||
*libzephyr.a:log_output.*(.rodata .rodata.*)
|
||||
*libzephyr.a:loader.*(.rodata .rodata.*)
|
||||
*libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*)
|
||||
*libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)
|
||||
*libzephyr.a:spi_flash_rom_patch.*(.rodata .rodata.*)
|
||||
|
||||
|
||||
KEEP(*(.jcr))
|
||||
*(.dram1 .dram1.*)
|
||||
. = ALIGN(4);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
|
||||
|
||||
#include <zephyr/linker/cplusplus-rom.ld>
|
||||
#include <zephyr/linker/thread-local-storage.ld>
|
||||
#include <snippets-data-sections.ld>
|
||||
#include <zephyr/linker/common-ram.ld>
|
||||
#include <snippets-ram-sections.ld>
|
||||
#include <zephyr/linker/cplusplus-ram.ld>
|
||||
|
||||
/* logging sections should be placed in RAM area to avoid flash cache disabled issues */
|
||||
#pragma push_macro("GROUP_ROM_LINK_IN")
|
||||
#undef GROUP_ROM_LINK_IN
|
||||
#define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN
|
||||
#include <zephyr/linker/common-rom/common-rom-logging.ld>
|
||||
#pragma pop_macro("GROUP_ROM_LINK_IN")
|
||||
|
||||
.dummy.dram.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
#include <snippets-rwdata.ld>
|
||||
_end = ABSOLUTE(.);
|
||||
_data_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
|
||||
|
||||
.iram0.text_end (NOLOAD) :
|
||||
{
|
||||
/* C3 memprot requires 512 B alignment for split lines */
|
||||
. = ALIGN (16);
|
||||
} GROUP_LINK_IN(IRAM_REGION)
|
||||
|
||||
.iram0.data :
|
||||
{
|
||||
. = ALIGN(16);
|
||||
*(.iram.data)
|
||||
*(.iram.data*)
|
||||
} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
|
||||
|
||||
.iram0.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(16);
|
||||
*(.iram.bss)
|
||||
*(.iram.bss*)
|
||||
|
||||
. = ALIGN(16);
|
||||
_iram_end = ABSOLUTE(.);
|
||||
} GROUP_LINK_IN(IRAM_REGION)
|
||||
|
||||
_image_irom_start = LOADADDR(.flash.text);
|
||||
_image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start;
|
||||
_image_irom_vaddr = ADDR(.flash.text);
|
||||
|
||||
.flash_text_dummy (NOLOAD): ALIGN(IROM_SEG_ALIGN)
|
||||
{
|
||||
. = SIZEOF(_RODATA_SECTION_NAME);
|
||||
. = ALIGN(0x10000) + 0x20;
|
||||
} GROUP_LINK_IN(FLASH_CODE_REGION)
|
||||
|
||||
.flash.text : ALIGN(IROM_SEG_ALIGN)
|
||||
{
|
||||
_stext = .;
|
||||
_text_start = ABSOLUTE(.);
|
||||
|
||||
#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)
|
||||
*libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*)
|
||||
*libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*)
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)
|
||||
*libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
|
||||
*libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
|
||||
#endif
|
||||
|
||||
*(.literal .text .literal.* .text.*)
|
||||
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||||
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
|
||||
*(.fini.literal)
|
||||
*(.fini)
|
||||
*(.gnu.version)
|
||||
|
||||
/** CPU will try to prefetch up to 16 bytes of
|
||||
* of instructions. This means that any configuration (e.g. MMU, PMS) must allow
|
||||
* safe access to up to 16 bytes after the last real instruction, add
|
||||
* dummy bytes to ensure this
|
||||
*/
|
||||
. += 16;
|
||||
|
||||
_text_end = ABSOLUTE(.);
|
||||
_etext = .;
|
||||
|
||||
/**
|
||||
* Similar to _iram_start, this symbol goes here so it is
|
||||
* resolved by addr2line in preference to the first symbol in
|
||||
* the flash.text segment.
|
||||
*/
|
||||
_flash_cache_start = ABSOLUTE(0);
|
||||
} GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION)
|
||||
|
||||
.rtc.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rtc.literal .rtc.text)
|
||||
*rtc_wake_stub*.o(.literal .text .literal.* .text.*)
|
||||
} GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION)
|
||||
|
||||
/* This section is required to skip rtc.text area because the text and
|
||||
* data segments reflect the same address space on different buses.
|
||||
*/
|
||||
.rtc.dummy (NOLOAD):
|
||||
{
|
||||
. = SIZEOF(.rtc.text);
|
||||
} GROUP_LINK_IN(rtc_iram_seg)
|
||||
|
||||
.rtc.data :
|
||||
{
|
||||
_rtc_data_start = ABSOLUTE(.);
|
||||
*(.rtc.data)
|
||||
*(.rtc.rodata)
|
||||
*rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)
|
||||
_rtc_data_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION)
|
||||
|
||||
.rtc.bss (NOLOAD) :
|
||||
{
|
||||
_rtc_bss_start = ABSOLUTE(.);
|
||||
*rtc_wake_stub*.o(.bss .bss.*)
|
||||
*rtc_wake_stub*.o(COMMON)
|
||||
_rtc_bss_end = ABSOLUTE(.);
|
||||
} GROUP_LINK_IN(rtc_iram_seg)
|
||||
|
||||
/**
|
||||
* This section located in RTC SLOW Memory area.
|
||||
* It holds data marked with RTC_SLOW_ATTR attribute.
|
||||
* See the file "esp_attr.h" for more information.
|
||||
*/
|
||||
.rtc.force_slow :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_rtc_force_slow_start = ABSOLUTE(.);
|
||||
*(.rtc.force_slow .rtc.force_slow.*)
|
||||
. = ALIGN(4) ;
|
||||
_rtc_force_slow_end = ABSOLUTE(.);
|
||||
} > rtc_slow_seg
|
||||
|
||||
/* Get size of rtc slow data */
|
||||
_rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start);
|
||||
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
#include <zephyr/linker/intlist.ld>
|
||||
#endif
|
||||
|
||||
#include <zephyr/linker/debug-sections.ld>
|
||||
/DISCARD/ : { *(.note.GNU-stack) }
|
||||
|
||||
SECTION_PROLOGUE(.riscv.attributes, 0,)
|
||||
{
|
||||
KEEP(*(.riscv.attributes))
|
||||
KEEP(*(.gnu.attributes))
|
||||
}
|
||||
}
|
||||
93
soc/espressif/esp32c3/loader.c
Normal file
93
soc/espressif/esp32c3/loader.c
Normal file
|
|
@ -0,0 +1,93 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <esp32c3/rom/cache.h>
|
||||
#include "soc/cache_memory.h"
|
||||
#include "soc/extmem_reg.h"
|
||||
#include <bootloader_flash_priv.h>
|
||||
|
||||
#include <zephyr/kernel.h>
|
||||
#include <soc.h>
|
||||
#include <zephyr/storage/flash_map.h>
|
||||
#include <esp_log.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#ifdef CONFIG_BOOTLOADER_MCUBOOT
|
||||
|
||||
#define BOOT_LOG_INF(_fmt, ...) \
|
||||
ets_printf("[" CONFIG_SOC_SERIES "] [INF] " _fmt "\n\r", ##__VA_ARGS__)
|
||||
|
||||
#define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used))
|
||||
|
||||
extern uint32_t _image_irom_start, _image_irom_size, _image_irom_vaddr;
|
||||
extern uint32_t _image_drom_start, _image_drom_size, _image_drom_vaddr;
|
||||
|
||||
void __start(void);
|
||||
|
||||
static HDR_ATTR void (*_entry_point)(void) = &__start;
|
||||
|
||||
static int map_rom_segments(void)
|
||||
{
|
||||
int rc = 0;
|
||||
|
||||
size_t _partition_offset = FIXED_PARTITION_OFFSET(slot0_partition);
|
||||
uint32_t _app_irom_start = _partition_offset + (uint32_t)&_image_irom_start;
|
||||
uint32_t _app_irom_size = (uint32_t)&_image_irom_size;
|
||||
uint32_t _app_irom_vaddr = (uint32_t)&_image_irom_vaddr;
|
||||
|
||||
uint32_t _app_drom_start = _partition_offset + (uint32_t)&_image_drom_start;
|
||||
uint32_t _app_drom_size = (uint32_t)&_image_drom_size;
|
||||
uint32_t _app_drom_vaddr = (uint32_t)&_image_drom_vaddr;
|
||||
|
||||
uint32_t autoload = esp_rom_Cache_Suspend_ICache();
|
||||
|
||||
esp_rom_Cache_Invalidate_ICache_All();
|
||||
|
||||
/* Clear the MMU entries that are already set up,
|
||||
* so the new app only has the mappings it creates.
|
||||
*/
|
||||
for (size_t i = 0; i < FLASH_MMU_TABLE_SIZE; i++) {
|
||||
FLASH_MMU_TABLE[i] = MMU_TABLE_INVALID_VAL;
|
||||
}
|
||||
|
||||
uint32_t drom_page_count = bootloader_cache_pages_to_map(_app_drom_size, _app_drom_vaddr);
|
||||
|
||||
rc |= esp_rom_Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, _app_drom_vaddr & 0xffff0000,
|
||||
_app_drom_start & 0xffff0000, 64, drom_page_count, 0);
|
||||
|
||||
uint32_t irom_page_count = bootloader_cache_pages_to_map(_app_irom_size, _app_irom_vaddr);
|
||||
|
||||
rc |= esp_rom_Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, _app_irom_vaddr & 0xffff0000,
|
||||
_app_irom_start & 0xffff0000, 64, irom_page_count, 0);
|
||||
|
||||
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS);
|
||||
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS);
|
||||
|
||||
esp_rom_Cache_Resume_ICache(autoload);
|
||||
|
||||
/* Show map segments continue using same log format as during MCUboot phase */
|
||||
BOOT_LOG_INF("DROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map",
|
||||
_app_drom_start, _app_drom_vaddr, _app_drom_size, _app_drom_size);
|
||||
BOOT_LOG_INF("IROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map\r\n",
|
||||
_app_irom_start, _app_irom_vaddr, _app_irom_size, _app_irom_size);
|
||||
esp_rom_uart_tx_wait_idle(0);
|
||||
|
||||
return rc;
|
||||
}
|
||||
#endif /* CONFIG_BOOTLOADER_MCUBOOT */
|
||||
|
||||
void __start(void)
|
||||
{
|
||||
#ifdef CONFIG_BOOTLOADER_MCUBOOT
|
||||
int err = map_rom_segments();
|
||||
|
||||
if (err != 0) {
|
||||
ets_printf("Failed to setup XIP, aborting\n");
|
||||
abort();
|
||||
}
|
||||
#endif
|
||||
__esp_platform_start();
|
||||
}
|
||||
339
soc/espressif/esp32c3/mcuboot.ld
Normal file
339
soc/espressif/esp32c3/mcuboot.ld
Normal file
|
|
@ -0,0 +1,339 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Linker command/script file
|
||||
*
|
||||
* Linker script for the esp32c3 platform.
|
||||
*/
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/linker/sections.h>
|
||||
#include <zephyr/linker/linker-defs.h>
|
||||
#include <zephyr/linker/linker-tool.h>
|
||||
|
||||
#ifdef CONFIG_XIP
|
||||
#error "ESP32C3 bootloader cannot use XIP"
|
||||
#endif /* CONFIG_XIP */
|
||||
|
||||
/* Disable all romable LMA */
|
||||
#udef GROUP_DATA_LINK_IN
|
||||
#define GROUP_DATA_LINK_IN(vregion, lregion) > vregion
|
||||
|
||||
#define RAMABLE_REGION dram_seg
|
||||
#define RODATA_REGION dram_seg
|
||||
|
||||
#define IRAM_REGION iram_seg
|
||||
#define IRAM_LOADER_REGION iram_loader_seg
|
||||
|
||||
#define ROMABLE_REGION dram_seg
|
||||
#define IROM_SEG_ALIGN 0x4
|
||||
|
||||
/* Global symbols required for espressif hal build */
|
||||
MEMORY
|
||||
{
|
||||
iram_seg (RX) : org = 0x403CA000, len = 0x6000
|
||||
iram_loader_seg (RX) : org = 0x403D0000, len = 0x4000
|
||||
dram_seg (RW) : org = 0x3FCD8000, len = 0x8000
|
||||
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Default entry point: */
|
||||
ENTRY(CONFIG_KERNEL_ENTRY)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
|
||||
{
|
||||
_rodata_start = ABSOLUTE(.);
|
||||
|
||||
*(.rodata_desc .rodata_desc.*)
|
||||
*(.rodata_custom_desc .rodata_custom_desc.*)
|
||||
|
||||
__rodata_region_start = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
#include <snippets-rodata.ld>
|
||||
. = ALIGN(4);
|
||||
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
|
||||
*(.xt_except_table)
|
||||
*(.gcc_except_table .gcc_except_table.*)
|
||||
*(.gnu.linkonce.e.*)
|
||||
*(.gnu.version_r)
|
||||
. = (. + 3) & ~ 3;
|
||||
__eh_frame = ABSOLUTE(.);
|
||||
KEEP(*(.eh_frame))
|
||||
. = (. + 7) & ~ 3;
|
||||
|
||||
/* C++ exception handlers table: */
|
||||
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
|
||||
*(.xt_except_desc)
|
||||
*(.gnu.linkonce.h.*)
|
||||
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc_end)
|
||||
*(.dynamic)
|
||||
*(.gnu.version_d)
|
||||
__rodata_region_end = .;
|
||||
_rodata_end = ABSOLUTE(.);
|
||||
/* Literals are also RO data. */
|
||||
_lit4_start = ABSOLUTE(.);
|
||||
*(*.lit4)
|
||||
*(.lit4.*)
|
||||
*(.gnu.linkonce.lit4.*)
|
||||
_lit4_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
_thread_local_start = ABSOLUTE(.);
|
||||
*(.tdata)
|
||||
*(.tdata.*)
|
||||
*(.tbss)
|
||||
*(.tbss.*)
|
||||
*(.srodata)
|
||||
*(.srodata.*)
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.rodata_wlog)
|
||||
*(.rodata_wlog*)
|
||||
_thread_local_end = ABSOLUTE(.);
|
||||
/* _rodata_reserved_end = ABSOLUTE(.); */
|
||||
. = ALIGN(4);
|
||||
} GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)
|
||||
|
||||
#include <zephyr/linker/common-rom/common-rom-cpp.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-kernel-devices.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-debug.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-misc.ld>
|
||||
|
||||
#include <snippets-sections.ld>
|
||||
|
||||
.dram0.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__data_start = ABSOLUTE(.);
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
*(.data1)
|
||||
#ifdef CONFIG_RISCV_GP
|
||||
__global_pointer$ = . + 0x800;
|
||||
#endif /* CONFIG_RISCV_GP */
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
|
||||
KEEP(*(.jcr))
|
||||
*(.dram1 .dram1.*)
|
||||
. = ALIGN(4);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
|
||||
|
||||
#include <zephyr/linker/cplusplus-rom.ld>
|
||||
#include <zephyr/linker/thread-local-storage.ld>
|
||||
#include <snippets-data-sections.ld>
|
||||
#include <zephyr/linker/common-ram.ld>
|
||||
#include <snippets-ram-sections.ld>
|
||||
#include <zephyr/linker/cplusplus-ram.ld>
|
||||
|
||||
#include <zephyr/linker/common-rom/common-rom-logging.ld>
|
||||
|
||||
.dram0.end :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
#include <snippets-rwdata.ld>
|
||||
. = ALIGN(4);
|
||||
_end = ABSOLUTE(.);
|
||||
__data_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
|
||||
|
||||
/* Shared RAM */
|
||||
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_bss_start = ABSOLUTE(.);
|
||||
__bss_start = ABSOLUTE(.);
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.share.mem)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN (8);
|
||||
__bss_end = ABSOLUTE(.);
|
||||
_bss_end = ABSOLUTE(.);
|
||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
||||
|
||||
SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.noinit)
|
||||
*(.noinit.*)
|
||||
. = ALIGN(4);
|
||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
||||
|
||||
.iram_loader.text :
|
||||
{
|
||||
. = ALIGN (16);
|
||||
_loader_text_start = ABSOLUTE(.);
|
||||
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||||
*(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
|
||||
*libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_flash_config_esp32c3.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_init_common.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_random.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
|
||||
*libzephyr.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
|
||||
*libzephyr.a:bootloader_efuse_esp32c3.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_utility.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_sha.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_console.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_panic.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_soc.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:esp_image_format.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:flash_encrypt.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:flash_partitions.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:secure_boot.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:esp_efuse_table.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:esp_efuse_fields.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:esp_efuse_api.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:esp_efuse_utility.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:esp_efuse_api_key_esp32xx.*(.literal .text .literal.* .text.*)
|
||||
*esp_mcuboot.*(.literal .text .literal.* .text.*)
|
||||
*esp_loader.*(.literal .text .literal.* .text.*)
|
||||
*(.fini.literal)
|
||||
*(.fini)
|
||||
*(.gnu.version)
|
||||
_loader_text_end = ABSOLUTE(.);
|
||||
} > iram_loader_seg
|
||||
|
||||
/* .iram0.text : ALIGN(4) */
|
||||
SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))
|
||||
{
|
||||
/* Vectors go to IRAM */
|
||||
_iram_start = ABSOLUTE(.);
|
||||
_init_start = ABSOLUTE(.);
|
||||
|
||||
KEEP(*(.exception_vectors.text));
|
||||
. = ALIGN(256);
|
||||
|
||||
_invalid_pc_placeholder = ABSOLUTE(.);
|
||||
|
||||
_iram_text_start = ABSOLUTE(.);
|
||||
|
||||
KEEP(*(.exception.entry*)); /* contains _isr_wrapper */
|
||||
*(.exception.other*)
|
||||
. = ALIGN(4);
|
||||
|
||||
*(.entry.text)
|
||||
*(.init.literal)
|
||||
*(.init)
|
||||
. = ALIGN(4);
|
||||
*(.iram1 .iram1.*)
|
||||
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
|
||||
|
||||
. = ALIGN(4);
|
||||
_init_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(IRAM_LOADER_REGION, ROMABLE_REGION)
|
||||
|
||||
.iram0.text_end (NOLOAD) :
|
||||
{
|
||||
/* C3 memprot requires 512 B alignment for split lines */
|
||||
. = ALIGN (16);
|
||||
} GROUP_LINK_IN(IRAM_LOADER_REGION)
|
||||
|
||||
.iram0.data :
|
||||
{
|
||||
. = ALIGN(16);
|
||||
*(.iram.data)
|
||||
*(.iram.data*)
|
||||
} GROUP_DATA_LINK_IN(IRAM_LOADER_REGION, ROMABLE_REGION)
|
||||
|
||||
.iram0.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(16);
|
||||
*(.iram.bss)
|
||||
*(.iram.bss*)
|
||||
|
||||
. = ALIGN(16);
|
||||
_iram_end = ABSOLUTE(.);
|
||||
} GROUP_LINK_IN(IRAM_LOADER_REGION)
|
||||
|
||||
.flash_text_dummy (NOLOAD): ALIGN(IROM_SEG_ALIGN)
|
||||
{
|
||||
. = SIZEOF(_RODATA_SECTION_NAME);
|
||||
. = ALIGN(4) + 0x20;
|
||||
_rodata_reserved_start = .;
|
||||
} GROUP_LINK_IN(IRAM_REGION)
|
||||
|
||||
.flash.text : ALIGN(IROM_SEG_ALIGN)
|
||||
{
|
||||
_stext = .;
|
||||
_text_start = ABSOLUTE(.);
|
||||
|
||||
*(.literal .text .literal.* .text.*)
|
||||
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||||
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
|
||||
*(.fini.literal)
|
||||
*(.fini)
|
||||
*(.gnu.version)
|
||||
|
||||
/* CPU will try to prefetch up to 16 bytes of
|
||||
* of instructions. This means that any configuration (e.g. MMU, PMS) must allow
|
||||
* safe access to up to 16 bytes after the last real instruction, add
|
||||
* dummy bytes to ensure this
|
||||
*/
|
||||
. += 16;
|
||||
|
||||
_text_end = ABSOLUTE(.);
|
||||
_etext = .;
|
||||
|
||||
/* Similar to _iram_start, this symbol goes here so it is
|
||||
* resolved by addr2line in preference to the first symbol in
|
||||
* the flash.text segment.
|
||||
*/
|
||||
_flash_cache_start = ABSOLUTE(0);
|
||||
} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
|
||||
|
||||
/* linker rel sections*/
|
||||
#include <zephyr/linker/rel-sections.ld>
|
||||
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
#include <zephyr/linker/intlist.ld>
|
||||
#endif
|
||||
|
||||
#include <zephyr/linker/debug-sections.ld>
|
||||
/DISCARD/ : { *(.note.GNU-stack) }
|
||||
|
||||
SECTION_PROLOGUE(.riscv.attributes, 0,)
|
||||
{
|
||||
KEEP(*(.riscv.attributes))
|
||||
KEEP(*(.gnu.attributes))
|
||||
}
|
||||
}
|
||||
78
soc/espressif/esp32c3/pinctrl_soc.h
Normal file
78
soc/espressif/esp32c3/pinctrl_soc.h
Normal file
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* ESP32C3 SoC specific helpers for pinctrl driver
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_RISCV_ESP32C3_PINCTRL_SOC_H_
|
||||
#define ZEPHYR_SOC_RISCV_ESP32C3_PINCTRL_SOC_H_
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/types.h>
|
||||
|
||||
#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
|
||||
|
||||
/** @cond INTERNAL_HIDDEN */
|
||||
|
||||
/** Type for ESP32 pin. */
|
||||
typedef struct pinctrl_soc_pin {
|
||||
/** Pinmux settings (pin, direction and signal). */
|
||||
uint32_t pinmux;
|
||||
/** Pincfg settings (bias). */
|
||||
uint32_t pincfg;
|
||||
} pinctrl_soc_pin_t;
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize pinmux field in #pinctrl_pin_t.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
*/
|
||||
#define Z_PINCTRL_ESP32_PINMUX_INIT(node_id, prop, idx) DT_PROP_BY_IDX(node_id, prop, idx)
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
*/
|
||||
#define Z_PINCTRL_ESP32_PINCFG_INIT(node_id) \
|
||||
(((ESP32_NO_PULL * DT_PROP(node_id, bias_disable)) << ESP32_PIN_BIAS_SHIFT) | \
|
||||
((ESP32_PULL_UP * DT_PROP(node_id, bias_pull_up)) << ESP32_PIN_BIAS_SHIFT) | \
|
||||
((ESP32_PULL_DOWN * DT_PROP(node_id, bias_pull_down)) << ESP32_PIN_BIAS_SHIFT) | \
|
||||
((ESP32_PUSH_PULL * DT_PROP(node_id, drive_push_pull)) << ESP32_PIN_DRV_SHIFT) | \
|
||||
((ESP32_OPEN_DRAIN * DT_PROP(node_id, drive_open_drain)) << ESP32_PIN_DRV_SHIFT) | \
|
||||
((ESP32_PIN_OUT_HIGH * DT_PROP(node_id, output_high)) << ESP32_PIN_OUT_SHIFT) | \
|
||||
((ESP32_PIN_OUT_LOW * DT_PROP(node_id, output_low)) << ESP32_PIN_OUT_SHIFT) | \
|
||||
((ESP32_PIN_OUT_EN * DT_PROP(node_id, output_enable)) << ESP32_PIN_EN_DIR_SHIFT) | \
|
||||
((ESP32_PIN_IN_EN * DT_PROP(node_id, input_enable)) << ESP32_PIN_EN_DIR_SHIFT))
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize each pin.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param prop Property name.
|
||||
* @param idx Property entry index.
|
||||
*/
|
||||
#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
|
||||
{.pinmux = Z_PINCTRL_ESP32_PINMUX_INIT(node_id, prop, idx), \
|
||||
.pincfg = Z_PINCTRL_ESP32_PINCFG_INIT(node_id)},
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize state pins contained in a given property.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param prop Property name describing state pins.
|
||||
*/
|
||||
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||
{ \
|
||||
DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \
|
||||
Z_PINCTRL_STATE_PIN_INIT) \
|
||||
}
|
||||
|
||||
/** @endcond */
|
||||
|
||||
#endif /* ZEPHYR_SOC_RISCV_ESP32C3_PINCTRL_SOC_H_ */
|
||||
44
soc/espressif/esp32c3/power.c
Normal file
44
soc/espressif/esp32c3/power.c
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/pm/pm.h>
|
||||
#include <zephyr/irq.h>
|
||||
#include <esp_sleep.h>
|
||||
|
||||
#include <zephyr/logging/log.h>
|
||||
LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
|
||||
|
||||
/* Invoke Low Power/System Off specific Tasks */
|
||||
void pm_state_set(enum pm_state state, uint8_t substate_id)
|
||||
{
|
||||
ARG_UNUSED(substate_id);
|
||||
|
||||
switch (state) {
|
||||
case PM_STATE_STANDBY:
|
||||
/* Nothing to do. */
|
||||
break;
|
||||
default:
|
||||
LOG_DBG("Unsupported power state %u", state);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Handle SOC specific activity after Low Power Mode Exit */
|
||||
void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
|
||||
{
|
||||
ARG_UNUSED(substate_id);
|
||||
|
||||
switch (state) {
|
||||
case PM_STATE_STANDBY:
|
||||
irq_unlock(MSTATUS_IEN);
|
||||
__asm__ volatile("wfi");
|
||||
esp_light_sleep_start();
|
||||
break;
|
||||
default:
|
||||
LOG_DBG("Unsupported power state %u", state);
|
||||
break;
|
||||
}
|
||||
}
|
||||
15
soc/espressif/esp32c3/poweroff.c
Normal file
15
soc/espressif/esp32c3/poweroff.c
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/sys/poweroff.h>
|
||||
|
||||
#include <esp_sleep.h>
|
||||
|
||||
void z_sys_poweroff(void)
|
||||
{
|
||||
/* Forces RTC domain to be always on */
|
||||
esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
|
||||
esp_deep_sleep_start();
|
||||
}
|
||||
180
soc/espressif/esp32c3/soc.c
Normal file
180
soc/espressif/esp32c3/soc.c
Normal file
|
|
@ -0,0 +1,180 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* Include esp-idf headers first to avoid redefining BIT() macro */
|
||||
#include <soc/rtc_cntl_reg.h>
|
||||
#include <soc/timer_group_reg.h>
|
||||
#include <soc/gpio_reg.h>
|
||||
#include <soc/syscon_reg.h>
|
||||
#include <soc/system_reg.h>
|
||||
#include <soc/cache_memory.h>
|
||||
#include "hal/soc_ll.h"
|
||||
#include "hal/wdt_hal.h"
|
||||
#include "esp_cpu.h"
|
||||
#include "esp_timer.h"
|
||||
#include "esp_spi_flash.h"
|
||||
#include "esp_clk_internal.h"
|
||||
#include <soc/interrupt_reg.h>
|
||||
#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
|
||||
|
||||
#include <zephyr/kernel_structs.h>
|
||||
#include <kernel_internal.h>
|
||||
#include <string.h>
|
||||
#include <zephyr/toolchain.h>
|
||||
#include <soc.h>
|
||||
|
||||
#ifdef CONFIG_MCUBOOT
|
||||
#include "bootloader_init.h"
|
||||
#endif /* CONFIG_MCUBOOT */
|
||||
|
||||
extern void esp_reset_reason_init(void);
|
||||
|
||||
/*
|
||||
* This is written in C rather than assembly since, during the port bring up,
|
||||
* Zephyr is being booted by the Espressif bootloader. With it, the C stack
|
||||
* is already set up.
|
||||
*/
|
||||
void __attribute__((section(".iram1"))) __esp_platform_start(void)
|
||||
{
|
||||
#ifdef CONFIG_RISCV_GP
|
||||
/* Configure the global pointer register
|
||||
* (This should be the first thing startup does, as any other piece of code could be
|
||||
* relaxed by the linker to access something relative to __global_pointer$)
|
||||
*/
|
||||
__asm__ __volatile__(".option push\n"
|
||||
".option norelax\n"
|
||||
"la gp, __global_pointer$\n"
|
||||
".option pop");
|
||||
#endif /* CONFIG_RISCV_GP */
|
||||
|
||||
__asm__ __volatile__("la t0, _esp32c3_vector_table\n"
|
||||
"csrw mtvec, t0\n");
|
||||
|
||||
z_bss_zero();
|
||||
|
||||
/* Disable normal interrupts. */
|
||||
csr_read_clear(mstatus, MSTATUS_MIE);
|
||||
|
||||
esp_reset_reason_init();
|
||||
|
||||
#ifdef CONFIG_MCUBOOT
|
||||
/* MCUboot early initialisation.
|
||||
*/
|
||||
bootloader_init();
|
||||
|
||||
#else
|
||||
/* ESP-IDF 2nd stage bootloader enables RTC WDT to check on startup sequence
|
||||
* related issues in application. Hence disable that as we are about to start
|
||||
* Zephyr environment.
|
||||
*/
|
||||
wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
|
||||
|
||||
wdt_hal_write_protect_disable(&rtc_wdt_ctx);
|
||||
wdt_hal_disable(&rtc_wdt_ctx);
|
||||
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
|
||||
|
||||
/* Configure the Cache MMU size for instruction and rodata in flash. */
|
||||
extern uint32_t esp_rom_cache_set_idrom_mmu_size(uint32_t irom_size,
|
||||
uint32_t drom_size);
|
||||
|
||||
extern int _rodata_reserved_start;
|
||||
uint32_t rodata_reserved_start_align =
|
||||
(uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1);
|
||||
uint32_t cache_mmu_irom_size =
|
||||
((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) *
|
||||
sizeof(uint32_t);
|
||||
|
||||
esp_rom_cache_set_idrom_mmu_size(cache_mmu_irom_size,
|
||||
CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
|
||||
|
||||
/* Enable wireless phy subsystem clock,
|
||||
* This needs to be done before the kernel starts
|
||||
*/
|
||||
REG_CLR_BIT(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_SDIOSLAVE_EN);
|
||||
SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN);
|
||||
|
||||
/* Configures the CPU clock, RTC slow and fast clocks, and performs
|
||||
* RTC slow clock calibration.
|
||||
*/
|
||||
esp_clk_init();
|
||||
|
||||
esp_timer_early_init();
|
||||
|
||||
#if CONFIG_SOC_FLASH_ESP32
|
||||
spi_flash_guard_set(&g_flash_guard_default_ops);
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_MCUBOOT */
|
||||
|
||||
/*Initialize the esp32c3 interrupt controller */
|
||||
esp_intr_initialize();
|
||||
|
||||
/* Start Zephyr */
|
||||
z_cstart();
|
||||
|
||||
CODE_UNREACHABLE;
|
||||
}
|
||||
|
||||
/* Boot-time static default printk handler, possibly to be overridden later. */
|
||||
int IRAM_ATTR arch_printk_char_out(int c)
|
||||
{
|
||||
if (c == '\n') {
|
||||
esp_rom_uart_tx_one_char('\r');
|
||||
}
|
||||
esp_rom_uart_tx_one_char(c);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void IRAM_ATTR esp_restart_noos(void)
|
||||
{
|
||||
/* Disable interrupts */
|
||||
csr_read_clear(mstatus, MSTATUS_MIE);
|
||||
|
||||
/* Flush any data left in UART FIFOs */
|
||||
esp_rom_uart_tx_wait_idle(0);
|
||||
esp_rom_uart_tx_wait_idle(1);
|
||||
|
||||
/* 2nd stage bootloader reconfigures SPI flash signals. */
|
||||
/* Reset them to the defaults expected by ROM */
|
||||
WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
|
||||
|
||||
/* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */
|
||||
SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,
|
||||
SYSTEM_BB_RST | SYSTEM_FE_RST | SYSTEM_MAC_RST | SYSTEM_BT_RST |
|
||||
SYSTEM_BTMAC_RST | SYSTEM_SDIO_RST | SYSTEM_EMAC_RST |
|
||||
SYSTEM_MACPWR_RST | SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST |
|
||||
BLE_REG_REST_BIT | BLE_PWR_REG_REST_BIT | BLE_BB_REG_REST_BIT);
|
||||
|
||||
REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
|
||||
|
||||
/* Reset uart0 core first, then reset apb side. */
|
||||
SET_PERI_REG_MASK(UART_CLK_CONF_REG(0), UART_RST_CORE_M);
|
||||
|
||||
/* Reset timer/spi/uart */
|
||||
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG,
|
||||
SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST);
|
||||
REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0);
|
||||
/* Reset dma */
|
||||
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);
|
||||
REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0);
|
||||
|
||||
/* Reset core */
|
||||
soc_ll_reset_core(0);
|
||||
|
||||
while (true) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void sys_arch_reboot(int type)
|
||||
{
|
||||
esp_restart_noos();
|
||||
}
|
||||
52
soc/espressif/esp32c3/soc.h
Normal file
52
soc/espressif/esp32c3/soc.h
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __SOC_H__
|
||||
#define __SOC_H__
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
#include <soc/soc.h>
|
||||
#include <rom/ets_sys.h>
|
||||
#include <rom/spi_flash.h>
|
||||
#include <zephyr/types.h>
|
||||
#include <stdbool.h>
|
||||
#include "esp32c3/clk.h"
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
void __esp_platform_start(void);
|
||||
|
||||
extern void esp_rom_intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
|
||||
extern void esp_rom_uart_attach(void);
|
||||
extern void esp_rom_uart_tx_wait_idle(uint8_t uart_no);
|
||||
extern int esp_rom_uart_tx_one_char(uint8_t chr);
|
||||
extern int esp_rom_uart_rx_one_char(uint8_t *chr);
|
||||
extern int esp_rom_gpio_matrix_in(uint32_t gpio, uint32_t signal_index, bool inverted);
|
||||
extern int esp_rom_gpio_matrix_out(uint32_t gpio, uint32_t signal_index,
|
||||
bool out_invrted, bool out_enabled_inverted);
|
||||
extern void esp_rom_ets_set_user_start(uint32_t start);
|
||||
extern void esprv_intc_int_set_threshold(int priority_threshold);
|
||||
uint32_t soc_intr_get_next_source(void);
|
||||
extern void esp_rom_Cache_Resume_ICache(uint32_t autoload);
|
||||
extern int esp_rom_Cache_Invalidate_Addr(uint32_t addr, uint32_t size);
|
||||
extern uint32_t esp_rom_Cache_Suspend_ICache(void);
|
||||
extern void esp_rom_Cache_Invalidate_ICache_All(void);
|
||||
extern int esp_rom_Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr,
|
||||
uint32_t psize, uint32_t num, uint32_t fixed);
|
||||
extern int esp_rom_Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr,
|
||||
uint32_t psize, uint32_t num, uint32_t fixed);
|
||||
extern void esp_rom_Cache_Resume_ICache(uint32_t autoload);
|
||||
extern spiflash_legacy_data_t esp_rom_spiflash_legacy_data;
|
||||
extern int esp_rom_gpio_matrix_in(uint32_t gpio, uint32_t signal_index,
|
||||
bool inverted);
|
||||
extern int esp_rom_gpio_matrix_out(uint32_t gpio, uint32_t signal_index,
|
||||
bool out_inverted,
|
||||
bool out_enabled_inverted);
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#endif /* __SOC_H__ */
|
||||
20
soc/espressif/esp32c3/soc_irq.S
Normal file
20
soc/espressif/esp32c3/soc_irq.S
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
/* Copyright 2021 Espressif Systems (Shanghai) PTE LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <offsets.h>
|
||||
#include <zephyr/toolchain.h>
|
||||
|
||||
/* Exports */
|
||||
GTEXT(__soc_handle_irq)
|
||||
GTEXT(soc_intr_get_next_source)
|
||||
|
||||
SECTION_FUNC(exception.other, __soc_handle_irq)
|
||||
addi sp, sp,-4
|
||||
sw ra, 0x00(sp)
|
||||
la t1, soc_intr_get_next_source
|
||||
jalr ra, t1, 0
|
||||
lw ra, 0x00(sp)
|
||||
addi sp, sp, 4
|
||||
ret
|
||||
70
soc/espressif/esp32c3/soc_irq.c
Normal file
70
soc/espressif/esp32c3/soc_irq.c
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <soc/rtc_cntl_reg.h>
|
||||
#include <soc/timer_group_reg.h>
|
||||
#include <soc/gpio_reg.h>
|
||||
#include <soc/syscon_reg.h>
|
||||
#include <soc/system_reg.h>
|
||||
#include <soc/cache_memory.h>
|
||||
#include "hal/soc_ll.h"
|
||||
#include <riscv/interrupt.h>
|
||||
#include <soc/interrupt_reg.h>
|
||||
#include <soc/periph_defs.h>
|
||||
#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
|
||||
|
||||
#include <zephyr/kernel_structs.h>
|
||||
#include <string.h>
|
||||
#include <zephyr/toolchain.h>
|
||||
#include <soc.h>
|
||||
#include <zephyr/arch/riscv/arch.h>
|
||||
|
||||
#define ESP32C3_INTSTATUS_SLOT1_THRESHOLD 32
|
||||
|
||||
void arch_irq_enable(unsigned int irq)
|
||||
{
|
||||
esp_intr_enable(irq);
|
||||
}
|
||||
|
||||
void arch_irq_disable(unsigned int irq)
|
||||
{
|
||||
esp_intr_disable(irq);
|
||||
}
|
||||
|
||||
int arch_irq_is_enabled(unsigned int irq)
|
||||
{
|
||||
bool res = false;
|
||||
uint32_t key = irq_lock();
|
||||
|
||||
if (irq < 32) {
|
||||
res = esp_intr_get_enabled_intmask(0) & BIT(irq);
|
||||
} else {
|
||||
res = esp_intr_get_enabled_intmask(1) & BIT(irq - 32);
|
||||
}
|
||||
|
||||
irq_unlock(key);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
uint32_t soc_intr_get_next_source(void)
|
||||
{
|
||||
uint32_t status;
|
||||
uint32_t source;
|
||||
|
||||
status = REG_READ(INTERRUPT_CORE0_INTR_STATUS_0_REG) &
|
||||
esp_intr_get_enabled_intmask(0);
|
||||
|
||||
if (status) {
|
||||
source = __builtin_ffs(status) - 1;
|
||||
} else {
|
||||
status = REG_READ(INTERRUPT_CORE0_INTR_STATUS_1_REG) &
|
||||
esp_intr_get_enabled_intmask(1);
|
||||
source = (__builtin_ffs(status) - 1 + ESP32C3_INTSTATUS_SLOT1_THRESHOLD);
|
||||
}
|
||||
|
||||
return source;
|
||||
}
|
||||
35
soc/espressif/esp32c3/vectors.S
Normal file
35
soc/espressif/esp32c3/vectors.S
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
/* Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "soc/interrupt_reg.h"
|
||||
#include "riscv/rvruntime-frames.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#include <zephyr/toolchain.h>
|
||||
|
||||
/* Imports */
|
||||
GTEXT(_isr_wrapper)
|
||||
|
||||
/* This is the vector table. MTVEC points here.
|
||||
*
|
||||
* Use 4-byte intructions here. 1 instruction = 1 entry of the table.
|
||||
* The CPU jumps to MTVEC (i.e. the first entry) in case of an exception,
|
||||
* and (MTVEC & 0xfffffffc) + (mcause & 0x7fffffff) * 4, in case of an interrupt.
|
||||
*
|
||||
* Note: for our CPU, we need to place this on a 256-byte boundary, as CPU
|
||||
* only uses the 24 MSBs of the MTVEC, i.e. (MTVEC & 0xffffff00).
|
||||
*/
|
||||
|
||||
.global _esp32c3_vector_table
|
||||
.section .exception_vectors.text
|
||||
.balign 0x100
|
||||
.type _esp32c3_vector_table, @function
|
||||
|
||||
_esp32c3_vector_table:
|
||||
.option push
|
||||
.option norvc
|
||||
.rept (32)
|
||||
j _isr_wrapper /* 32 identical entries, all pointing to the interrupt handler */
|
||||
.endr
|
||||
103
soc/espressif/esp32s2/CMakeLists.txt
Normal file
103
soc/espressif/esp32s2/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_sources(
|
||||
soc.c
|
||||
soc_cache.c
|
||||
loader.c
|
||||
)
|
||||
|
||||
zephyr_include_directories(.)
|
||||
|
||||
zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fix.c)
|
||||
|
||||
zephyr_library_sources_ifdef(CONFIG_PM power.c)
|
||||
zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c)
|
||||
|
||||
# get code-partition slot0 address
|
||||
dt_nodelabel(dts_partition_path NODELABEL "slot0_partition")
|
||||
dt_reg_addr(img_0_off PATH ${dts_partition_path})
|
||||
|
||||
# get code-partition boot address
|
||||
dt_nodelabel(dts_partition_path NODELABEL "boot_partition")
|
||||
dt_reg_addr(boot_off PATH ${dts_partition_path})
|
||||
|
||||
# get flash size to use in esptool as string
|
||||
math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000")
|
||||
|
||||
if(CONFIG_BOOTLOADER_ESP_IDF)
|
||||
include(ExternalProject)
|
||||
|
||||
## we use hello-world project, but I think any can be used.
|
||||
set(espidf_components_dir ${ESP_IDF_PATH}/components)
|
||||
set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf)
|
||||
set(espidf_build_dir ${espidf_prefix}/build)
|
||||
|
||||
ExternalProject_Add(
|
||||
EspIdfBootloader
|
||||
PREFIX ${espidf_prefix}
|
||||
SOURCE_DIR ${espidf_components_dir}/bootloader/subproject
|
||||
BINARY_DIR ${espidf_build_dir}/bootloader
|
||||
CONFIGURE_COMMAND
|
||||
${CMAKE_COMMAND} -G${CMAKE_GENERATOR}
|
||||
-S ${espidf_components_dir}/bootloader/subproject
|
||||
-B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig
|
||||
-DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES}
|
||||
-DPYTHON_DEPS_CHECKED=1
|
||||
-DCMAKE_C_COMPILER=${CMAKE_C_COMPILER}
|
||||
-DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER}
|
||||
-DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER}
|
||||
-DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME}
|
||||
-DPYTHON=${PYTHON_EXECUTABLE}
|
||||
BUILD_COMMAND
|
||||
${CMAKE_COMMAND} --build .
|
||||
INSTALL_COMMAND "" # This particular build system has no install command
|
||||
)
|
||||
|
||||
ExternalProject_Add(
|
||||
EspPartitionTable
|
||||
SOURCE_DIR ${espidf_components_dir}/partition_table
|
||||
BINARY_DIR ${espidf_build_dir}
|
||||
CONFIGURE_COMMAND ""
|
||||
BUILD_COMMAND
|
||||
${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q
|
||||
--offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin
|
||||
INSTALL_COMMAND ""
|
||||
)
|
||||
|
||||
set_property(TARGET bintools PROPERTY disassembly_flag_inline_source)
|
||||
|
||||
add_dependencies(app EspIdfBootloader EspPartitionTable)
|
||||
|
||||
board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin")
|
||||
|
||||
board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin")
|
||||
|
||||
board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000")
|
||||
|
||||
endif()
|
||||
|
||||
if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF)
|
||||
|
||||
if(CONFIG_BUILD_OUTPUT_BIN)
|
||||
set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
|
||||
COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py
|
||||
ARGS --chip esp32s2 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB
|
||||
-o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin
|
||||
${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf)
|
||||
endif()
|
||||
|
||||
if(CONFIG_MCUBOOT)
|
||||
board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin")
|
||||
endif()
|
||||
|
||||
endif()
|
||||
|
||||
board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}")
|
||||
|
||||
board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}")
|
||||
|
||||
if(CONFIG_MCUBOOT)
|
||||
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "")
|
||||
else()
|
||||
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "")
|
||||
endif()
|
||||
228
soc/espressif/esp32s2/Kconfig
Normal file
228
soc/espressif/esp32s2/Kconfig
Normal file
|
|
@ -0,0 +1,228 @@
|
|||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_ESP32S2
|
||||
select XTENSA
|
||||
select ATOMIC_OPERATIONS_C
|
||||
select DYNAMIC_INTERRUPTS
|
||||
select CLOCK_CONTROL
|
||||
select PINCTRL
|
||||
select XIP if !MCUBOOT
|
||||
select HAS_ESPRESSIF_HAL
|
||||
select ARCH_SUPPORTS_COREDUMP
|
||||
select HAS_PM
|
||||
select HAS_POWEROFF
|
||||
|
||||
if SOC_SERIES_ESP32S2
|
||||
|
||||
config IDF_TARGET_ESP32S2
|
||||
bool "ESP32S2 as target SOC"
|
||||
default y
|
||||
|
||||
config ESP_SYSTEM_RTC_EXT_XTAL
|
||||
bool
|
||||
|
||||
config ESP_SYSTEM_RTC_EXT_OSC
|
||||
bool
|
||||
|
||||
choice ESP32S2_RTC_CLK_SRC
|
||||
prompt "RTC clock source"
|
||||
default ESP32S2_RTC_CLK_SRC_INT_RC
|
||||
help
|
||||
Choose which clock is used as RTC clock source.
|
||||
|
||||
- "Internal 90kHz oscillator" option provides lowest deep sleep current
|
||||
consumption, and does not require extra external components. However
|
||||
frequency stability with respect to temperature is poor, so time may
|
||||
drift in deep/light sleep modes.
|
||||
- "External 32kHz crystal" provides better frequency stability, at the
|
||||
expense of slightly higher (1uA) deep sleep current consumption.
|
||||
- "External 32kHz oscillator" allows using 32kHz clock generated by an
|
||||
external circuit. In this case, external clock signal must be connected
|
||||
to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal,
|
||||
and <1V in case of square wave signal. Common mode voltage should be
|
||||
0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude.
|
||||
Additionally, 1nF capacitor must be connected between 32K_XP pin and
|
||||
ground. 32K_XP pin can not be used as a GPIO in this case.
|
||||
- "Internal 8MHz oscillator divided by 256" option results in higher
|
||||
deep sleep current (by 5uA) but has better frequency stability than
|
||||
the internal 90kHz oscillator. It does not require external components.
|
||||
|
||||
config ESP32S2_RTC_CLK_SRC_INT_RC
|
||||
bool "Internal 90kHz RC oscillator"
|
||||
|
||||
config ESP32S2_RTC_CLK_SRC_EXT_CRYS
|
||||
bool "External 32kHz crystal"
|
||||
select ESP_SYSTEM_RTC_EXT_XTAL
|
||||
|
||||
config ESP32S2_RTC_CLK_SRC_EXT_OSC
|
||||
bool "External 32kHz oscillator at 32K_XN pin"
|
||||
select ESP_SYSTEM_RTC_EXT_OSC
|
||||
|
||||
config ESP32S2_RTC_CLK_SRC_INT_8MD256
|
||||
bool "Internal 8MHz oscillator, divided by 256 (~32kHz)"
|
||||
|
||||
endchoice
|
||||
|
||||
config ESP32S2_RTC_CLK_CAL_CYCLES
|
||||
int "Number of cycles for RTC_SLOW_CLK calibration"
|
||||
default 3000 if ESP32S2_RTC_CLK_SRC_EXT_CRYS || ESP32S2_RTC_CLK_SRC_EXT_OSC || ESP32S2_RTC_CLK_SRC_INT_8MD256
|
||||
default 576 if ESP32S2_RTC_CLK_SRC_INT_RC
|
||||
range 0 125000
|
||||
help
|
||||
When the startup code initializes RTC_SLOW_CLK, it can perform
|
||||
calibration by comparing the RTC_SLOW_CLK frequency with main XTAL
|
||||
frequency. This option sets the number of RTC_SLOW_CLK cycles measured
|
||||
by the calibration routine. Higher numbers increase calibration
|
||||
precision, which may be important for applications which spend a lot of
|
||||
time in deep sleep. Lower numbers reduce startup time.
|
||||
|
||||
When this option is set to 0, clock calibration will not be performed at
|
||||
startup, and approximate clock frequencies will be assumed:
|
||||
|
||||
- 90000 Hz if internal RC oscillator is used as clock source. For this use value 1024.
|
||||
- 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
|
||||
In case more value will help improve the definition of the launch of the crystal.
|
||||
If the crystal could not start, it will be switched to internal RC.
|
||||
|
||||
menu "Cache config"
|
||||
|
||||
choice
|
||||
prompt "Instruction cache line size"
|
||||
default ESP32S2_INSTRUCTION_CACHE_LINE_32B
|
||||
|
||||
config ESP32S2_INSTRUCTION_CACHE_LINE_16B
|
||||
bool "16 Bytes"
|
||||
|
||||
config ESP32S2_INSTRUCTION_CACHE_LINE_32B
|
||||
bool "32 Bytes"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Instruction cache size"
|
||||
default ESP32S2_INSTRUCTION_CACHE_8KB
|
||||
|
||||
config ESP32S2_INSTRUCTION_CACHE_8KB
|
||||
bool "8KB instruction cache size"
|
||||
|
||||
config ESP32S2_INSTRUCTION_CACHE_16KB
|
||||
bool "16KB instruction cache size"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Data cache size"
|
||||
default ESP32S2_DATA_CACHE_0KB if !ESP_SPIRAM
|
||||
default ESP32S2_DATA_CACHE_8KB if ESP_SPIRAM
|
||||
|
||||
config ESP32S2_DATA_CACHE_0KB
|
||||
bool "0KB data cache size"
|
||||
|
||||
config ESP32S2_DATA_CACHE_8KB
|
||||
bool "8KB data cache size"
|
||||
|
||||
config ESP32S2_DATA_CACHE_16KB
|
||||
bool "16KB data cache size"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Data cache line size"
|
||||
default ESP32S2_DATA_CACHE_LINE_32B
|
||||
|
||||
config ESP32S2_DATA_CACHE_LINE_16B
|
||||
bool "16 Bytes"
|
||||
|
||||
config ESP32S2_DATA_CACHE_LINE_32B
|
||||
bool "32 Bytes"
|
||||
|
||||
endchoice
|
||||
|
||||
config ESP32S2_INSTRUCTION_CACHE_SIZE
|
||||
hex
|
||||
default 0x4000 if ESP32S2_INSTRUCTION_CACHE_16KB
|
||||
default 0x2000
|
||||
|
||||
config ESP32S2_DATA_CACHE_SIZE
|
||||
hex
|
||||
default 0x2000 if ESP32S2_DATA_CACHE_8KB
|
||||
default 0x4000 if ESP32S2_DATA_CACHE_16KB
|
||||
default 0x0000
|
||||
|
||||
endmenu # Cache config
|
||||
|
||||
menu "PSRAM clock and cs IO for ESP32-S2"
|
||||
depends on ESP_SPIRAM
|
||||
|
||||
config DEFAULT_PSRAM_CLK_IO
|
||||
int "PSRAM CLK IO number"
|
||||
range 0 33
|
||||
default 30
|
||||
help
|
||||
The PSRAM CLOCK IO can be any unused GPIO, user can config
|
||||
it based on hardware design.
|
||||
|
||||
config DEFAULT_PSRAM_CS_IO
|
||||
int "PSRAM CS IO number"
|
||||
range 0 33
|
||||
default 26
|
||||
help
|
||||
The PSRAM CS IO can be any unused GPIO, user can config it
|
||||
based on hardware design.
|
||||
|
||||
endmenu # PSRAM clock and cs IO for ESP32S2
|
||||
|
||||
choice ESP32S2_UNIVERSAL_MAC_ADDRESSES
|
||||
bool "Number of universally administered (by IEEE) MAC address"
|
||||
default ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO
|
||||
help
|
||||
Configure the number of universally administered (by IEEE) MAC addresses.
|
||||
During initialization, MAC addresses for each network interface are generated or
|
||||
derived from a single base MAC address. If the number of universal MAC addresses is two,
|
||||
all interfaces (WiFi station, WiFi softap) receive a universally administered MAC
|
||||
address.
|
||||
They are generated sequentially by adding 0, and 1 (respectively) to the final octet of
|
||||
the base MAC address. If the number of universal MAC addresses is one, only WiFi station
|
||||
receives a universally administered MAC address.
|
||||
The WiFi softap receives local MAC addresses. It's derived from the universal WiFi
|
||||
station MAC addresses.
|
||||
When using the default (Espressif-assigned) base MAC address, either setting can be used.
|
||||
When using a custom universal MAC address range, the correct setting will depend on the
|
||||
allocation of MAC addresses in this range (either 1 or 2 per device).
|
||||
|
||||
config ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE
|
||||
bool "One"
|
||||
select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
|
||||
|
||||
config ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO
|
||||
bool "Two"
|
||||
select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
|
||||
select ESP_MAC_ADDR_UNIVERSE_WIFI_AP
|
||||
|
||||
endchoice # ESP32S2_UNIVERSAL_MAC_ADDRESSES
|
||||
|
||||
config ESP_MAC_ADDR_UNIVERSE_WIFI_AP
|
||||
bool
|
||||
|
||||
config ESP_MAC_ADDR_UNIVERSE_WIFI_STA
|
||||
bool
|
||||
|
||||
config ESP32S2_UNIVERSAL_MAC_ADDRESSES
|
||||
int
|
||||
default 1 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE
|
||||
default 2 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO
|
||||
|
||||
config ESP32_PHY_MAX_WIFI_TX_POWER
|
||||
int "Max WiFi TX power (dBm)"
|
||||
range 10 20
|
||||
default 20
|
||||
help
|
||||
Set maximum transmit power for WiFi radio. Actual transmit power for high
|
||||
data rates may be lower than this setting.
|
||||
|
||||
config ESP32_PHY_MAX_TX_POWER
|
||||
int
|
||||
default ESP32_PHY_MAX_WIFI_TX_POWER
|
||||
|
||||
endif # SOC_SERIES_ESP32S2
|
||||
24
soc/espressif/esp32s2/Kconfig.defconfig
Normal file
24
soc/espressif/esp32s2/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_ESP32S2
|
||||
|
||||
config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
|
||||
default n
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
|
||||
|
||||
config XTENSA_CCOUNT_HZ
|
||||
default SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
|
||||
config ESPTOOLPY_FLASHFREQ_80M
|
||||
default y
|
||||
|
||||
config FLASH_SIZE
|
||||
default $(dt_node_reg_size_int,/soc/flash-controller@3f402000/flash@0,0)
|
||||
|
||||
config FLASH_BASE_ADDRESS
|
||||
default $(dt_node_reg_addr_hex,/soc/flash-controller@3f402000/flash@0)
|
||||
|
||||
endif # SOC_SERIES_ESP32S3
|
||||
27
soc/espressif/esp32s2/Kconfig.defconfig.series
Normal file
27
soc/espressif/esp32s2/Kconfig.defconfig.series
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_ESP32S2
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
|
||||
|
||||
config XTENSA_CCOUNT_HZ
|
||||
default SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
|
||||
config MP_MAX_NUM_CPUS
|
||||
default 1
|
||||
|
||||
config ISR_STACK_SIZE
|
||||
default 2048
|
||||
|
||||
config ESPTOOLPY_FLASHFREQ_80M
|
||||
default y
|
||||
|
||||
config FLASH_SIZE
|
||||
default $(dt_node_reg_size_int,/soc/flash-controller@3f402000/flash@0,0)
|
||||
|
||||
config FLASH_BASE_ADDRESS
|
||||
default $(dt_node_reg_addr_hex,/soc/flash-controller@3f402000/flash@0)
|
||||
|
||||
endif # SOC_SERIES_ESP32S2
|
||||
126
soc/espressif/esp32s2/Kconfig.soc
Normal file
126
soc/espressif/esp32s2/Kconfig.soc
Normal file
|
|
@ -0,0 +1,126 @@
|
|||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_ESP32S2
|
||||
bool
|
||||
select SOC_FAMILY_ESPRESSIF_ESP32
|
||||
help
|
||||
ESP32-S2 Series
|
||||
|
||||
config SOC_ESP32S2_R2
|
||||
bool
|
||||
select SOC_ESP32S2
|
||||
help
|
||||
ESP32S2_R2
|
||||
|
||||
config SOC_ESP32S2_FH2
|
||||
bool
|
||||
select SOC_ESP32S2
|
||||
help
|
||||
ESP32S2_FH2
|
||||
|
||||
config SOC_ESP32S2_FH4
|
||||
bool
|
||||
select SOC_ESP32S2
|
||||
help
|
||||
ESP32S2_FH4
|
||||
|
||||
config SOC_ESP32S2_FN4R2
|
||||
bool
|
||||
select SOC_ESP32S2
|
||||
help
|
||||
ESP32S2_FN4R2
|
||||
|
||||
# SiP with external flash / psram
|
||||
config SOC_ESP32S2_SOLO_N4
|
||||
bool
|
||||
select SOC_ESP32S2
|
||||
help
|
||||
ESP32S2_SOLO_N4
|
||||
|
||||
config SOC_ESP32S2_SOLO_N8
|
||||
bool
|
||||
select SOC_ESP32S2
|
||||
help
|
||||
ESP32S2_SOLO_N8
|
||||
|
||||
config SOC_ESP32S2_SOLO_N16
|
||||
bool
|
||||
select SOC_ESP32S2
|
||||
help
|
||||
ESP32S2_SOLO_N16
|
||||
|
||||
config SOC_ESP32S2_SOLO_N4R2
|
||||
bool
|
||||
select SOC_ESP32S2
|
||||
help
|
||||
ESP32S2_SOLO_N4R2
|
||||
|
||||
config SOC_ESP32S2_MINI_N4
|
||||
bool
|
||||
select SOC_ESP32S2
|
||||
help
|
||||
ESP32S2_MINI_N4
|
||||
|
||||
config SOC_ESP32S2_MINI_N4R2
|
||||
bool
|
||||
select SOC_ESP32S2
|
||||
help
|
||||
ESP32S2_MINI_N4R2
|
||||
|
||||
config SOC_ESP32S2_WROOM
|
||||
bool
|
||||
select SOC_ESP32S2
|
||||
help
|
||||
ESP32S2_WROOM
|
||||
|
||||
config SOC_ESP32S2_WROVER_N4R2
|
||||
bool
|
||||
select SOC_ESP32S2
|
||||
help
|
||||
ESP32S2_WROVER_N4R2
|
||||
|
||||
config SOC_ESP32S2_WROVER_N8R2
|
||||
bool
|
||||
select SOC_ESP32S2
|
||||
help
|
||||
ESP32S2_WROVER_N8R2
|
||||
|
||||
config SOC_ESP32S2_WROVER_N16R2
|
||||
bool
|
||||
select SOC_ESP32S2
|
||||
help
|
||||
ESP32S2_WROVER_N16R2
|
||||
|
||||
config SOC_ESP32S2
|
||||
bool
|
||||
select SOC_SERIES_ESP32S2
|
||||
help
|
||||
ESP32S2
|
||||
|
||||
config SOC_SERIES
|
||||
default "esp32s2" if SOC_SERIES_ESP32S2
|
||||
|
||||
config SOC
|
||||
default "esp32s2" if SOC_SERIES_ESP32S2
|
||||
|
||||
config SOC_PART_NUMBER
|
||||
default "ESP32S2" if SOC_ESP32S2
|
||||
default "ESP32S2_R2" if SOC_ESP32S2_R2
|
||||
default "ESP32S2_FH2" if SOC_ESP32S2_FH2
|
||||
default "ESP32S2_FH4" if SOC_ESP32S2_FH4
|
||||
default "ESP32S2_FN4R2" if SOC_ESP32S2_FN4R2
|
||||
default "ESP32S2_SOLO_N4" if SOC_ESP32S2_SOLO_N4
|
||||
default "ESP32S2_SOLO_N8" if SOC_ESP32S2_SOLO_N8
|
||||
default "ESP32S2_SOLO_N16" if SOC_ESP32S2_SOLO_N16
|
||||
default "ESP32S2_SOLO_N4R2" if SOC_ESP32S2_SOLO_N4R2
|
||||
default "ESP32S2_MINI_N4" if SOC_ESP32S2_MINI_N4
|
||||
default "ESP32S2_MINI_N4R2" if SOC_ESP32S2_MINI_N4R2
|
||||
default "ESP32S2_WROOM" if SOC_ESP32S2_WROOM
|
||||
default "ESP32S2_WROVER_N4R2" if SOC_ESP32S2_WROVER_N4R2
|
||||
default "ESP32S2_WROVER_N8R2" if SOC_ESP32S2_WROVER_N8R2
|
||||
default "ESP32S2_WROVER_N16R2" if SOC_ESP32S2_WROVER_N16R2
|
||||
|
||||
config SOC_TOOLCHAIN_NAME
|
||||
string
|
||||
default "espressif_esp32s2" if SOC_SERIES_ESP32S2
|
||||
563
soc/espressif/esp32s2/default.ld
Normal file
563
soc/espressif/esp32s2/default.ld
Normal file
|
|
@ -0,0 +1,563 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Linker command/script file
|
||||
*
|
||||
* Linker script for the esp32s2 platform.
|
||||
*/
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/linker/sections.h>
|
||||
#include <zephyr/linker/linker-defs.h>
|
||||
#include <zephyr/linker/linker-tool.h>
|
||||
|
||||
#define RAM_IRAM_START 0x40020000
|
||||
#define RAM_DRAM_START 0x3ffb0000
|
||||
|
||||
/* DATA_RAM_END is equivalent 2nd stage bootloader iram_loader_seg
|
||||
start address (that should not be overlapped) */
|
||||
#define DATA_RAM_END 0x3FFE0000
|
||||
|
||||
#define IRAM_ORG (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \
|
||||
+ CONFIG_ESP32S2_DATA_CACHE_SIZE)
|
||||
|
||||
#define DRAM_ORG (RAM_DRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \
|
||||
+ CONFIG_ESP32S2_DATA_CACHE_SIZE)
|
||||
|
||||
#define I_D_RAM_SIZE DATA_RAM_END - DRAM_ORG
|
||||
|
||||
#define RAMABLE_REGION dram0_0_seg
|
||||
#define RODATA_REGION drom0_0_seg
|
||||
#define IRAM_REGION iram0_0_seg
|
||||
#define FLASH_CODE_REGION irom0_0_seg
|
||||
|
||||
#define ROMABLE_REGION ROM
|
||||
|
||||
#ifdef CONFIG_FLASH_SIZE
|
||||
#define FLASH_SIZE CONFIG_FLASH_SIZE
|
||||
#else
|
||||
#define FLASH_SIZE 0x400000
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BOOTLOADER_ESP_IDF
|
||||
#define IROM_SEG_ORG 0x40080020
|
||||
#define IROM_SEG_LEN (FLASH_SIZE-0x20)
|
||||
#define IROM_SEG_ALIGN 0x4
|
||||
#else
|
||||
#define IROM_SEG_ORG 0x40080000
|
||||
#define IROM_SEG_LEN FLASH_SIZE
|
||||
#define IROM_SEG_ALIGN 0x10000
|
||||
#endif
|
||||
|
||||
/* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA.
|
||||
* Executing directly from LMA is not possible. */
|
||||
#undef GROUP_ROM_LINK_IN
|
||||
#define GROUP_ROM_LINK_IN(vregion, lregion) > RODATA_REGION AT > lregion
|
||||
|
||||
MEMORY
|
||||
{
|
||||
mcuboot_hdr (RX): org = 0x0, len = 0x20
|
||||
metadata (RX): org = 0x20, len = 0x20
|
||||
ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40
|
||||
iram0_0_seg(RX): org = IRAM_ORG, len = I_D_RAM_SIZE
|
||||
irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN
|
||||
dram0_0_seg(RW): org = DRAM_ORG, len = I_D_RAM_SIZE
|
||||
drom0_0_seg(R): org = 0x3f000040, len = FLASH_SIZE - 0x40
|
||||
|
||||
rtc_iram_seg(RWX): org = 0x40070000, len = 0x2000
|
||||
rtc_slow_seg(RW): org = 0x50000000, len = 0x2000
|
||||
#if defined(CONFIG_ESP_SPIRAM)
|
||||
ext_ram_seg(RW): org = 0x3f500000, len = CONFIG_ESP_SPIRAM_SIZE
|
||||
#endif
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Default entry point: */
|
||||
ENTRY(CONFIG_KERNEL_ENTRY)
|
||||
|
||||
_rom_store_table = 0;
|
||||
|
||||
_heap_sentry = 0x3fffe710;
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Reserve space for MCUboot header in the binary */
|
||||
.mcuboot_header :
|
||||
{
|
||||
QUAD(0x0)
|
||||
QUAD(0x0)
|
||||
QUAD(0x0)
|
||||
QUAD(0x0)
|
||||
} > mcuboot_hdr
|
||||
.metadata :
|
||||
{
|
||||
/* Magic byte for load header */
|
||||
LONG(0xace637d3)
|
||||
|
||||
/* Application entry point address */
|
||||
KEEP(*(.entry_addr))
|
||||
|
||||
/* IRAM metadata:
|
||||
* - Destination address (VMA) for IRAM region
|
||||
* - Flash offset (LMA) for start of IRAM region
|
||||
* - Size of IRAM region
|
||||
*/
|
||||
LONG(ADDR(.iram0.vectors))
|
||||
LONG(LOADADDR(.iram0.vectors))
|
||||
LONG(LOADADDR(.iram0.text) + SIZEOF(.iram0.text) - LOADADDR(.iram0.vectors))
|
||||
|
||||
/* DRAM metadata:
|
||||
* - Destination address (VMA) for DRAM region
|
||||
* - Flash offset (LMA) for start of DRAM region
|
||||
* - Size of DRAM region
|
||||
*/
|
||||
LONG(ADDR(.dram0.data))
|
||||
LONG(LOADADDR(.dram0.data))
|
||||
LONG(LOADADDR(.dummy.dram.data) + SIZEOF(.dummy.dram.data) - LOADADDR(.dram0.data))
|
||||
} > metadata
|
||||
|
||||
#include <zephyr/linker/rel-sections.ld>
|
||||
_image_drom_start = LOADADDR(_RODATA_SECTION_NAME);
|
||||
_image_drom_size = LOADADDR(_RODATA_SECTION_END) + SIZEOF(_RODATA_SECTION_END) - _image_drom_start;
|
||||
_image_drom_vaddr = ADDR(_RODATA_SECTION_NAME);
|
||||
|
||||
/* NOTE: .rodata section should be the first section in the linker script and no
|
||||
* other section should appear before .rodata section. This is the requirement
|
||||
* to align ROM section to 64K page offset.
|
||||
* Adding .rodata as first section helps to reduce size of generated binary by
|
||||
* few kBs.
|
||||
*/
|
||||
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(4))
|
||||
{
|
||||
_rodata_reserved_start = ABSOLUTE(.);
|
||||
__rodata_region_start = ABSOLUTE(.);
|
||||
|
||||
. = ALIGN(4);
|
||||
#include <snippets-rodata.ld>
|
||||
|
||||
. = ALIGN(4);
|
||||
*(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata)
|
||||
*(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata.*)
|
||||
|
||||
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
|
||||
*(.xt_except_table)
|
||||
*(.gcc_except_table .gcc_except_table.*)
|
||||
*(.gnu.linkonce.e.*)
|
||||
*(.gnu.version_r)
|
||||
. = (. + 3) & ~ 3;
|
||||
__eh_frame = ABSOLUTE(.);
|
||||
KEEP(*(.eh_frame))
|
||||
. = (. + 7) & ~ 3;
|
||||
|
||||
/* C++ exception handlers table: */
|
||||
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
|
||||
*(.xt_except_desc)
|
||||
*(.gnu.linkonce.h.*)
|
||||
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc_end)
|
||||
*(.dynamic)
|
||||
*(.gnu.version_d)
|
||||
. = ALIGN(4);
|
||||
__rodata_region_end = ABSOLUTE(.);
|
||||
/* Literals are also RO data. */
|
||||
_lit4_start = ABSOLUTE(.);
|
||||
*(*.lit4)
|
||||
*(.lit4.*)
|
||||
*(.gnu.linkonce.lit4.*)
|
||||
_lit4_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
*(.rodata_wlog)
|
||||
*(.rodata_wlog*)
|
||||
. = ALIGN(4);
|
||||
} GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)
|
||||
|
||||
#include <zephyr/linker/common-rom/common-rom-cpp.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-kernel-devices.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-ztest.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-net.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-debug.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-misc.ld>
|
||||
#include <zephyr/linker/thread-local-storage.ld>
|
||||
#include <snippets-sections.ld>
|
||||
|
||||
/* Create an explicit section at the end of all the data that shall be mapped into drom.
|
||||
* This is used to calculate the size of the _image_drom_size variable */
|
||||
SECTION_PROLOGUE(_RODATA_SECTION_END,,ALIGN(0x10))
|
||||
{
|
||||
_rodata_reserved_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
_image_rodata_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)
|
||||
|
||||
|
||||
/* Send .iram0 code to iram */
|
||||
.iram0.vectors : ALIGN(4)
|
||||
{
|
||||
_iram_start = ABSOLUTE(.);
|
||||
/* Vectors go to IRAM */
|
||||
_init_start = ABSOLUTE(.);
|
||||
/* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
|
||||
. = 0x0;
|
||||
KEEP(*(.WindowVectors.text));
|
||||
. = 0x180;
|
||||
KEEP(*(.Level2InterruptVector.text));
|
||||
. = 0x1c0;
|
||||
KEEP(*(.Level3InterruptVector.text));
|
||||
. = 0x200;
|
||||
KEEP(*(.Level4InterruptVector.text));
|
||||
. = 0x240;
|
||||
KEEP(*(.Level5InterruptVector.text));
|
||||
. = 0x280;
|
||||
KEEP(*(.DebugExceptionVector.text));
|
||||
. = 0x2c0;
|
||||
KEEP(*(.NMIExceptionVector.text));
|
||||
. = 0x300;
|
||||
KEEP(*(.KernelExceptionVector.text));
|
||||
. = 0x340;
|
||||
KEEP(*(.UserExceptionVector.text));
|
||||
. = 0x3C0;
|
||||
KEEP(*(.DoubleExceptionVector.text));
|
||||
. = 0x400;
|
||||
*(.*Vector.literal)
|
||||
|
||||
*(.UserEnter.literal);
|
||||
*(.UserEnter.text);
|
||||
. = ALIGN (16);
|
||||
*(.entry.text)
|
||||
*(.init.literal)
|
||||
*(.init)
|
||||
_init_end = ABSOLUTE(.);
|
||||
|
||||
/* This goes here, not at top of linker script, so addr2line finds it last,
|
||||
and uses it in preference to the first symbol in IRAM */
|
||||
} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
|
||||
|
||||
.iram0.text : ALIGN(4)
|
||||
{
|
||||
. = ALIGN(8);
|
||||
/* Code marked as running out of IRAM */
|
||||
*(.iram1 .iram1.*)
|
||||
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
|
||||
*libesp32.a:panic.*(.literal .text .literal.* .text.*)
|
||||
*librtc.a:(.literal .text .literal.* .text.*)
|
||||
*libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)
|
||||
*libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)
|
||||
*libsubsys__net__ip.a:(.literal .text .literal.* .text.*)
|
||||
*libsubsys__net.a:(.literal .text .literal.* .text.*)
|
||||
*libarch__xtensa__core.a:(.literal .text .literal.* .text.*)
|
||||
*libkernel.a:(.literal .text .literal.* .text.*)
|
||||
*libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)
|
||||
*libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)
|
||||
*libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)
|
||||
*libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)
|
||||
*libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:log_core.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)
|
||||
*libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:log_list.*(.literal .text .literal.* .text.*)
|
||||
*libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out)
|
||||
*libzephyr.a:log_output.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:loader.*(.literal .text .literal.* .text.*)
|
||||
*liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)
|
||||
*liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*)
|
||||
*libc.a:*(.literal .text .literal.* .text.*)
|
||||
*libphy.a:( .phyiram .phyiram.*)
|
||||
*libgcov.a:(.literal .text .literal.* .text.*)
|
||||
|
||||
#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)
|
||||
*libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*)
|
||||
*libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)
|
||||
*libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
|
||||
*libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
|
||||
#endif
|
||||
|
||||
/* align + add 16B for CPU dummy speculative instr. fetch */
|
||||
. = ALIGN(4) + 16;
|
||||
_iram_text = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
|
||||
|
||||
.dram0.dummy (NOLOAD):
|
||||
{
|
||||
/**
|
||||
* This section is required to skip .iram0.text area because iram0_0_seg and
|
||||
* dram0_0_seg reflect the same address space on different buses.
|
||||
*/
|
||||
. = ALIGN (8);
|
||||
. = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
|
||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
||||
|
||||
/* Shared RAM */
|
||||
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_bss_start = ABSOLUTE(.);
|
||||
__bss_start = ABSOLUTE(.);
|
||||
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.share.mem)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN (8);
|
||||
__bss_end = ABSOLUTE(.);
|
||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
||||
|
||||
#if defined(CONFIG_ESP_SPIRAM)
|
||||
.ext_ram.bss (NOLOAD):
|
||||
{
|
||||
_ext_ram_data_start = ABSOLUTE(.);
|
||||
_ext_ram_bss_start = ABSOLUTE(.);
|
||||
|
||||
#if defined(CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM)
|
||||
*libdrivers__wifi.a:(.noinit .noinit.*)
|
||||
*libsubsys__net__l2__ethernet.a:(.noinit .noinit.*)
|
||||
*libsubsys__net__lib__config.a:(.noinit .noinit.*)
|
||||
*libsubsys__net__ip.a:(.noinit .noinit.*)
|
||||
*libsubsys__net.a:(.noinit .noinit.*)
|
||||
#endif
|
||||
_spiram_heap_start = ABSOLUTE(.);
|
||||
. = . + CONFIG_ESP_SPIRAM_HEAP_SIZE;
|
||||
|
||||
*(.ext_ram.bss*)
|
||||
. = ALIGN(4);
|
||||
_ext_ram_bss_end = ABSOLUTE(.);
|
||||
|
||||
_ext_ram_data_end = ABSOLUTE(.);
|
||||
} > ext_ram_seg
|
||||
#endif
|
||||
|
||||
SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.noinit)
|
||||
*(.noinit.*)
|
||||
. = ALIGN(8);
|
||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
||||
|
||||
.dram0.data :
|
||||
{
|
||||
. = ALIGN (8);
|
||||
__data_start = ABSOLUTE(.);
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
/* rodata for panic handler(libarch__xtensa__core.a) and all
|
||||
* dependent functions should be placed in DRAM to avoid issue
|
||||
* when flash cache is disabled */
|
||||
*libarch__xtensa__core.a:(.rodata .rodata.*)
|
||||
*libkernel.a:fatal.*(.rodata .rodata.*)
|
||||
*libkernel.a:init.*(.rodata .rodata.*)
|
||||
*libzephyr.a:cbprintf_complete*(.rodata .rodata.*)
|
||||
*libzephyr.a:log_core.*(.rodata .rodata.*)
|
||||
*libzephyr.a:log_backend_uart.*(.rodata .rodata.*)
|
||||
*libzephyr.a:log_output.*(.rodata .rodata.*)
|
||||
*libzephyr.a:loader.*(.rodata .rodata.*)
|
||||
*libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*)
|
||||
*libzephyr.a:spi_flash_rom_patch.*(.rodata .rodata.*)
|
||||
*libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)
|
||||
|
||||
KEEP(*(.jcr))
|
||||
*(.dram1 .dram1.*)
|
||||
. = ALIGN(4);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
|
||||
|
||||
#include <zephyr/linker/cplusplus-rom.ld>
|
||||
#include <snippets-data-sections.ld>
|
||||
#include <zephyr/linker/common-ram.ld>
|
||||
#include <snippets-ram-sections.ld>
|
||||
#include <zephyr/linker/cplusplus-ram.ld>
|
||||
|
||||
/* logging sections should be placed in RAM area to avoid flash cache disabled issues */
|
||||
#pragma push_macro("GROUP_ROM_LINK_IN")
|
||||
#undef GROUP_ROM_LINK_IN
|
||||
#define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN
|
||||
#include <zephyr/linker/common-rom/common-rom-logging.ld>
|
||||
#pragma pop_macro("GROUP_ROM_LINK_IN")
|
||||
|
||||
.dummy.dram.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
#include <snippets-rwdata.ld>
|
||||
. = ALIGN(4);
|
||||
_end = ABSOLUTE(.);
|
||||
__data_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
|
||||
|
||||
.iram0.text_end (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_iram_end = ABSOLUTE(.);
|
||||
} GROUP_LINK_IN(IRAM_REGION)
|
||||
|
||||
_image_irom_start = LOADADDR(.flash.text);
|
||||
_image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start;
|
||||
_image_irom_vaddr = ADDR(.flash.text);
|
||||
|
||||
.flash_text_dummy (NOLOAD): ALIGN(IROM_SEG_ALIGN)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
. = SIZEOF(_RODATA_SECTION_NAME);
|
||||
} GROUP_LINK_IN(FLASH_CODE_REGION)
|
||||
|
||||
.flash.text : ALIGN(IROM_SEG_ALIGN)
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_stext = .;
|
||||
_text_start = ABSOLUTE(.);
|
||||
|
||||
#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)
|
||||
*libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*)
|
||||
*libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*)
|
||||
#endif
|
||||
|
||||
. = ALIGN(8);
|
||||
#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)
|
||||
*libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
|
||||
*libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
|
||||
#endif
|
||||
|
||||
. = ALIGN(8);
|
||||
*(.literal .text .literal.* .text.*)
|
||||
. = ALIGN(8);
|
||||
_text_end = ABSOLUTE(.);
|
||||
_etext = .;
|
||||
|
||||
/* Similar to _iram_start, this symbol goes here so it is
|
||||
resolved by addr2line in preference to the first symbol in
|
||||
the flash.text segment.
|
||||
*/
|
||||
_flash_cache_start = ABSOLUTE(0);
|
||||
} GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION)
|
||||
|
||||
/* RTC fast memory holds RTC wake stub code,
|
||||
including from any source file named rtc_wake_stub*.c
|
||||
*/
|
||||
.rtc.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rtc.literal .rtc.text)
|
||||
*rtc_wake_stub*.o(.literal .text .literal.* .text.*)
|
||||
} GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION)
|
||||
|
||||
/* RTC slow memory holds RTC wake stub
|
||||
data/rodata, including from any source file
|
||||
named rtc_wake_stub*.c
|
||||
*/
|
||||
.rtc.data :
|
||||
{
|
||||
_rtc_data_start = ABSOLUTE(.);
|
||||
*(.rtc.data)
|
||||
*(.rtc.rodata)
|
||||
*rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)
|
||||
_rtc_data_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION)
|
||||
|
||||
/* RTC bss, from any source file named rtc_wake_stub*.c */
|
||||
.rtc.bss (NOLOAD) :
|
||||
{
|
||||
_rtc_bss_start = ABSOLUTE(.);
|
||||
*rtc_wake_stub*.o(.bss .bss.*)
|
||||
*rtc_wake_stub*.o(COMMON)
|
||||
_rtc_bss_end = ABSOLUTE(.);
|
||||
} GROUP_LINK_IN(rtc_slow_seg)
|
||||
|
||||
/* This section located in RTC SLOW Memory area.
|
||||
It holds data marked with RTC_SLOW_ATTR attribute.
|
||||
See the file "esp_attr.h" for more information.
|
||||
*/
|
||||
.rtc.force_slow :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_rtc_force_slow_start = ABSOLUTE(.);
|
||||
*(.rtc.force_slow .rtc.force_slow.*)
|
||||
. = ALIGN(4) ;
|
||||
_rtc_force_slow_end = ABSOLUTE(.);
|
||||
} > rtc_slow_seg
|
||||
|
||||
/* Get size of rtc slow data */
|
||||
_rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start);
|
||||
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
#include <zephyr/linker/intlist.ld>
|
||||
#endif
|
||||
|
||||
#include <zephyr/linker/debug-sections.ld>
|
||||
|
||||
.xtensa.info 0 : { *(.xtensa.info) }
|
||||
.xt.insn 0 :
|
||||
{
|
||||
KEEP (*(.xt.insn))
|
||||
KEEP (*(.gnu.linkonce.x.*))
|
||||
}
|
||||
.xt.prop 0 :
|
||||
{
|
||||
KEEP (*(.xt.prop))
|
||||
KEEP (*(.xt.prop.*))
|
||||
KEEP (*(.gnu.linkonce.prop.*))
|
||||
}
|
||||
.xt.lit 0 :
|
||||
{
|
||||
KEEP (*(.xt.lit))
|
||||
KEEP (*(.xt.lit.*))
|
||||
KEEP (*(.gnu.linkonce.p.*))
|
||||
}
|
||||
.xt.profile_range 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_range))
|
||||
KEEP (*(.gnu.linkonce.profile_range.*))
|
||||
}
|
||||
.xt.profile_ranges 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_ranges))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
|
||||
}
|
||||
.xt.profile_files 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_files))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_files.*))
|
||||
}
|
||||
}
|
||||
|
||||
ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),
|
||||
"DRAM0 segment data does not fit.")
|
||||
|
||||
ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
|
||||
"IRAM0 segment data does not fit.")
|
||||
|
||||
#if defined(CONFIG_ESP_SPIRAM)
|
||||
ASSERT(((_ext_ram_data_end - _ext_ram_data_start) <= CONFIG_ESP_SPIRAM_SIZE),
|
||||
"External SPIRAM overflowed.")
|
||||
#endif /* CONFIG_ESP_SPIRAM */
|
||||
99
soc/espressif/esp32s2/loader.c
Normal file
99
soc/espressif/esp32s2/loader.c
Normal file
|
|
@ -0,0 +1,99 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/kernel.h>
|
||||
#include <soc.h>
|
||||
#include <zephyr/storage/flash_map.h>
|
||||
#include <esp_log.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#include <esp32s2/rom/cache.h>
|
||||
#include "soc/cache_memory.h"
|
||||
#include "soc/extmem_reg.h"
|
||||
#include <bootloader_flash_priv.h>
|
||||
|
||||
#ifdef CONFIG_BOOTLOADER_MCUBOOT
|
||||
|
||||
#define BOOT_LOG_INF(_fmt, ...) \
|
||||
ets_printf("[" CONFIG_SOC_SERIES "] [INF] " _fmt "\n\r", ##__VA_ARGS__)
|
||||
|
||||
#define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used))
|
||||
|
||||
extern uint32_t _image_irom_start, _image_irom_size, _image_irom_vaddr;
|
||||
extern uint32_t _image_drom_start, _image_drom_size, _image_drom_vaddr;
|
||||
|
||||
void __start(void);
|
||||
|
||||
static HDR_ATTR void (*_entry_point)(void) = &__start;
|
||||
|
||||
static int map_rom_segments(void)
|
||||
{
|
||||
int rc = 0;
|
||||
|
||||
size_t _partition_offset = FIXED_PARTITION_OFFSET(slot0_partition);
|
||||
uint32_t _app_irom_start = _partition_offset + (uint32_t)&_image_irom_start;
|
||||
uint32_t _app_irom_size = (uint32_t)&_image_irom_size;
|
||||
uint32_t _app_irom_vaddr = (uint32_t)&_image_irom_vaddr;
|
||||
|
||||
uint32_t _app_drom_start = _partition_offset + (uint32_t)&_image_drom_start;
|
||||
uint32_t _app_drom_size = (uint32_t)&_image_drom_size;
|
||||
uint32_t _app_drom_vaddr = (uint32_t)&_image_drom_vaddr;
|
||||
|
||||
uint32_t autoload = esp_rom_Cache_Suspend_ICache();
|
||||
|
||||
esp_rom_Cache_Invalidate_ICache_All();
|
||||
|
||||
/* Clear the MMU entries that are already set up,
|
||||
* so the new app only has the mappings it creates.
|
||||
*/
|
||||
for (size_t i = 0; i < FLASH_MMU_TABLE_SIZE; i++) {
|
||||
FLASH_MMU_TABLE[i] = MMU_TABLE_INVALID_VAL;
|
||||
}
|
||||
|
||||
uint32_t drom_page_count = bootloader_cache_pages_to_map(_app_drom_size, _app_drom_vaddr);
|
||||
|
||||
rc |= esp_rom_Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, _app_drom_vaddr & 0xffff0000,
|
||||
_app_drom_start & 0xffff0000, 64, drom_page_count, 0);
|
||||
|
||||
uint32_t irom_page_count = bootloader_cache_pages_to_map(_app_irom_size, _app_irom_vaddr);
|
||||
|
||||
if (_app_irom_vaddr + _app_irom_size > IRAM1_ADDRESS_LOW) {
|
||||
rc |= esp_rom_Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, IRAM0_ADDRESS_LOW, 0, 64, 64, 1);
|
||||
rc |= esp_rom_Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, IRAM1_ADDRESS_LOW, 0, 64, 64, 1);
|
||||
REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_IRAM1);
|
||||
}
|
||||
|
||||
rc |= esp_rom_Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, _app_irom_vaddr & 0xffff0000,
|
||||
_app_irom_start & 0xffff0000, 64, irom_page_count, 0);
|
||||
|
||||
REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, (EXTMEM_PRO_ICACHE_MASK_IRAM0) |
|
||||
(EXTMEM_PRO_ICACHE_MASK_IRAM1 & 0) | EXTMEM_PRO_ICACHE_MASK_DROM0);
|
||||
|
||||
esp_rom_Cache_Resume_ICache(autoload);
|
||||
|
||||
/* Show map segments continue using same log format as during MCUboot phase */
|
||||
BOOT_LOG_INF("DROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map",
|
||||
_app_drom_start, _app_drom_vaddr, _app_drom_size, _app_drom_size);
|
||||
BOOT_LOG_INF("IROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map\r\n",
|
||||
_app_irom_start, _app_irom_vaddr, _app_irom_size, _app_irom_size);
|
||||
esp_rom_uart_tx_wait_idle(0);
|
||||
|
||||
return rc;
|
||||
}
|
||||
#endif
|
||||
|
||||
void __start(void)
|
||||
{
|
||||
#ifdef CONFIG_BOOTLOADER_MCUBOOT
|
||||
int err = map_rom_segments();
|
||||
|
||||
if (err != 0) {
|
||||
ets_printf("Failed to setup XIP, aborting\n");
|
||||
abort();
|
||||
}
|
||||
#endif
|
||||
__esp_platform_start();
|
||||
}
|
||||
365
soc/espressif/esp32s2/mcuboot.ld
Normal file
365
soc/espressif/esp32s2/mcuboot.ld
Normal file
|
|
@ -0,0 +1,365 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Linker command/script file
|
||||
*
|
||||
* Linker script for the MCUboot on Xtensa platform.
|
||||
*/
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/linker/sections.h>
|
||||
#include <zephyr/linker/linker-defs.h>
|
||||
#include <zephyr/linker/linker-tool.h>
|
||||
|
||||
#ifdef CONFIG_XIP
|
||||
#error "Xtensa bootloader cannot use XIP"
|
||||
#endif /* CONFIG_XIP */
|
||||
|
||||
/* Disable all romable LMA */
|
||||
#udef GROUP_DATA_LINK_IN
|
||||
#define GROUP_DATA_LINK_IN(vregion, lregion) > vregion
|
||||
|
||||
#define RAMABLE_REGION dram_seg
|
||||
#define RAMABLE_REGION_1 dram_seg
|
||||
|
||||
#define RODATA_REGION dram_seg
|
||||
#define ROMABLE_REGION dram_seg
|
||||
|
||||
#define IRAM_REGION iram_seg
|
||||
#define FLASH_CODE_REGION iram_seg
|
||||
|
||||
#define IROM_SEG_ALIGN 16
|
||||
|
||||
MEMORY
|
||||
{
|
||||
iram_seg (RWX) : org = 0x40040000, len = 0x6000
|
||||
iram_loader_seg (RWX) : org = 0x40046000, len = 0x2000
|
||||
dram_seg (RW) : org = 0x3FFE6000, len = 0x6000
|
||||
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
ENTRY(CONFIG_KERNEL_ENTRY)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* NOTE: .rodata section should be the first section in the linker script and no
|
||||
* other section should appear before .rodata section. This is the requirement
|
||||
* to align ROM section to 64K page offset.
|
||||
* Adding .rodata as first section helps to reduce size of generated binary by
|
||||
* few kBs.
|
||||
*/
|
||||
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
|
||||
{
|
||||
__rodata_region_start = ABSOLUTE(.);
|
||||
|
||||
. = ALIGN(4);
|
||||
#include <snippets-rodata.ld>
|
||||
|
||||
. = ALIGN(4);
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
|
||||
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
|
||||
*(.xt_except_table)
|
||||
*(.gcc_except_table .gcc_except_table.*)
|
||||
*(.gnu.linkonce.e.*)
|
||||
*(.gnu.version_r)
|
||||
. = (. + 3) & ~ 3;
|
||||
__eh_frame = ABSOLUTE(.);
|
||||
KEEP(*(.eh_frame))
|
||||
. = (. + 7) & ~ 3;
|
||||
|
||||
/* C++ exception handlers table: */
|
||||
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
|
||||
*(.xt_except_desc)
|
||||
*(.gnu.linkonce.h.*)
|
||||
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc_end)
|
||||
*(.dynamic)
|
||||
*(.gnu.version_d)
|
||||
. = ALIGN(4);
|
||||
__rodata_region_end = ABSOLUTE(.);
|
||||
/* Literals are also RO data. */
|
||||
_lit4_start = ABSOLUTE(.);
|
||||
*(*.lit4)
|
||||
*(.lit4.*)
|
||||
*(.gnu.linkonce.lit4.*)
|
||||
_lit4_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
_thread_local_start = ABSOLUTE(.);
|
||||
*(.tdata)
|
||||
*(.tdata.*)
|
||||
*(.tbss)
|
||||
*(.tbss.*)
|
||||
*(.rodata_wlog)
|
||||
*(.rodata_wlog*)
|
||||
_thread_local_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
} GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)
|
||||
|
||||
#include <zephyr/linker/common-rom/common-rom-cpp.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-kernel-devices.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-ztest.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-net.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-bt.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-debug.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-misc.ld>
|
||||
#include <snippets-sections.ld>
|
||||
|
||||
.dram0.data :
|
||||
{
|
||||
__data_start = ABSOLUTE(.);
|
||||
|
||||
_btdm_data_start = ABSOLUTE(.);
|
||||
*libbtdm_app.a:(.data .data.*)
|
||||
. = ALIGN (4);
|
||||
_btdm_data_end = ABSOLUTE(.);
|
||||
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
|
||||
KEEP(*(.jcr))
|
||||
*(.dram1 .dram1.*)
|
||||
. = ALIGN(4);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
|
||||
|
||||
#include <zephyr/linker/cplusplus-rom.ld>
|
||||
#include <snippets-data-sections.ld>
|
||||
#include <zephyr/linker/common-ram.ld>
|
||||
#include <snippets-ram-sections.ld>
|
||||
#include <zephyr/linker/cplusplus-ram.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-logging.ld>
|
||||
|
||||
.dram0.end :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
#include <snippets-rwdata.ld>
|
||||
. = ALIGN(4);
|
||||
_end = ABSOLUTE(.);
|
||||
__data_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
|
||||
|
||||
/* Send .iram0 code to iram */
|
||||
.iram0.vectors : ALIGN(4)
|
||||
{
|
||||
/* Vectors go to IRAM */
|
||||
_init_start = ABSOLUTE(.);
|
||||
/* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
|
||||
. = 0x0;
|
||||
KEEP(*(.WindowVectors.text));
|
||||
. = 0x180;
|
||||
KEEP(*(.Level2InterruptVector.text));
|
||||
. = 0x1c0;
|
||||
KEEP(*(.Level3InterruptVector.text));
|
||||
. = 0x200;
|
||||
KEEP(*(.Level4InterruptVector.text));
|
||||
. = 0x240;
|
||||
KEEP(*(.Level5InterruptVector.text));
|
||||
. = 0x280;
|
||||
KEEP(*(.DebugExceptionVector.text));
|
||||
. = 0x2c0;
|
||||
KEEP(*(.NMIExceptionVector.text));
|
||||
. = 0x300;
|
||||
KEEP(*(.KernelExceptionVector.text));
|
||||
. = 0x340;
|
||||
KEEP(*(.UserExceptionVector.text));
|
||||
. = 0x3C0;
|
||||
KEEP(*(.DoubleExceptionVector.text));
|
||||
. = 0x400;
|
||||
*(.*Vector.literal)
|
||||
|
||||
*(.UserEnter.literal);
|
||||
*(.UserEnter.text);
|
||||
. = ALIGN (16);
|
||||
*(.entry.text)
|
||||
*(.init.literal)
|
||||
*(.init)
|
||||
_init_end = ABSOLUTE(.);
|
||||
|
||||
/* This goes here, not at top of linker script, so addr2line finds it last,
|
||||
and uses it in preference to the first symbol in IRAM */
|
||||
_iram_start = ABSOLUTE(0);
|
||||
} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
|
||||
|
||||
.iram_loader.text :
|
||||
{
|
||||
. = ALIGN (16);
|
||||
_loader_text_start = ABSOLUTE(.);
|
||||
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||||
*(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
|
||||
*libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_flash_config_esp32s2.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_init_common.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_random.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
|
||||
*libzephyr.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
|
||||
*libzephyr.a:bootloader_efuse_esp32s2.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_utility.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_sha.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_console.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_panic.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_soc.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:esp_image_format.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:flash_encrypt.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:flash_partitions.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:secure_boot.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:esp_efuse_table.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:esp_efuse_fields.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:esp_efuse_api.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:esp_efuse_utility.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:esp_efuse_api_key_esp32xx.*(.literal .text .literal.* .text.*)
|
||||
*esp_mcuboot.*(.literal .text .literal.* .text.*)
|
||||
*esp_loader.*(.literal .text .literal.* .text.*)
|
||||
*(.fini.literal)
|
||||
*(.fini)
|
||||
*(.gnu.version)
|
||||
_loader_text_end = ABSOLUTE(.);
|
||||
} > iram_loader_seg
|
||||
|
||||
SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))
|
||||
{
|
||||
/* Code marked as running out of IRAM */
|
||||
_iram_text_start = ABSOLUTE(.);
|
||||
|
||||
*(.iram1 .iram1.*)
|
||||
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
|
||||
|
||||
. = ALIGN(4);
|
||||
_iram_text_end = ABSOLUTE(.);
|
||||
_iram_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
|
||||
|
||||
/* Shared RAM */
|
||||
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_bss_start = ABSOLUTE(.); /* required by bluetooth library */
|
||||
__bss_start = ABSOLUTE(.);
|
||||
|
||||
_btdm_bss_start = ABSOLUTE(.);
|
||||
*libbtdm_app.a:(.bss .bss.* COMMON)
|
||||
. = ALIGN (4);
|
||||
_btdm_bss_end = ABSOLUTE(.);
|
||||
|
||||
/* Buffer for system heap should be placed in dram_seg */
|
||||
*libkernel.a:mempool.*(.noinit.kheap_buf__system_heap .noinit.*.kheap_buf__system_heap)
|
||||
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.share.mem)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN (8);
|
||||
__bss_end = ABSOLUTE(.);
|
||||
_bss_end = ABSOLUTE(.);
|
||||
_end = ABSOLUTE(.);
|
||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
||||
|
||||
ASSERT(((__bss_end - ORIGIN(RAMABLE_REGION)) <= LENGTH(RAMABLE_REGION)),
|
||||
"DRAM segment data does not fit.")
|
||||
|
||||
SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
*(.noinit)
|
||||
*(.noinit.*)
|
||||
. = ALIGN (8);
|
||||
} GROUP_LINK_IN(RAMABLE_REGION_1)
|
||||
|
||||
.flash.text : ALIGN(IROM_SEG_ALIGN)
|
||||
{
|
||||
_stext = .;
|
||||
_text_start = ABSOLUTE(.);
|
||||
|
||||
*(.literal .text .literal.* .text.*)
|
||||
. = ALIGN(4);
|
||||
_text_end = ABSOLUTE(.);
|
||||
_etext = .;
|
||||
|
||||
/* Similar to _iram_start, this symbol goes here so it is
|
||||
* resolved by addr2line in preference to the first symbol in
|
||||
* the flash.text segment.
|
||||
*/
|
||||
_flash_cache_start = ABSOLUTE(0);
|
||||
} GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION)
|
||||
|
||||
#include <zephyr/linker/debug-sections.ld>
|
||||
|
||||
.xtensa.info 0 : { *(.xtensa.info) }
|
||||
.xt.insn 0 :
|
||||
{
|
||||
KEEP (*(.xt.insn))
|
||||
KEEP (*(.gnu.linkonce.x.*))
|
||||
}
|
||||
.xt.prop 0 :
|
||||
{
|
||||
KEEP (*(.xt.prop))
|
||||
KEEP (*(.xt.prop.*))
|
||||
KEEP (*(.gnu.linkonce.prop.*))
|
||||
}
|
||||
.xt.lit 0 :
|
||||
{
|
||||
KEEP (*(.xt.lit))
|
||||
KEEP (*(.xt.lit.*))
|
||||
KEEP (*(.gnu.linkonce.p.*))
|
||||
}
|
||||
.xt.profile_range 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_range))
|
||||
KEEP (*(.gnu.linkonce.profile_range.*))
|
||||
}
|
||||
.xt.profile_ranges 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_ranges))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
|
||||
}
|
||||
.xt.profile_files 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_files))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_files.*))
|
||||
}
|
||||
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
#include <zephyr/linker/intlist.ld>
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
ASSERT(((_iram_end - ORIGIN(IRAM_REGION)) <= LENGTH(IRAM_REGION)),
|
||||
"IRAM0 segment data does not fit.")
|
||||
22
soc/espressif/esp32s2/newlib_fix.c
Normal file
22
soc/espressif/esp32s2/newlib_fix.c
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* Copyright (c) 2019, Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/toolchain.h>
|
||||
#include <stdio.h>
|
||||
#include <stddef.h>
|
||||
#include <unistd.h>
|
||||
#include <sys/stat.h>
|
||||
|
||||
#include <reent.h>
|
||||
|
||||
int __weak _gettimeofday_r(struct _reent *r, struct timeval *__tp, void *__tzp)
|
||||
{
|
||||
ARG_UNUSED(r);
|
||||
ARG_UNUSED(__tp);
|
||||
ARG_UNUSED(__tzp);
|
||||
|
||||
return -1;
|
||||
}
|
||||
78
soc/espressif/esp32s2/pinctrl_soc.h
Normal file
78
soc/espressif/esp32s2/pinctrl_soc.h
Normal file
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* ESP32S2 SoC specific helpers for pinctrl driver
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_XTENSA_ESP32S2_PINCTRL_SOC_H_
|
||||
#define ZEPHYR_SOC_XTENSA_ESP32S2_PINCTRL_SOC_H_
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/types.h>
|
||||
|
||||
#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
|
||||
|
||||
/** @cond INTERNAL_HIDDEN */
|
||||
|
||||
/** Type for ESP32 pin. */
|
||||
typedef struct pinctrl_soc_pin {
|
||||
/** Pinmux settings (pin, direction and signal). */
|
||||
uint32_t pinmux;
|
||||
/** Pincfg settings (bias). */
|
||||
uint32_t pincfg;
|
||||
} pinctrl_soc_pin_t;
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize pinmux field in #pinctrl_pin_t.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
*/
|
||||
#define Z_PINCTRL_ESP32_PINMUX_INIT(node_id, prop, idx) DT_PROP_BY_IDX(node_id, prop, idx)
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
*/
|
||||
#define Z_PINCTRL_ESP32_PINCFG_INIT(node_id) \
|
||||
(((ESP32_NO_PULL * DT_PROP(node_id, bias_disable)) << ESP32_PIN_BIAS_SHIFT) | \
|
||||
((ESP32_PULL_UP * DT_PROP(node_id, bias_pull_up)) << ESP32_PIN_BIAS_SHIFT) | \
|
||||
((ESP32_PULL_DOWN * DT_PROP(node_id, bias_pull_down)) << ESP32_PIN_BIAS_SHIFT) | \
|
||||
((ESP32_PUSH_PULL * DT_PROP(node_id, drive_push_pull)) << ESP32_PIN_DRV_SHIFT) | \
|
||||
((ESP32_OPEN_DRAIN * DT_PROP(node_id, drive_open_drain)) << ESP32_PIN_DRV_SHIFT) | \
|
||||
((ESP32_PIN_OUT_HIGH * DT_PROP(node_id, output_high)) << ESP32_PIN_OUT_SHIFT) | \
|
||||
((ESP32_PIN_OUT_LOW * DT_PROP(node_id, output_low)) << ESP32_PIN_OUT_SHIFT) | \
|
||||
((ESP32_PIN_OUT_EN * DT_PROP(node_id, output_enable)) << ESP32_PIN_EN_DIR_SHIFT) | \
|
||||
((ESP32_PIN_IN_EN * DT_PROP(node_id, input_enable)) << ESP32_PIN_EN_DIR_SHIFT))
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize each pin.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param prop Property name.
|
||||
* @param idx Property entry index.
|
||||
*/
|
||||
#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
|
||||
{.pinmux = Z_PINCTRL_ESP32_PINMUX_INIT(node_id, prop, idx), \
|
||||
.pincfg = Z_PINCTRL_ESP32_PINCFG_INIT(node_id)},
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize state pins contained in a given property.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param prop Property name describing state pins.
|
||||
*/
|
||||
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||
{ \
|
||||
DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \
|
||||
Z_PINCTRL_STATE_PIN_INIT) \
|
||||
}
|
||||
|
||||
/** @endcond */
|
||||
|
||||
#endif /* ZEPHYR_SOC_XTENSA_ESP32S2_PINCTRL_SOC_H_ */
|
||||
46
soc/espressif/esp32s2/power.c
Normal file
46
soc/espressif/esp32s2/power.c
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/kernel.h>
|
||||
#include <zephyr/pm/pm.h>
|
||||
#include <esp_sleep.h>
|
||||
|
||||
#include <zephyr/logging/log.h>
|
||||
LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
|
||||
|
||||
static uint32_t intenable;
|
||||
|
||||
/* Invoke Low Power/System Off specific Tasks */
|
||||
void pm_state_set(enum pm_state state, uint8_t substate_id)
|
||||
{
|
||||
ARG_UNUSED(substate_id);
|
||||
|
||||
switch (state) {
|
||||
case PM_STATE_STANDBY:
|
||||
intenable = XTENSA_RSR("INTENABLE");
|
||||
__asm__ volatile ("waiti 0");
|
||||
break;
|
||||
default:
|
||||
LOG_DBG("Unsupported power state %u", state);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Handle SOC specific activity after Low Power Mode Exit */
|
||||
void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
|
||||
{
|
||||
ARG_UNUSED(substate_id);
|
||||
|
||||
switch (state) {
|
||||
case PM_STATE_STANDBY:
|
||||
z_xt_ints_on(intenable);
|
||||
esp_light_sleep_start();
|
||||
break;
|
||||
default:
|
||||
LOG_DBG("Unsupported power state %u", state);
|
||||
break;
|
||||
}
|
||||
}
|
||||
15
soc/espressif/esp32s2/poweroff.c
Normal file
15
soc/espressif/esp32s2/poweroff.c
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/sys/poweroff.h>
|
||||
|
||||
#include <esp_sleep.h>
|
||||
|
||||
void z_sys_poweroff(void)
|
||||
{
|
||||
/* Forces RTC domain to be always on */
|
||||
esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
|
||||
esp_deep_sleep_start();
|
||||
}
|
||||
228
soc/espressif/esp32s2/soc.c
Normal file
228
soc/espressif/esp32s2/soc.c
Normal file
|
|
@ -0,0 +1,228 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* Include esp-idf headers first to avoid redefining BIT() macro */
|
||||
#include "soc.h"
|
||||
#include <soc/rtc_cntl_reg.h>
|
||||
#include <soc/timer_group_reg.h>
|
||||
#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
|
||||
#include <xtensa/config/core-isa.h>
|
||||
#include <xtensa/corebits.h>
|
||||
|
||||
#include <zephyr/kernel_structs.h>
|
||||
#include <kernel_internal.h>
|
||||
#include <string.h>
|
||||
#include <zephyr/toolchain.h>
|
||||
#include <zephyr/types.h>
|
||||
|
||||
#include "esp_private/system_internal.h"
|
||||
#include "esp32s2/rom/cache.h"
|
||||
#include "soc/gpio_periph.h"
|
||||
#include "esp_spi_flash.h"
|
||||
#include "esp_cpu.h"
|
||||
#include "hal/cpu_ll.h"
|
||||
#include "hal/soc_ll.h"
|
||||
#include "hal/wdt_hal.h"
|
||||
#include "esp_timer.h"
|
||||
#include "esp_err.h"
|
||||
#include "esp32s2/spiram.h"
|
||||
#include "esp_clk_internal.h"
|
||||
#include <zephyr/sys/printk.h>
|
||||
|
||||
#ifdef CONFIG_MCUBOOT
|
||||
#include "bootloader_init.h"
|
||||
#endif /* CONFIG_MCUBOOT */
|
||||
|
||||
extern void rtc_clk_cpu_freq_set_xtal(void);
|
||||
extern void esp_reset_reason_init(void);
|
||||
|
||||
#if CONFIG_ESP_SPIRAM
|
||||
extern int _ext_ram_bss_start;
|
||||
extern int _ext_ram_bss_end;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This is written in C rather than assembly since, during the port bring up,
|
||||
* Zephyr is being booted by the Espressif bootloader. With it, the C stack
|
||||
* is already set up.
|
||||
*/
|
||||
void __attribute__((section(".iram1"))) __esp_platform_start(void)
|
||||
{
|
||||
extern uint32_t _init_start;
|
||||
|
||||
/* Move the exception vector table to IRAM. */
|
||||
__asm__ __volatile__ (
|
||||
"wsr %0, vecbase"
|
||||
:
|
||||
: "r"(&_init_start));
|
||||
|
||||
/* Zero out BSS */
|
||||
z_bss_zero();
|
||||
|
||||
/*
|
||||
* Configure the mode of instruction cache :
|
||||
* cache size, cache associated ways, cache line size.
|
||||
*/
|
||||
esp_config_instruction_cache_mode();
|
||||
|
||||
/*
|
||||
* If we need use SPIRAM, we should use data cache, or if we want to
|
||||
* access rodata, we also should use data cache.
|
||||
* Configure the mode of data : cache size, cache associated ways, cache
|
||||
* line size.
|
||||
* Enable data cache, so if we don't use SPIRAM, it just works.
|
||||
*/
|
||||
#if CONFIG_ESP_SPIRAM
|
||||
esp_config_data_cache_mode();
|
||||
esp_rom_Cache_Enable_DCache(0);
|
||||
#endif
|
||||
|
||||
/* Disable normal interrupts. */
|
||||
__asm__ __volatile__ (
|
||||
"wsr %0, PS"
|
||||
:
|
||||
: "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE));
|
||||
|
||||
/* Initialize the architecture CPU pointer. Some of the
|
||||
* initialization code wants a valid _current before
|
||||
* arch_kernel_init() is invoked.
|
||||
*/
|
||||
__asm__ volatile("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0]));
|
||||
|
||||
esp_reset_reason_init();
|
||||
|
||||
#ifdef CONFIG_MCUBOOT
|
||||
/* MCUboot early initialisation. */
|
||||
if (bootloader_init()) {
|
||||
abort();
|
||||
}
|
||||
#else
|
||||
/* ESP-IDF 2nd stage bootloader enables RTC WDT to check on startup sequence
|
||||
* related issues in application. Hence disable that as we are about to start
|
||||
* Zephyr environment.
|
||||
*/
|
||||
wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
|
||||
|
||||
wdt_hal_write_protect_disable(&rtc_wdt_ctx);
|
||||
wdt_hal_disable(&rtc_wdt_ctx);
|
||||
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
|
||||
|
||||
/* Configures the CPU clock, RTC slow and fast clocks, and performs
|
||||
* RTC slow clock calibration.
|
||||
*/
|
||||
esp_clk_init();
|
||||
|
||||
esp_timer_early_init();
|
||||
|
||||
#if CONFIG_ESP_SPIRAM
|
||||
|
||||
memset(&_ext_ram_bss_start,
|
||||
0,
|
||||
(&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start));
|
||||
|
||||
esp_err_t err = esp_spiram_init();
|
||||
|
||||
if (err != ESP_OK) {
|
||||
printk("Failed to Initialize SPIRAM, aborting.\n");
|
||||
abort();
|
||||
}
|
||||
esp_spiram_init_cache();
|
||||
if (esp_spiram_get_size() < CONFIG_ESP_SPIRAM_SIZE) {
|
||||
printk("SPIRAM size is less than configured size, aborting.\n");
|
||||
abort();
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ESP_SPIRAM */
|
||||
|
||||
/* Scheduler is not started at this point. Hence, guard functions
|
||||
* must be initialized after esp_spiram_init_cache which internally
|
||||
* uses guard functions. Setting guard functions before SPIRAM
|
||||
* cache initialization will result in a crash.
|
||||
*/
|
||||
#if CONFIG_SOC_FLASH_ESP32 || CONFIG_ESP_SPIRAM
|
||||
spi_flash_guard_set(&g_flash_guard_default_ops);
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_MCUBOOT */
|
||||
|
||||
esp_intr_initialize();
|
||||
/* Start Zephyr */
|
||||
z_cstart();
|
||||
|
||||
CODE_UNREACHABLE;
|
||||
}
|
||||
|
||||
/* Boot-time static default printk handler, possibly to be overridden later. */
|
||||
int IRAM_ATTR arch_printk_char_out(int c)
|
||||
{
|
||||
if (c == '\n') {
|
||||
esp_rom_uart_tx_one_char('\r');
|
||||
}
|
||||
esp_rom_uart_tx_one_char(c);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void sys_arch_reboot(int type)
|
||||
{
|
||||
esp_restart_noos();
|
||||
}
|
||||
|
||||
void IRAM_ATTR esp_restart_noos(void)
|
||||
{
|
||||
/* Disable interrupts */
|
||||
z_xt_ints_off(0xFFFFFFFF);
|
||||
|
||||
/*
|
||||
* Reset and stall the other CPU.
|
||||
* CPU must be reset before stalling, in case it was running a s32c1i
|
||||
* instruction. This would cause memory pool to be locked by arbiter
|
||||
* to the stalled CPU, preventing current CPU from accessing this pool.
|
||||
*/
|
||||
const uint32_t core_id = cpu_ll_get_core_id();
|
||||
|
||||
/* Flush any data left in UART FIFOs */
|
||||
esp_rom_uart_tx_wait_idle(0);
|
||||
esp_rom_uart_tx_wait_idle(1);
|
||||
/* Disable cache */
|
||||
esp_rom_Cache_Disable_ICache();
|
||||
esp_rom_Cache_Disable_DCache();
|
||||
|
||||
/*
|
||||
* 2nd stage bootloader reconfigures SPI flash signals.
|
||||
* Reset them to the defaults expected by ROM
|
||||
*/
|
||||
WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
|
||||
|
||||
/* Reset wifi/ethernet/sdio (bb/mac) */
|
||||
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,
|
||||
DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST | DPORT_BT_RST |
|
||||
DPORT_BTMAC_RST | DPORT_SDIO_RST | DPORT_SDIO_RST |
|
||||
DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST |
|
||||
DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST);
|
||||
DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0);
|
||||
|
||||
/* Reset timer/spi/uart */
|
||||
DPORT_SET_PERI_REG_MASK(
|
||||
DPORT_PERIP_RST_EN_REG,
|
||||
DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST |
|
||||
DPORT_SPI3_RST | DPORT_SPI2_DMA_RST | DPORT_SPI3_DMA_RST |
|
||||
DPORT_UART_RST);
|
||||
DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
|
||||
|
||||
/* Reset CPUs */
|
||||
if (core_id == 0) {
|
||||
soc_ll_reset_core(0);
|
||||
}
|
||||
|
||||
while (true) {
|
||||
;
|
||||
}
|
||||
}
|
||||
79
soc/espressif/esp32s2/soc.h
Normal file
79
soc/espressif/esp32s2/soc.h
Normal file
|
|
@ -0,0 +1,79 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __SOC_H__
|
||||
#define __SOC_H__
|
||||
#include <soc/syscon_reg.h>
|
||||
#include <soc/system_reg.h>
|
||||
#include <soc/dport_access.h>
|
||||
#include <soc/rtc_cntl_reg.h>
|
||||
#include <soc/soc_caps.h>
|
||||
#include <esp32s2/rom/ets_sys.h>
|
||||
#include <esp32s2/rom/spi_flash.h>
|
||||
#include <esp32s2/rom/cache.h>
|
||||
#include <esp32s2/clk.h>
|
||||
#include <esp_rom_sys.h>
|
||||
|
||||
#include <zephyr/types.h>
|
||||
#include <stdbool.h>
|
||||
#include <zephyr/arch/xtensa/arch.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
void __esp_platform_start(void);
|
||||
|
||||
static inline uint32_t esp_core_id(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
extern void esp_rom_uart_attach(void);
|
||||
extern void esp_rom_uart_tx_wait_idle(uint8_t uart_no);
|
||||
extern int esp_rom_uart_tx_one_char(uint8_t chr);
|
||||
extern int esp_rom_uart_rx_one_char(uint8_t *chr);
|
||||
|
||||
extern int esp_rom_gpio_matrix_in(uint32_t gpio, uint32_t signal_index, bool inverted);
|
||||
extern int esp_rom_gpio_matrix_out(uint32_t gpio, uint32_t signal_index,
|
||||
bool out_invrted, bool out_enabled_inverted);
|
||||
|
||||
/* cache related rom functions */
|
||||
extern uint32_t esp_rom_Cache_Disable_ICache(void);
|
||||
extern uint32_t esp_rom_Cache_Disable_DCache(void);
|
||||
|
||||
extern void esp_rom_Cache_Allocate_SRAM(cache_layout_t sram0_layout, cache_layout_t sram1_layout,
|
||||
cache_layout_t sram2_layout, cache_layout_t sram3_layout);
|
||||
|
||||
extern uint32_t esp_rom_Cache_Suspend_ICache(void);
|
||||
|
||||
extern void esp_rom_Cache_Set_ICache_Mode(cache_size_t cache_size, cache_ways_t ways,
|
||||
cache_line_size_t cache_line_size);
|
||||
|
||||
extern void esp_rom_Cache_Invalidate_ICache_All(void);
|
||||
extern void esp_rom_Cache_Resume_ICache(uint32_t autoload);
|
||||
extern int esp_rom_Cache_Invalidate_Addr(uint32_t addr, uint32_t size);
|
||||
|
||||
/* data-cache related rom functions */
|
||||
extern void esp_rom_Cache_Set_DCache_Mode(cache_size_t cache_size, cache_ways_t ways,
|
||||
cache_line_size_t cache_line_size);
|
||||
|
||||
extern void esp_rom_Cache_Invalidate_DCache_All(void);
|
||||
extern void esp_rom_Cache_Enable_DCache(uint32_t autoload);
|
||||
|
||||
extern void esp_rom_Cache_Set_DCache_Mode(cache_size_t cache_size, cache_ways_t ways,
|
||||
cache_line_size_t cache_line_size);
|
||||
|
||||
extern int esp_rom_Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr,
|
||||
uint32_t psize, uint32_t num, uint32_t fixed);
|
||||
|
||||
/* ROM information related to SPI Flash chip timing and device */
|
||||
extern esp_rom_spiflash_chip_t g_rom_flashchip;
|
||||
extern uint8_t g_rom_spiflash_dummy_len_plus[];
|
||||
|
||||
extern uint32_t esp_rom_g_ticks_per_us_pro;
|
||||
|
||||
/* cache initialization functions */
|
||||
void esp_config_instruction_cache_mode(void);
|
||||
void esp_config_data_cache_mode(void);
|
||||
|
||||
#endif /* __SOC_H__ */
|
||||
91
soc/espressif/esp32s2/soc_cache.c
Normal file
91
soc/espressif/esp32s2/soc_cache.c
Normal file
|
|
@ -0,0 +1,91 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
/*
|
||||
* Instruction Cache definitions
|
||||
*/
|
||||
#if defined(CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB)
|
||||
#define ESP32S2_ICACHE_SIZE CACHE_SIZE_8KB
|
||||
#else
|
||||
#define ESP32S2_ICACHE_SIZE CACHE_SIZE_16KB
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B)
|
||||
#define ESP32S2_ICACHE_LINE_SIZE CACHE_LINE_SIZE_16B
|
||||
#else
|
||||
#define ESP32S2_ICACHE_LINE_SIZE CACHE_LINE_SIZE_32B
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Data Cache definitions
|
||||
*/
|
||||
#if defined(CONFIG_ESP32S2_DATA_CACHE_8KB)
|
||||
#define ESP32S2_DCACHE_SIZE CACHE_SIZE_8KB
|
||||
#else
|
||||
#define ESP32S2_DCACHE_SIZE CACHE_SIZE_16KB
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ESP32S2_DATA_CACHE_LINE_16B)
|
||||
#define ESP32S2_DCACHE_LINE_SIZE CACHE_LINE_SIZE_16B
|
||||
#else
|
||||
#define ESP32S2_DCACHE_LINE_SIZE CACHE_LINE_SIZE_32B
|
||||
#endif
|
||||
|
||||
void IRAM_ATTR esp_config_instruction_cache_mode(void)
|
||||
{
|
||||
cache_size_t cache_size;
|
||||
cache_ways_t cache_ways;
|
||||
cache_line_size_t cache_line_size;
|
||||
|
||||
#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
|
||||
esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_INVALID,
|
||||
CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
|
||||
#else
|
||||
esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,
|
||||
CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
|
||||
#endif
|
||||
cache_size = ESP32S2_ICACHE_SIZE;
|
||||
cache_ways = CACHE_4WAYS_ASSOC;
|
||||
cache_line_size = ESP32S2_ICACHE_LINE_SIZE;
|
||||
|
||||
esp_rom_Cache_Suspend_ICache();
|
||||
esp_rom_Cache_Set_ICache_Mode(cache_size, cache_ways, cache_line_size);
|
||||
esp_rom_Cache_Invalidate_ICache_All();
|
||||
esp_rom_Cache_Resume_ICache(0);
|
||||
}
|
||||
|
||||
void IRAM_ATTR esp_config_data_cache_mode(void)
|
||||
{
|
||||
cache_size_t cache_size;
|
||||
cache_ways_t cache_ways;
|
||||
cache_line_size_t cache_line_size;
|
||||
|
||||
#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
|
||||
#if CONFIG_ESP32S2_DATA_CACHE_8KB
|
||||
esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW,
|
||||
CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
|
||||
#else
|
||||
esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW,
|
||||
CACHE_MEMORY_DCACHE_HIGH, CACHE_MEMORY_INVALID);
|
||||
#endif
|
||||
#else
|
||||
#if CONFIG_ESP32S2_DATA_CACHE_8KB
|
||||
esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,
|
||||
CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_INVALID);
|
||||
#else
|
||||
esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,
|
||||
CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_DCACHE_HIGH);
|
||||
#endif
|
||||
#endif
|
||||
cache_size = ESP32S2_DCACHE_SIZE;
|
||||
cache_ways = CACHE_4WAYS_ASSOC;
|
||||
cache_line_size = ESP32S2_DCACHE_LINE_SIZE;
|
||||
|
||||
esp_rom_Cache_Set_DCache_Mode(cache_size, cache_ways, cache_line_size);
|
||||
esp_rom_Cache_Invalidate_DCache_All();
|
||||
}
|
||||
118
soc/espressif/esp32s3/CMakeLists.txt
Normal file
118
soc/espressif/esp32s3/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,118 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if(CONFIG_SOC_ESP32S3_APPCPU)
|
||||
zephyr_sources(soc_appcpu.c)
|
||||
else()
|
||||
zephyr_sources(
|
||||
soc.c
|
||||
soc_cache.c
|
||||
loader.c
|
||||
esp32s3-mp.c
|
||||
)
|
||||
endif()
|
||||
|
||||
zephyr_include_directories(.)
|
||||
|
||||
zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fix.c)
|
||||
|
||||
# get flash size to use in esptool as string
|
||||
math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000")
|
||||
|
||||
if(CONFIG_BOOTLOADER_ESP_IDF)
|
||||
include(ExternalProject)
|
||||
|
||||
## we use hello-world project, but I think any can be used.
|
||||
set(espidf_components_dir ${ESP_IDF_PATH}/components)
|
||||
set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf)
|
||||
set(espidf_build_dir ${espidf_prefix}/build)
|
||||
|
||||
ExternalProject_Add(
|
||||
EspIdfBootloader
|
||||
PREFIX ${espidf_prefix}
|
||||
SOURCE_DIR ${espidf_components_dir}/bootloader/subproject
|
||||
BINARY_DIR ${espidf_build_dir}/bootloader
|
||||
CONFIGURE_COMMAND
|
||||
${CMAKE_COMMAND} -G${CMAKE_GENERATOR}
|
||||
-S ${espidf_components_dir}/bootloader/subproject
|
||||
-B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig
|
||||
-DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES}
|
||||
-DPYTHON_DEPS_CHECKED=1
|
||||
-DCMAKE_C_COMPILER=${CMAKE_C_COMPILER}
|
||||
-DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER}
|
||||
-DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER}
|
||||
-DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME}
|
||||
-DPYTHON=${PYTHON_EXECUTABLE}
|
||||
BUILD_COMMAND
|
||||
${CMAKE_COMMAND} --build .
|
||||
INSTALL_COMMAND "" # This particular build system has no install command
|
||||
)
|
||||
|
||||
ExternalProject_Add(
|
||||
EspPartitionTable
|
||||
SOURCE_DIR ${espidf_components_dir}/partition_table
|
||||
BINARY_DIR ${espidf_build_dir}
|
||||
CONFIGURE_COMMAND ""
|
||||
BUILD_COMMAND
|
||||
${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q
|
||||
--offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin
|
||||
INSTALL_COMMAND ""
|
||||
)
|
||||
|
||||
set_property(TARGET bintools PROPERTY disassembly_flag_inline_source)
|
||||
|
||||
add_dependencies(app EspIdfBootloader EspPartitionTable)
|
||||
|
||||
board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin")
|
||||
|
||||
board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin")
|
||||
|
||||
board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000")
|
||||
|
||||
endif()
|
||||
|
||||
if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF)
|
||||
if(CONFIG_BUILD_OUTPUT_BIN)
|
||||
set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
|
||||
COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py
|
||||
ARGS --chip esp32s3 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB
|
||||
-o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin
|
||||
${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf)
|
||||
endif()
|
||||
|
||||
if(CONFIG_MCUBOOT)
|
||||
board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin")
|
||||
endif()
|
||||
endif()
|
||||
|
||||
## When building for APPCPU
|
||||
if(CONFIG_SOC_ESP32S3_APPCPU)
|
||||
if(CONFIG_BUILD_OUTPUT_BIN)
|
||||
set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
|
||||
COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esp_bin2c_array.py
|
||||
ARGS -i ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin
|
||||
-o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.c
|
||||
-a "esp32s3_appcpu_fw_array")
|
||||
endif()
|
||||
else()
|
||||
set_property(TARGET bintools PROPERTY disassembly_flag_inline_source)
|
||||
|
||||
# get code-partition slot0 address
|
||||
dt_nodelabel(dts_partition_path NODELABEL "slot0_partition")
|
||||
dt_reg_addr(img_0_off PATH ${dts_partition_path})
|
||||
|
||||
# get code-partition boot address
|
||||
dt_nodelabel(dts_partition_path NODELABEL "boot_partition")
|
||||
dt_reg_addr(boot_off PATH ${dts_partition_path})
|
||||
|
||||
board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}")
|
||||
|
||||
board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}")
|
||||
endif()
|
||||
|
||||
if(CONFIG_MCUBOOT)
|
||||
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "")
|
||||
elseif(CONFIG_SOC_ESP32S3_APPCPU)
|
||||
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default_appcpu.ld CACHE INTERNAL "")
|
||||
else()
|
||||
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "")
|
||||
endif()
|
||||
313
soc/espressif/esp32s3/Kconfig
Normal file
313
soc/espressif/esp32s3/Kconfig
Normal file
|
|
@ -0,0 +1,313 @@
|
|||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_ESP32S3
|
||||
select XTENSA
|
||||
select DYNAMIC_INTERRUPTS
|
||||
select ARCH_SUPPORTS_COREDUMP
|
||||
select CLOCK_CONTROL
|
||||
select PINCTRL
|
||||
select XIP if !MCUBOOT
|
||||
select HAS_ESPRESSIF_HAL
|
||||
select CPU_HAS_FPU
|
||||
|
||||
if SOC_SERIES_ESP32S3
|
||||
|
||||
config IDF_TARGET_ESP32S3
|
||||
bool "ESP32S3 as target SOC"
|
||||
default y
|
||||
|
||||
config ESP32S3_APPCPU_IRAM
|
||||
hex "ESP32S3 APPCPU IRAM size"
|
||||
depends on SOC_ESP32S3_PROCPU || SOC_ESP32S3_APPCPU
|
||||
default 0x20000
|
||||
help
|
||||
Defines APPCPU IRAM area in bytes.
|
||||
|
||||
config ESP32S3_APPCPU_DRAM
|
||||
hex "ESP32S3 APPCPU DRAM size"
|
||||
depends on SOC_ESP32S3_PROCPU || SOC_ESP32S3_APPCPU
|
||||
default 0x10000
|
||||
help
|
||||
Defines APPCPU DRAM area in bytes.
|
||||
|
||||
config SOC_ESP32S3_PROCPU
|
||||
bool
|
||||
help
|
||||
This hidden configuration defines that build is targeted for PROCPU (core 0).
|
||||
|
||||
config SOC_ESP32S3_APPCPU
|
||||
bool
|
||||
help
|
||||
This hidden configuration defines that build is targeted for APPCPU (core 1).
|
||||
|
||||
config SOC_ENABLE_APPCPU
|
||||
bool
|
||||
default y
|
||||
depends on IPM && SOC_ESP32S3_PROCPU
|
||||
help
|
||||
This hidden configuration lets PROCPU core to map and start APPCPU whenever IPM is enabled.
|
||||
|
||||
choice ESP32S3_RTC_CLK_SRC
|
||||
prompt "RTC clock source"
|
||||
default ESP32S3_RTC_CLK_SRC_INT_RC
|
||||
help
|
||||
Choose which clock is used as RTC clock source.
|
||||
|
||||
config ESP32S3_RTC_CLK_SRC_INT_RC
|
||||
bool "Internal 150kHz RC oscillator"
|
||||
config ESP32S3_RTC_CLK_SRC_EXT_CRYS
|
||||
bool "External 32kHz crystal"
|
||||
select ESP_SYSTEM_RTC_EXT_XTAL
|
||||
config ESP32S3_RTC_CLK_SRC_EXT_OSC
|
||||
bool "External 32kHz oscillator at 32K_XP pin"
|
||||
select ESP_SYSTEM_RTC_EXT_OSC
|
||||
config ESP32S3_RTC_CLK_SRC_INT_8MD256
|
||||
bool "Internal 8MHz oscillator, divided by 256 (~32kHz)"
|
||||
endchoice
|
||||
|
||||
config ESP32S3_RTC_CLK_CAL_CYCLES
|
||||
int "Number of cycles for RTC_SLOW_CLK calibration"
|
||||
default 3000 if ESP32S3_RTC_CLK_SRC_EXT_CRYS || ESP32S3_RTC_CLK_SRC_EXT_OSC || ESP32S3_RTC_CLK_SRC_INT_8MD256
|
||||
default 1024 if ESP32S3_RTC_CLK_SRC_INT_RC
|
||||
range 0 27000 if ESP32S3_RTC_CLK_SRC_EXT_CRYS || ESP32S3_RTC_CLK_SRC_EXT_OSC || ESP32S3_RTC_CLK_SRC_INT_8MD256
|
||||
range 0 32766 if ESP32S3_RTC_CLK_SRC_INT_RC
|
||||
help
|
||||
When the startup code initializes RTC_SLOW_CLK, it can perform
|
||||
calibration by comparing the RTC_SLOW_CLK frequency with main XTAL
|
||||
frequency. This option sets the number of RTC_SLOW_CLK cycles measured
|
||||
by the calibration routine. Higher numbers increase calibration
|
||||
precision, which may be important for applications which spend a lot of
|
||||
time in deep sleep. Lower numbers reduce startup time.
|
||||
|
||||
When this option is set to 0, clock calibration will not be performed at
|
||||
startup, and approximate clock frequencies will be assumed:
|
||||
|
||||
- 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024.
|
||||
- 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
|
||||
In case more value will help improve the definition of the launch of the crystal.
|
||||
If the crystal could not start, it will be switched to internal RC.
|
||||
|
||||
choice ESP32_UNIVERSAL_MAC_ADDRESSES
|
||||
bool "Number of universally administered (by IEEE) MAC address"
|
||||
default ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
|
||||
help
|
||||
Configure the number of universally administered (by IEEE) MAC addresses.
|
||||
During initialization, MAC addresses for each network interface are generated or
|
||||
derived from a single base MAC address. If the number of universal MAC addresses is four,
|
||||
all four interfaces (WiFi station, WiFi softap, Bluetooth and Ethernet) receive a universally
|
||||
administered MAC address. These are generated sequentially by adding 0, 1, 2 and 3 (respectively)
|
||||
to the final octet of the base MAC address. If the number of universal MAC addresses is two,
|
||||
only two interfaces (WiFi station and Bluetooth) receive a universally administered MAC address.
|
||||
These are generated sequentially by adding 0 and 1 (respectively) to the base MAC address.
|
||||
The remaining two interfaces (WiFi softap and Ethernet) receive local MAC addresses.
|
||||
These are derived from the universal WiFi station and Bluetooth MAC addresses, respectively.
|
||||
When using the default (Espressif-assigned) base MAC address, either setting can be used.
|
||||
When using a custom universal MAC address range, the correct setting will depend on the
|
||||
allocation of MAC addresses in this range (either 2 or 4 per device.)
|
||||
|
||||
config ESP32_UNIVERSAL_MAC_ADDRESSES_TWO
|
||||
bool "Two"
|
||||
select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
|
||||
select ESP_MAC_ADDR_UNIVERSE_BT
|
||||
|
||||
config ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
|
||||
bool "Four"
|
||||
select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
|
||||
select ESP_MAC_ADDR_UNIVERSE_WIFI_AP
|
||||
select ESP_MAC_ADDR_UNIVERSE_BT
|
||||
select ESP_MAC_ADDR_UNIVERSE_ETH
|
||||
|
||||
endchoice # ESP32_UNIVERSAL_MAC_ADDRESSES
|
||||
|
||||
config ESP_MAC_ADDR_UNIVERSE_WIFI_AP
|
||||
bool
|
||||
|
||||
config ESP_MAC_ADDR_UNIVERSE_WIFI_STA
|
||||
bool
|
||||
|
||||
config ESP_MAC_ADDR_UNIVERSE_BT
|
||||
bool
|
||||
|
||||
config ESP_MAC_ADDR_UNIVERSE_ETH
|
||||
bool
|
||||
|
||||
config ESP32_UNIVERSAL_MAC_ADDRESSES
|
||||
int
|
||||
default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO
|
||||
default 4 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
|
||||
|
||||
config ESP32_PHY_MAX_WIFI_TX_POWER
|
||||
int "Max WiFi/BLE TX power (dBm)"
|
||||
range 10 20
|
||||
default 20
|
||||
help
|
||||
Set maximum transmit power for WiFi radio. Actual transmit power for high
|
||||
data rates may be lower than this setting.
|
||||
|
||||
config ESP32_PHY_MAX_TX_POWER
|
||||
int
|
||||
default ESP32_PHY_MAX_WIFI_TX_POWER
|
||||
|
||||
menu "Cache config"
|
||||
|
||||
choice ESP32S3_INSTRUCTION_CACHE_SIZE
|
||||
prompt "Instruction cache size"
|
||||
default ESP32S3_INSTRUCTION_CACHE_16KB
|
||||
help
|
||||
Instruction cache size to be set on application startup.
|
||||
If you use 16KB instruction cache rather than 32KB instruction cache,
|
||||
then the other 16KB will be managed by heap allocator.
|
||||
|
||||
config ESP32S3_INSTRUCTION_CACHE_16KB
|
||||
bool "16KB"
|
||||
config ESP32S3_INSTRUCTION_CACHE_32KB
|
||||
bool "32KB"
|
||||
endchoice
|
||||
|
||||
config ESP32S3_INSTRUCTION_CACHE_SIZE
|
||||
hex
|
||||
default 0x4000 if ESP32S3_INSTRUCTION_CACHE_16KB
|
||||
default 0x8000 if ESP32S3_INSTRUCTION_CACHE_32KB
|
||||
|
||||
choice ESP32S3_ICACHE_ASSOCIATED_WAYS
|
||||
prompt "Instruction cache associated ways"
|
||||
default ESP32S3_INSTRUCTION_CACHE_8WAYS
|
||||
help
|
||||
Instruction cache associated ways to be set on application startup.
|
||||
|
||||
config ESP32S3_INSTRUCTION_CACHE_4WAYS
|
||||
bool "4 ways"
|
||||
config ESP32S3_INSTRUCTION_CACHE_8WAYS
|
||||
bool "8 ways"
|
||||
endchoice
|
||||
|
||||
config ESP32S3_ICACHE_ASSOCIATED_WAYS
|
||||
int
|
||||
default 4 if ESP32S3_INSTRUCTION_CACHE_4WAYS
|
||||
default 8 if ESP32S3_INSTRUCTION_CACHE_8WAYS
|
||||
|
||||
choice ESP32S3_INSTRUCTION_CACHE_LINE_SIZE
|
||||
prompt "Instruction cache line size"
|
||||
default ESP32S3_INSTRUCTION_CACHE_LINE_32B
|
||||
help
|
||||
Instruction cache line size to be set on application startup.
|
||||
|
||||
config ESP32S3_INSTRUCTION_CACHE_LINE_16B
|
||||
bool "16 Bytes"
|
||||
depends on ESP32S3_INSTRUCTION_CACHE_16KB
|
||||
config ESP32S3_INSTRUCTION_CACHE_LINE_32B
|
||||
bool "32 Bytes"
|
||||
endchoice
|
||||
|
||||
config ESP32S3_INSTRUCTION_CACHE_LINE_SIZE
|
||||
int
|
||||
default 16 if ESP32S3_INSTRUCTION_CACHE_LINE_16B
|
||||
default 32 if ESP32S3_INSTRUCTION_CACHE_LINE_32B
|
||||
|
||||
config ESP32S3_INSTRUCTION_CACHE_WRAP
|
||||
bool "Define instruction cache wrap mode"
|
||||
help
|
||||
If enabled, instruction cache will use wrap mode to read spi flash or spi ram.
|
||||
The wrap length equals to ESP32S3_INSTRUCTION_CACHE_LINE_SIZE.
|
||||
However, it depends on complex conditions.
|
||||
|
||||
choice ESP32S3_DATA_CACHE_SIZE
|
||||
prompt "Data cache size"
|
||||
default ESP32S3_DATA_CACHE_32KB
|
||||
help
|
||||
Data cache size to be set on application startup.
|
||||
If you use 32KB data cache rather than 64KB data cache,
|
||||
the other 32KB will be added to the heap.
|
||||
|
||||
config ESP32S3_DATA_CACHE_16KB
|
||||
bool "16KB"
|
||||
config ESP32S3_DATA_CACHE_32KB
|
||||
bool "32KB"
|
||||
config ESP32S3_DATA_CACHE_64KB
|
||||
bool "64KB"
|
||||
endchoice
|
||||
|
||||
config ESP32S3_DATA_CACHE_SIZE
|
||||
hex
|
||||
# For 16KB the actual configuration is 32kb cache, but 16kb will be reserved for heap at startup
|
||||
default 0x8000 if ESP32S3_DATA_CACHE_16KB
|
||||
default 0x8000 if ESP32S3_DATA_CACHE_32KB
|
||||
default 0x10000 if ESP32S3_DATA_CACHE_64KB
|
||||
|
||||
choice ESP32S3_DCACHE_ASSOCIATED_WAYS
|
||||
prompt "Data cache associated ways"
|
||||
default ESP32S3_DATA_CACHE_8WAYS
|
||||
help
|
||||
Data cache associated ways to be set on application startup.
|
||||
|
||||
config ESP32S3_DATA_CACHE_4WAYS
|
||||
bool "4 ways"
|
||||
config ESP32S3_DATA_CACHE_8WAYS
|
||||
bool "8 ways"
|
||||
endchoice
|
||||
|
||||
config ESP32S3_DCACHE_ASSOCIATED_WAYS
|
||||
int
|
||||
default 4 if ESP32S3_DATA_CACHE_4WAYS
|
||||
default 8 if ESP32S3_DATA_CACHE_8WAYS
|
||||
|
||||
choice ESP32S3_DATA_CACHE_LINE_SIZE
|
||||
prompt "Data cache line size"
|
||||
default ESP32S3_DATA_CACHE_LINE_32B
|
||||
help
|
||||
Data cache line size to be set on application startup.
|
||||
|
||||
config ESP32S3_DATA_CACHE_LINE_16B
|
||||
bool "16 Bytes"
|
||||
depends on ESP32S3_DATA_CACHE_16KB || ESP32S3_DATA_CACHE_32KB
|
||||
config ESP32S3_DATA_CACHE_LINE_32B
|
||||
bool "32 Bytes"
|
||||
config ESP32S3_DATA_CACHE_LINE_64B
|
||||
bool "64 Bytes"
|
||||
endchoice
|
||||
|
||||
config ESP32S3_DATA_CACHE_LINE_SIZE
|
||||
int
|
||||
default 16 if ESP32S3_DATA_CACHE_LINE_16B
|
||||
default 32 if ESP32S3_DATA_CACHE_LINE_32B
|
||||
default 64 if ESP32S3_DATA_CACHE_LINE_64B
|
||||
|
||||
config ESP32S3_DATA_CACHE_WRAP
|
||||
bool "Define data cache wrap mode"
|
||||
help
|
||||
If enabled, data cache will use wrap mode to read spi flash or spi ram.
|
||||
The wrap length equals to ESP32S3_DATA_CACHE_LINE_SIZE.
|
||||
However, it depends on complex conditions.
|
||||
|
||||
config MAC_BB_PD
|
||||
bool "Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled"
|
||||
depends on SOC_SERIES_ESP32S3 && TICKLESS_KERNEL
|
||||
default n
|
||||
help
|
||||
If enabled, the MAC and baseband of Wi-Fi and Bluetooth will be powered
|
||||
down when PHY is disabled. Enabling this setting reduces power consumption
|
||||
by a small amount but increases RAM use by approximat
|
||||
|
||||
endmenu # Cache config
|
||||
|
||||
menu "PSRAM Clock and CS IO for ESP32S3"
|
||||
depends on ESP_SPIRAM
|
||||
|
||||
config DEFAULT_PSRAM_CLK_IO
|
||||
int "PSRAM CLK IO number"
|
||||
range 0 33
|
||||
default 30
|
||||
help
|
||||
The PSRAM Clock IO can be any unused GPIO, please refer to your hardware design.
|
||||
|
||||
config DEFAULT_PSRAM_CS_IO
|
||||
int "PSRAM CS IO number"
|
||||
range 0 33
|
||||
default 26
|
||||
help
|
||||
The PSRAM CS IO can be any unused GPIO, please refer to your hardware design.
|
||||
|
||||
endmenu # PSRAM clock and cs IO for ESP32S3
|
||||
|
||||
endif # SOC_SERIES_ESP32S3
|
||||
24
soc/espressif/esp32s3/Kconfig.defconfig
Normal file
24
soc/espressif/esp32s3/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_ESP32S3
|
||||
|
||||
config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
|
||||
default n
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
|
||||
|
||||
config XTENSA_CCOUNT_HZ
|
||||
default SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
|
||||
config ESPTOOLPY_FLASHFREQ_80M
|
||||
default y
|
||||
|
||||
config FLASH_SIZE
|
||||
default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0)
|
||||
|
||||
config FLASH_BASE_ADDRESS
|
||||
default $(dt_node_reg_addr_hex,/soc/flash-controller@60002000/flash@0)
|
||||
|
||||
endif # SOC_SERIES_ESP32S3
|
||||
146
soc/espressif/esp32s3/Kconfig.soc
Normal file
146
soc/espressif/esp32s3/Kconfig.soc
Normal file
|
|
@ -0,0 +1,146 @@
|
|||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_ESP32S3
|
||||
bool
|
||||
select SOC_FAMILY_ESPRESSIF_ESP32
|
||||
help
|
||||
ESP32-S3 Series
|
||||
|
||||
config SOC_ESP32S3_R2
|
||||
bool
|
||||
select SOC_ESP32S3
|
||||
help
|
||||
ESP32S3_R2
|
||||
|
||||
config SOC_ESP32S3_R8
|
||||
bool
|
||||
select SOC_ESP32S3
|
||||
help
|
||||
ESP32S3_R8
|
||||
|
||||
config SOC_ESP32S3_R8V
|
||||
bool
|
||||
select SOC_ESP32S3
|
||||
help
|
||||
ESP32S3_R8V
|
||||
|
||||
config SOC_ESP32S3_FN8
|
||||
bool
|
||||
select SOC_ESP32S3
|
||||
help
|
||||
ESP32S3_FN8
|
||||
|
||||
config SOC_ESP32S3_PICO_N8R2
|
||||
bool
|
||||
select SOC_ESP32S3
|
||||
help
|
||||
ESP32S3_PICO_N8R2
|
||||
|
||||
config SOC_ESP32S3_PICO_N8R8
|
||||
bool
|
||||
select SOC_ESP32S3
|
||||
help
|
||||
ESP32S3_PICO_N8R8
|
||||
|
||||
# SiP with flash and/or psram
|
||||
config SOC_ESP32S3_MINI_N8
|
||||
bool
|
||||
select SOC_ESP32S3
|
||||
help
|
||||
ESP32S3_MINI_N8
|
||||
|
||||
config SOC_ESP32S3_MINI_N4R2
|
||||
bool
|
||||
select SOC_ESP32S3
|
||||
help
|
||||
ESP32S3_MINI_N4R2
|
||||
|
||||
config SOC_ESP32S3_WROOM_N4
|
||||
bool
|
||||
select SOC_ESP32S3
|
||||
help
|
||||
ESP32S3_WROOM_N4
|
||||
|
||||
config SOC_ESP32S3_WROOM_N8
|
||||
bool
|
||||
select SOC_ESP32S3
|
||||
help
|
||||
ESP32S3_WROOM_N8
|
||||
|
||||
config SOC_ESP32S3_WROOM_N16
|
||||
bool
|
||||
select SOC_ESP32S3
|
||||
help
|
||||
ESP32S3_WROOM_N16
|
||||
|
||||
config SOC_ESP32S3_WROOM_N4R8
|
||||
bool
|
||||
select SOC_ESP32S3
|
||||
help
|
||||
ESP32S3_WROOM_N4R8
|
||||
|
||||
config SOC_ESP32S3_WROOM_N8R8
|
||||
bool
|
||||
select SOC_ESP32S3
|
||||
help
|
||||
ESP32S3_WROOM_N8R8
|
||||
|
||||
config SOC_ESP32S3_WROOM_N16R8
|
||||
bool
|
||||
select SOC_ESP32S3
|
||||
help
|
||||
ESP32S3_WROOM_N16R8
|
||||
|
||||
config SOC_ESP32S3_WROOM_N4R2
|
||||
bool
|
||||
select SOC_ESP32S3
|
||||
help
|
||||
ESP32S3_WROOM_N4R2
|
||||
|
||||
config SOC_ESP32S3_WROOM_N8R2
|
||||
bool
|
||||
select SOC_ESP32S3
|
||||
help
|
||||
ESP32S3_WROOM_N8R2
|
||||
|
||||
config SOC_ESP32S3_WROOM_N16R2
|
||||
bool
|
||||
select SOC_ESP32S3
|
||||
help
|
||||
ESP32S3_WROOM_N16R2
|
||||
|
||||
config SOC_ESP32S3
|
||||
bool
|
||||
select SOC_SERIES_ESP32S3
|
||||
help
|
||||
ESP32S3
|
||||
|
||||
config SOC_SERIES
|
||||
default "esp32s3" if SOC_SERIES_ESP32S3
|
||||
|
||||
config SOC
|
||||
default "esp32s3" if SOC_SERIES_ESP32S3
|
||||
|
||||
config SOC_PART_NUMBER
|
||||
default "ESP32S3_R2" if SOC_ESP32S3_R2
|
||||
default "ESP32S3_R8" if SOC_ESP32S3_R8
|
||||
default "ESP32S3_R8V" if SOC_ESP32S3_R8V
|
||||
default "ESP32S3_FN8" if SOC_ESP32S3_FN8
|
||||
default "ESP32S3_PICO_N8R2" if SOC_ESP32S3_PICO_N8R2
|
||||
default "ESP32S3_PICO_N8R8" if SOC_ESP32S3_PICO_N8R8
|
||||
default "ESP32S3_MINI_N8" if SOC_ESP32S3_MINI_N8
|
||||
default "ESP32S3_MINI_N4R2" if SOC_ESP32S3_MINI_N4R2
|
||||
default "ESP32S3_WROOM_N4" if SOC_ESP32S3_WROOM_N4
|
||||
default "ESP32S3_WROOM_N8" if SOC_ESP32S3_WROOM_N8
|
||||
default "ESP32S3_WROOM_N16" if SOC_ESP32S3_WROOM_N16
|
||||
default "ESP32S3_WROOM_N4R8" if SOC_ESP32S3_WROOM_N4R8
|
||||
default "ESP32S3_WROOM_N8R8" if SOC_ESP32S3_WROOM_N8R8
|
||||
default "ESP32S3_WROOM_N16R8" if SOC_ESP32S3_WROOM_N16R8
|
||||
default "ESP32S3_WROOM_N4R2" if SOC_ESP32S3_WROOM_N4R2
|
||||
default "ESP32S3_WROOM_N8R2" if SOC_ESP32S3_WROOM_N8R2
|
||||
default "ESP32S3_WROOM_N16R2" if SOC_ESP32S3_WROOM_N16R2
|
||||
|
||||
config SOC_TOOLCHAIN_NAME
|
||||
string
|
||||
default "espressif_esp32s3" if SOC_SERIES_ESP32S3
|
||||
693
soc/espressif/esp32s3/default.ld
Normal file
693
soc/espressif/esp32s3/default.ld
Normal file
|
|
@ -0,0 +1,693 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Linker command/script file
|
||||
*
|
||||
* Linker script for the ESP32S3 platform.
|
||||
*/
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/linker/sections.h>
|
||||
#include <zephyr/linker/linker-defs.h>
|
||||
#include <zephyr/linker/linker-tool.h>
|
||||
|
||||
#define SRAM_IRAM_START 0x40370000
|
||||
#define SRAM_DIRAM_I_START 0x40378000
|
||||
/* SRAM_IRAM_END is equivalent 2nd stage bootloader iram_loader_seg
|
||||
start address (that should not be overlapped) */
|
||||
#define SRAM_IRAM_END 0x403BA000
|
||||
#define I_D_SRAM_OFFSET (SRAM_DIRAM_I_START - SRAM_DRAM_START)
|
||||
|
||||
#define SRAM_DRAM_START 0x3FC88000
|
||||
#define SRAM_DRAM_END (SRAM_IRAM_END - I_D_SRAM_OFFSET)
|
||||
#define I_D_SRAM_SIZE (SRAM_DRAM_END - SRAM_DRAM_START)
|
||||
|
||||
#define ICACHE_SIZE 0x8000
|
||||
#define SRAM_IRAM_ORG (SRAM_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)
|
||||
#define SRAM_IRAM_SIZE (I_D_SRAM_SIZE + ICACHE_SIZE - CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)
|
||||
|
||||
#define DCACHE_SIZE 0x10000
|
||||
#define SRAM_DRAM_ORG (SRAM_DRAM_START)
|
||||
|
||||
#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE
|
||||
|
||||
#define FLASH_CODE_REGION irom0_0_seg
|
||||
#define RODATA_REGION drom0_0_seg
|
||||
#define IRAM_REGION iram0_0_seg
|
||||
#define RAMABLE_REGION dram0_0_seg
|
||||
#define ROMABLE_REGION ROM
|
||||
|
||||
#define EXT_RAM_ORG (0x3E000000 - CONFIG_ESP_SPIRAM_SIZE)
|
||||
|
||||
#ifdef CONFIG_FLASH_SIZE
|
||||
#define FLASH_SIZE CONFIG_FLASH_SIZE
|
||||
#else
|
||||
#define FLASH_SIZE 0x800000
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BOOTLOADER_ESP_IDF
|
||||
#define IROM_SEG_ORG 0x42000020
|
||||
#define IROM_SEG_LEN FLASH_SIZE-0x20
|
||||
#else
|
||||
#define IROM_SEG_ORG 0x42000000
|
||||
#define IROM_SEG_LEN FLASH_SIZE
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_ENABLE_APPCPU
|
||||
#define APPCPU_IRAM_SIZE CONFIG_ESP32S3_APPCPU_IRAM
|
||||
#define APPCPU_DRAM_SIZE CONFIG_ESP32S3_APPCPU_DRAM
|
||||
#else
|
||||
#define APPCPU_IRAM_SIZE 0x0
|
||||
#define APPCPU_DRAM_SIZE 0x0
|
||||
#endif
|
||||
|
||||
#define IROM_SEG_ALIGN 0x10000
|
||||
|
||||
/* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA.
|
||||
* Executing directly from LMA is not possible. */
|
||||
#undef GROUP_ROM_LINK_IN
|
||||
#define GROUP_ROM_LINK_IN(vregion, lregion) > RODATA_REGION AT > lregion
|
||||
|
||||
MEMORY
|
||||
{
|
||||
mcuboot_hdr (RX): org = 0x0, len = 0x20
|
||||
metadata (RX): org = 0x20, len = 0x20
|
||||
ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40
|
||||
iram0_0_seg(RX): org = SRAM_IRAM_ORG, len = SRAM_IRAM_SIZE - APPCPU_IRAM_SIZE
|
||||
dram0_0_seg(RW): org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN - APPCPU_DRAM_SIZE
|
||||
|
||||
irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN
|
||||
|
||||
/* DROM is the first segment placed in generated binary.
|
||||
* MCUboot binary for ESP32 has image header of 0x20 bytes.
|
||||
* Additional load header of 0x20 bytes are appended to the image.
|
||||
* Hence, an offset of 0x40 is added to DROM segment origin.
|
||||
*/
|
||||
drom0_0_seg(R): org = 0x3C000040, len = FLASH_SIZE - 0x40
|
||||
/**
|
||||
* `extern_ram_seg` and `drom0_0_seg` share the same bus and the address region.
|
||||
* so we allocate `extern_ram_seg` at the end of the address region.
|
||||
*/
|
||||
#if defined(CONFIG_ESP_SPIRAM)
|
||||
ext_ram_seg(RWX): org = EXT_RAM_ORG, len = CONFIG_ESP_SPIRAM_SIZE
|
||||
#endif
|
||||
|
||||
/* RTC fast memory (executable). Persists over deep sleep.
|
||||
*/
|
||||
rtc_iram_seg(RWX): org = 0x600fe000, len = 0x2000
|
||||
|
||||
/* RTC fast memory (same block as above), viewed from data bus
|
||||
*/
|
||||
rtc_data_seg(RW): org = 0x600fe000, len = 0x2000
|
||||
|
||||
/* RTC slow memory (data accessible). Persists over deep sleep.
|
||||
*/
|
||||
rtc_slow_seg(RW): org = 0x50000000, len = 0x2000
|
||||
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Default entry point: */
|
||||
ENTRY(CONFIG_KERNEL_ENTRY)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Reserve space for MCUboot header in the binary */
|
||||
.mcuboot_header :
|
||||
{
|
||||
QUAD(0x0)
|
||||
QUAD(0x0)
|
||||
QUAD(0x0)
|
||||
QUAD(0x0)
|
||||
} > mcuboot_hdr
|
||||
.metadata :
|
||||
{
|
||||
/* Magic byte for load header */
|
||||
LONG(0xace637d3)
|
||||
|
||||
/* Application entry point address */
|
||||
KEEP(*(.entry_addr))
|
||||
|
||||
/* IRAM metadata:
|
||||
* - Destination address (VMA) for IRAM region
|
||||
* - Flash offset (LMA) for start of IRAM region
|
||||
* - Size of IRAM region
|
||||
*/
|
||||
LONG(ADDR(.iram0.vectors))
|
||||
LONG(LOADADDR(.iram0.vectors))
|
||||
LONG(LOADADDR(.iram0.text) + SIZEOF(.iram0.text) - LOADADDR(.iram0.vectors))
|
||||
|
||||
/* DRAM metadata:
|
||||
* - Destination address (VMA) for DRAM region
|
||||
* - Flash offset (LMA) for start of DRAM region
|
||||
* - Size of DRAM region
|
||||
*/
|
||||
LONG(ADDR(.dram0.data))
|
||||
LONG(LOADADDR(.dram0.data))
|
||||
LONG(LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - LOADADDR(.dram0.data))
|
||||
} > metadata
|
||||
|
||||
#include <zephyr/linker/rel-sections.ld>
|
||||
|
||||
_image_drom_start = LOADADDR(_RODATA_SECTION_NAME);
|
||||
_image_drom_size = LOADADDR(_RODATA_SECTION_END) + SIZEOF(_RODATA_SECTION_END) - _image_drom_start;
|
||||
_image_drom_vaddr = ADDR(_RODATA_SECTION_NAME);
|
||||
|
||||
/* NOTE: .rodata section should be the first section in the linker script and no
|
||||
* other section should appear before .rodata section. This is the requirement
|
||||
* to align ROM section to 64K page offset.
|
||||
* Adding .rodata as first section helps to reduce size of generated binary by
|
||||
* few kBs.
|
||||
*/
|
||||
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(0x10))
|
||||
{
|
||||
_rodata_reserved_start = ABSOLUTE(.);
|
||||
_rodata_start = ABSOLUTE(.);
|
||||
|
||||
*(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */
|
||||
*(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */
|
||||
|
||||
__rodata_region_start = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
#include <snippets-rodata.ld>
|
||||
|
||||
. = ALIGN(4);
|
||||
*(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__serial.a:uart_esp32.*) .rodata)
|
||||
*(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__serial.a:uart_esp32.*) .rodata.*)
|
||||
|
||||
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
|
||||
*(.xt_except_table)
|
||||
*(.gcc_except_table .gcc_except_table.*)
|
||||
*(.gnu.linkonce.e.*)
|
||||
*(.gnu.version_r)
|
||||
. = (. + 3) & ~ 3;
|
||||
__eh_frame = ABSOLUTE(.);
|
||||
KEEP(*(.eh_frame))
|
||||
. = (. + 7) & ~ 3;
|
||||
|
||||
/* C++ exception handlers table: */
|
||||
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
|
||||
*(.xt_except_desc)
|
||||
*(.gnu.linkonce.h.*)
|
||||
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc_end)
|
||||
*(.dynamic)
|
||||
*(.gnu.version_d)
|
||||
. = ALIGN(4);
|
||||
__rodata_region_end = ABSOLUTE(.);
|
||||
/* Literals are also RO data. */
|
||||
_lit4_start = ABSOLUTE(.);
|
||||
*(*.lit4)
|
||||
*(.lit4.*)
|
||||
*(.gnu.linkonce.lit4.*)
|
||||
_lit4_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
*(.rodata_wlog)
|
||||
*(.rodata_wlog*)
|
||||
. = ALIGN(4);
|
||||
} GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)
|
||||
|
||||
#include <zephyr/linker/common-rom/common-rom-cpp.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-kernel-devices.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-ztest.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-net.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-bt.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-debug.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-misc.ld>
|
||||
#include <zephyr/linker/thread-local-storage.ld>
|
||||
#include <snippets-sections.ld>
|
||||
|
||||
/* Create an explicit section at the end of all the data that shall be mapped into drom.
|
||||
* This is used to calculate the size of the _image_drom_size variable */
|
||||
SECTION_PROLOGUE(_RODATA_SECTION_END,,ALIGN(0x10))
|
||||
{
|
||||
_rodata_reserved_end = ABSOLUTE(.);
|
||||
. = ALIGN(16);
|
||||
_image_rodata_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)
|
||||
|
||||
#if defined(CONFIG_ESP_SPIRAM)
|
||||
/* This section holds .ext_ram.bss data, and will be put in PSRAM */
|
||||
.ext_ram.bss (NOLOAD) :
|
||||
{
|
||||
_ext_ram_data_start = ABSOLUTE(.);
|
||||
_ext_ram_bss_start = ABSOLUTE(.);
|
||||
*(.ext_ram.bss*)
|
||||
. = ALIGN(4);
|
||||
_ext_ram_bss_end = ABSOLUTE(.);
|
||||
} > ext_ram_seg
|
||||
|
||||
.ext_ram_noinit (NOLOAD) :
|
||||
{
|
||||
#if defined(CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM)
|
||||
*libdrivers__wifi.a:(.noinit .noinit.*)
|
||||
*libsubsys__net__l2__ethernet.a:(.noinit .noinit.*)
|
||||
*libsubsys__net__lib__config.a:(.noinit .noinit.*)
|
||||
*libsubsys__net__ip.a:(.noinit .noinit.*)
|
||||
*libsubsys__net.a:(.noinit .noinit.*)
|
||||
#endif
|
||||
_spiram_heap_start = ABSOLUTE(.);
|
||||
. = . + CONFIG_ESP_SPIRAM_HEAP_SIZE;
|
||||
|
||||
_ext_ram_data_end = ABSOLUTE(.);
|
||||
} > ext_ram_seg
|
||||
#endif
|
||||
|
||||
/* Send .iram0 code to iram */
|
||||
.iram0.vectors : ALIGN(4)
|
||||
{
|
||||
_iram_start = ABSOLUTE(.);
|
||||
/* Vectors go to IRAM */
|
||||
_init_start = ABSOLUTE(.);
|
||||
/* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
|
||||
. = 0x0;
|
||||
KEEP(*(.WindowVectors.text));
|
||||
. = 0x180;
|
||||
KEEP(*(.Level2InterruptVector.text));
|
||||
. = 0x1c0;
|
||||
KEEP(*(.Level3InterruptVector.text));
|
||||
. = 0x200;
|
||||
KEEP(*(.Level4InterruptVector.text));
|
||||
. = 0x240;
|
||||
KEEP(*(.Level5InterruptVector.text));
|
||||
. = 0x280;
|
||||
KEEP(*(.DebugExceptionVector.text));
|
||||
. = 0x2c0;
|
||||
KEEP(*(.NMIExceptionVector.text));
|
||||
. = 0x300;
|
||||
KEEP(*(.KernelExceptionVector.text));
|
||||
. = 0x340;
|
||||
KEEP(*(.UserExceptionVector.text));
|
||||
. = 0x3C0;
|
||||
KEEP(*(.DoubleExceptionVector.text));
|
||||
. = 0x400;
|
||||
_invalid_pc_placeholder = ABSOLUTE(.);
|
||||
*(.*Vector.literal)
|
||||
|
||||
*(.UserEnter.literal);
|
||||
*(.UserEnter.text);
|
||||
. = ALIGN (16);
|
||||
*(.entry.text)
|
||||
*(.init.literal)
|
||||
*(.init)
|
||||
_init_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
|
||||
|
||||
.iram0.text : ALIGN(4)
|
||||
{
|
||||
/* Code marked as running out of IRAM */
|
||||
_iram_text_start = ABSOLUTE(.);
|
||||
*(.iram1 .iram1.*)
|
||||
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
|
||||
*libesp32.a:panic.*(.literal .text .literal.* .text.*)
|
||||
*librtc.a:(.literal .text .literal.* .text.*)
|
||||
*libarch__xtensa__core.a:(.literal .text .literal.* .text.*)
|
||||
*libkernel.a:(.literal .text .literal.* .text.*)
|
||||
*libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)
|
||||
*libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)
|
||||
*libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:spiram*.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:spi_timing*.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:spi_flash*.*(.literal .text .literal.* .text.*)
|
||||
*libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)
|
||||
*libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:systimer_hal.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:log_core.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)
|
||||
*libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:log_list.*(.literal .text .literal.* .text.*)
|
||||
*libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out)
|
||||
*libzephyr.a:log_output.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:loader.*(.literal .text .literal.* .text.*)
|
||||
*liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)
|
||||
*liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*)
|
||||
*libc.a:*(.literal .text .literal.* .text.*)
|
||||
*libphy.a:(.phyiram .phyiram.*)
|
||||
*libgcov.a:(.literal .text .literal.* .text.*)
|
||||
|
||||
#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)
|
||||
*libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*)
|
||||
*libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)
|
||||
*libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
|
||||
*libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
|
||||
#endif
|
||||
|
||||
. = ALIGN(4) + 16;
|
||||
|
||||
} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
|
||||
|
||||
/* Marks the end of IRAM code segment */
|
||||
.iram0.text_end (NOLOAD) :
|
||||
{
|
||||
/* ESP32-S3 memprot requires 16B padding for possible CPU
|
||||
* prefetch and 256B alignment for PMS split lines */
|
||||
. = ALIGN(16);
|
||||
_iram_text_end = ABSOLUTE(.);
|
||||
} GROUP_LINK_IN(IRAM_REGION)
|
||||
|
||||
.iram0.data :
|
||||
{
|
||||
. = ALIGN(16);
|
||||
*(.iram.data)
|
||||
*(.iram.data*)
|
||||
} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
|
||||
|
||||
.iram0.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(16);
|
||||
*(.iram.bss)
|
||||
*(.iram.bss*)
|
||||
|
||||
. = ALIGN(16);
|
||||
_iram_end = ABSOLUTE(.);
|
||||
} GROUP_LINK_IN(IRAM_REGION)
|
||||
|
||||
|
||||
/* This section is required to skip .iram0.text area because iram0_0_seg and
|
||||
* dram0_0_seg reflect the same address space on different buses.
|
||||
*/
|
||||
.dram0.dummy (NOLOAD):
|
||||
{
|
||||
. = ALIGN (8);
|
||||
. = ORIGIN(dram0_0_seg) + MAX(_iram_end, SRAM_DIRAM_I_START) - SRAM_DIRAM_I_START;
|
||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
||||
|
||||
/* Shared RAM */
|
||||
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_bss_start = ABSOLUTE(.); /* required by bluetooth library */
|
||||
__bss_start = ABSOLUTE(.);
|
||||
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.share.mem)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN (8);
|
||||
__bss_end = ABSOLUTE(.);
|
||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
||||
|
||||
ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.")
|
||||
|
||||
SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.noinit)
|
||||
*(.noinit.*)
|
||||
. = ALIGN(8) ;
|
||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
||||
|
||||
.dram0.data :
|
||||
{
|
||||
. = ALIGN (8);
|
||||
__data_start = ABSOLUTE(.);
|
||||
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
/* rodata for panic handler(libarch__xtensa__core.a) and all
|
||||
* dependent functions should be placed in DRAM to avoid issue
|
||||
* when flash cache is disabled */
|
||||
*libarch__xtensa__core.a:(.rodata .rodata.*)
|
||||
*libkernel.a:fatal.*(.rodata .rodata.*)
|
||||
*libkernel.a:init.*(.rodata .rodata.*)
|
||||
*libzephyr.a:cbprintf_complete*(.rodata .rodata.*)
|
||||
*libzephyr.a:systimer_hal.*(.rodata .rodata.*)
|
||||
*libzephyr.a:log_core.*(.rodata .rodata.*)
|
||||
*libzephyr.a:log_backend_uart.*(.rodata .rodata.*)
|
||||
*libzephyr.a:log_output.*(.rodata .rodata.*)
|
||||
*libzephyr.a:loader.*(.rodata .rodata.*)
|
||||
*libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)
|
||||
*libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*)
|
||||
|
||||
KEEP(*(.jcr))
|
||||
*(.dram1 .dram1.*)
|
||||
. = ALIGN(4);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
|
||||
|
||||
#include <zephyr/linker/cplusplus-rom.ld>
|
||||
#include <snippets-data-sections.ld>
|
||||
#include <zephyr/linker/common-ram.ld>
|
||||
#include <snippets-ram-sections.ld>
|
||||
#include <zephyr/linker/cplusplus-ram.ld>
|
||||
|
||||
/* logging sections should be placed in RAM area to avoid flash cache disabled issues */
|
||||
#pragma push_macro("GROUP_ROM_LINK_IN")
|
||||
#undef GROUP_ROM_LINK_IN
|
||||
#define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN
|
||||
#include <zephyr/linker/common-rom/common-rom-logging.ld>
|
||||
#pragma pop_macro("GROUP_ROM_LINK_IN")
|
||||
|
||||
.dram0.end :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
|
||||
#include <snippets-rwdata.ld>
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = ABSOLUTE(.);
|
||||
__data_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
|
||||
|
||||
_image_irom_start = LOADADDR(.flash.text);
|
||||
_image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start;
|
||||
_image_irom_vaddr = ADDR(.flash.text);
|
||||
|
||||
.flash_text_dummy (NOLOAD): ALIGN(IROM_SEG_ALIGN)
|
||||
{
|
||||
. = SIZEOF(_RODATA_SECTION_NAME);
|
||||
. = ALIGN(IROM_SEG_ALIGN) + 0x20;
|
||||
} GROUP_LINK_IN(FLASH_CODE_REGION)
|
||||
|
||||
.flash.text : ALIGN(IROM_SEG_ALIGN)
|
||||
{
|
||||
_stext = .;
|
||||
_text_start = ABSOLUTE(.);
|
||||
|
||||
#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)
|
||||
*libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*)
|
||||
*libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*)
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)
|
||||
*libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
|
||||
*libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
|
||||
#endif
|
||||
|
||||
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||||
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
|
||||
*(.fini.literal)
|
||||
*(.fini)
|
||||
*(.gnu.version)
|
||||
*(.literal .text .literal.* .text.*)
|
||||
|
||||
/* CPU will try to prefetch up to 16 bytes of
|
||||
* of instructions. This means that any configuration (e.g. MMU, PMS) must allow
|
||||
* safe access to up to 16 bytes after the last real instruction, add
|
||||
* dummy bytes to ensure this
|
||||
*/
|
||||
. += 16;
|
||||
|
||||
_text_end = ABSOLUTE(.);
|
||||
_etext = .;
|
||||
|
||||
/* Similar to _iram_start, this symbol goes here so it is
|
||||
* resolved by addr2line in preference to the first symbol in
|
||||
* the flash.text segment.
|
||||
*/
|
||||
_flash_cache_start = ABSOLUTE(0);
|
||||
} GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION)
|
||||
|
||||
/* RTC fast memory holds RTC wake stub code,
|
||||
* including from any source file named rtc_wake_stub*.c
|
||||
*/
|
||||
.rtc.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_rtc_text_start = ABSOLUTE(.);
|
||||
*(.rtc.literal .rtc.text)
|
||||
*(.rtc.entry.text)
|
||||
*rtc_wake_stub*.*(.literal .text .literal.* .text.*)
|
||||
_rtc_text_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION)
|
||||
|
||||
/* This section is required to skip rtc.text area because rtc_iram_seg and
|
||||
* rtc_data_seg are reflect the same address space on different buses.
|
||||
*/
|
||||
.rtc.dummy :
|
||||
{
|
||||
_rtc_dummy_start = ABSOLUTE(.);
|
||||
_rtc_fast_start = ABSOLUTE(.);
|
||||
. = SIZEOF(.rtc.text);
|
||||
_rtc_dummy_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(rtc_data_seg, ROMABLE_REGION)
|
||||
|
||||
/* This section located in RTC FAST Memory area.
|
||||
* It holds data marked with RTC_FAST_ATTR attribute.
|
||||
* See the file "esp_attr.h" for more information.
|
||||
*/
|
||||
.rtc.force_fast :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_rtc_force_fast_start = ABSOLUTE(.);
|
||||
|
||||
*(.rtc.force_fast .rtc.force_fast.*)
|
||||
. = ALIGN(4) ;
|
||||
_rtc_force_fast_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(rtc_data_seg, ROMABLE_REGION)
|
||||
|
||||
/* RTC data section holds RTC wake stub
|
||||
* data/rodata, including from any source file
|
||||
* named rtc_wake_stub*.c and the data marked with
|
||||
* RTC_DATA_ATTR, RTC_RODATA_ATTR attributes.
|
||||
*/
|
||||
.rtc.data :
|
||||
{
|
||||
_rtc_data_start = ABSOLUTE(.);
|
||||
*(.rtc.data)
|
||||
*(.rtc.rodata)
|
||||
*rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)
|
||||
_rtc_data_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION)
|
||||
|
||||
/* RTC bss, from any source file named rtc_wake_stub*.c */
|
||||
.rtc.bss (NOLOAD) :
|
||||
{
|
||||
_rtc_bss_start = ABSOLUTE(.);
|
||||
*rtc_wake_stub*.*(.bss .bss.*)
|
||||
*rtc_wake_stub*.*(COMMON)
|
||||
|
||||
*(.rtc.data)
|
||||
*(.rtc.rodata)
|
||||
|
||||
_rtc_bss_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION)
|
||||
|
||||
/* RTC bss, from any source file named rtc_wake_stub*.c */
|
||||
.rtc.bss (NOLOAD) :
|
||||
{
|
||||
_rtc_bss_start = ABSOLUTE(.);
|
||||
*rtc_wake_stub*.*(.bss .bss.*)
|
||||
*rtc_wake_stub*.*(COMMON)
|
||||
|
||||
_rtc_bss_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION)
|
||||
|
||||
/* This section holds data that should not be initialized at power up
|
||||
* and will be retained during deep sleep.
|
||||
* User data marked with RTC_NOINIT_ATTR will be placed
|
||||
* into this section. See the file "esp_attr.h" for more information.
|
||||
*/
|
||||
.rtc_noinit (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_rtc_noinit_start = ABSOLUTE(.);
|
||||
*(.rtc_noinit .rtc_noinit.*)
|
||||
. = ALIGN(4) ;
|
||||
_rtc_noinit_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION)
|
||||
|
||||
/* This section located in RTC SLOW Memory area.
|
||||
* It holds data marked with RTC_SLOW_ATTR attribute.
|
||||
* See the file "esp_attr.h" for more information.
|
||||
*/
|
||||
.rtc.force_slow :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_rtc_force_slow_start = ABSOLUTE(.);
|
||||
*(.rtc.force_slow .rtc.force_slow.*)
|
||||
. = ALIGN(4) ;
|
||||
_rtc_force_slow_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION)
|
||||
|
||||
/* Get size of rtc slow data based on rtc_data_location alias */
|
||||
_rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start);
|
||||
_rtc_fast_length = (_rtc_force_fast_end - _rtc_fast_start);
|
||||
|
||||
ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)), "RTC_SLOW segment data does not fit.")
|
||||
ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)), "RTC_FAST segment data does not fit.")
|
||||
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
#include <zephyr/linker/intlist.ld>
|
||||
#endif
|
||||
|
||||
_heap_sentry = 0x3fceb910;
|
||||
|
||||
#include <zephyr/linker/debug-sections.ld>
|
||||
|
||||
.xtensa.info 0 : { *(.xtensa.info) }
|
||||
.xt.insn 0 :
|
||||
{
|
||||
KEEP (*(.xt.insn))
|
||||
KEEP (*(.gnu.linkonce.x.*))
|
||||
}
|
||||
.xt.prop 0 :
|
||||
{
|
||||
KEEP (*(.xt.prop))
|
||||
KEEP (*(.xt.prop.*))
|
||||
KEEP (*(.gnu.linkonce.prop.*))
|
||||
}
|
||||
.xt.lit 0 :
|
||||
{
|
||||
KEEP (*(.xt.lit))
|
||||
KEEP (*(.xt.lit.*))
|
||||
KEEP (*(.gnu.linkonce.p.*))
|
||||
}
|
||||
.xt.profile_range 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_range))
|
||||
KEEP (*(.gnu.linkonce.profile_range.*))
|
||||
}
|
||||
.xt.profile_ranges 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_ranges))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
|
||||
}
|
||||
.xt.profile_files 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_files))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_files.*))
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
|
||||
"IRAM0 segment data does not fit.")
|
||||
|
||||
#if defined(CONFIG_ESP_SPIRAM)
|
||||
ASSERT(((_ext_ram_data_end - _ext_ram_data_start) <= CONFIG_ESP_SPIRAM_SIZE),
|
||||
"External SPIRAM overflowed.")
|
||||
#endif /* CONFIG_ESP_SPIRAM */
|
||||
372
soc/espressif/esp32s3/default_appcpu.ld
Normal file
372
soc/espressif/esp32s3/default_appcpu.ld
Normal file
|
|
@ -0,0 +1,372 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/linker/sections.h>
|
||||
#include <zephyr/linker/linker-defs.h>
|
||||
#include <zephyr/linker/linker-tool.h>
|
||||
|
||||
#define SRAM_IRAM_START 0x40370000
|
||||
#define SRAM_DIRAM_I_START 0x40378000
|
||||
#define SRAM_IRAM_END 0x403BA000
|
||||
#define I_D_SRAM_OFFSET (SRAM_DIRAM_I_START - SRAM_DRAM_START)
|
||||
|
||||
#define SRAM_DRAM_START 0x3FC88000
|
||||
#define SRAM_DRAM_END (SRAM_IRAM_END - I_D_SRAM_OFFSET)
|
||||
|
||||
#define IRAM_REGION iram0_0_seg
|
||||
#define RAMABLE_REGION dram0_0_seg
|
||||
#define ROMABLE_REGION iram0_0_seg
|
||||
|
||||
#define IROM_SEG_ALIGN 0x4
|
||||
|
||||
MEMORY
|
||||
{
|
||||
iram0_0_seg(RX): org = SRAM_IRAM_END - CONFIG_ESP32S3_APPCPU_IRAM, len = CONFIG_ESP32S3_APPCPU_IRAM
|
||||
dram0_0_seg(RW): org = SRAM_DRAM_END - CONFIG_ESP32S3_APPCPU_DRAM, len = CONFIG_ESP32S3_APPCPU_DRAM
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Default entry point: */
|
||||
ENTRY(__app_cpu_start)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
#include <zephyr/linker/rel-sections.ld>
|
||||
|
||||
/* Send .iram0 code to iram */
|
||||
.iram0.vectors : ALIGN(4)
|
||||
{
|
||||
/* Vectors go to IRAM */
|
||||
_init_start = ABSOLUTE(.);
|
||||
/* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
|
||||
. = 0x0;
|
||||
KEEP(*(.WindowVectors.text));
|
||||
. = 0x180;
|
||||
KEEP(*(.Level2InterruptVector.text));
|
||||
. = 0x1c0;
|
||||
KEEP(*(.Level3InterruptVector.text));
|
||||
. = 0x200;
|
||||
KEEP(*(.Level4InterruptVector.text));
|
||||
. = 0x240;
|
||||
KEEP(*(.Level5InterruptVector.text));
|
||||
. = 0x280;
|
||||
KEEP(*(.DebugExceptionVector.text));
|
||||
. = 0x2c0;
|
||||
KEEP(*(.NMIExceptionVector.text));
|
||||
. = 0x300;
|
||||
KEEP(*(.KernelExceptionVector.text));
|
||||
. = 0x340;
|
||||
KEEP(*(.UserExceptionVector.text));
|
||||
. = 0x3C0;
|
||||
KEEP(*(.DoubleExceptionVector.text));
|
||||
. = 0x400;
|
||||
_invalid_pc_placeholder = ABSOLUTE(.);
|
||||
*(.*Vector.literal)
|
||||
|
||||
*(.UserEnter.literal);
|
||||
*(.UserEnter.text);
|
||||
. = ALIGN (16);
|
||||
*(.entry.text)
|
||||
*(.init.literal)
|
||||
*(.init)
|
||||
. = ALIGN (4);
|
||||
_init_end = ABSOLUTE(.);
|
||||
|
||||
_iram_start = ABSOLUTE(.);
|
||||
} GROUP_LINK_IN(IRAM_REGION)
|
||||
|
||||
SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))
|
||||
{
|
||||
/* Code marked as running out of IRAM */
|
||||
_iram_text_start = ABSOLUTE(.);
|
||||
*(.iram1 .iram1.*)
|
||||
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
|
||||
*libesp32.a:panic.*(.literal .text .literal.* .text.*)
|
||||
*librtc.a:(.literal .text .literal.* .text.*)
|
||||
*libarch__xtensa__core.a:(.literal .text .literal.* .text.*)
|
||||
*libkernel.a:(.literal .text .literal.* .text.*)
|
||||
*libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)
|
||||
*libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)
|
||||
*libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)
|
||||
*libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)
|
||||
*libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:systimer_hal.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:log_core.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)
|
||||
*libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:log_list.*(.literal .text .literal.* .text.*)
|
||||
*libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out)
|
||||
*libzephyr.a:log_output.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:loader.*(.literal .text .literal.* .text.*)
|
||||
*liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)
|
||||
*liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*)
|
||||
*libc.a:*(.literal .text .literal.* .text.*)
|
||||
*libphy.a:(.phyiram .phyiram.*)
|
||||
*libgcov.a:(.literal .text .literal.* .text.*)
|
||||
|
||||
. = ALIGN(4);
|
||||
_iram_end = ABSOLUTE(.);
|
||||
. = ALIGN(4) + 16;
|
||||
|
||||
} GROUP_LINK_IN(IRAM_REGION)
|
||||
|
||||
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
|
||||
{
|
||||
_rodata_start = ABSOLUTE(.);
|
||||
|
||||
*(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */
|
||||
*(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */
|
||||
|
||||
__rodata_region_start = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
#include <snippets-rodata.ld>
|
||||
|
||||
. = ALIGN(4);
|
||||
*(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__serial.a:uart_esp32.*) .rodata)
|
||||
*(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__serial.a:uart_esp32.*) .rodata.*)
|
||||
|
||||
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
|
||||
*(.xt_except_table)
|
||||
*(.gcc_except_table .gcc_except_table.*)
|
||||
*(.gnu.linkonce.e.*)
|
||||
*(.gnu.version_r)
|
||||
. = (. + 3) & ~ 3;
|
||||
__eh_frame = ABSOLUTE(.);
|
||||
KEEP(*(.eh_frame))
|
||||
. = (. + 7) & ~ 3;
|
||||
|
||||
/* C++ exception handlers table: */
|
||||
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
|
||||
*(.xt_except_desc)
|
||||
*(.gnu.linkonce.h.*)
|
||||
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc_end)
|
||||
*(.dynamic)
|
||||
*(.gnu.version_d)
|
||||
. = ALIGN(4);
|
||||
__rodata_region_end = ABSOLUTE(.);
|
||||
/* Literals are also RO data. */
|
||||
_lit4_start = ABSOLUTE(.);
|
||||
*(*.lit4)
|
||||
*(.lit4.*)
|
||||
*(.gnu.linkonce.lit4.*)
|
||||
_lit4_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
_thread_local_start = ABSOLUTE(.);
|
||||
*(.tdata)
|
||||
*(.tdata.*)
|
||||
*(.tbss)
|
||||
*(.tbss.*)
|
||||
*(.rodata_wlog)
|
||||
*(.rodata_wlog*)
|
||||
_thread_local_end = ABSOLUTE(.);
|
||||
_rodata_reserved_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, IRAM_REGION)
|
||||
|
||||
/* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA.
|
||||
* Executing directly from LMA is not possible. */
|
||||
#pragma push_macro("GROUP_ROM_LINK_IN")
|
||||
#undef GROUP_ROM_LINK_IN
|
||||
#define GROUP_ROM_LINK_IN(vregion, lregion) > RAMABLE_REGION AT > lregion
|
||||
#include <zephyr/linker/common-rom/common-rom-cpp.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-kernel-devices.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-ztest.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-net.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-bt.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-debug.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-misc.ld>
|
||||
#pragma pop_macro("GROUP_ROM_LINK_IN")
|
||||
|
||||
/* Create an explicit section at the end of all the data that shall be mapped into drom.
|
||||
* This is used to calculate the size of the _image_drom_size variable */
|
||||
SECTION_PROLOGUE(_RODATA_SECTION_END,,)
|
||||
{
|
||||
. = ALIGN(16);
|
||||
_image_rodata_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, IRAM_REGION)
|
||||
|
||||
#include <snippets-sections.ld>
|
||||
|
||||
.dram0.data :
|
||||
{
|
||||
. = ALIGN (8);
|
||||
__data_start = ABSOLUTE(.);
|
||||
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
/* rodata for panic handler(libarch__xtensa__core.a) and all
|
||||
* dependent functions should be placed in DRAM to avoid issue
|
||||
* when flash cache is disabled */
|
||||
*libarch__xtensa__core.a:(.rodata .rodata.*)
|
||||
*libkernel.a:fatal.*(.rodata .rodata.*)
|
||||
*libkernel.a:init.*(.rodata .rodata.*)
|
||||
*libzephyr.a:cbprintf_complete*(.rodata .rodata.*)
|
||||
*libzephyr.a:systimer_hal.*(.rodata .rodata.*)
|
||||
*libzephyr.a:log_core.*(.rodata .rodata.*)
|
||||
*libzephyr.a:log_backend_uart.*(.rodata .rodata.*)
|
||||
*libzephyr.a:log_output.*(.rodata .rodata.*)
|
||||
*libzephyr.a:loader.*(.rodata .rodata.*)
|
||||
*libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)
|
||||
*libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*)
|
||||
|
||||
KEEP(*(.jcr))
|
||||
*(.dram1 .dram1.*)
|
||||
. = ALIGN(4);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, IRAM_REGION)
|
||||
|
||||
#include <zephyr/linker/cplusplus-rom.ld>
|
||||
#include <snippets-data-sections.ld>
|
||||
#include <zephyr/linker/common-ram.ld>
|
||||
#include <snippets-ram-sections.ld>
|
||||
#include <zephyr/linker/cplusplus-ram.ld>
|
||||
|
||||
/* logging sections should be placed in RAM area to avoid flash cache disabled issues */
|
||||
#pragma push_macro("GROUP_ROM_LINK_IN")
|
||||
#undef GROUP_ROM_LINK_IN
|
||||
#define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN
|
||||
#include <zephyr/linker/common-rom/common-rom-logging.ld>
|
||||
#pragma pop_macro("GROUP_ROM_LINK_IN")
|
||||
|
||||
.dram0.end :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
|
||||
#include <snippets-rwdata.ld>
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = ABSOLUTE(.);
|
||||
_heap_sentry = .;
|
||||
. = ALIGN(4);
|
||||
__data_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, IRAM_REGION)
|
||||
|
||||
/* Shared RAM */
|
||||
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_bss_start = ABSOLUTE(.); /* required by bluetooth library */
|
||||
__bss_start = ABSOLUTE(.);
|
||||
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.share.mem)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN (8);
|
||||
__bss_end = ABSOLUTE(.);
|
||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
||||
|
||||
ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.")
|
||||
|
||||
SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.noinit)
|
||||
*(.noinit.*)
|
||||
. = ALIGN(8) ;
|
||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
||||
|
||||
.flash.text : ALIGN(IROM_SEG_ALIGN)
|
||||
{
|
||||
_stext = .;
|
||||
_text_start = ABSOLUTE(.);
|
||||
|
||||
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||||
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
|
||||
*(.fini.literal)
|
||||
*(.fini)
|
||||
*(.gnu.version)
|
||||
*(.literal .text .literal.* .text.*)
|
||||
|
||||
/* CPU will try to prefetch up to 16 bytes of
|
||||
* of instructions. This means that any configuration (e.g. MMU, PMS) must allow
|
||||
* safe access to up to 16 bytes after the last real instruction, add
|
||||
* dummy bytes to ensure this
|
||||
*/
|
||||
. += 16;
|
||||
|
||||
_text_end = ABSOLUTE(.);
|
||||
_etext = .;
|
||||
|
||||
/* Similar to _iram_start, this symbol goes here so it is
|
||||
* resolved by addr2line in preference to the first symbol in
|
||||
* the flash.text segment.
|
||||
*/
|
||||
. = ALIGN(4);
|
||||
_flash_cache_start = ABSOLUTE(0);
|
||||
} GROUP_LINK_IN(IRAM_REGION)
|
||||
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
#include <zephyr/linker/intlist.ld>
|
||||
#endif
|
||||
|
||||
#include <zephyr/linker/debug-sections.ld>
|
||||
|
||||
.xtensa.info 0 : { *(.xtensa.info) }
|
||||
.xt.insn 0 :
|
||||
{
|
||||
KEEP (*(.xt.insn))
|
||||
KEEP (*(.gnu.linkonce.x.*))
|
||||
}
|
||||
.xt.prop 0 :
|
||||
{
|
||||
KEEP (*(.xt.prop))
|
||||
KEEP (*(.xt.prop.*))
|
||||
KEEP (*(.gnu.linkonce.prop.*))
|
||||
}
|
||||
.xt.lit 0 :
|
||||
{
|
||||
KEEP (*(.xt.lit))
|
||||
KEEP (*(.xt.lit.*))
|
||||
KEEP (*(.gnu.linkonce.p.*))
|
||||
}
|
||||
.xt.profile_range 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_range))
|
||||
KEEP (*(.gnu.linkonce.profile_range.*))
|
||||
}
|
||||
.xt.profile_ranges 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_ranges))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
|
||||
}
|
||||
.xt.profile_files 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_files))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_files.*))
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
|
||||
"IRAM0 segment data does not fit.")
|
||||
45
soc/espressif/esp32s3/esp32s3-mp.c
Normal file
45
soc/espressif/esp32s3/esp32s3-mp.c
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/device.h>
|
||||
#include <zephyr/kernel.h>
|
||||
#include <zephyr/spinlock.h>
|
||||
#include <zephyr/kernel_structs.h>
|
||||
|
||||
#include <soc.h>
|
||||
#include <esp_cpu.h>
|
||||
#include <hal/soc_hal.h>
|
||||
#include <hal/soc_ll.h>
|
||||
#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
|
||||
|
||||
static struct k_spinlock loglock;
|
||||
|
||||
void smp_log(const char *msg)
|
||||
{
|
||||
while (*msg) {
|
||||
esp_rom_uart_tx_one_char(*msg++);
|
||||
}
|
||||
esp_rom_uart_tx_one_char('\r');
|
||||
esp_rom_uart_tx_one_char('\n');
|
||||
}
|
||||
|
||||
void esp_appcpu_start(void *entry_point)
|
||||
{
|
||||
soc_ll_unstall_core(1);
|
||||
|
||||
if (!REG_GET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN)) {
|
||||
REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN);
|
||||
REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL);
|
||||
REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING);
|
||||
REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING);
|
||||
}
|
||||
|
||||
esp_rom_ets_set_appcpu_boot_addr((void *)entry_point);
|
||||
|
||||
ets_delay_us(50000);
|
||||
|
||||
smp_log("ESP32S3: CPU1 start sequence complete");
|
||||
}
|
||||
98
soc/espressif/esp32s3/loader.c
Normal file
98
soc/espressif/esp32s3/loader.c
Normal file
|
|
@ -0,0 +1,98 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/kernel.h>
|
||||
#include <soc.h>
|
||||
#include <zephyr/storage/flash_map.h>
|
||||
#include <esp_log.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#include <esp32s3/rom/cache.h>
|
||||
#include "esp32s3/dport_access.h"
|
||||
#include "soc/cache_memory.h"
|
||||
#include <soc/dport_reg.h>
|
||||
#include "soc/extmem_reg.h"
|
||||
#include <bootloader_flash_priv.h>
|
||||
|
||||
#ifdef CONFIG_BOOTLOADER_MCUBOOT
|
||||
|
||||
#define BOOT_LOG_INF(_fmt, ...) \
|
||||
ets_printf("[" CONFIG_SOC_SERIES "] [INF] " _fmt "\n\r", ##__VA_ARGS__)
|
||||
|
||||
#define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used))
|
||||
|
||||
extern uint32_t _image_irom_start, _image_irom_size, _image_irom_vaddr;
|
||||
extern uint32_t _image_drom_start, _image_drom_size, _image_drom_vaddr;
|
||||
|
||||
void __start(void);
|
||||
|
||||
static HDR_ATTR void (*_entry_point)(void) = &__start;
|
||||
|
||||
static int map_rom_segments(void)
|
||||
{
|
||||
int rc = 0;
|
||||
size_t _partition_offset = FIXED_PARTITION_OFFSET(slot0_partition);
|
||||
uint32_t _app_irom_start = _partition_offset + (uint32_t)&_image_irom_start;
|
||||
uint32_t _app_irom_size = (uint32_t)&_image_irom_size;
|
||||
uint32_t _app_irom_vaddr = (uint32_t)&_image_irom_vaddr;
|
||||
|
||||
uint32_t _app_drom_start = _partition_offset + (uint32_t)&_image_drom_start;
|
||||
uint32_t _app_drom_size = (uint32_t)&_image_drom_size;
|
||||
uint32_t _app_drom_vaddr = (uint32_t)&_image_drom_vaddr;
|
||||
|
||||
uint32_t autoload = Cache_Suspend_DCache();
|
||||
|
||||
Cache_Invalidate_DCache_All();
|
||||
|
||||
/* Clear the MMU entries that are already set up,
|
||||
* so the new app only has the mappings it creates.
|
||||
*/
|
||||
for (size_t i = 0; i < FLASH_MMU_TABLE_SIZE; i++) {
|
||||
FLASH_MMU_TABLE[i] = MMU_TABLE_INVALID_VAL;
|
||||
}
|
||||
|
||||
uint32_t drom_page_count = bootloader_cache_pages_to_map(_app_drom_size, _app_drom_vaddr);
|
||||
|
||||
rc |= esp_rom_Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH,
|
||||
_app_drom_vaddr & MMU_FLASH_MASK,
|
||||
_app_drom_start & MMU_FLASH_MASK,
|
||||
64, drom_page_count, 0);
|
||||
|
||||
uint32_t irom_page_count = bootloader_cache_pages_to_map(_app_irom_size, _app_irom_vaddr);
|
||||
|
||||
rc |= esp_rom_Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH,
|
||||
_app_irom_vaddr & MMU_FLASH_MASK,
|
||||
_app_irom_start & MMU_FLASH_MASK,
|
||||
64, irom_page_count, 0);
|
||||
|
||||
REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, EXTMEM_DCACHE_SHUT_CORE0_BUS);
|
||||
REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, EXTMEM_DCACHE_SHUT_CORE1_BUS);
|
||||
|
||||
Cache_Resume_DCache(autoload);
|
||||
|
||||
/* Show map segments continue using same log format as during MCUboot phase */
|
||||
BOOT_LOG_INF("DROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map",
|
||||
_app_drom_start, _app_drom_vaddr, _app_drom_size, _app_drom_size);
|
||||
BOOT_LOG_INF("IROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map\r\n",
|
||||
_app_irom_start, _app_irom_vaddr, _app_irom_size, _app_irom_size);
|
||||
esp_rom_uart_tx_wait_idle(0);
|
||||
|
||||
return rc;
|
||||
}
|
||||
#endif /* CONFIG_BOOTLOADER_MCUBOOT */
|
||||
|
||||
void __start(void)
|
||||
{
|
||||
#ifdef CONFIG_BOOTLOADER_MCUBOOT
|
||||
int err = map_rom_segments();
|
||||
|
||||
if (err != 0) {
|
||||
ets_printf("Failed to setup XIP, aborting\n");
|
||||
abort();
|
||||
}
|
||||
#endif
|
||||
__esp_platform_start();
|
||||
}
|
||||
374
soc/espressif/esp32s3/mcuboot.ld
Normal file
374
soc/espressif/esp32s3/mcuboot.ld
Normal file
|
|
@ -0,0 +1,374 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Linker command/script file
|
||||
*
|
||||
* Linker script for the Xtensa platform.
|
||||
*/
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/linker/sections.h>
|
||||
#include <zephyr/linker/linker-defs.h>
|
||||
#include <zephyr/linker/linker-tool.h>
|
||||
|
||||
#ifdef CONFIG_XIP
|
||||
#error "Xtensa bootloader cannot use XIP"
|
||||
#endif /* CONFIG_XIP */
|
||||
|
||||
/* Disable all romable LMA */
|
||||
#undef GROUP_DATA_LINK_IN
|
||||
#define GROUP_DATA_LINK_IN(vregion, lregion) > vregion
|
||||
|
||||
#define RAMABLE_REGION dram_seg
|
||||
#define RAMABLE_REGION_1 dram_seg
|
||||
|
||||
#define RODATA_REGION dram_seg
|
||||
#define ROMABLE_REGION dram_seg
|
||||
|
||||
#define IRAM_REGION iram_seg
|
||||
#define FLASH_CODE_REGION iram_seg
|
||||
|
||||
#define IROM_SEG_ALIGN 16
|
||||
|
||||
MEMORY
|
||||
{
|
||||
iram_seg(RWX) : org = 0x403B6000, len = 0x8000
|
||||
iram_loader_seg(RWX) : org = 0x403BE000, len = 0x2000
|
||||
dram_seg(RW) : org = 0x3FCD0000, len = 0x6000
|
||||
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Default entry point: */
|
||||
ENTRY(CONFIG_KERNEL_ENTRY)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(0x10))
|
||||
{
|
||||
__rodata_region_start = ABSOLUTE(.);
|
||||
|
||||
. = ALIGN(4);
|
||||
#include <snippets-rodata.ld>
|
||||
|
||||
. = ALIGN(4);
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
|
||||
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
|
||||
*(.xt_except_table)
|
||||
*(.gcc_except_table .gcc_except_table.*)
|
||||
*(.gnu.linkonce.e.*)
|
||||
*(.gnu.version_r)
|
||||
. = (. + 3) & ~ 3;
|
||||
__eh_frame = ABSOLUTE(.);
|
||||
KEEP(*(.eh_frame))
|
||||
. = (. + 7) & ~ 3;
|
||||
|
||||
/* C++ exception handlers table: */
|
||||
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
|
||||
*(.xt_except_desc)
|
||||
*(.gnu.linkonce.h.*)
|
||||
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc_end)
|
||||
*(.dynamic)
|
||||
*(.gnu.version_d)
|
||||
. = ALIGN(4);
|
||||
__rodata_region_end = ABSOLUTE(.);
|
||||
/* Literals are also RO data. */
|
||||
_lit4_start = ABSOLUTE(.);
|
||||
*(*.lit4)
|
||||
*(.lit4.*)
|
||||
*(.gnu.linkonce.lit4.*)
|
||||
_lit4_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
_thread_local_start = ABSOLUTE(.);
|
||||
*(.tdata)
|
||||
*(.tdata.*)
|
||||
*(.tbss)
|
||||
*(.tbss.*)
|
||||
*(.rodata_wlog)
|
||||
*(.rodata_wlog*)
|
||||
_thread_local_end = ABSOLUTE(.);
|
||||
/* _rodata_reserved_end = ABSOLUTE(.); */
|
||||
. = ALIGN(4);
|
||||
} GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)
|
||||
|
||||
#include <zephyr/linker/common-rom/common-rom-cpp.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-kernel-devices.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-debug.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-misc.ld>
|
||||
#include <snippets-sections.ld>
|
||||
|
||||
.dram0.data :
|
||||
{
|
||||
__data_start = ABSOLUTE(.);
|
||||
|
||||
_btdm_data_start = ABSOLUTE(.);
|
||||
*libbtdm_app.a:(.data .data.*)
|
||||
. = ALIGN (4);
|
||||
_btdm_data_end = ABSOLUTE(.);
|
||||
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
KEEP(*(.jcr))
|
||||
*(.dram1 .dram1.*)
|
||||
. = ALIGN(4);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
|
||||
|
||||
#include <zephyr/linker/cplusplus-rom.ld>
|
||||
#include <snippets-data-sections.ld>
|
||||
#include <zephyr/linker/common-ram.ld>
|
||||
#include <snippets-ram-sections.ld>
|
||||
#include <zephyr/linker/cplusplus-ram.ld>
|
||||
#include <zephyr/linker/common-rom/common-rom-logging.ld>
|
||||
|
||||
.dram0.end :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
#include <snippets-rwdata.ld>
|
||||
. = ALIGN(4);
|
||||
_end = ABSOLUTE(.);
|
||||
_heap_sentry = .;
|
||||
__data_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
|
||||
|
||||
/* Send .iram0 code to iram */
|
||||
.iram0.vectors : ALIGN(4)
|
||||
{
|
||||
/* Vectors go to IRAM */
|
||||
_init_start = ABSOLUTE(.);
|
||||
/* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
|
||||
. = 0x0;
|
||||
KEEP(*(.WindowVectors.text));
|
||||
. = 0x180;
|
||||
KEEP(*(.Level2InterruptVector.text));
|
||||
. = 0x1c0;
|
||||
KEEP(*(.Level3InterruptVector.text));
|
||||
. = 0x200;
|
||||
KEEP(*(.Level4InterruptVector.text));
|
||||
. = 0x240;
|
||||
KEEP(*(.Level5InterruptVector.text));
|
||||
. = 0x280;
|
||||
KEEP(*(.DebugExceptionVector.text));
|
||||
. = 0x2c0;
|
||||
KEEP(*(.NMIExceptionVector.text));
|
||||
. = 0x300;
|
||||
KEEP(*(.KernelExceptionVector.text));
|
||||
. = 0x340;
|
||||
KEEP(*(.UserExceptionVector.text));
|
||||
. = 0x3C0;
|
||||
KEEP(*(.DoubleExceptionVector.text));
|
||||
. = 0x400;
|
||||
_invalid_pc_placeholder = ABSOLUTE(.);
|
||||
*(.*Vector.literal)
|
||||
|
||||
*(.UserEnter.literal);
|
||||
*(.UserEnter.text);
|
||||
. = ALIGN (16);
|
||||
*(.entry.text)
|
||||
*(.init.literal)
|
||||
*(.init)
|
||||
_init_end = ABSOLUTE(.);
|
||||
|
||||
/* This goes here, not at top of linker script, so addr2line finds it last,
|
||||
* and uses it in preference to the first symbol in IRAM
|
||||
*/
|
||||
_iram_start = ABSOLUTE(0);
|
||||
} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
|
||||
|
||||
.iram_loader.text :
|
||||
{
|
||||
. = ALIGN (16);
|
||||
_loader_text_start = ABSOLUTE(.);
|
||||
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||||
*(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
|
||||
*libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_flash_config_esp32s3.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_init_common.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_random.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
|
||||
*libzephyr.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
|
||||
*libzephyr.a:bootloader_efuse_esp32s3.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_utility.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_sha.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_console.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_panic.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:bootloader_soc.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:esp_image_format.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:flash_encrypt.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:flash_partitions.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:secure_boot.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:esp_efuse_table.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:esp_efuse_fields.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:esp_efuse_api.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:esp_efuse_utility.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:esp_efuse_api_key_esp32xx.*(.literal .text .literal.* .text.*)
|
||||
*libzephyr.a:app_cpu_start.*(.literal .text .literal.* .text.*)
|
||||
*esp_mcuboot.*(.literal .text .literal.* .text.*)
|
||||
*esp_loader.*(.literal .text .literal.* .text.*)
|
||||
*(.fini.literal)
|
||||
*(.fini)
|
||||
*(.gnu.version)
|
||||
_loader_text_end = ABSOLUTE(.);
|
||||
} > iram_loader_seg
|
||||
|
||||
SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))
|
||||
{
|
||||
/* Code marked as running out of IRAM */
|
||||
_iram_text_start = ABSOLUTE(.);
|
||||
|
||||
*(.iram1 .iram1.*)
|
||||
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
|
||||
|
||||
. = ALIGN(16);
|
||||
_iram_text_end = ABSOLUTE(.); */
|
||||
_iram_end = ABSOLUTE(.);
|
||||
} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
|
||||
|
||||
/* Shared RAM */
|
||||
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_bss_start = ABSOLUTE(.); /* required by bluetooth library */
|
||||
__bss_start = ABSOLUTE(.);
|
||||
|
||||
_btdm_bss_start = ABSOLUTE(.);
|
||||
*libbtdm_app.a:(.bss .bss.* COMMON)
|
||||
. = ALIGN (4);
|
||||
_btdm_bss_end = ABSOLUTE(.);
|
||||
|
||||
/* Buffer for system heap should be placed in dram_seg */
|
||||
*libkernel.a:mempool.*(.noinit.kheap_buf__system_heap .noinit.*.kheap_buf__system_heap)
|
||||
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.share.mem)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN (8);
|
||||
__bss_end = ABSOLUTE(.);
|
||||
_bss_end = ABSOLUTE(.);
|
||||
_end = ABSOLUTE(.);
|
||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
||||
|
||||
ASSERT(((__bss_end - ORIGIN(dram_seg)) <= LENGTH(dram_seg)), "DRAM segment data does not fit.")
|
||||
|
||||
SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.noinit)
|
||||
*(.noinit.*)
|
||||
. = ALIGN(8) ;
|
||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
||||
|
||||
.flash.text :
|
||||
{
|
||||
_stext = .;
|
||||
_text_start = ABSOLUTE(.);
|
||||
|
||||
*(.literal .text .literal.* .text.*)
|
||||
. = ALIGN(4);
|
||||
|
||||
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||||
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
|
||||
*(.fini.literal)
|
||||
*(.fini)
|
||||
*(.gnu.version)
|
||||
|
||||
/* CPU will try to prefetch up to 16 bytes of
|
||||
* of instructions. This means that any configuration (e.g. MMU, PMS) must allow
|
||||
* safe access to up to 16 bytes after the last real instruction, add
|
||||
* dummy bytes to ensure this
|
||||
*/
|
||||
. += 16;
|
||||
|
||||
_text_end = ABSOLUTE(.);
|
||||
_etext = .;
|
||||
|
||||
/* Similar to _iram_start, this symbol goes here so it is
|
||||
* resolved by addr2line in preference to the first symbol in
|
||||
* the flash.text segment.
|
||||
*/
|
||||
_flash_cache_start = ABSOLUTE(0);
|
||||
} GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION)
|
||||
|
||||
#include <zephyr/linker/debug-sections.ld>
|
||||
|
||||
.xtensa.info 0 : { *(.xtensa.info) }
|
||||
.xt.insn 0 :
|
||||
{
|
||||
KEEP (*(.xt.insn))
|
||||
KEEP (*(.gnu.linkonce.x.*))
|
||||
}
|
||||
.xt.prop 0 :
|
||||
{
|
||||
KEEP (*(.xt.prop))
|
||||
KEEP (*(.xt.prop.*))
|
||||
KEEP (*(.gnu.linkonce.prop.*))
|
||||
}
|
||||
.xt.lit 0 :
|
||||
{
|
||||
KEEP (*(.xt.lit))
|
||||
KEEP (*(.xt.lit.*))
|
||||
KEEP (*(.gnu.linkonce.p.*))
|
||||
}
|
||||
.xt.profile_range 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_range))
|
||||
KEEP (*(.gnu.linkonce.profile_range.*))
|
||||
}
|
||||
.xt.profile_ranges 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_ranges))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
|
||||
}
|
||||
.xt.profile_files 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_files))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_files.*))
|
||||
}
|
||||
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
#include <zephyr/linker/intlist.ld>
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
ASSERT(((_iram_end - ORIGIN(IRAM_REGION)) <= LENGTH(IRAM_REGION)),
|
||||
"IRAM0 segment data does not fit.")
|
||||
22
soc/espressif/esp32s3/newlib_fix.c
Normal file
22
soc/espressif/esp32s3/newlib_fix.c
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* Copyright (c) 2019, Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/toolchain.h>
|
||||
#include <stdio.h>
|
||||
#include <stddef.h>
|
||||
#include <unistd.h>
|
||||
#include <sys/stat.h>
|
||||
|
||||
#include <reent.h>
|
||||
|
||||
int __weak _gettimeofday_r(struct _reent *r, struct timeval *__tp, void *__tzp)
|
||||
{
|
||||
ARG_UNUSED(r);
|
||||
ARG_UNUSED(__tp);
|
||||
ARG_UNUSED(__tzp);
|
||||
|
||||
return -1;
|
||||
}
|
||||
80
soc/espressif/esp32s3/pinctrl_soc.h
Normal file
80
soc/espressif/esp32s3/pinctrl_soc.h
Normal file
|
|
@ -0,0 +1,80 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* ESP32S3 SoC specific helpers for pinctrl driver
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_XTENSA_ESP32S3_PINCTRL_SOC_H_
|
||||
#define ZEPHYR_SOC_XTENSA_ESP32S3_PINCTRL_SOC_H_
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/types.h>
|
||||
|
||||
#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
|
||||
|
||||
/** @cond INTERNAL_HIDDEN */
|
||||
|
||||
/** Type for ESP32 pin. */
|
||||
struct pinctrl_soc_pin {
|
||||
/** Pinmux settings (pin, direction and signal). */
|
||||
uint32_t pinmux;
|
||||
/** Pincfg settings (bias). */
|
||||
uint32_t pincfg;
|
||||
};
|
||||
|
||||
typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize pinmux field in #pinctrl_pin_t.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
*/
|
||||
#define Z_PINCTRL_ESP32_PINMUX_INIT(node_id, prop, idx) DT_PROP_BY_IDX(node_id, prop, idx)
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
*/
|
||||
#define Z_PINCTRL_ESP32_PINCFG_INIT(node_id) \
|
||||
(((ESP32_NO_PULL * DT_PROP(node_id, bias_disable)) << ESP32_PIN_BIAS_SHIFT) | \
|
||||
((ESP32_PULL_UP * DT_PROP(node_id, bias_pull_up)) << ESP32_PIN_BIAS_SHIFT) | \
|
||||
((ESP32_PULL_DOWN * DT_PROP(node_id, bias_pull_down)) << ESP32_PIN_BIAS_SHIFT) | \
|
||||
((ESP32_PUSH_PULL * DT_PROP(node_id, drive_push_pull)) << ESP32_PIN_DRV_SHIFT) | \
|
||||
((ESP32_OPEN_DRAIN * DT_PROP(node_id, drive_open_drain)) << ESP32_PIN_DRV_SHIFT) | \
|
||||
((ESP32_PIN_OUT_HIGH * DT_PROP(node_id, output_high)) << ESP32_PIN_OUT_SHIFT) | \
|
||||
((ESP32_PIN_OUT_LOW * DT_PROP(node_id, output_low)) << ESP32_PIN_OUT_SHIFT) | \
|
||||
((ESP32_PIN_OUT_EN * DT_PROP(node_id, output_enable)) << ESP32_PIN_EN_DIR_SHIFT) | \
|
||||
((ESP32_PIN_IN_EN * DT_PROP(node_id, input_enable)) << ESP32_PIN_EN_DIR_SHIFT))
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize each pin.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param prop Property name.
|
||||
* @param idx Property entry index.
|
||||
*/
|
||||
#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
|
||||
{.pinmux = Z_PINCTRL_ESP32_PINMUX_INIT(node_id, prop, idx), \
|
||||
.pincfg = Z_PINCTRL_ESP32_PINCFG_INIT(node_id)},
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize state pins contained in a given property.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param prop Property name describing state pins.
|
||||
*/
|
||||
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||
{ \
|
||||
DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \
|
||||
Z_PINCTRL_STATE_PIN_INIT) \
|
||||
}
|
||||
|
||||
/** @endcond */
|
||||
|
||||
#endif /* ZEPHYR_SOC_XTENSA_ESP32S3_PINCTRL_SOC_H_ */
|
||||
322
soc/espressif/esp32s3/soc.c
Normal file
322
soc/espressif/esp32s3/soc.c
Normal file
|
|
@ -0,0 +1,322 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Intel Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* Include esp-idf headers first to avoid redefining BIT() macro */
|
||||
#include <soc.h>
|
||||
#include <soc/rtc_cntl_reg.h>
|
||||
#include <soc/timer_group_reg.h>
|
||||
#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
|
||||
#include <xtensa/config/core-isa.h>
|
||||
#include <xtensa/corebits.h>
|
||||
|
||||
#include <zephyr/kernel_structs.h>
|
||||
#include <string.h>
|
||||
#include <zephyr/toolchain.h>
|
||||
#include <zephyr/types.h>
|
||||
#include <zephyr/linker/linker-defs.h>
|
||||
#include <kernel_internal.h>
|
||||
#include <zephyr/sys/util.h>
|
||||
|
||||
#include "esp_private/system_internal.h"
|
||||
#include "esp32s3/rom/cache.h"
|
||||
#include "esp32s3/rom/rtc.h"
|
||||
#include "soc/syscon_reg.h"
|
||||
#include "hal/soc_ll.h"
|
||||
#include "hal/wdt_hal.h"
|
||||
#include "soc/cpu.h"
|
||||
#include "soc/gpio_periph.h"
|
||||
#include "esp_spi_flash.h"
|
||||
#include "esp_err.h"
|
||||
#include "esp_timer.h"
|
||||
#include "esp_app_format.h"
|
||||
#include "esp_clk_internal.h"
|
||||
|
||||
#include "esp32s3/spiram.h"
|
||||
|
||||
#ifdef CONFIG_MCUBOOT
|
||||
#include "bootloader_init.h"
|
||||
#endif /* CONFIG_MCUBOOT */
|
||||
#include <zephyr/sys/printk.h>
|
||||
|
||||
#if CONFIG_ESP_SPIRAM
|
||||
extern int _ext_ram_bss_start;
|
||||
extern int _ext_ram_bss_end;
|
||||
#endif
|
||||
|
||||
extern void z_cstart(void);
|
||||
extern void esp_reset_reason_init(void);
|
||||
|
||||
#if CONFIG_SOC_ENABLE_APPCPU
|
||||
extern const unsigned char esp32s3_appcpu_fw_array[];
|
||||
|
||||
void IRAM_ATTR esp_start_appcpu(void)
|
||||
{
|
||||
esp_image_header_t *header = (esp_image_header_t *)&esp32s3_appcpu_fw_array[0];
|
||||
esp_image_segment_header_t *segment =
|
||||
(esp_image_segment_header_t *)&esp32s3_appcpu_fw_array[sizeof(esp_image_header_t)];
|
||||
uint8_t *segment_payload;
|
||||
uint32_t entry_addr = header->entry_addr;
|
||||
uint32_t idx = sizeof(esp_image_header_t) + sizeof(esp_image_segment_header_t);
|
||||
|
||||
for (int i = 0; i < header->segment_count; i++) {
|
||||
segment_payload = (uint8_t *)&esp32s3_appcpu_fw_array[idx];
|
||||
|
||||
if (segment->load_addr >= SOC_IRAM_LOW && segment->load_addr < SOC_IRAM_HIGH) {
|
||||
/* IRAM segment only accepts 4 byte access, avoid memcpy usage here */
|
||||
volatile uint32_t *src = (volatile uint32_t *)segment_payload;
|
||||
volatile uint32_t *dst = (volatile uint32_t *)segment->load_addr;
|
||||
|
||||
for (int i = 0; i < segment->data_len / 4; i++) {
|
||||
dst[i] = src[i];
|
||||
}
|
||||
|
||||
} else if (segment->load_addr >= SOC_DRAM_LOW &&
|
||||
segment->load_addr < SOC_DRAM_HIGH) {
|
||||
memcpy((void *)segment->load_addr, (const void *)segment_payload,
|
||||
segment->data_len);
|
||||
}
|
||||
|
||||
idx += segment->data_len;
|
||||
segment = (esp_image_segment_header_t *)&esp32s3_appcpu_fw_array[idx];
|
||||
idx += sizeof(esp_image_segment_header_t);
|
||||
}
|
||||
|
||||
esp_appcpu_start((void *)entry_addr);
|
||||
}
|
||||
#endif /* CONFIG_SOC_ENABLE_APPCPU */
|
||||
|
||||
#ifndef CONFIG_MCUBOOT
|
||||
/*
|
||||
* This function is a container for SoC patches
|
||||
* that needs to be applied during the startup.
|
||||
*/
|
||||
static void IRAM_ATTR esp_errata(void)
|
||||
{
|
||||
/* Handle the clock gating fix */
|
||||
REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN);
|
||||
/* The clock gating signal of the App core is invalid. We use RUNSTALL and RESETTING
|
||||
* signals to ensure that the App core stops running in single-core mode.
|
||||
*/
|
||||
REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL);
|
||||
REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING);
|
||||
|
||||
/* Handle the Dcache case following the IDF startup code */
|
||||
#if CONFIG_ESP32S3_DATA_CACHE_16KB
|
||||
Cache_Invalidate_DCache_All();
|
||||
Cache_Occupy_Addr(SOC_DROM_LOW, 0x4000);
|
||||
#endif
|
||||
}
|
||||
#endif /* CONFIG_MCUBOOT */
|
||||
|
||||
/*
|
||||
* This is written in C rather than assembly since, during the port bring up,
|
||||
* Zephyr is being booted by the Espressif bootloader. With it, the C stack
|
||||
* is already set up.
|
||||
*/
|
||||
void IRAM_ATTR __esp_platform_start(void)
|
||||
{
|
||||
extern uint32_t _init_start;
|
||||
|
||||
/* Move the exception vector table to IRAM. */
|
||||
__asm__ __volatile__("wsr %0, vecbase" : : "r"(&_init_start));
|
||||
|
||||
z_bss_zero();
|
||||
|
||||
/* Disable normal interrupts. */
|
||||
__asm__ __volatile__("wsr %0, PS" : : "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE));
|
||||
|
||||
/* Initialize the architecture CPU pointer. Some of the
|
||||
* initialization code wants a valid _current before
|
||||
* arch_kernel_init() is invoked.
|
||||
*/
|
||||
__asm__ __volatile__("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0]));
|
||||
|
||||
#ifdef CONFIG_MCUBOOT
|
||||
/* MCUboot early initialisation. */
|
||||
if (bootloader_init()) {
|
||||
abort();
|
||||
}
|
||||
#else
|
||||
/* Configure the mode of instruction cache : cache size, cache line size. */
|
||||
esp_config_instruction_cache_mode();
|
||||
|
||||
/* If we need use SPIRAM, we should use data cache.
|
||||
* Configure the mode of data : cache size, cache line size.
|
||||
*/
|
||||
esp_config_data_cache_mode();
|
||||
|
||||
/* Apply SoC patches */
|
||||
esp_errata();
|
||||
|
||||
#if CONFIG_ESP_SPIRAM
|
||||
esp_err_t err = esp_spiram_init();
|
||||
|
||||
if (err != ESP_OK) {
|
||||
printk("Failed to Initialize external RAM, aborting.\n");
|
||||
abort();
|
||||
}
|
||||
|
||||
esp_spiram_init_cache();
|
||||
if (esp_spiram_get_size() < CONFIG_ESP_SPIRAM_SIZE) {
|
||||
printk("External RAM size is less than configured, aborting.\n");
|
||||
abort();
|
||||
}
|
||||
|
||||
if (!esp_spiram_test()) {
|
||||
printk("External RAM failed memory test!\n");
|
||||
abort();
|
||||
}
|
||||
|
||||
memset(&_ext_ram_bss_start, 0,
|
||||
(&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start));
|
||||
|
||||
#endif /* CONFIG_ESP_SPIRAM */
|
||||
|
||||
/* ESP-IDF/MCUboot 2nd stage bootloader enables RTC WDT to check on startup sequence
|
||||
* related issues in application. Hence disable that as we are about to start
|
||||
* Zephyr environment.
|
||||
*/
|
||||
wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
|
||||
|
||||
wdt_hal_write_protect_disable(&rtc_wdt_ctx);
|
||||
wdt_hal_disable(&rtc_wdt_ctx);
|
||||
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
|
||||
|
||||
esp_reset_reason_init();
|
||||
|
||||
esp_clk_init();
|
||||
|
||||
esp_timer_early_init();
|
||||
|
||||
#if CONFIG_SOC_ENABLE_APPCPU
|
||||
/* start the ESP32S3 APP CPU */
|
||||
esp_start_appcpu();
|
||||
#endif
|
||||
|
||||
#if CONFIG_SOC_FLASH_ESP32
|
||||
spi_flash_guard_set(&g_flash_guard_default_ops);
|
||||
#endif
|
||||
#endif /* CONFIG_MCUBOOT */
|
||||
|
||||
esp_intr_initialize();
|
||||
|
||||
/* Start Zephyr */
|
||||
z_cstart();
|
||||
|
||||
CODE_UNREACHABLE;
|
||||
}
|
||||
|
||||
/* Boot-time static default printk handler, possibly to be overridden later. */
|
||||
int IRAM_ATTR arch_printk_char_out(int c)
|
||||
{
|
||||
if (c == '\n') {
|
||||
esp_rom_uart_tx_one_char('\r');
|
||||
}
|
||||
esp_rom_uart_tx_one_char(c);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void sys_arch_reboot(int type)
|
||||
{
|
||||
esp_restart_noos();
|
||||
}
|
||||
|
||||
void IRAM_ATTR esp_restart_noos(void)
|
||||
{
|
||||
/* disable interrupts */
|
||||
z_xt_ints_off(0xFFFFFFFF);
|
||||
|
||||
/* enable RTC watchdog for 1 second */
|
||||
wdt_hal_context_t wdt_ctx;
|
||||
uint32_t timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
|
||||
|
||||
wdt_hal_init(&wdt_ctx, WDT_RWDT, 0, false);
|
||||
wdt_hal_write_protect_disable(&wdt_ctx);
|
||||
wdt_hal_config_stage(&wdt_ctx, WDT_STAGE0, timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
|
||||
wdt_hal_config_stage(&wdt_ctx, WDT_STAGE1, timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
|
||||
|
||||
/* enable flash boot mode so that flash booting after restart is protected by the RTC WDT */
|
||||
wdt_hal_set_flashboot_en(&wdt_ctx, true);
|
||||
wdt_hal_write_protect_enable(&wdt_ctx);
|
||||
|
||||
/* disable TG0/TG1 watchdogs */
|
||||
wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
|
||||
|
||||
wdt_hal_write_protect_disable(&wdt0_context);
|
||||
wdt_hal_disable(&wdt0_context);
|
||||
wdt_hal_write_protect_enable(&wdt0_context);
|
||||
|
||||
wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
|
||||
|
||||
wdt_hal_write_protect_disable(&wdt1_context);
|
||||
wdt_hal_disable(&wdt1_context);
|
||||
wdt_hal_write_protect_enable(&wdt1_context);
|
||||
|
||||
/* Flush any data left in UART FIFOs */
|
||||
esp_rom_uart_tx_wait_idle(0);
|
||||
esp_rom_uart_tx_wait_idle(1);
|
||||
esp_rom_uart_tx_wait_idle(2);
|
||||
|
||||
/* Disable cache */
|
||||
Cache_Disable_ICache();
|
||||
Cache_Disable_DCache();
|
||||
|
||||
const uint32_t core_id = cpu_hal_get_core_id();
|
||||
#if CONFIG_SMP
|
||||
const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
|
||||
|
||||
soc_ll_reset_core(other_core_id);
|
||||
soc_ll_stall_core(other_core_id);
|
||||
#endif
|
||||
|
||||
/* 2nd stage bootloader reconfigures SPI flash signals. */
|
||||
/* Reset them to the defaults expected by ROM */
|
||||
WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
|
||||
|
||||
/* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */
|
||||
SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,
|
||||
SYSTEM_BB_RST | SYSTEM_FE_RST | SYSTEM_MAC_RST | SYSTEM_BT_RST |
|
||||
SYSTEM_BTMAC_RST | SYSTEM_SDIO_RST | SYSTEM_SDIO_HOST_RST |
|
||||
SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | SYSTEM_RW_BTMAC_RST |
|
||||
SYSTEM_RW_BTLP_RST | SYSTEM_BLE_REG_RST | SYSTEM_PWR_REG_RST);
|
||||
REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
|
||||
|
||||
/* Reset timer/spi/uart */
|
||||
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST |
|
||||
SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST);
|
||||
REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0);
|
||||
|
||||
/* Reset DMA */
|
||||
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);
|
||||
REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0);
|
||||
|
||||
SET_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET);
|
||||
CLEAR_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET);
|
||||
|
||||
rtc_clk_cpu_freq_set_xtal();
|
||||
|
||||
/* Reset CPUs */
|
||||
if (core_id == 0) {
|
||||
/* Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. */
|
||||
soc_ll_reset_core(1);
|
||||
soc_ll_reset_core(0);
|
||||
} else {
|
||||
/* Running on APP CPU: need to reset PRO CPU and unstall it, */
|
||||
/* then reset APP CPU */
|
||||
soc_ll_reset_core(0);
|
||||
soc_ll_stall_core(0);
|
||||
soc_ll_reset_core(1);
|
||||
}
|
||||
|
||||
while (true) {
|
||||
;
|
||||
}
|
||||
}
|
||||
81
soc/espressif/esp32s3/soc.h
Normal file
81
soc/espressif/esp32s3/soc.h
Normal file
|
|
@ -0,0 +1,81 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Intel Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __SOC_H__
|
||||
#define __SOC_H__
|
||||
#include <soc/dport_reg.h>
|
||||
#include <soc/rtc_cntl_reg.h>
|
||||
#include <soc/soc_caps.h>
|
||||
#include <esp32s3/rom/ets_sys.h>
|
||||
#include <esp32s3/rom/spi_flash.h>
|
||||
#include "esp32s3/rom/cache.h"
|
||||
#include <esp_rom_uart.h>
|
||||
#include "soc/extmem_reg.h"
|
||||
#include "soc/cache_memory.h"
|
||||
#include "hal/cpu_hal.h"
|
||||
#include "hal/cpu_types.h"
|
||||
#include <esp_rom_sys.h>
|
||||
|
||||
#include <zephyr/types.h>
|
||||
#include <stdbool.h>
|
||||
#include <zephyr/arch/xtensa/arch.h>
|
||||
|
||||
#include <xtensa/core-macros.h>
|
||||
#include <esp32s3/clk.h>
|
||||
|
||||
void __esp_platform_start(void);
|
||||
|
||||
static inline void esp32_set_mask32(uint32_t v, uint32_t mem_addr)
|
||||
{
|
||||
sys_write32(sys_read32(mem_addr) | v, mem_addr);
|
||||
}
|
||||
|
||||
static inline void esp32_clear_mask32(uint32_t v, uint32_t mem_addr)
|
||||
{
|
||||
sys_write32(sys_read32(mem_addr) & ~v, mem_addr);
|
||||
}
|
||||
|
||||
static inline uint32_t esp_core_id(void)
|
||||
{
|
||||
uint32_t id;
|
||||
|
||||
__asm__ volatile (
|
||||
"rsr.prid %0\n"
|
||||
"extui %0,%0,13,1" : "=r" (id));
|
||||
return id;
|
||||
}
|
||||
|
||||
extern void esp_rom_intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
|
||||
|
||||
extern int esp_rom_gpio_matrix_in(uint32_t gpio, uint32_t signal_index,
|
||||
bool inverted);
|
||||
extern int esp_rom_gpio_matrix_out(uint32_t gpio, uint32_t signal_index,
|
||||
bool out_inverted,
|
||||
bool out_enabled_inverted);
|
||||
|
||||
extern void esp_rom_uart_attach(void);
|
||||
extern void esp_rom_uart_tx_wait_idle(uint8_t uart_no);
|
||||
extern int esp_rom_uart_tx_one_char(uint8_t chr);
|
||||
extern int esp_rom_uart_rx_one_char(uint8_t *chr);
|
||||
extern void esp_rom_uart_set_clock_baudrate(uint8_t uart_no, uint32_t clock_hz, uint32_t baud_rate);
|
||||
|
||||
extern void esp_rom_ets_set_appcpu_boot_addr(void *addr);
|
||||
void esp_appcpu_start(void *entry_point);
|
||||
|
||||
extern int esp_rom_Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr,
|
||||
uint32_t psize, uint32_t num, uint32_t fixed);
|
||||
extern int esp_rom_Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr,
|
||||
uint32_t psize, uint32_t num, uint32_t fixed);
|
||||
|
||||
/* ROM functions which read/write internal i2c control bus for PLL, APLL */
|
||||
extern uint8_t esp_rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add);
|
||||
extern void esp_rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
|
||||
|
||||
/* cache initialization functions */
|
||||
void esp_config_instruction_cache_mode(void);
|
||||
void esp_config_data_cache_mode(void);
|
||||
|
||||
#endif /* __SOC_H__ */
|
||||
172
soc/espressif/esp32s3/soc_appcpu.c
Normal file
172
soc/espressif/esp32s3/soc_appcpu.c
Normal file
|
|
@ -0,0 +1,172 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <soc.h>
|
||||
#include <soc/rtc_cntl_reg.h>
|
||||
#include <soc/timer_group_reg.h>
|
||||
#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
|
||||
#include <xtensa/config/core-isa.h>
|
||||
#include <xtensa/corebits.h>
|
||||
|
||||
#include <zephyr/kernel_structs.h>
|
||||
#include <string.h>
|
||||
#include <zephyr/toolchain/gcc.h>
|
||||
#include <zephyr/types.h>
|
||||
#include <zephyr/linker/linker-defs.h>
|
||||
#include <kernel_internal.h>
|
||||
#include <zephyr/sys/util.h>
|
||||
|
||||
#include <esp_private/system_internal.h>
|
||||
#include <esp32s3/rom/cache.h>
|
||||
#include <esp32s3/rom/rtc.h>
|
||||
#include <soc/syscon_reg.h>
|
||||
#include <hal/soc_ll.h>
|
||||
#include <hal/wdt_hal.h>
|
||||
#include <soc/cpu.h>
|
||||
#include <soc/gpio_periph.h>
|
||||
#include <esp_spi_flash.h>
|
||||
#include <esp_err.h>
|
||||
#include <esp_timer.h>
|
||||
#include <esp_app_format.h>
|
||||
#include <esp_clk_internal.h>
|
||||
|
||||
extern void z_cstart(void);
|
||||
|
||||
static void core_intr_matrix_clear(void)
|
||||
{
|
||||
uint32_t core_id = cpu_hal_get_core_id();
|
||||
|
||||
for (int i = 0; i < ETS_MAX_INTR_SOURCE; i++) {
|
||||
intr_matrix_set(core_id, i, ETS_INVALID_INUM);
|
||||
}
|
||||
}
|
||||
|
||||
void IRAM_ATTR __app_cpu_start(void)
|
||||
{
|
||||
extern uint32_t _init_start;
|
||||
extern uint32_t _bss_start;
|
||||
extern uint32_t _bss_end;
|
||||
|
||||
/* Move the exception vector table to IRAM. */
|
||||
__asm__ __volatile__("wsr %0, vecbase" : : "r"(&_init_start));
|
||||
|
||||
/* Zero out BSS. Clobber _bss_start to avoid memset() elision. */
|
||||
z_bss_zero();
|
||||
|
||||
__asm__ __volatile__("" : : "g"(&__bss_start) : "memory");
|
||||
|
||||
/* Disable normal interrupts. */
|
||||
__asm__ __volatile__("wsr %0, PS" : : "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE));
|
||||
|
||||
/* Initialize the architecture CPU pointer. Some of the
|
||||
* initialization code wants a valid _current before
|
||||
* arch_kernel_init() is invoked.
|
||||
*/
|
||||
__asm__ __volatile__("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[1]));
|
||||
|
||||
core_intr_matrix_clear();
|
||||
|
||||
esp_intr_initialize();
|
||||
|
||||
/* Start Zephyr */
|
||||
z_cstart();
|
||||
|
||||
CODE_UNREACHABLE;
|
||||
}
|
||||
|
||||
/* Boot-time static default printk handler, possibly to be overridden later. */
|
||||
int IRAM_ATTR arch_printk_char_out(int c)
|
||||
{
|
||||
ARG_UNUSED(c);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void sys_arch_reboot(int type)
|
||||
{
|
||||
esp_restart_noos();
|
||||
}
|
||||
|
||||
void IRAM_ATTR esp_restart_noos(void)
|
||||
{
|
||||
/* disable interrupts */
|
||||
z_xt_ints_off(0xFFFFFFFF);
|
||||
|
||||
/* enable RTC watchdog for 1 second */
|
||||
wdt_hal_context_t wdt_ctx;
|
||||
uint32_t timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
|
||||
|
||||
wdt_hal_init(&wdt_ctx, WDT_RWDT, 0, false);
|
||||
wdt_hal_write_protect_disable(&wdt_ctx);
|
||||
wdt_hal_config_stage(&wdt_ctx, WDT_STAGE0, timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
|
||||
wdt_hal_config_stage(&wdt_ctx, WDT_STAGE1, timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
|
||||
|
||||
/* enable flash boot mode so that flash booting after restart is protected by the RTC WDT */
|
||||
wdt_hal_set_flashboot_en(&wdt_ctx, true);
|
||||
wdt_hal_write_protect_enable(&wdt_ctx);
|
||||
|
||||
/* disable TG0/TG1 watchdogs */
|
||||
wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
|
||||
|
||||
wdt_hal_write_protect_disable(&wdt0_context);
|
||||
wdt_hal_disable(&wdt0_context);
|
||||
wdt_hal_write_protect_enable(&wdt0_context);
|
||||
|
||||
wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
|
||||
|
||||
wdt_hal_write_protect_disable(&wdt1_context);
|
||||
wdt_hal_disable(&wdt1_context);
|
||||
wdt_hal_write_protect_enable(&wdt1_context);
|
||||
|
||||
/* Flush any data left in UART FIFOs */
|
||||
esp_rom_uart_tx_wait_idle(0);
|
||||
esp_rom_uart_tx_wait_idle(1);
|
||||
esp_rom_uart_tx_wait_idle(2);
|
||||
|
||||
/* Disable cache */
|
||||
Cache_Disable_ICache();
|
||||
Cache_Disable_DCache();
|
||||
|
||||
/* 2nd stage bootloader reconfigures SPI flash signals. */
|
||||
/* Reset them to the defaults expected by ROM */
|
||||
WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
|
||||
WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
|
||||
|
||||
/* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */
|
||||
SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,
|
||||
SYSTEM_BB_RST | SYSTEM_FE_RST | SYSTEM_MAC_RST | SYSTEM_BT_RST |
|
||||
SYSTEM_BTMAC_RST | SYSTEM_SDIO_RST | SYSTEM_SDIO_HOST_RST |
|
||||
SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | SYSTEM_RW_BTMAC_RST |
|
||||
SYSTEM_RW_BTLP_RST | SYSTEM_BLE_REG_RST | SYSTEM_PWR_REG_RST);
|
||||
REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
|
||||
|
||||
/* Reset timer/spi/uart */
|
||||
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST |
|
||||
SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST);
|
||||
REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0);
|
||||
|
||||
/* Reset DMA */
|
||||
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);
|
||||
REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0);
|
||||
|
||||
SET_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET);
|
||||
CLEAR_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET);
|
||||
|
||||
rtc_clk_cpu_freq_set_xtal();
|
||||
|
||||
/* Running on APP CPU: need to reset PRO CPU and unstall it, */
|
||||
/* then reset APP CPU */
|
||||
soc_ll_reset_core(0);
|
||||
soc_ll_stall_core(0);
|
||||
soc_ll_reset_core(1);
|
||||
|
||||
while (true) {
|
||||
;
|
||||
}
|
||||
}
|
||||
58
soc/espressif/esp32s3/soc_cache.c
Normal file
58
soc/espressif/esp32s3/soc_cache.c
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#ifndef CONFIG_MCUBOOT
|
||||
extern int _rodata_reserved_start;
|
||||
extern int _rodata_reserved_end;
|
||||
extern void rom_config_data_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways,
|
||||
uint8_t cfg_cache_line_size);
|
||||
extern void rom_config_instruction_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways,
|
||||
uint8_t cfg_cache_line_size);
|
||||
extern uint32_t Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size);
|
||||
extern void Cache_Set_IDROM_MMU_Info(uint32_t instr_page_num, uint32_t rodata_page_num,
|
||||
uint32_t rodata_start, uint32_t rodata_end,
|
||||
int i_off, int ro_off);
|
||||
extern void Cache_Enable_ICache(uint32_t autoload);
|
||||
|
||||
void IRAM_ATTR esp_config_instruction_cache_mode(void)
|
||||
{
|
||||
rom_config_instruction_cache_mode(CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE,
|
||||
CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS,
|
||||
CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE);
|
||||
|
||||
Cache_Suspend_DCache();
|
||||
}
|
||||
|
||||
void IRAM_ATTR esp_config_data_cache_mode(void)
|
||||
{
|
||||
int s_instr_flash2spiram_off = 0;
|
||||
int s_rodata_flash2spiram_off = 0;
|
||||
|
||||
rom_config_data_cache_mode(CONFIG_ESP32S3_DATA_CACHE_SIZE,
|
||||
CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS,
|
||||
CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE);
|
||||
Cache_Resume_DCache(0);
|
||||
|
||||
/* Configure the Cache MMU size for instruction and rodata in flash. */
|
||||
uint32_t rodata_reserved_start_align =
|
||||
(uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1);
|
||||
uint32_t cache_mmu_irom_size =
|
||||
((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) * sizeof(uint32_t);
|
||||
uint32_t cache_mmu_drom_size =
|
||||
(((uint32_t)&_rodata_reserved_end - rodata_reserved_start_align + MMU_PAGE_SIZE - 1)
|
||||
/ MMU_PAGE_SIZE) * sizeof(uint32_t);
|
||||
Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
|
||||
|
||||
Cache_Set_IDROM_MMU_Info(cache_mmu_irom_size / sizeof(uint32_t),
|
||||
cache_mmu_drom_size / sizeof(uint32_t),
|
||||
(uint32_t)&_rodata_reserved_start,
|
||||
(uint32_t)&_rodata_reserved_end,
|
||||
s_instr_flash2spiram_off,
|
||||
s_rodata_flash2spiram_off);
|
||||
}
|
||||
#endif /* CONFIG_MCUBOOT */
|
||||
21
soc/espressif/soc.yml
Normal file
21
soc/espressif/soc.yml
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
family:
|
||||
- name: espressif_esp32
|
||||
series:
|
||||
- name: esp32
|
||||
socs:
|
||||
- name: esp32
|
||||
cpuclusters:
|
||||
- name: procpu
|
||||
- name: appcpu
|
||||
- name: esp32s2
|
||||
socs:
|
||||
- name: esp32s2
|
||||
- name: esp32s3
|
||||
socs:
|
||||
- name: esp32s3
|
||||
cpuclusters:
|
||||
- name: procpu
|
||||
- name: appcpu
|
||||
- name: esp32c3
|
||||
socs:
|
||||
- name: esp32c3
|
||||
Loading…
Add table
Add a link
Reference in a new issue