hwmv2: Introduce Hardware model version 2 and convert devices
This is a squash of the ``collab-hwm`` branch which converts all
in-tree boards to hardware model version 2 including build system
changes, board updates and soc conversions.
This squash is a combination of the following commits:
ca214745a1 soc: Remove soc_legacy folder and move ARM Kconfig
f12cb0979f scripts: ci: check_compliance: remove HWMv1 checks
1807bcf4d4 boards: mimx8mq_evk: port to HWMv2
3ec2299c62 soc: nxp: port imx8mq SOC to HWMv2
8ea02f4e63 boards: verdin_imx8mp: convert to HVMv2
f2eb7652ce boards: phyboard_pollux: move to HVMv2
ab509a5ee0 boards: nxp: mimx8mp_evk: port M7 core to HWMv2
06ad037f99 soc: nxp: imx8mp: port M7 core to HWMv2
3f9e706859 boards: mimx8mm_phyboard: convert to HVMv2
204372d264 boards: imx8mm_evk: port CM4 core to HWMv2
f82c961a46 soc: nxp: imx8mm: port iMX8MM M4 core to HVMv2
6987b2e305 boards: pico_pi: convert to HVMv2
84484e6707 boards: warp7: convert to HWMv2
ae443d1e3c boards: meerkat96: port to HWMv2
e3629c64e6 boards: colibri_imx7d: port to HWMv2
fc835d893d soc: nxp: convert iMX7 Dual core to HWMv2
29ef2f23eb boards: udoo_neo_full: convert to HWMv2
fd49b1749e soc: nxp: convert iMX6 SoloX core to HWMv2
1e59b7a3fd soc: nxp: imxrt11xx: only set
CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION for M7
69bb0eb258 hwmv2: MAINTAINERS: Fix NXP maintainer yaml
1c4458890f boards: firefly: roc_rk3568_pc: Fix SMP configuration
651a4370ad boards: Fix variants and revisions
196cfda66d tests/samples: Drop default revision identifiers
6ec6b1d75a boards: Drop revision from twister identifiers for
default revisions
b774cdd59f scripts: utils: board_v1_to_v2: drop board_legacy prefix
7aa36e6640 boards: riscv: esp32c3_luatos_core: make usb variant
fe25709a9c twister: add unit_testing soc and board
f88f211b4e scripts: ci: check_compliance: improve the "not sorted"
command
b21a455dfb bluetooth: controller: Fix openisa checks
fdc76c48a7 workflow: compliance: Add rename limit
14ecafc67d dts: bindings: vendor-prefixes: Sort entries
dbc366c3c7 soc: nxp: lpc: Move wrong configurations
8e02c08f96 maintainers: Fix invalid paths
b1b85e2495 boards: up: Fix spaces
58cc4013b3 maintainers: Fix xen path
66ce5c0b09 boards/soc: Add missing copyright headers
bb47243254 boards: qemu: x86: Remove pointless file
2e816a8a3a samples: tests: update esp32-based board naming
9aeab17139 samples: tests: remove platform_exclude of esp32 boards
a4fe97b9de boards: shields: m5stack_core2_ext: update board name
615fcab94a samples: ipm_esp32: fix board labels and skip testing
7752f69b7f boards: legacy: remove index entry for xtensa/riscv
boards.
3eba827956 MAINTAINERS: update Espressif entries
914362bbd5 boards: xtensa: yd_esp32: Convert to v2
a62278fd23 boards: xtensa: xiao_esp32s3: Convert to v2
b6a11ccec4 boards: xtensa: olimex_esp32_evb: Convert to v2
c1067c16d2 boards: xtensa: odroid_go: Convert to v2
b8340b0109 boards: xtensa: m5stickc_plus: Convert to v2
9d81e417be boards: xtensa: m5stack_stamps3: Convert to v2
c296672720 boards: xtensa: m5stack_core2: Convert to v2
fada12aa9d boards: xtensa: m5stack_atoms3_lite: Convert to v2
fe37ebac1e boards: xtensa: m5stack_atoms3: Convert to v2
d32828fe6a boards: xtensa: kincony_kc868_a32: Convert to v2
5afba7855b boards: xtensa: heltec_wireless_stick_lite_v3: Convert to
v2
ca48c17723 boards: xtensa: heltec_wifi_lora32_v2: Convert to v2
db1fd4d229 boards: xtensa: esp32s3_luatos_core: Convert to v2
a78b2552eb boards: xtensa: esp32s3_devkitm: Convert to v2
cc96061d96 boards: xtensa: esp32s2_saola: Convert to v2
ed854e05d1 boards: xtensa: esp32s2_lolin_mini: Convert to v2
4fa1ae8110 boards: xtensa: esp32s2_franzininho: Convert to v2
5543040a18 boards: xtensa: esp_wrover_kit: Convert to v2
2335ae79b3 boards: xtensa: esp32_ethernet_kit: Convert to v2
f910b7ad4f boards: xtensa: esp32_devkitc_wrover: Convert to v2
32104db555 boards: xtensa: esp32_devkitc_wroom: Convert to v2
e23a41200d boards: riscv: icev_wireless: Convert to v2
3c670e4e53 boards: riscv: xiao_esp32c3: Convert to v2
fc7c6a060b boards: riscv: stamp_c3: Convert to v2
22c2edb89c boards: riscv: esp32c3_luatos_core: Convert to v2
0a96dcb778 boards: riscv: esp32c3_devkitm: Convert to v2
be1ee1c446 vendors: update vendors lists
5e6c62137f soc: espressif_esp32: Port to HWMv2
037a3b52a4 boards: Raspberry Pi pico pwm led adjustment
7277cae6fa samples: blinky_pwm: enable pwm_leds in rpi_pico overlay
da3e49d34e boards: nxp: update selection of
FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
bc8424dd3b soc: nxp: imxrt: move FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
to SOC level
041cb52939 soc: brcm: bcm_vk: Rename to bcnvk
576b43a95c soc: Fix SOC_FAMILY name mismatches
e8f3e6494d hwmv2: boards: intel: adsp: Fix runner after paths
renamed
550399e927 boards: weact: stm32g431_core: Add wrongly deleted file
back
08708c909e tests: drivers: flash: Renamed missed board rename
06dac41e68 hwmv2: Convert Seagate Faze board to hwmv2
dd8f842b40 hwmv2: nxp: update MAINTAINER paths for hwmv2
b4d1c04978 hwmv2: lpc: updated overlay and conf files in samples and
tests
067c69089e boards: nxp: convert lpcxpresso55s69 to hwmv2
097205b40a hwmv2: Global fix of lpc54114_m4 overlay and conf files
d8cfa6fb29 boards: nxp: convert lpcxpresso54114 to hwmv2
c29ed228c6 boards: nxp: convert lpcxpresso55s36 to hwmv2
88cfd3d6ac boards: nxp: convert lpcxpresso55s28 to hwmv2
ad30c940ee boards: nxp: convert lpcxpresso55s16 to hwmv2
9e5a10ec80 boards: nxp: convert lpcxpresso55s06 to hwmv2
5650c83268 boards: nxp: convert lpcxpresso51u68 to hwmv2
82cf44be45 boards: nxp: convert lpcxpresso11u68 to hwmv2
1a9c405a6f soc: nxp: convert LPC SOC family to hardware model V2
f2b536d253 boards: intel: doc: hwmv2: Fix some renamed paths
5ee6058710 samples/tests: Use board revisions
b76687602f boards: Add yaml files for boards missing revisions
32ae4918d0 boards: nordic: Fix board names
cc1dabca65 MAINTAINERS: Update for renamed folders
a37ddce659 soc: xilinx: Rename to xlnx
a1393a07f6 soc: xenvm: Rename to xen
813ed00f67 soc: raspberry_pi: Rename to raspberrypi
71317d6798 soc: cadence: Rename to cdns
8cb0c51ec6 soc: broadcom: Rename to brcm
2b9db15c69 soc: andes: Rename to andestech
0101216ce1 soc: altera: Rename to altr
4b4c3ca65d boards: wurth_elektronik: Rename to we
cdc3ef499f boards: ublox: Rename to u-blox
cabdd4ad05 boards: space_cubics: Rename to sc
4b5bd7ae8a boards: seeed_studio: Rename to seeed
a992785ceb boards: raspberry_pi: Rename to raspberrypi
3c1cdc20fe boards: laird_connect: Rename to lairdconnect
291c7cde2b boards: cadence: Rename to cdns
95db897526 boards: broadcom: Rename to brcm
0a47b94879 boards: beagleboard: Change to beagle
9f9f221c24 boards: andes: Rename to andestech
e7869ca38a boards: altera: Rename to altr
bf2fb5eca3 various: Change SOC_FAMILY_NRF to SOC_FAMILY_NORDIC_NRF
e25730ba56 modules: tf-m: Rename from nordic_nrf to nordic
9e3466606a boards: nordic_nrf: Rename to nordic
09a398dcc8 soc: nordic_nrf: Rename to nordic
cb8ffc74f8 boards: renode: Add documentation index
2291ff4b55 boards: arm: riscv32_virtual: Convert to v2
484b7f1996 soc: riscv_renode_virtual: Port to HWMv2
cc5c2fb0c7 soc: raspberry_pi: Fix SOC_SERIES and SOC mismatch
59cb580513 soc: arm: designstart: Fix SOC_SERIES and SOC mismatch
aa9e0de7af samples: Fix invalid links
a1480cf1cf maintainers: Fix paths
0d719e004b boards: Update documentation links
eb5c3e6f79 boards: wurth_elektronik: Drop duplicate prefix
a34a3640b7 boards: waveshare: Drop duplicate prefix
cf50e950e7 boards: weact: Drop duplicate prefix
737cfb548f boards: sparkfun: Drop duplicate prefix
505494c97a boards: segger: Drop duplicate prefix
4eaf69f37a boards: ruuvi: Drop duplicate prefix
a1335caeae boards: ronoth: Drop duplicate prefix
a9f7f30bf6 boards: raytac: Drop duplicate prefix
80db4c81b3 boards: qemu: Drop duplicate prefix
433d7e9976 boards: particle: Drop duplicate prefix
4ea79d19e7 boards: olimex: Drop duplicate prefix
fd4ae6f6a8 boards: mikroe: Drop duplicate prefix
36080549bd boards: khados: Drop duplicate prefix
169bf8ae1d boards: intel: Drop duplicate prefix
25f04d5222 boards: holyiot: Drop duplicate prefix
11c2af0de8 boards: google: Drop duplicate prefix
d5128f4016 boards: ebyte: Drop duplicate prefix
44fbc68cad boards: dragino: Drop duplicate prefix
f7fe431b44 boards: contextual_electronics: Drop duplicate prefix
9094fea63b boards: circuit_dojo: Drop duplicate prefix
b632acc1fc boards: blue_clover: Drop duplicate prefix
1a3316ebdc boards: bbc: Drop duplicate prefix
71c0344f8c boards: arduino: Drop duplicate prefix
f0176fc25f boards: altera: Drop duplicate prefix
36b920ed0f boards: adi: Drop duplicate prefix
22520368d9 boards: adafruit: Drop duplicate prefix
296acfb2bc boards: actinius: Drop duplicate prefix
55063380b7 boards: 96boards: Drop duplicate prefix
1f93394b55 boards: nxp: convert mimxrt595_evk to hardware model v2
e7a4fd2ec1 soc: nxp: rt5xx: convert RT5xx SOC to HWMv2
01942f1d11 twister: normalize platform name when storing files/data
477c8b84dd twister: tests: test with slashes in platform names
64e3e816c4 soc: Add include guards
3a7aa2fa49 gitignore: update the compliance file list
84e1c17ad9 scripts: ci: check_compliance: add a check for board yml
file
a90f53ad57 boards: sync up the vendor tags and vendor-list
af9aa65299 dts: vendor-prefixes: add keep-sorted markers
50f0bf05a3 dts: vendor-prefixes: sort the vendor list
a10b614aa4 dts: vendor-prefixes: ensure all prefixes are lowercase
5abe735e93 manifest: update SOF sha for NXP HWMv2
9ab8f64ca9 modules: rename SOC_FAMILY_IMX
483ff8dd4d modules: mcux: remove SOC_FAMILY_NXP_ADSP
f113dd5342 samples: update board name
39b31287d9 boards: nxp: Convert i.MX ADSP boards to hardware model
v2
1511e356a2 soc: nxp: Port i.MX ADSP family to hardware model v2
c91e25ab47 soc: mec: rename all mec1501x reference to mec15xx
1c231fd939 hwmv2: boards: Convert IMXRT boards
417cff1e60 hwmv2: soc: Port IMXRT family to HWMV2
28d4e41b1b hwmv2: clean up arm64 soc and board empty directory
2b520f83cb hwmv2: port NXP SoC LS1046A to V2
bf7899c645 hwmv2: port nxp_ls1046ardb board to V2
33f7b61866 samples/tests: Rename numaker boards
8f20ea6e93 boards: nuvoton: numaker_pfm: Split into 2 boards
7cf4ff43a1 drivers: pinctrl: imx: align with hwm v2
c68e1fea4e drivers: clock_control: ccm_rev2: align with hwm v2
update
3b49014a0f hwmv2: move imx8mn EVK board to V2
14f344eeab hwmv2: move imx8mp EVK board to V2
40f3f8f22d hwmv2: move imx8mm EVK board to V2
10bf79ea51 hwmv2: move imx8m soc for a-core to V2
8727d5ca80 hwmv2: move imx93 EVK board to V2
c81ef01563 hwmv2: move imx93 soc to V2
5836c1b699 modules: mcux: introduce CONFIG_MCUX_CORE_SUFFIX
338f6f2bf1 doc: update board porting guide to match new hardware
model
9639a1b5dc soc: silabs: drop useless defconfigs
981807444e soc: silabs: introduce SOC_GECKO_SDID
5d07e82485 soc: silabs: SOC_FAMILY_* replace SOC_GECKO_SERIES*
2fd081ac86 soc: silabs: align comments with soc tree
66d425f571 soc: silabs: split in families
5bd38f47a9 arch: arch: kconfig: Fix wrong placement of endmenu
00c6ef25be tests/samples: Rename overlay files for renamed boards
0c639b8378 boards: Fix bools and selections
c2ef907d1d drivers: flash: it8xxx2: Add missing Kconfigs
553de2ebc9 soc: ite: ec: it8xxx2: Fix SOC_SERIES being in wrong file
b8ec0080c2 boards: Documentation link fixes
eb7025e50f tests: Update board names for hwmv2
10ef3d4bd2 boards: silab: Add documentation index file
ba9fdaa1d6 boards: arm: efr32_radio: Convert to v2
86c8d4a0ca boards: arm: efm32pg_stk3402a: Convert to v2
575ac5cafb manifest: Update hal_silabs
87b2907304 boards: arm: efr32_thunderboard: Convert to v2
14b30055ab boards: arm: efr32mg_sltb004a: Convert to v2
0012bfc15d boards: arm: efr32xg24_dk2601b: Convert to v2
f526225ead boards: arm: efm32wg_stk3800: Convert to v2
19e7df29df boards: arm: efm32pg_stk3401a: Convert to v2
0bd7d963d6 boards: arm: efm32hg_slstk3400a: Convert to v2
795a90f9bf boards: arm: efm32gg_stk3701a: Convert to v2
43d5540be7 boards: arm: efm32gg_slwstk6121a: Convert to v2
065148d856 boards: arm: efm32gg_sltb009a: Convert to v2
1dc9a8aa17 soc: silabs_exx32: Port to HWMv2
763571e878 tests: Expand names
dae301b8a3 boards: xen: xenvm: Expand name
19e60eef36 boards: qemu: qemu_cortex_a53: Expand names
a0a7c30f28 soc: intel: intel_adsp: Fix issues
df9a4223fe scripts: ci: introduce soc name check in check_compliance
ed401abaff soc: emsdsp: align SoC name defined in soc.yml to Kconfig
SOC setting
fc78e5eaa4 MAINTAINERS: update RISC-V arch area paths
4e586958ff boards: convert QEMU RISC-V 64 bit board to Zephyr HWMv2
f4c31a2b86 boards: convert QEMU RV32E board to Zephyr HWMv2
5b2ffc652b boards: convert QEMU RISC-V 32 bit board to Zephyr HWMv2
5db061a4c6 soc/riscv: convert the QEMU virt RISCV-32 SoC to HWMv2
6547845e9d boards: convert SparkFun RED-V Things Plus to Zephyr
HWMv2
95a1f96399 boards: convert SiFive HiFive Unmatched to Zephyr HWMv2
e563eb0a62 soc/sifive/sifive_freedom: add SiFive Freedom FU740 SoC
8914bc58b6 boards: convert SiFive HiFive Unleashed to Zephyr HWMv2
7e8de1e781 soc/sifive/sifive_freedom: add SiFive Freedom U540 SoC
bfcc2ed18f boards: convert SiFive HiFive1 Rev. B to Zephyr HWMv2
330fc38f9f boards: convert SiFive HiFive1 to Zephyr HWMv2
b9e06f4c38 soc/sifive/sifive_freedom: add SiFive Freedom E310 SoC
4b90b30b9d scripts: west_commands: completion: Add hwmv2 complete to
fish
0f6842e2fa scripts: west_commands: completion: Add hwmv2 complete to
zsh
b2af1e1737 scripts: west: list_boards: Fix hwmv2 output
686a4b78b8 scripts: west_commands: completion: Add hwmv2 complete to
bash
396b6bb856 soc: nxp: fix typo in SoC name
765299c627 soc: broadcom: align SoC names defined in soc.yml to
Kconfig SOC setting
7efd46eb41 soc: arm: align SoC names defined in soc.yml to Kconfig
SOC setting
505cbc5c42 soc: mec: align SoC names defined in soc.yml to Kconfig
SOC setting
951a140701 soc: ti: define SOC name in Kconfig
a795d28810 snippets: Initial HWMv2 support
f9a957e6f6 boards: nordic: nrf9160dk: Fix missing nrf52840 config
df994e7ee8 soc: xilinx: zync7000: Remove xilinx from soc series name
8dfabd56ca soc: cypress: Add protection guard to file
447b951593 tests: kernel: tickless: Remove old board name
bad5dfa71f boards: nordic: nrf5340dk: Fix board names
ad2e863f39 soc: atmel: Use new family prefix
3f08e714b2 soc: intel_adsp: hwmv2: Align SOC_SERIES_INTEL_ACE name
and value
6734597a76 soc: intel_adsp_cavs: hwmv2: Align SOC_SERIES name and
value
2908af0bcc boards: nrf51dk/dongle: change SoC to nRF51822
d1ceb29fca soc: align CONFIG_SOC values to match soc.yml names
4768ccaf70 tests: drivers: gpio: gpio_api_1pin: exclude hifive1
ebdb0879ad boards: nxp: s32z2xxdc2: convert to hwmv2
ae82580d08 boards: nxp: mr_canhubk3: convert to hwmv2
c5f0defbae boards: nxp: ucans32k1sic: convert to hwmv2
1e46cabce6 soc: nxp: convert NXP S32 family to hwmv2
f2f85133f2 soc: stm32: Rename series path
86642f4e78 soc: stm32: Rename Kconfig SOC_SERIES symbols
c61e807896 soc: stm32: Cleanup Kconfig.defconfig files
ca46c8abc9 tests: Fix board names
fbfed5f48f maintainers: Update synopsys entries
8cd8b1cc47 boards: synopsys: Add documentation index
6f6cc57a04 boards: arc: hsdk4xd: Convert to v2
c4c14a54ca soc: snps_arc_hsdk4xd: Port to HWMv2
06c2054e5c boards: arc: iotdk: Convert to v2
ff0e0fce1b soc: snps_arc_iot: Port to HWMv2
334264c46a boards: arc: emsdp: Convert to v2
8b947a0e91 soc: snps_emsdp: Port to HWMv2
990417bbde tests: Update board names for hwmv2
e12719154a boards: arc: em_starterkit: Convert to v2
437a430fbe soc: snps_emsk: Port to HWMv2
f93387f968 boards: arc: hsdk: Convert to v2
1cf2498b13 soc: snps_arc_hsdk: Port to HWMv2
47abe81256 boards: arc: nsim: Convert to v2
1e33786dc4 soc: snps_nsim: Port to HWMv2
7f081914db boards: arc: qemu_arc: Convert to v2
bc97349dbd soc: snps_qemu: Port to HWMv2
a9902ff58e boards: Use zephyr_file for file links
126e1a4e72 boards: Fix invalid documentation links
899f0257c3 boards: stm32wb: Restore missing .defconfig files
790c10b1ee soc: x86/atom: imply mmu, do not select it
faee62088d boards: x86: remove qemu_x86_tiny_768
c34d186a57 x86: atom: remove soc.h with unused content
1be3a9e9d3 x86: remove legacy ia32, use atom instead
60e6b400f9 boards: qemu: move qemu_x86 -> x86
c4fbac27e8 boards: infineon: Add documentation index
b4dd29a9c4 maintainers: Update paths for hwmv2
380f5fdb2b boards: cypress: Add documentation index
9de981be05 boards: arm: xmc47_relax_kit: Convert to v2
6394e8a348 boards: arm: xmc45_relax_kit: Convert to v2
04dbf17e19 soc: xmc_4xxx: Port to HWMv2
c9731f1bce boards: arm: cy8cproto_063_ble: Convert to v2
53d41869d1 boards: arm: cy8cproto_062_4343w: Convert to v2
46c4f01427 boards: arm: cy8ckit_062s4: Convert to v2
d285e19cf2 boards: arm: cy8ckit_062_wifi_bt: Convert to v2
2bebd7298c boards: arm: cy8ckit_062_ble: Convert to v2
af243274c2 soc: psoc6 and psoc_6: Port to HWMv2
105a2bae84 cmake: modules: boards: Fix board deprecation for HWMv2
dca54e000a cmake: modules: boards: Enhance board aliases for HWMv2
fc314e8e3f cmake: modules: boards: Fix BOARD_ALIAS
9a7c2ce6d5 soc: gaisler: Move Kconfig file
1ac56d0501 soc: soc_legacy: mips: Remove out file
c054381a7a boards: adjust few boards/ paths
4d93b8d9fd boards: convert all microchip MEC boards to hwmv2
ab2fcb1245 soc: convert microchip_mec to hwmv2
ead4b57a7b soc: arm64: intel_socfpga: hwmv2: Rename SoCs
d4c143d306 MAINTAINERS: intel_socfpga: Adjust to HWMv2 move
70a66ac03a boards: arm64: intel_socfpga: Move boards to
subdirectories
8a85c07799 boards: arm64: intel_socfpga_agilex5_socdk: move to HWMv2
8c253a99fc boards: arm64: intel_socfpga_agilex_socdk: move to HWMv2
ab883b8019 soc: arm64: intel_socfpga: Move and convert to HWMv2
7c8b7a153b soc: arm: intel_socfpga_std: Rename with HWMv2
8dc2b911f6 soc: board: intel_socfpga_std: Align names to 'Cyclone V'
402366117a soc: arm: intel_socfpga_std: Align board subdirectory
f0a8d12745 boards: arm: cyclonev_socdk: Move to HWMv2
2271f17a86 soc: arm: intel_socfpga_std: Move and convert to HWMv2
841c2a9d99 boards: riscv: beaglev_fire: Convert to v2
3b314531ab boards: riscv: mpfs_icicle: Convert to v2
d4ea2bf70b boards: riscv: m2gl025_miv: Convert to v2
5256e9fcc3 soc: microchip_miv: Port to HWMv2
18e5cf1d51 maintainers: Update path for hwmv2
eab8628f98 boards: arm: qemu_cortex_m3: Convert to v2
1532f2fee1 soc: ti_lm3s6965: Port to HWMv2
430ca6a475 maintainers: Update ambiq paths
a9b9b41b91 boards: ambiq: Add index
db0271ecbb boards: arm: apollo4p_blue_kxr_evb: Convert to v2
957e2b2061 boards: arm: apollo4p_evb: Convert to v2
5a90a44454 soc: ambiq: Port to HWMv2
a20c113fbd boards: nxp: convert ip_k66f to hwmv2
34e3852a54 boards: nxp: convert usb_kw24d512 to hwmv2
20ad604de6 boards: nxp: convert twr_kv58f220m to hwmv2
2e2a7b7656 boards: nxp: twr_ke18f: convert to hwmv2
f7dcc2eb5e boards: nxp: convert rddrone_fmuk66 to hwmv2
b58e90a2e9 boards: nxp: convert hexiwear to hwmv2
aae6e9e454 boards: nxp: frdm_kw41z: convert to hwmv2
1d3baac2d6 boards: nxp: convert frdm_kl25z to hwmv2
3b1d21483f boards: nxp: frdm_k82f: port to hwmv2
6046e6ded9 boards: nxp: port frdm_k64f to hwmv2
0a7bf9fd79 boards: nxp: port frdm_k22f to hwmv2
dce697c823 boards: nxp: add toctree placeholder
666a353409 soc: nxp: kinetis: convert kinetis SOC family to hardware
model V2
89f0a6034b maintainers: Update paths for renesas boards/socs
004bd43c48 tests/samples/snippets: Update board names for hwmv2
a6d756923d boards: arm and arm64: rcar_h3ulcb: Convert to v2
3801216b8d boards: arm64: rcar_salvator_xs_m3: Convert to v2
b7cc30aaea boards: arm: rcar_h3_salvatorx_cr7: Convert to v2
866427ea29 boards: arm: arduino_uno_r4: Convert to v2
2689b3f0ee soc: ra: Port to HWMv2
e7ebc727c8 boards: arm: da1469x_dk_pro: Convert to v2
903265b2bb boards: arm: da14695_dk_usb: Convert to v2
529a78ed51 soc: smartbond: Port to HWMv2
97cf636ae0 boards: arm: rcar_spider_cr52: Convert to v2
6d0c53f3a1 soc: rcar: Port to HWMv2
44e0aa0668 soc: renesas: rzt2m: Move folder structure for more SoCs
85238fc205 boards: misc: Fixed STM32 based boards doc links
dffc08af56 boards: riscv: niosv_m: move and convert to HWMv2
545093abe4 boards: riscv: niosv_g: move and convert to HWMv2
ecfa192f1b soc: riscv: intel_niosv: move and convert to HWMv2
fd1e8cdc30 hwmv2: sof: intel_adsp: submanifest provisional link
8bf067e625 doc: boards: intel_adsp: Re-order pages
4833275ccd MAINTAINERS: intel_adsp: Adjust to HWMv2 move
b9a70e5ea2 soc: intel_adsp: tools: pylint compliance workaround
18c70cc4bf hwmv2: tests: boards: intel_adsp: Adjust board names
ca52baf9de hwmv2: boards: intel_adsp: Overhaul board configurations
d1b3bcce64 soc: boards: xtensa: intel_adsp_ace: Rename with HWMv2
f362a8ae2c doc: soc: boards: intel_adsp_cavs25: Rename with HWMv2
51dee5da92 tests: samples: boards: intel_adsp_cavs25: Rename with
HWMv2
e66c35e0d0 boards: xtensa: intel_adsp_cavs25: Rename board with
HWMv2
d1491a4810 soc: boards: xtensa: intel_adsp_cavs25: Rename with HWMv2
fa0fca79c4 scripts: west: runners: intel_adsp: Adjust path to HWMv2
acd18bfaf7 boards: xtensa: intel_adsp_ace20_lnl: move and convert to
HWMv2
546c94b958 boards: xtensa: intel_adsp_ace15_mtpm: move and convert
to HWMv2
8aab718c3e boards: xtensa: intel_adsp_cavs25_tgph: change to board
variant
30f17424a4 boards: xtensa: intel_adsp_cavs25: move and convert to
HWMv2
35a97cb524 soc: xtensa: intel_adsp: HWMv2 workaround for SOF config
fdc20fdff6 soc: xtensa: intel_adsp: move and convert to HWMv2
22dc2b6391 cmake: improved board handling for revisions
2f1e33a2e6 cmake: improve arch error message for invalid arch
selection
c47c37d3db sample: basic: blinky_pwm: Exclude rpi_pico w variant
7a788b9a18 boards: raspberry_pi: rpi_pico: Use full name for w
variant
7046b92d41 tests: atmel_sam: adc: Fix sam4e_xpro adc build
253ee9638c tests: atmel_sam0: Update platform name
ccb4c63324 samples: atmel_sam0: Update platform name
2d4acf9230 boards: arduino_nano_33_iot: Convert to HWMv2
a60d28969a boards: arduino_mkrzero: Convert to HWMv2
0409e51d3f boards: arduino_zero: Convert to HWMv2
1b2528df1b boards: wio_terminal: Convert to HWMv2
af1096e7ca boards: ev11l78a: Convert to HWMv2
0b1db9c53d boards: adafruit_trinket_m0: Convert to HWMv2
e9874671e2 boards: adafruit_itsybitsy_m4_express: Convert to HWMv2
ba6c014071 boards: adafruit_grand_central_m4_express: Convert to
HWMv2
33ad4a51ca boards: adafruit_feather_m0_lora: Convert to HWMv2
9812f3d54e boards: adafruit_feather_m0_basic_proto: Convert to HWMv2
c76b1fbeca boards: serpente: Convert to HWMv2
649789e433 boards: seeeduino_xiao: Convert to HWMv2
6b3bdb7364 boards: same54_xpro: Convert to HWMv2
93dda5ee4b boards: samr34_xpro: Convert to HWMv2
e48e1f5d5b boards: samc21n_xpro: Convert to HWMv2
f11cf73df1 boards: saml21_xpro: Convert to HWMv2
ac73ed6dcd boards: samd20_xpro: Convert to HWMv2
0fdbe3552e boards: samd21_xpro: Convert to HWMv2
854cff3905 boards: samr21_xpro: Convert to HWMv2
a87ea5bc0a soc: atmel: sam0: Port to HWMv2
706e5d27cd boards: riscv: neorv32: Convert to v2
d1edcdd088 soc: neorv32: Port to HWMv2
0f7add89ca boards: native_sim/posix: Add 64bit versions as variants
b6edad8d68 soc: soc_legacy: remove the arm/st_stm32 folder
c58e0822a6 boards: Convert nucleo_f207zg to HWM v2
b987093a80 soc: v2: stm32: Migrate STM32F2 series
2096fd4652 samples: bluetooth: hci_uart: Fix wrongly converted board
names
830f9c5a82 MAINTAINERS: Update Atmel entries
527cd9d8cd CODEOWNERS: Update Atmel entries
83af7d0c1c samples: atmel_sam: Update platform name
fd9b84d457 tests: atmel_sam: Update platform name
3c72fe863c boards: arduino_due: Convert to HWMv2
37dfacbf9e boards: RoboKit1: Convert to HWMv2
1108d7b0ed boards: sam_v71_xult: Convert to HWMv2
bed44a5c28 boards: sam_e70_xplained: Convert to HWMv2
40448c5a9f boards: sam4s_xplained: Convert to HWMv2
31273692c0 boards: sam4l_ek: Convert to HWMv2
35b5d33ef0 boards: sam4e_xpro: Convert to HWMv2
3b84b9910a soc: atmel: Port SAM family to HWMv2
da00d0e7b9 boards: Convert nucleo_wba55cg to HWM v2
fb2103f89e boards: Convert nucleo_wba52cg to HWM v2
1f9a533fbc soc: st: stm32: Migrate STM32WBA series
3f92f65b28 boards: fix documentation for alientek and blues boards
7646b74aaf boards: stm32l4: doc: add zephyr_file to defconfig path
fea54ddcd9 boards: Convert adi_eval_adin2111ebz to HWM v2
d47f1878b1 boards: Convert adi_eval_adin1110ebz to HWM v2
ae42be236b boards: Convert swan_r5 to HWM v2
83bd1a9ecc boards: Convert stm32l4r9i_disco to HWM v2
39c26f09ed boards: Convert stm32l496g_disco to HWM v2
29d03c970b boards: Convert stm32l476g_disco to HWM v2
74acec315c boards: Convert sensortile_box to HWM v2
fee6d8676e boards: Convert pandora_stm32l475 to HWM v2
008b5d9392 boards: Convert nucleo_l4r5zi to HWM v2
24e357d623 boards: Convert nucleo_l4a6zg to HWM v2
2c5f9dcce0 boards: Convert nucleo_l496zg to HWM v2
4da061646f boards: Convert nucleo_l476rg to HWM v2
15956a69b8 tests: drivers: flash: stm32: update platform name
80324f7707 boards: Convert nucleo_l452re_p to HWM v2
9893e0d111 boards: Convert nucleo_l452re to HWM v2
46f92b227b boards: Convert nucleo_l433rc_p to HWM v2
ed5d1bb4cd boards: Convert nucleo_l432kc to HWM v2
325f95ec20 boards: Convert nucleo_l412rb_p to HWM v2
d055676307 boards: Convert disco_l475_iot1 to HWM v2
c7a415d92c boards: Convert b_l4s5i_iot01a to HWM v2
d15144f582 soc: st: stm32: Migrate STM32L4 series
a63ff71bcb boards: nrf_bsim: Add new nrf5340 board definitions
b53c6f412c boards: nrf_bsim: Remove redundant option setting
83eb4fc069 MAINTAINERS: intel_ish: Adjust to HWMv2 move
715685b19f boards: x86: intel_ish: move and convert intel_ish boards
to HWMv2
5b9ef94106 soc: x86: intel_ish: move and convert to HWMv2
12b297707a boards: Convert stm32wb5mmg to HWM v2
cdcea932bc boards: Convert stm32wb5mm_dk to HWM v2
0a3ae2b223 boards: Convert nucleo_wb55rg to HWM v2
20b4ce17d5 soc: st: stm32: Migrate STM32WB series
47c65400d6 soc: st: stm32: fix stm32l0 family
59ec56f9e6 boards: Convert stm32h573i_dk to HWM v2
dc5977dbba boards: Convert nucleo_h563zi to HWM v2
a6e4928543 soc: st: stm32: Migrate STM32H5 series
99f248e048 soc: stm32u5: Fix references after conversion to hw
modelv2
15f16834e6 boards: Convert stm32u5a9j_dk to HWM v2
c1ee449ef1 boards: Convert sensortile_box_pro to HWM v2
db4deddf9d boards: Convert nucleo_u5a5zj_q to HWM v2
2fd3ed43d2 boards: Convert nucleo_u575zi_q to HWM v2
902fceb173 boards: Convert b_u585i_iot02a to HWM v2
d716ca1a10 soc: st: Migrate stm32u5 series to new hw model
b7abc89428 hwmv2: boards: x86: doc: Adjust common docs to new
locations
69b334f54b MAINTAINERS: Change paths to native and nrf*bsim boards
614611a528 boards: nrf*_bsim: Convert to HW model v2
5821b9ec2e board: native_sim/posix: Convert to hwmv2
04cbad174e soc: native: Convert to HWMv2
24ca0febfc boards: nrf_bsim: Fix path to pinctrl_soc.h
9a32559a2d cmake: FindHostTools: Fix for hwmv2 for host based
targets
c4b11e0251 boards: longan_nano: port to HWMv2
97edd05be3 boards: gd32vf103c_starter: port to HWMv2
9cf624c410 boards: gd32vf103v_eval: port to HWMv2
b40bf25e5e soc: gd_gd32: reorganize folders
71600d7e95 soc: gd_gd32: move pinctrl_soc.h content back to soc
folder
2bd84a1bc5 soc: gd_gd32: port gd32vf103 series to HWMv2
9dc342143b boards: doc: fix a bunch of broken reference
10392d693d doc: boards: split out shields
b2def8ed3a boards: acrn: fix title
bf7d3efe78 boards: riscv: tlsr9518adk80d: Convert to v2
c579770e1d soc: telink_tlsr: Port to HWMv2
9131540109 soc: stm32h7: Couple of tests fixes following migration
2efcefc089 boards: Convert stm32h7b3i_dk to HWM v2
d9b295a85b boards: Convert stm32h750b_dk to HWM v2
a2f56bdcd5 boards: Convert stm32h747i_disco to HWM v2
00314155df boards: Convert stm32h735g_disco to HWM v2
b08819dff7 boards: Convert nucleo_h7a3zi_q to HWM v2
56456c16e5 boards: Convert nucleo_h753zi to HWM v2
91f9198dc4 boards: Convert nucleo_h745zi_q to HWM v2
96f1bafbf9 boards: Convert nucleo_h743zi to HWM v2
b290f25baa boards: Convert nucleo_h723zg to HWM v2
9fbe6bf191 boards: Convert fk7b0m1_vbt6 to HWM v2
44bcfe57c7 boards: Convert arduino_portenta_h7 to HWM v2
4c86af7eae boards: Convert arduino_opta_m4 to HWM v2
b4f852f738 boards: Convert arduino_giga_r1 to HWM v2
bac9789264 soc: st: Migrate stm32h7 series to new hw model
a954e1722d boards: stm32l0: Cleanup board _defconfig files after
migration
7e8515b241 boards: Convert ronoth_lodev to HWM v2
25246c21ef boards: Convert nucleo_l073rz to HWM v2
09396eb2e6 boards: Convert nucleo_l053r8 to HWM v2
70c004fd83 boards: Convert nucleo_l031k6 to HWM v2
e3daa98e79 boards: Convert nucleo_l011k4 to HWM v2
a2de60c6da boards: Convert dragino_nbsn95 to HWM v2
e877ce9cec boards: Convert dragino_lsn50 to HWM v2
2b50218c23 boards: Convert b_l072z_lrwan1 to HWM v2
4a65f55916 soc: st: Migrate stm32l0 series to new hw model
cc6e6be01f boards: fix few leftover ITE board references
a837303268 soc: stm32: Protect Kconfig symbols by SOC_FAMILY_STM32
88e5959f17 hwm2: Fix unit_testing: it is also a legacy board by now
95e06e8663 cmake: Fix uses of old SOC path
d517d3cc24 soc: set linker script for ra4m1
68f9aeddab soc: ite: add SOC_SERIES_ITE_IT8XXX2 guards around ITE
options
ccf4f48f01 boards: convert ite boards to hwmv2
4a6e286a3b soc: convert ite_ec to hwmv2
12e375f826 doc: handle arch / soc / board docs in new hardware model
b4db917de9 boards: Add documentation index files
d6e0d27efe samples: bluetooth: hci_uart: Fix wrong named files
bc16a7a727 tests: Update board names for hwmv2
2834883843 boards: riscv: rv32m1_vega: Convert to v2
9c68231ba9 soc: openisa_rv32m1: Port to HWMv2
986e9619fd soc: starfive_jh71xx: Port to HWMv2
e82932e787 boards: riscv: litex_vexriscv: Convert to v2
cb9339f88f soc: litex_vexriscv: Port to HWMv2
1cd4c34654 boards: riscv: opentitan_earlgrey: Convert to v2
92eadf06b8 soc: opentitan: Port to HWMv2
a8659e170b boards: riscv: titanium_ti60_f225: Convert to v2
359133d725 soc: efinix_sapphire: Port to HWMv2
6d466429ed soc: soc_legacy: riscv: litex_vexriscv: Add updated paths
a1ff441eb3 boards: riscv: adp_xc7k_ae350: Convert to v2
ef82a8255c soc: ae350: Port to HWMv2
282204758a samples: boards: stm32: ccm: fix include path
8ca9341195 samples: basic: threads: fix broken reference
8a947f446d boards: nrf52840dk: fix rst syntax
324cb41153 boards: nordic_nrf: fix broken references
963c74df1c boards: intel_(ish|adl|ehl|rpl), up_squared: fix include
paths
8d518ce504 boards: legacy: drop empty folders
0fef0cef5b boards: mps2: fix table formatting
e52ccc244f boards: add HWMv2 board index
c7426eca5e boards: arm: add legacy tag
1eba9d8a8f boards: acrn: create vendor folder
8d92edc727 tests: kernel: Adjust qemu_x86_tiny_768 configuration
HWMv2
75117d1b2d scripts: ensure posix path is used with --cmakeformat
0b0384b56a maintainers: update paths after HWMv2 changes
c1b77b223d boards: arm: pan1783: Convert to v2
91a077b2ab boards: posix: nrf_bsim: Update paths
413b6c2a40 cmake: modules: configuration_files: Add board identifier
overlay file
4f572ba24f treewide: Update board names for hwmv2
cb348c7edf boards: arm: nrf54l15pdk_nrf54l15: Convert to v2
811ad90566 boards: arm: nrf54h20pdk_nrf54h20: Convert to v2
d44ef90cf8 soc: nordic_nrf: Migrate nRF54H/nRF54L to v2 and fix nrf
c860f205de boards: arm: nrf9151dk_nrf9151: Convert to v2
fba98a1763 soc: nordic_nrf: Migrate nRF9151 to v2
5c156a2d35 boards: arm: 96b_carbon_nrf51: Convert to v2
cfc47a3a4b boards: arm: nrf9161dk_nrf9161: Convert to v2
37129b4e44 boards: arm: nrf9131ek_nrf9131: Convert to v2
a923beba5d boards: arm: bl5340_dvk: Convert to v2
d242b2703b boards: arm: raytac_mdbt53v_db_40_nrf5340: Convert to v2
9c80d4e644 boards: arm: raytac_mdbt53_db_40: Convert to v2
28268c4938 boards: arm: nrf5340_audio_dk_nrf5340: Convert to v2
33ad2b5bc6 boards: arm: thingy53_nrf5340: Convert to v2
40daa94f2d boards: arm: nrf9160_innblue22: Convert to v2
2b0dbb9d51 boards: arm: nrf9160_innblue21: Convert to v2
ee6f7697ac boards: arm: sparkfun_thing_plus_nrf9160: Convert to v2
594e4bad6b boards: arm: circuitdojo_feather_nrf9160: Convert to v2
a5803ba099 boards: arm: actinius_icarus: Convert to v2
db8c275456 boards: arm: actinius_icarus_bee: Convert to v2
30177cf53d boards: arm: actinius_icarus_som: Convert to v2
486504cf24 boards: arm: actinius_icarus_som_dk: Convert to v2
dd0672a64c boards: arm: nrf9160dk_*: Convert to v2
c1565b3d14 boards: arm: xiao_ble: Convert to v2
6dd2723314 boards: arm: qemu_cortex_m0: Convert to v2
ee1ce24a42 boards: arm: bbc_microbit: Convert to v2
1952d559f2 boards: arm: rm1xx_dvk: Convert to v2
9e12c3d8bd boards: arm: nrf51dongle_nrf51422: Convert to v2
0ffbc1da33 boards: arm: nrf51_blenano: Convert to v2
be52dfb7b6 boards: arm: nrf51_vbluno51: Convert to v2
4c29d1827f boards: arm: nrf51_ble400: Convert to v2
5b4a9556fd boards: arm: raytac_mdbt53_db_40_nrf5340: Fix typo
69e5d87a15 boards: arm: contextualelectronics_abc: Convert to v2
5e4ace1bbe boards: arm: degu_evk: Convert to v2
2762460a64 boards: arm: pan1781_evb: Convert to v2
fdc3913e76 boards: arm: ubx_evkninab1_nrf52832: Convert to v2
9c9c3a09a1 boards: arm: holyiot_yj16019: Convert to v2
109edc296f boards: arm: blueclover_plt_demo_v2_nrf52832: Convert to
v2
7bfcdbbe8f boards: arm: decawave_dwm1001_dev: Convert to v2
0fbb543983 boards: arm: acn52832: Convert to v2
073e0f8080 boards: arm: we_proteus2ev_nrf52832: Convert to v2
197a19f396 boards: arm: ebyte_e73_tbb_nrf52832: Convert to v2
1616fc8ae5 boards: arm: nrf52_vbluno52: Convert to v2
5622077738 boards: arm: nrf52_sparkfun: Convert to v2
a6289516e4 boards: arm: 96b_nitrogen: Convert to v2
439d836883 boards: arm: nrf52_blenano2: Convert to v2
16e65f09c4 boards: arm: arduino_nicla_sense_me: Convert to v2
862efd5a21 boards: arm: thingy52_nrf52832: Convert to v2
dede0f6cd3 boards: arm: nrf52_adafruit_feather: Convert to v2
91e864ea29 boards: arm: nrf52832_mdk: Convert to v2
47ec3e416b boards: arm: ruuvi_ruuvitag: Convert to v2
52f797a227 boards: arm: pinetime_devkit0: Convert to v2
433db339f9 boards: arm: ubx_evkannab1_nrf52832: Convert to v2
a646d3f2d5 boards: arm: ubx_bmd300eval_nrf52832: Convert to v2
d0d434bf86 cmake: print identifier instead of variant
c3f5ed8157 boards: arm: we_proteus3ev_nrf52840: Convert to v2
eecff8ee7a boards: arm: nrf52840_mdk_usb_dongle: Convert to v2
34507614f6 boards: arm: nrf52840_mdk: Convert to v2
f02b56cb96 boards: arm: nrf52840_blip: Convert to v2
600c55c92a boards: arm: nrf52840_papyr: Convert to v2
f294bfc5e4 boards: arm: reel_board: Convert to v2
882524d2a0 boards: arm: nrf21540dk_nrf52840: Convert to v2
4bce0e9b39 boards: arm: nrf52840dongle_nrf52840: Convert to v2
d0229c771f boards: arm: particle_argon: Convert to v2
23a0570e64 boards: arm: particle_boron: Convert to v2
b6d3e1764f boards: arm: particle_xenon: Convert to v2
499f3e7902 boards: arm: rak5010_nrf52840: Convert to v2
9ae6b1804d boards: arm: rak4631_nrf52840: Convert to v2
fe2c90da5c boards: arm: pinnacle_100_dvk: Convert to v2
3d4d46698c boards: arm: ubx_evkninab3_nrf52840: Convert to v2
b1afbf0158 boards: arm: ubx_bmd380eval_nrf52840: Convert to v2
9f9897c872 boards: arm: ubx_bmd345eval_nrf52840: Convert to v2
f7fb2030c7 boards: arm: ubx_bmd340eval_nrf52840: Convert to v2
7186432662 boards: arm: raytac_mdbt50q_db_40_nrf52840: Convert to v2
32c4bdc0c4 boards: arm: pan1780_evb: Convert to v2
7b64c638a8 boards: arm: pan1770_evb: Convert to v2
156ee8ad8a boards: arm: mg100: Convert to v2
3d33dadeb0 boards: arm: arduino_nano_33_ble: Convert to v2
4fee7371d2 boards: arm: adafruit_itsybitsy_nrf52840: Convert to v2
ad37a0c222 boards: arm: adafruit_feather_nrf52840: Convert to v2
cf85b7169f boards: arm: bt510: Convert to v2
44b67ac430 boards: arm: bt610: Convert to v2
7dbb65d371 boards: arm: ubx_evkninab4_nrf52833: Convert to v2
5e79cb957d boards: arm: raytac_mdbt50q_db_33_nrf52833: Convert to v2
12bd83a218 boards: arm: pan1782_evb: Convert to v2
1a135ec352 boards: arm: bbc_microbit_v2: Convert to v2
4dbe97e5ea boards: arm: nrf52833dk: Convert to v2
d632b90043 boards: arm: ubx_bmd360eval_nrf52811: Convert to v2
cc1a30f24b boards: arm: we_ophelia1ev_nrf52805: Convert to v2
df0df9000b boards: arm: ubx_bmd330eval_nrf52810: Convert to v2
d2c7972a9a boards: arm: nrf52dk: Convert to v2
202c2bf447 boards: arm: bl654_sensor_board: Convert to v2
c3e36f2042 boards: arm: bl654_usb: Convert to v2
b9dd58aea1 boards: arm: bl654_dvk: Convert to v2
0e1898b093 boards: arm: bl653_dvk: Convert to v2
286f4a7524 boards: arm: bl652_dvk: Convert to v2
d1709cdb37 boards: update nRF51dk board to board scheme v2.
8f040cff2c boards: Update nrf5340dk_nrf5340 to HWMv2 scheme
8c90fae8e0 boards: update nRF52840dk_nrf52840/nrf52811 board to
board scheme v2.
c828dcc60e boards: common: openocd-nrf5: Add HWMv2 support
c79f1b0d94 kconfig: soc: adopt Nordic SoC series to support hw model
v2 scheme
3584b30fc1 tests: Update board names for hwmv2
94024d940e boards: arm: arty_a7: Convert to v2
8053c3a8df boards: arm: scobc_module1: Convert to v2
d5473b76fe soc: designstart: Port to HWMv2
f5792b05e7 boards: arm: fvp_baser_aemv8r_aarch32: Convert to v2
ff202daa8e soc: fvp_aemv8r_aarch32: Port to HWMv2
e66cbc2945 boards: arm: v2m_musca_s1: Convert to v2
33b47b2edb boards: arm: v2m_musca_b1: Convert to v2
baeebd31d2 soc: musca: Port to HWMv2
73b257a3f9 boards: arm: v2m_beetle: Convert to v2
85de0888ec soc: beetle: Port to HWMv2
867960a891 manifest: Update modules
6ca677ed3a boards: arm: mps2: Convert to v2
bcf4ad19d4 twister: build_dir: convert / to _ to support hwmv2
0ac386683f soc: Kconfig.v2: Add SOC_PART_NUMBER
9242c3c78f soc: stm32: soc.yml: reorder series
248d17f160 boards: stm32: cleanup
0a67265e99 boards: stm32: fix for boards with revisions
f8d44317ee soc: stm32l5: Rename overlays for nucleo_l552ze_q ns
target.
400343d17e soc: stm32: Set default on USE_DT_CODE_PARTITION
d783ef549a soc: stm32l5: Update stm32l5 non secure targets in
various places
643aeac552 boards: Convert stm32l562e_dk to HWM v2
e601d64344 boards: Convert nucleo_l552ze_q to HWM v2
2f7a387b32 soc: st: Migrate stm32l5 series to new hw model
519752efcd boards: xenvm: doc: Remove reference to deleted file
06263dd717 boards: xenvm: Unset HEAP_MEM_POOL_SIZE in gicv3 variant
66b0df5526 boards: qemu_cortex_a53: Fix Kconfig warnings in SMP
variant
fa07bd9419 boards: mps3: Fix non-secure variant
8f6f0726dd boards: Move xenvm under xen
7b155a7031 boards: Raspberry Pi vendor fix
804697afa5 boards: Move 96b_aerocore to 96boards
d2f001e320 boards: x86: acrn: move and convert to HWMv2
ec7f7b3c30 tests: kernel: qemu_x86: adjust to the HWMv2
89dfcddc7e boards: x86: qemu_x86_tiny@768: change to board variant
eb724eb6a7 boards: x86: qemu_x86: optimize default HWMv2
configurations
6f1043cde6 boards: x86: qemu_x86: move and convert to HWMv2
cab924cbfb soc: x86: ia32: move and convert to HWMv2
237fdff918 soc: x86: lakemont: move and convert to HWMv2
03042b7704 boards: move 96b_carbon to 96boards folder
767b94414e boards: rename vendor seeed to seeed_studio
07fa3a3d79 boards: Convert olimex_lora_stm32wl_devkit to HWM v2
ba01d3beca boards: Convert nucleo_wl55jc to HWM v2
7ce84f4041 boards: Convert lora_e5_mini to HWM v2
b988bae576 boards: Convert lora_e5_dev_board to HWM v2
6fbf39c726 soc: v2: stm32: Migrate STM32WL series
4a41878442 soc: st: stm32g4: add missing include
1e79ba15f6 boards: Convert weact_stm32g431_core to HWM v2
ffdcb60185 boards: Convert nucleo_g474re to HWM v2
d6acb08d3e boards: Convert nucleo_g431rb to HWM v2
90e592ffd1 boards: Convert b_g474e_dpow1 to HWM v2
eb8a7e3441 soc: st: stm32: Migrate STM32G4 series
ada469f237 tests: Update board names for hwmv2
0342433187 boards: arm: npcx9m6f_evb: Convert to v2
c10248d964 boards: arm: npcx7m6fb_evb: Convert to v2
21ddc5e6a6 boards: arm: npcx4m8f_evb: Convert to v2
5500f3ef21 soc: npcx*: Port to HWMv2
e7baf09ede soc: m48x: Port to HWMv2
5bae4a6480 boards: arm: numaker_pfm_m467: Convert to v2
3b0bd70c8c soc: m46x: Port to HWMv2
d52eab9e83 boards: Convert stm32g081b_eval to HWM v2
6f2835cb11 boards: Convert stm32g071b_disco to HWM v2
ca36d331d2 boards: Convert stm32g0316_disco to HWM v2
662cc4e09b boards: Convert nucleo_g0b1re to HWM v2
dd9bc29769 boards: Convert nucleo_g071rb to HWM v2
353da23ffb boards: Convert nucleo_g070rb to HWM v2
acc932b424 boards: Convert nucleo_g031k8 to HWM v2
cea9b140fd boards: Convert google_twinkie_v2 to HWM v2
52e025943a soc: st: stm32: Migrate STM32G0 series
1c7347686a ci: update check_compliance to not create duplicate lines
in Kconfig
9debd98799 hwmv2: boards: up_squared_pro_700: Add missed intel_adl
changes
adab07c42f boards: Convert msp_exp432p401r_launchxl to HWM v2
642aacdcdf soc: ti_simplelink: Add missing SoC
48637066d3 boards: Fix file paths in documentation
e983bc2a23 samples/tests: Fix mps3 board name
61e0f32716 boards: Convert stm32f3_seco_d23 to HWM v2
a1688ff641 boards: Convert stm32f3_disco to HWM v2
35fb228599 boards: Convert stm32373c_eval to HWM v2
10e5d1122b boards: Convert nucleo_f334r8 to HWM v2
c319cb19f0 boards: Convert nucleo_f303re to HWM v2
11725ccac1 boards: Convert nucleo_f303k8 to HWM v2
400f7f6a4f boards: Convert nucleo_f302r8 to HWM v2
8d84861390 soc: v2: stm32: Migrate STM32F3 series
85b9eee7e8 boards: arm: kv260_r5: Convert to v2
dafbd638e4 boards: arm: mercury_xu: Convert to v2
3ecd12f415 boards: arm: qemu_cortex_r5: Convert to v2
5db2390e9d soc: xilinx_zyncmp: Port to HWMv2
9ba8195cdc boards: arm: qemu_cortex_a9: Convert to v2
8e94b85361 boards: arm: zybo: Convert to v2
c970127fc2 soc: xilinx_zynq7000: Port to HWMv2
394c75373c boards: arm: ast1030_evb: Convert to v2
f2a1cc8714 soc: ast10x0: Port to HWMv2
28f3f25945 boards: arm: cc3235sf_launchxl: Convert to v2
c3e480f740 boards: arm: cc3220sf_launchxl: Convert to v2
fd5847123f boards: arm: beagleconnect_freedom: Convert to v2
76ba9a0587 boards: arm: cc1352p1_launchxl: Convert to v2
719baa8850 boards: arm: cc1352r1_launchxl: Convert to v2
5060a61ae1 boards: arm: cc1352r_sensortag: Convert to v2
99584be1c5 boards: arm: cc26x2r1_launchxl: Convert to v2
2dc8933942 soc: ti_simplelink: Port to HWMv2
a5b004663b scripts/utils/board_v1_to_v2.py: couple of fixes
77c2c333e5 boards: move 96b_stm32_sensor_mez to 96boards
c14ff98650 boards: stm32f411e_disco: delete obsolete file
bcdc268ccf boards: Convert stm32mp157c_dk2 to HWM v2
0c8ba92e1f boards: Convert 96b_avenger96 to HWM v2
b54fe33077 soc: v2: stm32: Migrate STM32MP1 series
2ba3639b2a boards: Convert nucleo_c031c6 to HWM v2
dbc5ed79f5 soc: st: stm32: Migrate STM32C0 series
ce6d493aa3 boards: Convert stm32l1_disco to HWM v2
a28086a9ca boards: Convert nucleo_l152re to HWM v2
1b2a511d06 boards: Convert 96b_wistrio to HWM v2
ce281f09ab soc: v2: stm32: Migrate STM32L1 series
cdb5364fd7 boards: Convert stm32f769i_disco to HWM v2
768f173dcb boards: Convert stm32f7508_dk to HWM v2
21bbbbd9cb boards: Convert stm32f746g_disco to HWM v2
bab4265693 boards: Convert stm32f723e_disco to HWM v2
58f8fe82ba boards: Convert nucleo_f767zi to HWM v2
37e9084070 boards: Convert nucleo_f756zg to HWM v2
d467e7053a boards: Convert nucleo_f746zg to HWM v2
5f2808d7cc boards: Convert nucleo_f722ze to HWM v2
bbb73e7550 soc: st: Migrate stm32f7 series to new hw model
e9094afc4d soc: st: stm32: stm32f4: change SOC_STM32F405XG to
SOC_STM32F405XX
a1712cdd53 boards: Convert stm32f4_disco to HWM v2
5be404b365 boards: Convert stm32f469i_disco to HWM v2
baaa697ab2 boards: Convert stm32f429i_disc1 to HWM v2
69ecab3c90 boards: Convert stm32f412g_disco to HWM v2
2a572e3fb0 boards: Convert stm32f411e_disco to HWM v2
ecfbf42757 boards: Convert stm32f401_mini to HWM v2
e0191d03bb boards: Convert steval_fcu001v1 to HWM v2
4454648976 boards: Convert segger_trb_stm32f407 to HWM v2
f0ad6ee6b8 boards: Convert olimex_stm32_p405 to HWM v2
1f5e228ec8 boards: Convert olimex_stm32_h407 to HWM v2
834bdb615e boards: Convert olimex_stm32_h405 to HWM v2
8f27fa8de2 boards: Convert olimex_stm32_e407 to HWM v2
f8633a9038 boards: Convert nucleo_f446ze to HWM v2
07e0bd2c07 boards: Convert nucleo_f446re to HWM v2
24d7f625dc boards: Convert nucleo_f429zi to HWM v2
157a8cde53 boards: Convert nucleo_f413zh to HWM v2
4ec99c31b0 boards: Convert nucleo_f412zg to HWM v2
a21546140a boards: Convert nucleo_f411re to HWM v2
43f01ab6de boards: Convert nucleo_f410rb to HWM v2
60c16bcb8b boards: Convert nucleo_f401re to HWM v2
2db228d730 boards: Convert mikroe_mini_m4_for_stm32 to HWM v2
73fc26225c boards: Convert mikroe_clicker_2 to HWM v2
6b62d90114 boards: Convert google_dragonclaw to HWM v2
fa845af309 boards: Convert blackpill_f411ce to HWM v2
5c8c3c3be0 boards: Convert blackpill_f401ce to HWM v2
3c02db1290 boards: Convert blackpill_f401cc to HWM v2
7eeb723cb7 boards: Convert black_f407zg_pro to HWM v2
4f9461d068 boards: Convert black_f407ve to HWM v2
a821de8532 boards: Convert az3166_iotdevkit to HWM v2
ba580c7236 boards: Convert adi_sdp_k1 to HWM v2
eb272ddf19 boards: Convert adafruit_feather_stm32f405 to HWM v2
58ed121c3a boards: Convert 96b_stm32_sensor_mez to HWM v2
b0d70959d3 boards: Convert 96b_neonkey to HWM v2
b1088baadc boards: Convert 96b_carbon to HWM v2
18d867b0a9 boards: Convert 96b_argonkey to HWM v2
ee6ede7119 boards: Convert 96b_aerocore2 to HWM v2
b48e70ead9 soc: v2: stm32: Migrate STM32F4 series
14d2b955da cmake: convert path to CMake style before writing Kconfig
files
9c4ac6a202 boards: posix: bsim: Update paths
14b57f56d7 tests: drivers: gpio: gpio_ite_it8xxx2_v2: Temp fix
f3b173be18 scripts: board_v1_to_v2: Update following move to
boards_legacy
05b50f6691 cmake: CMake soc dir variable improvements for HWMv2
a188e01a12 hwmv2: move all ported boards and socs to their final
location
22c53e97b5 hwmv2: move all non-ported legacy boards and socs to
legacy folders
53f3b181b0 soc: ti_k3: Port to HWMv2
9f19a2075a soc: rk3568: Port to HWMv2
b8928b1628 soc: rk3399: Port to HWMv2
cda3a74868 boards: arm64: qemu_kvm_arm64: Convert to v2
70d704bd20 soc: x86: atom: move and convert to HWMv2
4789e1068e boards: x86: intel_rpl: move and convert raptor_lake
boards to HWMv2
384307e3dc soc: x86: raptor_lake: move and convert to HWMv2
ed025df674 boards: x86: intel_ehl: move and convert elkhart_lake
boards to HWMv2
994b6e1731 soc: x86: elkhart_lake: move and convert to HWMv2
73b30a04cf boards: x86: up_squared_pro_7000: move and convert to
HWMv2
83b133c207 boards: x86: intel_adl: move and convert alder_lake
boards to HWMv2
847a12f1e4 soc: alder_lake: move and convert to HWMv2
67f4c8d2a1 samples: up_squared: adjust gpio_counter to HWMv2
5326b5bfc0 boards: x86: up_squared: move and convert to HWMv2
cfd5e691b4 soc: apollo_lake: move and convert to HWMv2
ac9c235741 boards: xtensa: qemu_xtensa: Convert to v2
f198c3a761 ci: update to osource for soc/Kconfig.defconfig files
e438e6cad4 ci: add SOC_SERIES_ as false positive in
check_compliance.py
95e34da7c1 soc: v2: Convert st_stm32 to st/stm32
313717df76 soc: mps3: Fix missing family
392c3969ed boards: arm: am62x_m4: Convert to v2
8f245d764d tests: Update board names for hwmv2
8f71bb7b4f boards: arm64: khadas_edgev: Convert to v2
e27d23aad0 soc: rk3399: Port to HWMv2
80823b860e boards: arm64: roc_rk3568_pc: Convert to v2
72e4483dec soc: rk3568: Port to HWMv2
bed94669e3 boards: arm64: phycore_am62x_a53: Convert to v2
c01af5a7b8 soc: ti_k3: Port to HWMv2
1e563b4ca3 boards: arm64: xenvm: Convert to v2
76e484adae soc: xenvm: Port to HWMv2
34412f7fe2 boards: arm64: rpi_4b: Convert to v2
9be50e2ca9 soc: bcm2711: Port to HWMv2
bbbed12c2f boards: arm64: qemu_kvm_arm64: Convert to v2
4f5ec7ff8f soc: qemu_virt_arm64: Port to HWMv2
d8d1b9f200 boards: arm64: qemu_cortex_a53: Convert to v2
30bd34b31e soc: qemu_cortex_a53: Port to HWMv2
c20d0dcbb6 boards: arm64: fvp_baser_aemv8r: Convert to v2
02ed6af463 boards: arm64: fvp_base_revc_2xaemv8a: Convert to v2
1b175003a4 soc: fvp_aemv8*: Port to HWMv2
de231b911d boards: v2: Clean up obsolete comments
aa9597f6d9 boards: Convert waveshare_open103z to HWM v2
9644828c81 boards: Convert stm32vl_disco to HWM v2
86ab2bd430 boards: Convert stm32_min_dev to HWM v2
d88d3ddcc4 boards: Convert stm32f103_mini to HWM v2
0ccc0204e1 boards: Convert stm3210c_eval to HWM v2
dd9972d782 boards: Convert olimex_stm32_h103 to HWM v2
a2c2e1406d boards: Convert olimexino_stm32 to HWM v2
2d9c62e118 boards: Convert nucleo_f103rb to HWM v2
e8ba99dc59 soc: v2: stm32: Migrate STM32F1 series
9a93916604 tests: Update board names for hwmv2
9c4d94844d boards: arm: bcm958401m2: Convert to v2
feaf4ffba1 boards: arm: bcm958402m2: Convert to v2
87f0827121 soc: bcm_vk: Port to HWMv2
4526be24a5 boards: arm: quick_feather: Convert to v2
cd921d2b97 boards: arm: qomu: Convert to v2
b3c04051fc soc: quicklogic_eos_s3: Port to HWMv2
a73a9e7533 boards: v2: Clean up obsolete comments
8d87bcc167 boards: Convert stm32f0_disco to HWM v2
1933585785 boards: Convert stm32f072_eval to HWM v2
6f9fe5429d boards: Convert stm32f072b_disco to HWM v2
9dc78e4025 boards: Convert stm32f030_demo to HWM v2
35113e8923 boards: Convert nucleo_f091rc to HWM v2
b276aee9a4 boards: Convert nucleo_f070rb to HWM v2
795f8d611b boards: Convert nucleo_f042k6 to HWM v2
2d82646443 boards: Convert nucleo_f031k6 to HWM v2
959786f12d boards: Convert nucleo_f030r8 to HWM v2
81670db2e9 boards: Convert legend to HWM v2
8980430aad boards: Convert google_kukui to HWM v2
ac020f66e0 dts: stm32f0: fix few warnings
5140e4551a boards: v2: doc: Add vendors
77d640e0c9 soc: v2: stm32: Migrate STM32F0 series
0131e1c159 soc: v2: Add st_stm32 structure and common folder
36b63787a7 boards: v2: Add documentation index for converted boards
ae02fc5047 boards: sparc: qemu_leon3: Convert to v2
f38f7bb223 boards: sparc: gr716a: Convert to v2
d3cca3580e soc: gr716a: Port to HWMv2
6a8a0c1647 boards: sparc: generic_leon3: Convert to v2
faf22185ce soc: leon3: Port to HWMv2
e94762ecdc tests: Update board names for hwmv2
9afcc27e05 boards: xtensa: qemu_xtensa: Convert to v2
3e4a17018f soc: dc233c: Port to HWMv2
9188fdcd78 boards: xtensa: xt-sim: Convert to v2
fcaa41cb5d soc: xtensa_sample_controller: Port to HWMv2
dbc413f7f7 scripts: board_v1_to_v2: Fix CONFIG_SOC_SERIES_ exclusion
6be3d4bc80 kconfig: remove Kconfig BOARD_RPI_PICO_W safe guard.
f4442fa698 boards: v2: Add documentation index for converted boards
ec5fbd67f7 boards: nios2: qemu_nios2: Convert to v2
d3ef220460 soc: nios2-qemu: Port to HWMv2
a223f284b5 boards: nios2: altera_max10: Convert to v2
c381edcb73 soc: nios2f-zephyr: Port to HWMv2
97401c7d2a boards: mips: qemu_malta: Convert to v2
e7a3243a24 soc: qemu_malta: Port to HWMv2
bec82c690d boards: v2: Add documentation index for converted boards
94f6f9b636 boards: arm: w5500_evb_pico: Convert to v2
209235ab6e boards: arm: sparkfun_pro_micro_rp2040: Convert to v2
e5b1885907 boards: arm: adafruit_qt_py_rp2040: Convert to v2
4c750818f9 boards: arm: adafruit_kb2040: Convert to v2
8d3896caa4 boards: arm: rpi_pico: Convert to v2
42cff42c42 soc: rpi_pico: Port to HWMv2
c2df4ca9cb scripts: improve yaml schema and board.yml validation for
revisions
3970f90f71 cmake: clear BOARD_CACHE when invalid board identifier is
given
3a70ee9ccd cmake: improve board revision handling
3cda715fae scripts: board_v1_to_v2: Don't add select
CONFIG_SOC_SERIES_FOO
dc56a543f3 scripts: board_v1_to_v2: Add License + copyright
87147f88c4 cmake: prefer cache BOARD_IDENTIFIER over extracting from
BOARD
65f5dc5b8c cmake: fail when board identifier is applied in legacy hw
model
7db2b6efd8 cmake: cache BOARD_IDENTIFIER to preserve it between
CMake invocations
85dddac5a2 scripts: using extend in list_boards for variant list
6ae5c4e7fd scripts: utils: add board v1->v2 conversion utility
ef834a12d0 maintainers: update Renesas RZT2M path
3ab7830625 boards: renesas: add documentation entry
a0c2ca0491 boards: arm: add documentation entry
27ff3654b7 boards: gigadevice: add documentation entry
6e02f43c0a maintainers: update GD32 paths
1bfcf1d974 boards: gd32l233r_eval: convert to HWMv2
6e621ee43f boards: gd32f470i_eval: convert to HWMv2
219b149768 boards: gd32f450z_eval: convert to HWMv2
91c52b0d39 boards: gd32f450v_start: convert to HWMv2
f0e0a973f6 boards: gd32f407v_start: convert to HWMv2
6f592b64c9 boards: gd32f403z_eval: convert to HWMv2
4bcb4b2ac8 boards: gd32f350r_eval: convert to HWMv2
fdc7ed6eb0 boards: gd32e507z_eval: convert to HWMv2
770376250d boards: gd32e507v_start: convert to HWMv2
a6d8b92e86 boards: gd32e103v_eval: convert to HWMv2
a5f8e5daa1 boards: gd32a503v_eval: convert to HWMv2
5ee799cc5f boards: gd32f450i_eval: convert to HWMv2
8aa8ce4ac8 soc: gigadevice: port to HWMv2
4e203c14c7 cmake: enhanced board entry file handling
312265ee04 scripts: make SoC field mandatory in board.yml
c12ae3bcbc boards: update Renesas rzt2m board.yml to contain SoC
information
c5321c1dbe cmake: make SoC optional for boards containing a single
SoC
bcc06c60ae scripts: support SoC list output for boards
db9e46010c twister: update testcase.yaml and sample.yaml to
mps3/an547 identifier
a988adee7d boards: update arm mps3 an547 board to HWMv2 scheme
7dc2c9db0c soc: use HWMv2 for arm mps3 SoC
c506675b7c boards: update Renesas Starter Kit+ for RZ/T2M board to
HWMv2 scheme
3abb792073 soc: use HWMv2 for renesas_rzt2m SoC
4f52bc646e cmake: support hw model v2 in arch/Kconfig tree
a712b5005b scripts: extend kconfig compliance to verify board / SoC
scheme v2
baa55141a1 twister: update twister testplan.py to handle HWMv2
boards
1f026f70eb boards: extend list_boards.py and update boards CMake
module
bd854a3af8 cmake: introduce arch and soc cmake modules for hw model
v2
c9edefa8fd arch: add existing archs to archs.yml for HWMv2 support
61bbfb5ba2 scripts: introduce list_hardware.py for listing of
architectures and SoCs
a4d1980c35 build: board/ soc: introduce hw model v2 scheme
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
Signed-off-by: David Leach <david.leach@nxp.com>
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This commit is contained in:
Torsten Rasmussen
Anas Nashif
parent
418b0a1e65
commit
8dc3f85622
13315 changed files with 159282 additions and 157416 deletions
9
soc/atmel/sam/CMakeLists.txt
Normal file
9
soc/atmel/sam/CMakeLists.txt
Normal file
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@ -0,0 +1,9 @@
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# Makefile - Atmel SAM MCU family
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#
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# Copyright (c) 2016 Piotr Mienkowski
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# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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#
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add_subdirectory(common)
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add_subdirectory(${SOC_SERIES})
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12
soc/atmel/sam/Kconfig
Normal file
12
soc/atmel/sam/Kconfig
Normal file
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@ -0,0 +1,12 @@
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# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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config SOC_FAMILY_ATMEL_SAM
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select ASF
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select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
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if SOC_FAMILY_ATMEL_SAM
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rsource "*/Kconfig"
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endif # SOC_FAMILY_ATMEL_SAM
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26
soc/atmel/sam/Kconfig.defconfig
Normal file
26
soc/atmel/sam/Kconfig.defconfig
Normal file
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# Atmel SAM MCU family default configuration options
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# Copyright (c) 2016 Piotr Mienkowski
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# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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if SOC_FAMILY_ATMEL_SAM
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|
||||
rsource "*/Kconfig.defconfig"
|
||||
|
||||
config CLOCK_CONTROL
|
||||
default y
|
||||
|
||||
config GPIO
|
||||
default y
|
||||
|
||||
config PINCTRL
|
||||
default y
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
|
||||
|
||||
config WATCHDOG
|
||||
default y
|
||||
|
||||
endif # SOC_FAMILY_ATMEL_SAM
|
||||
10
soc/atmel/sam/Kconfig.soc
Normal file
10
soc/atmel/sam/Kconfig.soc
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_FAMILY_ATMEL_SAM
|
||||
bool
|
||||
|
||||
config SOC_FAMILY
|
||||
default "atmel_sam" if SOC_FAMILY_ATMEL_SAM
|
||||
|
||||
rsource "*/Kconfig.soc"
|
||||
14
soc/atmel/sam/common/CMakeLists.txt
Normal file
14
soc/atmel/sam/common/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_include_directories(.)
|
||||
|
||||
zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_pmc.c)
|
||||
zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_gpio.c)
|
||||
zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_supc.c)
|
||||
zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_power.c)
|
||||
zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_poweroff.c)
|
||||
|
||||
zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_SAM4L soc_sam4l_pm.c)
|
||||
zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_SAM4L soc_sam4l_gpio.c)
|
||||
zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_SAM4L soc_sam4l_poweroff.c)
|
||||
96
soc/atmel/sam/common/Kconfig
Normal file
96
soc/atmel/sam/common/Kconfig
Normal file
|
|
@ -0,0 +1,96 @@
|
|||
# Atmel SAM MCU series general configuration options
|
||||
|
||||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_FAMILY_ATMEL_SAM && !SOC_SERIES_SAM4L
|
||||
|
||||
menu "Clocks"
|
||||
|
||||
config SOC_ATMEL_SAM_EXT_SLCK
|
||||
bool "Use external crystal oscillator for slow clock"
|
||||
help
|
||||
Says y if you want to use external 32 kHz crystal oscillator to drive
|
||||
the slow clock. Note that this adds a few seconds to boot time, as the
|
||||
crystal needs to stabilize after power-up.
|
||||
|
||||
Says n if you do not need accurate and precise timers. The slow clock
|
||||
will be driven by the internal fast RC oscillator running at 32 kHz.
|
||||
|
||||
config SOC_ATMEL_SAM_EXT_MAINCK
|
||||
bool "Use external crystal oscillator for main clock"
|
||||
default y
|
||||
help
|
||||
The main clock is being used to drive the PLL, and thus driving the
|
||||
processor clock.
|
||||
|
||||
Says y if you want to use external crystal oscillator to drive the
|
||||
main clock. Note that this adds about a second to boot time, as the
|
||||
crystal needs to stabilize after power-up.
|
||||
|
||||
The crystal used here can be from 3 to 20 MHz.
|
||||
|
||||
Says n here will use the internal fast RC oscillator running at 12 MHz.
|
||||
|
||||
menu "PLL A"
|
||||
|
||||
config SOC_ATMEL_SAM_PLLA_MULA
|
||||
int "PLL MULA"
|
||||
default 6 if SOC_SERIES_SAM3X
|
||||
default 9 if SOC_SERIES_SAM4S || SOC_SERIES_SAM4E
|
||||
default 24 if SOC_SERIES_SAME70 || SOC_SERIES_SAMV71
|
||||
range 1 62
|
||||
help
|
||||
This is the multiplier (MULA) used by the PLL.
|
||||
The processor clock is (MAINCK * (MULA + 1) / DIVA).
|
||||
|
||||
Board config file can override this settings for a particular board.
|
||||
|
||||
With default of MULA == N, and DIVA == 1 the PLL will run at N+1 times
|
||||
the main clock frequency.
|
||||
|
||||
config SOC_ATMEL_SAM_PLLA_DIVA
|
||||
int "PLL DIVA"
|
||||
default 1
|
||||
range 1 255
|
||||
help
|
||||
This is the divider (DIVA) used by the PLL.
|
||||
The processor clock is (MAINCK * (MULA + 1) / DIVA).
|
||||
|
||||
Board config file can override this settings
|
||||
for a particular board.
|
||||
|
||||
With default of MULA == N, and DIVA == 1 the PLL will run at N+1 times
|
||||
the main clock frequency.
|
||||
|
||||
config SOC_ATMEL_SAM_MDIV
|
||||
int "MDIV"
|
||||
depends on SOC_SERIES_SAME70 || SOC_SERIES_SAMV71
|
||||
default 2
|
||||
range 1 4
|
||||
help
|
||||
This divisor defines a ratio between processor clock (HCLK)
|
||||
and master clock (MCK) where the maximum value is 150MHz:
|
||||
MCK = HCLK / MDIV
|
||||
|
||||
endmenu # PLL A
|
||||
endmenu # clocks
|
||||
|
||||
config SOC_ATMEL_SAM_WAIT_MODE
|
||||
bool "CPU goes to Wait mode instead of Sleep mode"
|
||||
depends on SOC_ATMEL_SAM_EXT_MAINCK
|
||||
default y if DEBUG
|
||||
help
|
||||
For JTAG debugging CPU clock (HCLK) should not stop. In order to
|
||||
achieve this, make CPU go to Wait mode instead of Sleep mode while
|
||||
using external crystal oscillator for main clock.
|
||||
|
||||
config SOC_ATMEL_SAM_DISABLE_ERASE_PIN
|
||||
bool "Disable ERASE pin"
|
||||
help
|
||||
At reset ERASE pin is configured in System IO mode. Asserting the
|
||||
ERASE pin at '1' will completely erase Flash memory. Setting this
|
||||
option will switch the pin to general IO mode giving control of the
|
||||
pin to the GPIO module.
|
||||
|
||||
endif # SOC_FAMILY_ATMEL_SAM && !SOC_SERIES_SAM4L
|
||||
21
soc/atmel/sam/common/atmel_sam_dt.h
Normal file
21
soc/atmel/sam/common/atmel_sam_dt.h
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Linaro Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/** @file
|
||||
* @brief Atmel SAM MCU family devicetree helper macros
|
||||
*/
|
||||
|
||||
#ifndef _ATMEL_SAM_DT_H_
|
||||
#define _ATMEL_SAM_DT_H_
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
|
||||
/* Devicetree macros related to clock */
|
||||
|
||||
#define ATMEL_SAM_DT_CPU_CLK_FREQ_HZ \
|
||||
DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
|
||||
|
||||
#endif /* _ATMEL_SAM_SOC_DT_H_ */
|
||||
17
soc/atmel/sam/common/pinctrl_soc.h
Normal file
17
soc/atmel/sam/common/pinctrl_soc.h
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2022, Gerson Fernando Budke <nandojve@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* Atmel SAM SoC specific helpers for pinctrl driver
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_ARM_ATMEL_SAM_COMMON_PINCTRL_SOC_H_
|
||||
#define ZEPHYR_SOC_ARM_ATMEL_SAM_COMMON_PINCTRL_SOC_H_
|
||||
|
||||
#include <zephyr/drivers/pinctrl/pinctrl_soc_sam_common.h>
|
||||
|
||||
#endif /* ZEPHYR_SOC_ARM_ATMEL_SAM_COMMON_PINCTRL_SOC_H_ */
|
||||
17
soc/atmel/sam/common/pwm_fixup.h
Normal file
17
soc/atmel/sam/common/pwm_fixup.h
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _ATMEL_SAM_PWM_FIXUP_H_
|
||||
#define _ATMEL_SAM_PWM_FIXUP_H_
|
||||
|
||||
/* The SAMV71 HALs change the name of the field, so we need to
|
||||
* define it this way to match how the other SoC variants name it
|
||||
*/
|
||||
#if defined(CONFIG_SOC_SERIES_SAMV71)
|
||||
#define PWM_CH_NUM PwmChNum
|
||||
#endif
|
||||
|
||||
#endif /* _ATMEL_SAM_PWM_FIXUP_H_ */
|
||||
204
soc/atmel/sam/common/soc_gpio.c
Normal file
204
soc/atmel/sam/common/soc_gpio.c
Normal file
|
|
@ -0,0 +1,204 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Piotr Mienkowski
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/** @file
|
||||
* @brief Atmel SAM MCU family General Purpose Input Output (GPIO)
|
||||
* module HAL driver.
|
||||
*/
|
||||
|
||||
#include <zephyr/sys/__assert.h>
|
||||
#include "soc_gpio.h"
|
||||
|
||||
/*
|
||||
* There exist minor differences between SAM MCU family members in naming
|
||||
* of some of the registers. Check that our expectations are met.
|
||||
*/
|
||||
#if (!defined(PIO_IFSCER_P0) && !defined(PIO_DIFSR_P0)) \
|
||||
|| (!defined(PIO_IFSCDR_P0) && !defined(PIO_SCIFSR_P0)) \
|
||||
|| (!defined(PIO_ABCDSR_P0) && !defined(PIO_ABSR_P0))
|
||||
#error "Unsupported Atmel SAM MCU series"
|
||||
#endif
|
||||
|
||||
static void configure_common_attr(Pio *pio, uint32_t mask, uint32_t flags)
|
||||
{
|
||||
/* Disable interrupts on the pin(s) */
|
||||
pio->PIO_IDR = mask;
|
||||
|
||||
/* Configure pull-up(s) */
|
||||
if (flags & SOC_GPIO_PULLUP) {
|
||||
pio->PIO_PUER = mask;
|
||||
} else {
|
||||
pio->PIO_PUDR = mask;
|
||||
}
|
||||
|
||||
/* Configure pull-down only for MCU series that support it */
|
||||
#if defined PIO_PPDER_P0
|
||||
/* Configure pull-down(s) */
|
||||
if (flags & SOC_GPIO_PULLDOWN) {
|
||||
pio->PIO_PPDER = mask;
|
||||
} else {
|
||||
pio->PIO_PPDDR = mask;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Configure open drain (multi-drive) */
|
||||
if (flags & SOC_GPIO_OPENDRAIN) {
|
||||
pio->PIO_MDER = mask;
|
||||
} else {
|
||||
pio->PIO_MDDR = mask;
|
||||
}
|
||||
}
|
||||
|
||||
static void configure_input_attr(Pio *pio, uint32_t mask, uint32_t flags)
|
||||
{
|
||||
/* Configure input filter */
|
||||
if ((flags & SOC_GPIO_IN_FILTER_MASK) != 0U) {
|
||||
if ((flags & SOC_GPIO_IN_FILTER_MASK) == SOC_GPIO_IN_FILTER_DEBOUNCE) {
|
||||
/* Enable de-bounce, disable de-glitch */
|
||||
#if defined PIO_IFSCER_P0
|
||||
pio->PIO_IFSCER = mask;
|
||||
#elif defined PIO_DIFSR_P0
|
||||
pio->PIO_DIFSR = mask;
|
||||
#endif
|
||||
} else {
|
||||
/* Disable de-bounce, enable de-glitch */
|
||||
#if defined PIO_IFSCDR_P0
|
||||
pio->PIO_IFSCDR = mask;
|
||||
#elif defined PIO_SCIFSR_P0
|
||||
pio->PIO_SCIFSR = mask;
|
||||
#endif
|
||||
}
|
||||
pio->PIO_IFER = mask;
|
||||
} else {
|
||||
pio->PIO_IFDR = mask;
|
||||
}
|
||||
|
||||
/* Configure interrupt */
|
||||
if (flags & SOC_GPIO_INT_ENABLE) {
|
||||
if ((flags & SOC_GPIO_INT_TRIG_MASK) == SOC_GPIO_INT_TRIG_DOUBLE_EDGE) {
|
||||
/* Disable additional interrupt modes, enable the default */
|
||||
pio->PIO_AIMDR = mask;
|
||||
} else {
|
||||
/* Configure additional interrupt mode */
|
||||
if ((flags & SOC_GPIO_INT_TRIG_MASK) == SOC_GPIO_INT_TRIG_EDGE) {
|
||||
/* Select edge detection event */
|
||||
pio->PIO_ESR = mask;
|
||||
} else {
|
||||
/* Select level detection event */
|
||||
pio->PIO_LSR = mask;
|
||||
}
|
||||
|
||||
if (flags & SOC_GPIO_INT_ACTIVE_HIGH) {
|
||||
pio->PIO_REHLSR = mask;
|
||||
} else {
|
||||
pio->PIO_FELLSR = mask;
|
||||
}
|
||||
/* Enable additional interrupt mode */
|
||||
pio->PIO_AIMER = mask;
|
||||
}
|
||||
/* Enable interrupts on the pin(s) */
|
||||
pio->PIO_IER = mask;
|
||||
} else {
|
||||
/* Nothing to do. All interrupts were disabled in the
|
||||
* beginning.
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
static void configure_output_attr(Pio *pio, uint32_t mask, uint32_t flags)
|
||||
{
|
||||
/* Enable control of the I/O line by the PIO_ODSR register */
|
||||
pio->PIO_OWER = mask;
|
||||
}
|
||||
|
||||
void soc_gpio_configure(const struct soc_gpio_pin *pin)
|
||||
{
|
||||
uint32_t mask = pin->mask;
|
||||
Pio *pio = pin->regs;
|
||||
uint8_t periph_id = pin->periph_id;
|
||||
uint32_t flags = pin->flags;
|
||||
uint32_t type = pin->flags & SOC_GPIO_FUNC_MASK;
|
||||
|
||||
/* Configure pin attributes common to all functions */
|
||||
configure_common_attr(pio, mask, flags);
|
||||
|
||||
switch (type) {
|
||||
case SOC_GPIO_FUNC_A:
|
||||
#if defined PIO_ABCDSR_P0
|
||||
pio->PIO_ABCDSR[0] &= ~mask;
|
||||
pio->PIO_ABCDSR[1] &= ~mask;
|
||||
#elif defined PIO_ABSR_P0
|
||||
pio->PIO_ABSR &= ~mask;
|
||||
#endif
|
||||
/* Connect pin to the peripheral (disconnect PIO block) */
|
||||
pio->PIO_PDR = mask;
|
||||
break;
|
||||
|
||||
case SOC_GPIO_FUNC_B:
|
||||
#if defined PIO_ABCDSR_P0
|
||||
pio->PIO_ABCDSR[0] |= mask;
|
||||
pio->PIO_ABCDSR[1] &= ~mask;
|
||||
#elif defined PIO_ABSR_P0
|
||||
pio->PIO_ABSR |= mask;
|
||||
#endif
|
||||
/* Connect pin to the peripheral (disconnect PIO block) */
|
||||
pio->PIO_PDR = mask;
|
||||
break;
|
||||
|
||||
#if defined PIO_ABCDSR_P0
|
||||
case SOC_GPIO_FUNC_C:
|
||||
pio->PIO_ABCDSR[0] &= ~mask;
|
||||
pio->PIO_ABCDSR[1] |= mask;
|
||||
/* Connect pin to the peripheral (disconnect PIO block) */
|
||||
pio->PIO_PDR = mask;
|
||||
break;
|
||||
|
||||
case SOC_GPIO_FUNC_D:
|
||||
pio->PIO_ABCDSR[0] |= mask;
|
||||
pio->PIO_ABCDSR[1] |= mask;
|
||||
/* Connect pin to the peripheral (disconnect PIO block) */
|
||||
pio->PIO_PDR = mask;
|
||||
break;
|
||||
#endif
|
||||
|
||||
case SOC_GPIO_FUNC_IN:
|
||||
/* Enable module's clock */
|
||||
soc_pmc_peripheral_enable(periph_id);
|
||||
/* Configure pin attributes related to input function */
|
||||
configure_input_attr(pio, mask, flags);
|
||||
/* Configure pin as input */
|
||||
pio->PIO_ODR = mask;
|
||||
pio->PIO_PER = mask;
|
||||
break;
|
||||
|
||||
case SOC_GPIO_FUNC_OUT_1:
|
||||
case SOC_GPIO_FUNC_OUT_0:
|
||||
/* Set initial pin value */
|
||||
if (type == SOC_GPIO_FUNC_OUT_1) {
|
||||
pio->PIO_SODR = mask;
|
||||
} else {
|
||||
pio->PIO_CODR = mask;
|
||||
}
|
||||
|
||||
/* Configure pin attributes related to output function */
|
||||
configure_output_attr(pio, mask, flags);
|
||||
/* Configure pin(s) as output(s) */
|
||||
pio->PIO_OER = mask;
|
||||
pio->PIO_PER = mask;
|
||||
break;
|
||||
|
||||
default:
|
||||
__ASSERT(0, "Unsupported pin function, check pin.flags value");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
void soc_gpio_list_configure(const struct soc_gpio_pin pins[],
|
||||
unsigned int size)
|
||||
{
|
||||
for (int i = 0; i < size; i++) {
|
||||
soc_gpio_configure(&pins[i]);
|
||||
}
|
||||
}
|
||||
218
soc/atmel/sam/common/soc_gpio.h
Normal file
218
soc/atmel/sam/common/soc_gpio.h
Normal file
|
|
@ -0,0 +1,218 @@
|
|||
/*
|
||||
* Copyright (c) 2016-2017 Piotr Mienkowski
|
||||
* Copyright (c) 2020 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/** @file
|
||||
* @brief Atmel SAM MCU family General Purpose Input Output (GPIO)
|
||||
* module HAL driver.
|
||||
*/
|
||||
|
||||
#ifndef _ATMEL_SAM_SOC_GPIO_H_
|
||||
#define _ATMEL_SAM_SOC_GPIO_H_
|
||||
|
||||
#include <zephyr/types.h>
|
||||
#include <soc.h>
|
||||
|
||||
/*
|
||||
* Pin flags/attributes
|
||||
*/
|
||||
|
||||
/* TODO: replace hard coded pin attribute values with defines provided
|
||||
* in gpio.h, once the official API is clean.
|
||||
*/
|
||||
|
||||
#define SOC_GPIO_DEFAULT (0)
|
||||
|
||||
#define SOC_GPIO_FLAGS_POS (0)
|
||||
#define SOC_GPIO_FLAGS_MASK (7 << SOC_GPIO_FLAGS_POS)
|
||||
#define SOC_GPIO_PULLUP_POS (0)
|
||||
#define SOC_GPIO_PULLUP (1 << SOC_GPIO_PULLUP_POS)
|
||||
#define SOC_GPIO_PULLDOWN_POS (1)
|
||||
#define SOC_GPIO_PULLDOWN (1 << SOC_GPIO_PULLDOWN_POS)
|
||||
#define SOC_GPIO_OPENDRAIN_POS (2)
|
||||
#define SOC_GPIO_OPENDRAIN (1 << SOC_GPIO_OPENDRAIN_POS)
|
||||
|
||||
/* Bit field: SOC_GPIO_IN_FILTER */
|
||||
#define SOC_GPIO_IN_FILTER_POS (3)
|
||||
#define SOC_GPIO_IN_FILTER_MASK (3 << SOC_GPIO_IN_FILTER_POS)
|
||||
#define SOC_GPIO_IN_FILTER_NONE (0 << SOC_GPIO_IN_FILTER_POS)
|
||||
#define SOC_GPIO_IN_FILTER_DEBOUNCE (1 << SOC_GPIO_IN_FILTER_POS)
|
||||
#define SOC_GPIO_IN_FILTER_DEGLITCH (2 << SOC_GPIO_IN_FILTER_POS)
|
||||
|
||||
#define SOC_GPIO_INT_ENABLE (1 << 5)
|
||||
|
||||
/* Bit field: SOC_GPIO_INT_TRIG */
|
||||
#define SOC_GPIO_INT_TRIG_POS (6)
|
||||
#define SOC_GPIO_INT_TRIG_MASK (3 << SOC_GPIO_INT_TRIG_POS)
|
||||
/** Interrupt is triggered by a level detection event. */
|
||||
#define SOC_GPIO_INT_TRIG_LEVEL (0 << SOC_GPIO_INT_TRIG_POS)
|
||||
/** Interrupt is triggered by an edge detection event. */
|
||||
#define SOC_GPIO_INT_TRIG_EDGE (1 << SOC_GPIO_INT_TRIG_POS)
|
||||
/** Interrupt is triggered by any edge detection event. */
|
||||
#define SOC_GPIO_INT_TRIG_DOUBLE_EDGE (2 << SOC_GPIO_INT_TRIG_POS)
|
||||
|
||||
/** Interrupt is triggered by a high level / rising edge detection event */
|
||||
#define SOC_GPIO_INT_ACTIVE_HIGH (1 << 8)
|
||||
|
||||
/* Bit field: SOC_GPIO_FUNC */
|
||||
#define SOC_GPIO_FUNC_POS (16)
|
||||
#define SOC_GPIO_FUNC_MASK (15 << SOC_GPIO_FUNC_POS)
|
||||
/** Connect pin to peripheral A. */
|
||||
#define SOC_GPIO_FUNC_A (0 << SOC_GPIO_FUNC_POS)
|
||||
/** Connect pin to peripheral B. */
|
||||
#define SOC_GPIO_FUNC_B (1 << SOC_GPIO_FUNC_POS)
|
||||
/** Connect pin to peripheral C. */
|
||||
#define SOC_GPIO_FUNC_C (2 << SOC_GPIO_FUNC_POS)
|
||||
/** Connect pin to peripheral D. */
|
||||
#define SOC_GPIO_FUNC_D (3 << SOC_GPIO_FUNC_POS)
|
||||
/** Connect pin to peripheral E. */
|
||||
#define SOC_GPIO_FUNC_E (4 << SOC_GPIO_FUNC_POS)
|
||||
/** Connect pin to peripheral F. */
|
||||
#define SOC_GPIO_FUNC_F (5 << SOC_GPIO_FUNC_POS)
|
||||
/** Connect pin to peripheral G. */
|
||||
#define SOC_GPIO_FUNC_G (6 << SOC_GPIO_FUNC_POS)
|
||||
/** Connect pin to peripheral H. */
|
||||
#define SOC_GPIO_FUNC_H (7 << SOC_GPIO_FUNC_POS)
|
||||
/** Configure pin as input. */
|
||||
#define SOC_GPIO_FUNC_IN (8 << SOC_GPIO_FUNC_POS)
|
||||
/** Configure pin as output and set it initial value to 0. */
|
||||
#define SOC_GPIO_FUNC_OUT_0 (9 << SOC_GPIO_FUNC_POS)
|
||||
/** Configure pin as output and set it initial value to 1. */
|
||||
#define SOC_GPIO_FUNC_OUT_1 (10 << SOC_GPIO_FUNC_POS)
|
||||
|
||||
struct soc_gpio_pin {
|
||||
uint32_t mask; /** pin(s) bit mask */
|
||||
#ifdef ID_GPIO
|
||||
Gpio *regs; /** pointer to registers of the GPIO controller */
|
||||
#else
|
||||
Pio *regs; /** pointer to registers of the PIO controller */
|
||||
#endif
|
||||
uint8_t periph_id; /** peripheral ID of the PIO controller */
|
||||
uint32_t flags; /** pin flags/attributes */
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Configure GPIO pin(s).
|
||||
*
|
||||
* Configure one or several pins belonging to the same GPIO port.
|
||||
* Example scenarios:
|
||||
* - configure pin(s) as input with debounce filter enabled.
|
||||
* - connect pin(s) to a peripheral B and enable pull-up.
|
||||
* - configure pin(s) as open drain output.
|
||||
* All pins are configured in the same way.
|
||||
*
|
||||
* @remark The function will enable the GPIO module's clock only if
|
||||
* any of its pins is configured as an input. This is typically what
|
||||
* a user wants. A pin will function correctly without clock enabled
|
||||
* when configured as an output or connected to a peripheral.
|
||||
* In some cases, e.g. when a pin is configured as an output with
|
||||
* a pull-up and user wants to read pin's input value it is necessary
|
||||
* to enable GPIO module's clock separately.
|
||||
*
|
||||
* @param pin pin's configuration data such as pin mask, pin attributes, etc.
|
||||
*/
|
||||
void soc_gpio_configure(const struct soc_gpio_pin *pin);
|
||||
|
||||
/**
|
||||
* @brief Configure a list of GPIO pin(s).
|
||||
*
|
||||
* Configure an arbitrary amount of pins in an arbitrary way. Each
|
||||
* configuration entry is a single item in an array passed as an
|
||||
* argument to the function.
|
||||
*
|
||||
* @param pins an array where each item contains pin's configuration data.
|
||||
* @param size size of the pin list.
|
||||
*/
|
||||
void soc_gpio_list_configure(const struct soc_gpio_pin pins[],
|
||||
unsigned int size);
|
||||
|
||||
/**
|
||||
* @brief Set pin(s) high.
|
||||
*
|
||||
* Set pin(s) defined in the mask parameter to high. The pin(s) have to be
|
||||
* configured as output by the configure function. The flags field which
|
||||
* is part of pin struct is ignored.
|
||||
*
|
||||
* @param pin pointer to a pin instance describing one or more pins.
|
||||
*/
|
||||
static inline void soc_gpio_set(const struct soc_gpio_pin *pin)
|
||||
{
|
||||
#ifdef ID_GPIO
|
||||
pin->regs->OVRS = pin->mask;
|
||||
#else
|
||||
pin->regs->PIO_SODR = pin->mask;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set pin(s) low.
|
||||
*
|
||||
* Set pin(s) defined in the mask field to low. The pin(s) have to be
|
||||
* configured as output by the configure function. The flags field which
|
||||
* is part of pin struct is ignored.
|
||||
*
|
||||
* @param pin pointer to a pin instance describing one or more pins.
|
||||
*/
|
||||
static inline void soc_gpio_clear(const struct soc_gpio_pin *pin)
|
||||
{
|
||||
#ifdef ID_GPIO
|
||||
pin->regs->OVRC = pin->mask;
|
||||
#else
|
||||
pin->regs->PIO_CODR = pin->mask;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get pin(s) value.
|
||||
*
|
||||
* Get value of the pin(s) defined in the mask field.
|
||||
*
|
||||
* @param pin pointer to a pin instance describing one or more pins.
|
||||
* @return pin(s) value. To assess value of a specific pin the pin's bit
|
||||
* field has to be read.
|
||||
*/
|
||||
static inline uint32_t soc_gpio_get(const struct soc_gpio_pin *pin)
|
||||
{
|
||||
#ifdef ID_GPIO
|
||||
return pin->regs->PVR & pin->mask;
|
||||
#else
|
||||
return pin->regs->PIO_PDSR & pin->mask;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the length of the debounce window.
|
||||
*
|
||||
* The debouncing filter automatically rejects a pulse with a duration of less
|
||||
* than 1/2 programmable divided slow clock period tdiv_slck, while a pulse with
|
||||
* a duration of one or more tdiv_slck cycles is accepted. For pulse durations
|
||||
* between 1/2 selected clock cycle and one tdiv_slck clock cycle, the pulse may
|
||||
* or may not be taken into account, depending on the precise timing of its
|
||||
* occurrence.
|
||||
*
|
||||
* tdiv_slck = ((div + 1) x 2) x tslck
|
||||
* where tslck is the slow clock, typically 32.768 kHz.
|
||||
*
|
||||
* Setting the length of the debounce window is only meaningful if the pin is
|
||||
* configured as input and the debounce pin option is enabled.
|
||||
*
|
||||
* @param pin pointer to a pin instance describing one or more pins.
|
||||
* @param div slow clock divider, valid values: from 0 to 2^14 - 1
|
||||
*/
|
||||
static inline void soc_gpio_debounce_length_set(const struct soc_gpio_pin *pin,
|
||||
uint32_t div)
|
||||
{
|
||||
#ifdef ID_GPIO
|
||||
if (div) {
|
||||
pin->regs->STERS = pin->mask;
|
||||
} else {
|
||||
pin->regs->STERC = pin->mask;
|
||||
}
|
||||
#else
|
||||
pin->regs->PIO_SCDR = PIO_SCDR_DIV(div);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* _ATMEL_SAM_SOC_GPIO_H_ */
|
||||
70
soc/atmel/sam/common/soc_pmc.c
Normal file
70
soc/atmel/sam/common/soc_pmc.c
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Piotr Mienkowski
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/** @file
|
||||
* @brief Atmel SAM MCU family Power Management Controller (PMC) module
|
||||
* HAL driver.
|
||||
*/
|
||||
|
||||
#include <soc.h>
|
||||
#include <zephyr/sys/__assert.h>
|
||||
#include <zephyr/sys/util.h>
|
||||
|
||||
#if ID_PERIPH_COUNT > 74
|
||||
#error "Unsupported SoC, update soc_pmc.c functions"
|
||||
#endif
|
||||
|
||||
void soc_pmc_peripheral_enable(uint32_t id)
|
||||
{
|
||||
__ASSERT(id < ID_PERIPH_COUNT, "Invalid peripheral id");
|
||||
|
||||
if (id < 32) {
|
||||
PMC->PMC_PCER0 = BIT(id);
|
||||
#if ID_PERIPH_COUNT > 32
|
||||
} else if (id < 64) {
|
||||
PMC->PMC_PCER1 = BIT(id & 0x1F);
|
||||
#endif
|
||||
#if ID_PERIPH_COUNT > 64
|
||||
} else {
|
||||
/* Nothing to do, thes peripherals can't be enabled */
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
void soc_pmc_peripheral_disable(uint32_t id)
|
||||
{
|
||||
__ASSERT(id < ID_PERIPH_COUNT, "Invalid peripheral id");
|
||||
|
||||
if (id < 32) {
|
||||
PMC->PMC_PCDR0 = BIT(id);
|
||||
#if ID_PERIPH_COUNT > 32
|
||||
} else if (id < 64) {
|
||||
PMC->PMC_PCDR1 = BIT(id & 0x1F);
|
||||
#endif
|
||||
#if ID_PERIPH_COUNT > 64
|
||||
} else {
|
||||
/* Nothing to do, these peripherals can't be disabled */
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t soc_pmc_peripheral_is_enabled(uint32_t id)
|
||||
{
|
||||
__ASSERT(id < ID_PERIPH_COUNT, "Invalid peripheral id");
|
||||
|
||||
if (id < 32) {
|
||||
return (PMC->PMC_PCSR0 & BIT(id)) != 0;
|
||||
#if ID_PERIPH_COUNT > 32
|
||||
} else if (id < 64) {
|
||||
return (PMC->PMC_PCSR1 & BIT(id & 0x1F)) != 0;
|
||||
#endif
|
||||
#if ID_PERIPH_COUNT > 64
|
||||
} else {
|
||||
/* These peripherals are always enabled */
|
||||
return 1;
|
||||
#endif
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
523
soc/atmel/sam/common/soc_pmc.h
Normal file
523
soc/atmel/sam/common/soc_pmc.h
Normal file
|
|
@ -0,0 +1,523 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Piotr Mienkowski
|
||||
* Copyright (c) 2023 Basalte bv
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/** @file
|
||||
* @brief Atmel SAM MCU family Power Management Controller (PMC) module
|
||||
* HAL driver.
|
||||
*/
|
||||
|
||||
#ifndef _ATMEL_SAM_SOC_PMC_H_
|
||||
#define _ATMEL_SAM_SOC_PMC_H_
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <zephyr/sys/__assert.h>
|
||||
#include <zephyr/sys/util.h>
|
||||
#include <zephyr/types.h>
|
||||
#include <soc.h>
|
||||
|
||||
/**
|
||||
* @brief Enable the clock of specified peripheral module.
|
||||
*
|
||||
* @param id peripheral module id, as defined in data sheet.
|
||||
*/
|
||||
void soc_pmc_peripheral_enable(uint32_t id);
|
||||
|
||||
/**
|
||||
* @brief Disable the clock of specified peripheral module.
|
||||
*
|
||||
* @param id peripheral module id, as defined in data sheet.
|
||||
*/
|
||||
void soc_pmc_peripheral_disable(uint32_t id);
|
||||
|
||||
/**
|
||||
* @brief Check if specified peripheral module is enabled.
|
||||
*
|
||||
* @param id peripheral module id, as defined in data sheet.
|
||||
* @return 1 if peripheral is enabled, 0 otherwise
|
||||
*/
|
||||
uint32_t soc_pmc_peripheral_is_enabled(uint32_t id);
|
||||
|
||||
#if !defined(CONFIG_SOC_SERIES_SAM4L)
|
||||
|
||||
enum soc_pmc_fast_rc_freq {
|
||||
#if defined(CKGR_MOR_MOSCRCF_4_MHz)
|
||||
SOC_PMC_FAST_RC_FREQ_4MHZ = CKGR_MOR_MOSCRCF_4_MHz,
|
||||
#endif
|
||||
#if defined(CKGR_MOR_MOSCRCF_8_MHz)
|
||||
SOC_PMC_FAST_RC_FREQ_8MHZ = CKGR_MOR_MOSCRCF_8_MHz,
|
||||
#endif
|
||||
#if defined(CKGR_MOR_MOSCRCF_12_MHz)
|
||||
SOC_PMC_FAST_RC_FREQ_12MHZ = CKGR_MOR_MOSCRCF_12_MHz,
|
||||
#endif
|
||||
};
|
||||
|
||||
enum soc_pmc_mck_src {
|
||||
#if defined(PMC_MCKR_CSS_SLOW_CLK)
|
||||
SOC_PMC_MCK_SRC_SLOW_CLK = PMC_MCKR_CSS_SLOW_CLK,
|
||||
#endif
|
||||
#if defined(PMC_MCKR_CSS_MAIN_CLK)
|
||||
SOC_PMC_MCK_SRC_MAIN_CLK = PMC_MCKR_CSS_MAIN_CLK,
|
||||
#endif
|
||||
#if defined(PMC_MCKR_CSS_PLLA_CLK)
|
||||
SOC_PMC_MCK_SRC_PLLA_CLK = PMC_MCKR_CSS_PLLA_CLK,
|
||||
#endif
|
||||
#if defined(PMC_MCKR_CSS_PLLB_CLK)
|
||||
SOC_PMC_MCK_SRC_PLLB_CLK = PMC_MCKR_CSS_PLLB_CLK,
|
||||
#endif
|
||||
#if defined(PMC_MCKR_CSS_UPLL_CLK)
|
||||
SOC_PMC_MCK_SRC_UPLL_CLK = PMC_MCKR_CSS_UPLL_CLK,
|
||||
#endif
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Set the prescaler of the Master clock.
|
||||
*
|
||||
* @param prescaler the prescaler value.
|
||||
*/
|
||||
static ALWAYS_INLINE void soc_pmc_mck_set_prescaler(uint32_t prescaler)
|
||||
{
|
||||
uint32_t reg_val;
|
||||
|
||||
switch (prescaler) {
|
||||
case 1:
|
||||
reg_val = PMC_MCKR_PRES_CLK_1;
|
||||
break;
|
||||
case 2:
|
||||
reg_val = PMC_MCKR_PRES_CLK_2;
|
||||
break;
|
||||
case 4:
|
||||
reg_val = PMC_MCKR_PRES_CLK_4;
|
||||
break;
|
||||
case 8:
|
||||
reg_val = PMC_MCKR_PRES_CLK_8;
|
||||
break;
|
||||
case 16:
|
||||
reg_val = PMC_MCKR_PRES_CLK_16;
|
||||
break;
|
||||
case 32:
|
||||
reg_val = PMC_MCKR_PRES_CLK_32;
|
||||
break;
|
||||
case 64:
|
||||
reg_val = PMC_MCKR_PRES_CLK_64;
|
||||
break;
|
||||
case 3:
|
||||
reg_val = PMC_MCKR_PRES_CLK_3;
|
||||
break;
|
||||
default:
|
||||
__ASSERT(false, "Invalid MCK prescaler");
|
||||
reg_val = PMC_MCKR_PRES_CLK_1;
|
||||
break;
|
||||
}
|
||||
|
||||
PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | reg_val;
|
||||
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SOC_SERIES_SAME70) || defined(CONFIG_SOC_SERIES_SAMV71)
|
||||
|
||||
/**
|
||||
* @brief Set the divider of the Master clock.
|
||||
*
|
||||
* @param divider the divider value.
|
||||
*/
|
||||
static ALWAYS_INLINE void soc_pmc_mck_set_divider(uint32_t divider)
|
||||
{
|
||||
uint32_t reg_val;
|
||||
|
||||
switch (divider) {
|
||||
case 1:
|
||||
reg_val = PMC_MCKR_MDIV_EQ_PCK;
|
||||
break;
|
||||
case 2:
|
||||
reg_val = PMC_MCKR_MDIV_PCK_DIV2;
|
||||
break;
|
||||
case 3:
|
||||
reg_val = PMC_MCKR_MDIV_PCK_DIV3;
|
||||
break;
|
||||
case 4:
|
||||
reg_val = PMC_MCKR_MDIV_PCK_DIV4;
|
||||
break;
|
||||
default:
|
||||
__ASSERT(false, "Invalid MCK divider");
|
||||
reg_val = PMC_MCKR_MDIV_EQ_PCK;
|
||||
break;
|
||||
}
|
||||
|
||||
PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_MDIV_Msk)) | reg_val;
|
||||
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SOC_SERIES_SAME70 || CONFIG_SOC_SERIES_SAMV71 */
|
||||
|
||||
/**
|
||||
* @brief Set the source of the Master clock.
|
||||
*
|
||||
* @param source the source identifier.
|
||||
*/
|
||||
static ALWAYS_INLINE void soc_pmc_mck_set_source(enum soc_pmc_mck_src source)
|
||||
{
|
||||
PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | (uint32_t)source;
|
||||
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Switch main clock source selection to internal fast RC.
|
||||
*
|
||||
* @param freq the internal fast RC desired frequency 4/8/12MHz.
|
||||
*/
|
||||
static ALWAYS_INLINE void soc_pmc_switch_mainck_to_fastrc(enum soc_pmc_fast_rc_freq freq)
|
||||
{
|
||||
/* Enable Fast RC oscillator but DO NOT switch to RC now */
|
||||
PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN;
|
||||
|
||||
/* Wait for the Fast RC to stabilize */
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {
|
||||
}
|
||||
|
||||
/* Change Fast RC oscillator frequency */
|
||||
PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk)
|
||||
| CKGR_MOR_KEY_PASSWD
|
||||
| (uint32_t)freq;
|
||||
|
||||
/* Wait for the Fast RC to stabilize */
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {
|
||||
}
|
||||
|
||||
/* Switch to Fast RC */
|
||||
PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL)
|
||||
| CKGR_MOR_KEY_PASSWD;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable internal fast RC oscillator.
|
||||
*
|
||||
* @param freq the internal fast RC desired frequency 4/8/12MHz.
|
||||
*/
|
||||
static ALWAYS_INLINE void soc_pmc_osc_enable_fastrc(enum soc_pmc_fast_rc_freq freq)
|
||||
{
|
||||
/* Enable Fast RC oscillator but DO NOT switch to RC */
|
||||
PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN;
|
||||
|
||||
/* Wait for the Fast RC to stabilize */
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {
|
||||
}
|
||||
|
||||
/* Change Fast RC oscillator frequency */
|
||||
PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk)
|
||||
| CKGR_MOR_KEY_PASSWD
|
||||
| (uint32_t)freq;
|
||||
|
||||
/* Wait for the Fast RC to stabilize */
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable internal fast RC oscillator.
|
||||
*/
|
||||
static ALWAYS_INLINE void soc_pmc_osc_disable_fastrc(void)
|
||||
{
|
||||
/* Disable Fast RC oscillator */
|
||||
PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN & ~CKGR_MOR_MOSCRCF_Msk)
|
||||
| CKGR_MOR_KEY_PASSWD;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if the internal fast RC is ready.
|
||||
*
|
||||
* @return true if internal fast RC is ready, false otherwise
|
||||
*/
|
||||
static ALWAYS_INLINE bool soc_pmc_osc_is_ready_fastrc(void)
|
||||
{
|
||||
return (PMC->PMC_SR & PMC_SR_MOSCRCS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the external crystal oscillator.
|
||||
*
|
||||
* @param xtal_startup_time crystal start-up time, in number of slow clocks.
|
||||
*/
|
||||
static ALWAYS_INLINE void soc_pmc_osc_enable_main_xtal(uint32_t xtal_startup_time)
|
||||
{
|
||||
uint32_t mor = PMC->CKGR_MOR;
|
||||
|
||||
mor &= ~(CKGR_MOR_MOSCXTBY | CKGR_MOR_MOSCXTEN);
|
||||
mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCXTST(xtal_startup_time);
|
||||
|
||||
PMC->CKGR_MOR = mor;
|
||||
|
||||
/* Wait the main Xtal to stabilize */
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Bypass the external crystal oscillator.
|
||||
*/
|
||||
static ALWAYS_INLINE void soc_pmc_osc_bypass_main_xtal(void)
|
||||
{
|
||||
uint32_t mor = PMC->CKGR_MOR;
|
||||
|
||||
mor &= ~(CKGR_MOR_MOSCXTBY | CKGR_MOR_MOSCXTEN);
|
||||
mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY;
|
||||
|
||||
/* Enable Crystal oscillator but DO NOT switch now. Keep MOSCSEL to 0 */
|
||||
PMC->CKGR_MOR = mor;
|
||||
/* The MOSCXTS in PMC_SR is automatically set */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the external crystal oscillator.
|
||||
*/
|
||||
static ALWAYS_INLINE void soc_pmc_osc_disable_main_xtal(void)
|
||||
{
|
||||
uint32_t mor = PMC->CKGR_MOR;
|
||||
|
||||
mor &= ~(CKGR_MOR_MOSCXTBY | CKGR_MOR_MOSCXTEN);
|
||||
|
||||
PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if the external crystal oscillator is bypassed.
|
||||
*
|
||||
* @return true if external crystal oscillator is bypassed, false otherwise
|
||||
*/
|
||||
static ALWAYS_INLINE bool soc_pmc_osc_is_bypassed_main_xtal(void)
|
||||
{
|
||||
return (PMC->CKGR_MOR & CKGR_MOR_MOSCXTBY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if the external crystal oscillator is ready.
|
||||
*
|
||||
* @return true if external crystal oscillator is ready, false otherwise
|
||||
*/
|
||||
static ALWAYS_INLINE bool soc_pmc_osc_is_ready_main_xtal(void)
|
||||
{
|
||||
return (PMC->PMC_SR & PMC_SR_MOSCXTS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Switch main clock source selection to external crystal oscillator.
|
||||
*
|
||||
* @param bypass select bypass or xtal
|
||||
* @param xtal_startup_time crystal start-up time, in number of slow clocks
|
||||
*/
|
||||
static ALWAYS_INLINE void soc_pmc_switch_mainck_to_xtal(bool bypass, uint32_t xtal_startup_time)
|
||||
{
|
||||
soc_pmc_osc_enable_main_xtal(xtal_startup_time);
|
||||
|
||||
/* Enable Main Xtal oscillator */
|
||||
if (bypass) {
|
||||
PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN)
|
||||
| CKGR_MOR_KEY_PASSWD
|
||||
| CKGR_MOR_MOSCXTBY
|
||||
| CKGR_MOR_MOSCSEL;
|
||||
} else {
|
||||
PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY)
|
||||
| CKGR_MOR_KEY_PASSWD
|
||||
| CKGR_MOR_MOSCXTEN
|
||||
| CKGR_MOR_MOSCXTST(xtal_startup_time);
|
||||
|
||||
/* Wait for the Xtal to stabilize */
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
|
||||
}
|
||||
|
||||
PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the external crystal oscillator.
|
||||
*
|
||||
* @param bypass select bypass or xtal
|
||||
*/
|
||||
static ALWAYS_INLINE void soc_pmc_osc_disable_xtal(bool bypass)
|
||||
{
|
||||
/* Disable xtal oscillator */
|
||||
if (bypass) {
|
||||
PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY)
|
||||
| CKGR_MOR_KEY_PASSWD;
|
||||
} else {
|
||||
PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN)
|
||||
| CKGR_MOR_KEY_PASSWD;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if the main clock is ready. Depending on MOSCEL, main clock can be one
|
||||
* of external crystal, bypass or internal RC.
|
||||
*
|
||||
* @return true if main clock is ready, false otherwise
|
||||
*/
|
||||
static ALWAYS_INLINE bool soc_pmc_osc_is_ready_mainck(void)
|
||||
{
|
||||
return PMC->PMC_SR & PMC_SR_MOSCSELS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Wait Mode.
|
||||
*/
|
||||
static ALWAYS_INLINE void soc_pmc_enable_waitmode(void)
|
||||
{
|
||||
PMC->PMC_FSMR |= PMC_FSMR_LPM;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Clock Failure Detector.
|
||||
*/
|
||||
static ALWAYS_INLINE void soc_pmc_enable_clock_failure_detector(void)
|
||||
{
|
||||
uint32_t mor = PMC->CKGR_MOR;
|
||||
|
||||
PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_CFDEN | mor;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Clock Failure Detector.
|
||||
*/
|
||||
static ALWAYS_INLINE void soc_pmc_disable_clock_failure_detector(void)
|
||||
{
|
||||
uint32_t mor = PMC->CKGR_MOR & (~CKGR_MOR_CFDEN);
|
||||
|
||||
PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor;
|
||||
}
|
||||
|
||||
#if defined(PMC_MCKR_CSS_PLLA_CLK)
|
||||
|
||||
/**
|
||||
* @brief Disable the PLLA clock.
|
||||
*/
|
||||
static ALWAYS_INLINE void soc_pmc_disable_pllack(void)
|
||||
{
|
||||
PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the PLLA clock.
|
||||
*
|
||||
* @param mula PLLA multiplier
|
||||
* @param pllacount PLLA lock counter, in number of slow clocks
|
||||
* @param diva PLLA Divider
|
||||
*/
|
||||
static ALWAYS_INLINE void soc_pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva)
|
||||
{
|
||||
__ASSERT(diva > 0, "Invalid PLLA divider");
|
||||
|
||||
/* first disable the PLL to unlock the lock */
|
||||
soc_pmc_disable_pllack();
|
||||
|
||||
PMC->CKGR_PLLAR = CKGR_PLLAR_ONE
|
||||
| CKGR_PLLAR_DIVA(diva)
|
||||
| CKGR_PLLAR_PLLACOUNT(pllacount)
|
||||
| CKGR_PLLAR_MULA(mula);
|
||||
|
||||
while ((PMC->PMC_SR & PMC_SR_LOCKA) == 0) {
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if the PLLA is locked.
|
||||
*
|
||||
* @return true if PLLA is locked, false otherwise
|
||||
*/
|
||||
static ALWAYS_INLINE bool soc_pmc_is_locked_pllack(void)
|
||||
{
|
||||
return (PMC->PMC_SR & PMC_SR_LOCKA);
|
||||
}
|
||||
|
||||
#endif /* PMC_MCKR_CSS_PLLA_CLK */
|
||||
|
||||
#if defined(PMC_MCKR_CSS_PLLB_CLK)
|
||||
|
||||
/**
|
||||
* @brief Disable the PLLB clock.
|
||||
*/
|
||||
static ALWAYS_INLINE void soc_pmc_disable_pllbck(void)
|
||||
{
|
||||
PMC->CKGR_PLLBR = CKGR_PLLBR_MULB(0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the PLLB clock.
|
||||
*
|
||||
* @param mulb PLLB multiplier
|
||||
* @param pllbcount PLLB lock counter, in number of slow clocks
|
||||
* @param divb PLLB Divider
|
||||
*/
|
||||
static ALWAYS_INLINE void soc_pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb)
|
||||
{
|
||||
__ASSERT(divb > 0, "Invalid PLLB divider");
|
||||
|
||||
/* first disable the PLL to unlock the lock */
|
||||
soc_pmc_disable_pllbck();
|
||||
|
||||
PMC->CKGR_PLLBR = CKGR_PLLBR_DIVB(divb)
|
||||
| CKGR_PLLBR_PLLBCOUNT(pllbcount)
|
||||
| CKGR_PLLBR_MULB(mulb);
|
||||
|
||||
while ((PMC->PMC_SR & PMC_SR_LOCKB) == 0) {
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if the PLLB is locked.
|
||||
*
|
||||
* @return true if PLLB is locked, false otherwise
|
||||
*/
|
||||
static ALWAYS_INLINE bool soc_pmc_is_locked_pllbck(void)
|
||||
{
|
||||
return (PMC->PMC_SR & PMC_SR_LOCKB);
|
||||
}
|
||||
|
||||
#endif /* PMC_MCKR_CSS_PLLB_CLK */
|
||||
|
||||
#if defined(PMC_MCKR_CSS_UPLL_CLK)
|
||||
|
||||
/**
|
||||
* @brief Enable the UPLL clock.
|
||||
*/
|
||||
static ALWAYS_INLINE void soc_pmc_enable_upllck(uint32_t upllcount)
|
||||
{
|
||||
PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(upllcount)
|
||||
| CKGR_UCKR_UPLLEN;
|
||||
|
||||
/* Wait UTMI PLL Lock Status */
|
||||
while (!(PMC->PMC_SR & PMC_SR_LOCKU)) {
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the UPLL clock.
|
||||
*/
|
||||
static ALWAYS_INLINE void soc_pmc_disable_upllck(void)
|
||||
{
|
||||
PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if the UPLL is locked.
|
||||
*
|
||||
* @return true if UPLL is locked, false otherwise
|
||||
*/
|
||||
static ALWAYS_INLINE bool soc_pmc_is_locked_upllck(void)
|
||||
{
|
||||
return (PMC->PMC_SR & PMC_SR_LOCKU);
|
||||
}
|
||||
|
||||
#endif /* PMC_MCKR_CSS_UPLL_CLK */
|
||||
|
||||
#endif /* !CONFIG_SOC_SERIES_SAM4L */
|
||||
|
||||
#endif /* _ATMEL_SAM_SOC_PMC_H_ */
|
||||
37
soc/atmel/sam/common/soc_power.c
Normal file
37
soc/atmel/sam/common/soc_power.c
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Basalte bv
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#define SAM_DT_RSTC_DRIVER DT_INST(0, atmel_sam_rstc)
|
||||
|
||||
#include <zephyr/kernel.h>
|
||||
#if defined(CONFIG_REBOOT)
|
||||
#include <zephyr/sys/reboot.h>
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_REBOOT)
|
||||
#if DT_NODE_HAS_STATUS(SAM_DT_RSTC_DRIVER, okay)
|
||||
|
||||
void sys_arch_reboot(int type)
|
||||
{
|
||||
Rstc *regs = (Rstc *)DT_REG_ADDR(SAM_DT_RSTC_DRIVER);
|
||||
|
||||
switch (type) {
|
||||
case SYS_REBOOT_COLD:
|
||||
regs->RSTC_CR = RSTC_CR_KEY_PASSWD
|
||||
| RSTC_CR_PROCRST
|
||||
#if defined(CONFIG_SOC_SERIES_SAM3X) || defined(CONFIG_SOC_SERIES_SAM4S) || \
|
||||
defined(CONFIG_SOC_SERIES_SAM4E)
|
||||
| RSTC_CR_PERRST
|
||||
#endif /* CONFIG_SOC_SERIES_SAM3X || CONFIG_SOC_SERIES_SAM4S || CONFIG_SOC_SERIES_SAM4E */
|
||||
;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* DT_NODE_HAS_STATUS */
|
||||
#endif /* CONFIG_REBOOT */
|
||||
33
soc/atmel/sam/common/soc_poweroff.c
Normal file
33
soc/atmel/sam/common/soc_poweroff.c
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Bjarki Arge Andreasen
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/sys/poweroff.h>
|
||||
#include <soc.h>
|
||||
|
||||
/*
|
||||
* Poweroff will make the chip enter the backup low-power mode, which
|
||||
* achieves the lowest possible power consumption. Wakeup from this mode
|
||||
* requires enabling a wakeup source or input, or power cycling the device.
|
||||
*/
|
||||
|
||||
static void soc_core_sleepdeep_enable(void)
|
||||
{
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
}
|
||||
|
||||
static void soc_core_sleepdeep_wait(void)
|
||||
{
|
||||
__WFE();
|
||||
__WFI();
|
||||
}
|
||||
|
||||
void z_sys_poweroff(void)
|
||||
{
|
||||
soc_core_sleepdeep_enable();
|
||||
soc_supc_core_voltage_regulator_off();
|
||||
soc_core_sleepdeep_wait();
|
||||
|
||||
CODE_UNREACHABLE;
|
||||
}
|
||||
189
soc/atmel/sam/common/soc_sam4l_gpio.c
Normal file
189
soc/atmel/sam/common/soc_sam4l_gpio.c
Normal file
|
|
@ -0,0 +1,189 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/** @file
|
||||
* @brief Atmel SAM MCU family General-Purpose Input/Output Controller (GPIO)
|
||||
* module HAL driver.
|
||||
*/
|
||||
|
||||
#include <zephyr/sys/__assert.h>
|
||||
#include "soc_gpio.h"
|
||||
|
||||
static void configure_common_attr(volatile Gpio *gpio,
|
||||
uint32_t mask, uint32_t flags)
|
||||
{
|
||||
flags &= SOC_GPIO_FLAGS_MASK;
|
||||
|
||||
/* Disable interrupts on the pin(s) */
|
||||
gpio->IERC = mask;
|
||||
|
||||
/* Configure pull-up(s) */
|
||||
if (flags & SOC_GPIO_PULLUP) {
|
||||
gpio->PUERS = mask;
|
||||
} else {
|
||||
gpio->PUERC = mask;
|
||||
}
|
||||
|
||||
/* Configure pull-down(s) */
|
||||
if (flags & SOC_GPIO_PULLDOWN) {
|
||||
gpio->PDERS = mask;
|
||||
} else {
|
||||
gpio->PDERC = mask;
|
||||
}
|
||||
|
||||
/* Configure open drain (multi-drive) */
|
||||
if (flags & SOC_GPIO_OPENDRAIN) {
|
||||
gpio->ODMERS = mask;
|
||||
} else {
|
||||
gpio->ODMERC = mask;
|
||||
}
|
||||
}
|
||||
|
||||
static void configure_input_attr(volatile Gpio *gpio,
|
||||
uint32_t mask, uint32_t flags)
|
||||
{
|
||||
/* Configure input filter */
|
||||
if ((flags & SOC_GPIO_IN_FILTER_MASK) != 0U) {
|
||||
if ((flags & SOC_GPIO_IN_FILTER_MASK) ==
|
||||
SOC_GPIO_IN_FILTER_DEBOUNCE) {
|
||||
/* Enable de-bounce, disable de-glitch */
|
||||
gpio->GFERC = mask;
|
||||
} else {
|
||||
/* Disable de-bounce, enable de-glitch */
|
||||
gpio->GFERS = mask;
|
||||
}
|
||||
} else {
|
||||
gpio->GFERC = mask;
|
||||
}
|
||||
|
||||
/* Configure interrupt */
|
||||
if (flags & SOC_GPIO_INT_ENABLE) {
|
||||
if ((flags & SOC_GPIO_INT_TRIG_MASK) ==
|
||||
SOC_GPIO_INT_TRIG_DOUBLE_EDGE) {
|
||||
gpio->IMR0C = mask;
|
||||
gpio->IMR1C = mask;
|
||||
} else {
|
||||
if (flags & SOC_GPIO_INT_ACTIVE_HIGH) {
|
||||
/* Rising Edge*/
|
||||
gpio->IMR0S = mask;
|
||||
gpio->IMR1C = mask;
|
||||
} else {
|
||||
/* Falling Edge */
|
||||
gpio->IMR0C = mask;
|
||||
gpio->IMR1S = mask;
|
||||
}
|
||||
}
|
||||
/* Enable interrupts on the pin(s) */
|
||||
gpio->IERS = mask;
|
||||
} else {
|
||||
gpio->IERC = mask;
|
||||
}
|
||||
}
|
||||
|
||||
void soc_gpio_configure(const struct soc_gpio_pin *pin)
|
||||
{
|
||||
uint32_t mask = pin->mask;
|
||||
volatile Gpio *gpio = pin->regs;
|
||||
uint8_t periph_id = pin->periph_id;
|
||||
uint32_t flags = pin->flags;
|
||||
uint32_t type = pin->flags & SOC_GPIO_FUNC_MASK;
|
||||
|
||||
/* Configure pin attributes common to all functions */
|
||||
configure_common_attr(gpio, mask, flags);
|
||||
|
||||
switch (type) {
|
||||
case SOC_GPIO_FUNC_A:
|
||||
gpio->PMR0C = mask;
|
||||
gpio->PMR1C = mask;
|
||||
gpio->PMR2C = mask;
|
||||
gpio->GPERC = mask;
|
||||
break;
|
||||
|
||||
case SOC_GPIO_FUNC_B:
|
||||
gpio->PMR0S = mask;
|
||||
gpio->PMR1C = mask;
|
||||
gpio->PMR2C = mask;
|
||||
gpio->GPERC = mask;
|
||||
break;
|
||||
|
||||
case SOC_GPIO_FUNC_C:
|
||||
gpio->PMR0C = mask;
|
||||
gpio->PMR1S = mask;
|
||||
gpio->PMR2C = mask;
|
||||
gpio->GPERC = mask;
|
||||
break;
|
||||
|
||||
case SOC_GPIO_FUNC_D:
|
||||
gpio->PMR0S = mask;
|
||||
gpio->PMR1S = mask;
|
||||
gpio->PMR2C = mask;
|
||||
gpio->GPERC = mask;
|
||||
break;
|
||||
|
||||
case SOC_GPIO_FUNC_E:
|
||||
gpio->PMR0C = mask;
|
||||
gpio->PMR1C = mask;
|
||||
gpio->PMR2S = mask;
|
||||
gpio->GPERC = mask;
|
||||
break;
|
||||
|
||||
case SOC_GPIO_FUNC_F:
|
||||
gpio->PMR0S = mask;
|
||||
gpio->PMR1C = mask;
|
||||
gpio->PMR2S = mask;
|
||||
gpio->GPERC = mask;
|
||||
break;
|
||||
|
||||
case SOC_GPIO_FUNC_G:
|
||||
gpio->PMR0C = mask;
|
||||
gpio->PMR1S = mask;
|
||||
gpio->PMR2S = mask;
|
||||
gpio->GPERC = mask;
|
||||
break;
|
||||
|
||||
case SOC_GPIO_FUNC_H:
|
||||
gpio->PMR0S = mask;
|
||||
gpio->PMR1S = mask;
|
||||
gpio->PMR2S = mask;
|
||||
gpio->GPERC = mask;
|
||||
break;
|
||||
|
||||
case SOC_GPIO_FUNC_IN:
|
||||
soc_pmc_peripheral_enable(periph_id);
|
||||
configure_input_attr(gpio, mask, flags);
|
||||
|
||||
gpio->ODERC = mask;
|
||||
gpio->STERS = mask;
|
||||
gpio->GPERS = mask;
|
||||
break;
|
||||
|
||||
case SOC_GPIO_FUNC_OUT_1:
|
||||
case SOC_GPIO_FUNC_OUT_0:
|
||||
if (type == SOC_GPIO_FUNC_OUT_1) {
|
||||
gpio->OVRS = mask;
|
||||
} else {
|
||||
gpio->OVRC = mask;
|
||||
}
|
||||
|
||||
gpio->ODCR0S = mask;
|
||||
gpio->ODCR1S = mask;
|
||||
gpio->ODERS = mask;
|
||||
gpio->STERC = mask;
|
||||
gpio->GPERS = mask;
|
||||
break;
|
||||
|
||||
default:
|
||||
__ASSERT(0, "Unsupported pin function, check pin.flags value");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
void soc_gpio_list_configure(const struct soc_gpio_pin pins[],
|
||||
unsigned int size)
|
||||
{
|
||||
for (int i = 0; i < size; i++) {
|
||||
soc_gpio_configure(&pins[i]);
|
||||
}
|
||||
}
|
||||
122
soc/atmel/sam/common/soc_sam4l_pm.c
Normal file
122
soc/atmel/sam/common/soc_sam4l_pm.c
Normal file
|
|
@ -0,0 +1,122 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/** @file
|
||||
* @brief Atmel SAM4L MCU family Power Management (PM) module
|
||||
* HAL driver.
|
||||
*/
|
||||
|
||||
#include <soc.h>
|
||||
#include <zephyr/sys/__assert.h>
|
||||
#include <zephyr/sys/util.h>
|
||||
|
||||
/**
|
||||
* SAM4L define peripheral-ids out of order. This maps peripheral-id group
|
||||
* to right register index.
|
||||
*/
|
||||
static const uint32_t bridge_peripheral_ids[] = {
|
||||
2, /* PBA GRP */
|
||||
3, /* PBB GRP */
|
||||
4, /* PBC GRP */
|
||||
5, /* PBD GRP */
|
||||
1, /* HSB GRP */
|
||||
0, /* CPU GRP */
|
||||
};
|
||||
|
||||
static const uint32_t bridge_peripheral_instances[] = {
|
||||
1, /* CPU MASK Instances */
|
||||
10, /* HSB MASK Instances */
|
||||
24, /* PBA MASK Instances */
|
||||
7, /* PBB MASK Instances */
|
||||
5, /* PBC MASK Instances */
|
||||
6, /* PBD MASK Instances */
|
||||
};
|
||||
|
||||
void soc_pmc_peripheral_enable(uint32_t id)
|
||||
{
|
||||
uint32_t bus_grp = id >> 5;
|
||||
uint32_t per_idx = id & 0x1F;
|
||||
uint32_t bus_id;
|
||||
uint32_t mask;
|
||||
|
||||
if (bus_grp >= 6) {
|
||||
return;
|
||||
}
|
||||
|
||||
bus_id = bridge_peripheral_ids[bus_grp];
|
||||
|
||||
if (per_idx >= bridge_peripheral_instances[bus_id]) {
|
||||
return;
|
||||
}
|
||||
|
||||
mask = *(&PM->CPUMASK + bus_id);
|
||||
mask |= (1U << per_idx);
|
||||
PM->UNLOCK = PM_UNLOCK_KEY(0xAAu) |
|
||||
PM_UNLOCK_ADDR(((uint32_t)&PM->CPUMASK -
|
||||
(uint32_t)PM) +
|
||||
(4 * bus_id));
|
||||
*(&PM->CPUMASK + bus_id) = mask;
|
||||
}
|
||||
|
||||
void soc_pmc_peripheral_disable(uint32_t id)
|
||||
{
|
||||
uint32_t bus_grp = id >> 5;
|
||||
uint32_t per_idx = id & 0x1F;
|
||||
uint32_t bus_id;
|
||||
uint32_t mask;
|
||||
|
||||
if (bus_grp >= 6) {
|
||||
return;
|
||||
}
|
||||
|
||||
bus_id = bridge_peripheral_ids[bus_grp];
|
||||
|
||||
if (per_idx >= bridge_peripheral_instances[bus_id]) {
|
||||
return;
|
||||
}
|
||||
|
||||
mask = *(&PM->CPUMASK + bus_id);
|
||||
mask &= ~(1U << per_idx);
|
||||
PM->UNLOCK = PM_UNLOCK_KEY(0xAAu) |
|
||||
PM_UNLOCK_ADDR(((uint32_t)&PM->CPUMASK -
|
||||
(uint32_t)PM) +
|
||||
(4 * bus_id));
|
||||
*(&PM->CPUMASK + bus_id) = mask;
|
||||
}
|
||||
|
||||
uint32_t soc_pmc_peripheral_is_enabled(uint32_t id)
|
||||
{
|
||||
uint32_t bus_grp = id >> 5;
|
||||
uint32_t per_idx = id & 0x1F;
|
||||
uint32_t bus_id;
|
||||
uint32_t mask;
|
||||
|
||||
if (bus_grp >= 6) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
bus_id = bridge_peripheral_ids[bus_grp];
|
||||
|
||||
if (per_idx >= bridge_peripheral_instances[bus_id]) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
mask = *(&PM->CPUMASK + bus_id);
|
||||
|
||||
return ((mask & (1U << per_idx)) > 0);
|
||||
}
|
||||
|
||||
void soc_pm_enable_pba_divmask(uint32_t mask)
|
||||
{
|
||||
uint32_t temp_mask;
|
||||
|
||||
temp_mask = PM->PBADIVMASK;
|
||||
temp_mask |= mask;
|
||||
|
||||
PM->UNLOCK = PM_UNLOCK_KEY(0xAAu) |
|
||||
PM_UNLOCK_ADDR((uint32_t)&PM->PBADIVMASK -
|
||||
(uint32_t)PM);
|
||||
PM->PBADIVMASK = temp_mask;
|
||||
}
|
||||
33
soc/atmel/sam/common/soc_sam4l_poweroff.c
Normal file
33
soc/atmel/sam/common/soc_sam4l_poweroff.c
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Bjarki Arge Andreasen
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/sys/poweroff.h>
|
||||
#include <soc.h>
|
||||
|
||||
/*
|
||||
* Poweroff will make the chip enter the backup low-power mode, which
|
||||
* achieves the lowest possible power consumption. Wakeup from this mode
|
||||
* requires enabling a wakeup source or input, or power cycling the device.
|
||||
*/
|
||||
|
||||
static void soc_core_sleepdeep_enable(void)
|
||||
{
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
}
|
||||
|
||||
static void soc_core_sleepdeep_wait(void)
|
||||
{
|
||||
__WFE();
|
||||
__WFI();
|
||||
}
|
||||
|
||||
void z_sys_poweroff(void)
|
||||
{
|
||||
soc_core_sleepdeep_enable();
|
||||
BPM->PMCON |= BPM_PMCON_BKUP;
|
||||
soc_core_sleepdeep_wait();
|
||||
|
||||
CODE_UNREACHABLE;
|
||||
}
|
||||
32
soc/atmel/sam/common/soc_supc.c
Normal file
32
soc/atmel/sam/common/soc_supc.c
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Bjarki Arge Andreasen
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/device.h>
|
||||
#include <zephyr/sys/util_macro.h>
|
||||
#include <soc.h>
|
||||
|
||||
#define SOC_SUPC_WAKEUP_SOURCE_IDS (3)
|
||||
|
||||
void soc_supc_core_voltage_regulator_off(void)
|
||||
{
|
||||
SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_VROFF_STOP_VREG;
|
||||
}
|
||||
|
||||
void soc_supc_slow_clock_select_crystal_osc(void)
|
||||
{
|
||||
SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL_CRYSTAL_SEL;
|
||||
|
||||
/* Wait for oscillator to be stabilized. */
|
||||
while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL)) {
|
||||
}
|
||||
}
|
||||
|
||||
void soc_supc_enable_wakeup_source(uint32_t wakeup_source_id)
|
||||
{
|
||||
__ASSERT(wakeup_source_id <= SOC_SUPC_WAKEUP_SOURCE_IDS,
|
||||
"Wakeup source channel is invalid");
|
||||
|
||||
SUPC->SUPC_WUMR |= 1 << wakeup_source_id;
|
||||
}
|
||||
26
soc/atmel/sam/common/soc_supc.h
Normal file
26
soc/atmel/sam/common/soc_supc.h
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Bjarki Arge Andreasen
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _ATMEL_SAM_SOC_SUPC_H_
|
||||
#define _ATMEL_SAM_SOC_SUPC_H_
|
||||
|
||||
#include <zephyr/types.h>
|
||||
|
||||
/**
|
||||
* @brief Enable the clock of specified peripheral module.
|
||||
*/
|
||||
void soc_supc_core_voltage_regulator_off(void);
|
||||
|
||||
/**
|
||||
* @brief Switch slow clock source to external crystal oscillator
|
||||
*/
|
||||
void soc_supc_slow_clock_select_crystal_osc(void);
|
||||
|
||||
/**
|
||||
* @brief Enable wakeup source
|
||||
*/
|
||||
void soc_supc_enable_wakeup_source(uint32_t wakeup_source_id);
|
||||
|
||||
#endif /* _ATMEL_SAM_SOC_SUPC_H_ */
|
||||
10
soc/atmel/sam/sam3x/CMakeLists.txt
Normal file
10
soc/atmel/sam/sam3x/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_include_directories(.)
|
||||
|
||||
zephyr_sources(
|
||||
soc.c
|
||||
)
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
|
||||
15
soc/atmel/sam/sam3x/Kconfig
Normal file
15
soc/atmel/sam/sam3x/Kconfig
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
# Atmel SAM3X MCU series
|
||||
|
||||
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Intel Corporation.
|
||||
# Copyright (c) 2017 Justin Watson
|
||||
# Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_SAM3X
|
||||
select ARM
|
||||
select CPU_CORTEX_M3
|
||||
select CPU_CORTEX_M_HAS_DWT
|
||||
select CPU_HAS_ARM_MPU
|
||||
select PLATFORM_SPECIFIC_INIT
|
||||
select HAS_POWEROFF
|
||||
14
soc/atmel/sam/sam3x/Kconfig.defconfig
Normal file
14
soc/atmel/sam/sam3x/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
# Atmel SAM3X MCU series configuration options
|
||||
|
||||
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Intel Corporation.
|
||||
# Copyright (c) 2017 Justin Watson
|
||||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_SAM3X
|
||||
|
||||
config NUM_IRQS
|
||||
default 45
|
||||
|
||||
endif # SOC_SERIES_SAM3X
|
||||
43
soc/atmel/sam/sam3x/Kconfig.soc
Normal file
43
soc/atmel/sam/sam3x/Kconfig.soc
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
# Atmel SAM3X MCU series
|
||||
|
||||
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Intel Corporation.
|
||||
# Copyright (c) 2017 Justin Watson
|
||||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_SAM3X
|
||||
bool
|
||||
select SOC_FAMILY_ATMEL_SAM
|
||||
help
|
||||
Enable support for Atmel SAM3X MCU Series
|
||||
|
||||
config SOC_SERIES
|
||||
default "sam3x" if SOC_SERIES_SAM3X
|
||||
|
||||
config SOC_SAM3X4C
|
||||
bool
|
||||
select SOC_SERIES_SAM3X
|
||||
|
||||
config SOC_SAM3X4E
|
||||
bool
|
||||
select SOC_SERIES_SAM3X
|
||||
|
||||
config SOC_SAM3X8C
|
||||
bool
|
||||
select SOC_SERIES_SAM3X
|
||||
|
||||
config SOC_SAM3X8E
|
||||
bool
|
||||
select SOC_SERIES_SAM3X
|
||||
|
||||
config SOC_SAM3X8H
|
||||
bool
|
||||
select SOC_SERIES_SAM3X
|
||||
|
||||
config SOC
|
||||
default "sam3x4c" if SOC_SAM3X4C
|
||||
default "sam3x4e" if SOC_SAM3X4E
|
||||
default "sam3x8c" if SOC_SAM3X8C
|
||||
default "sam3x8e" if SOC_SAM3X8E
|
||||
default "sam3x8h" if SOC_SAM3X8H
|
||||
112
soc/atmel/sam/sam3x/soc.c
Normal file
112
soc/atmel/sam/sam3x/soc.c
Normal file
|
|
@ -0,0 +1,112 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2015 Wind River Systems, Inc.
|
||||
* Copyright (c) 2016 Intel Corporation.
|
||||
* Copyright (c) 2023 Basalte bv
|
||||
* Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Atmel SAM3X MCU series initialization code
|
||||
*
|
||||
* This module provides routines to initialize and support board-level hardware
|
||||
* for the Atmel SAM3X series processor.
|
||||
*/
|
||||
|
||||
#include <soc.h>
|
||||
#include <soc_pmc.h>
|
||||
#include <soc_supc.h>
|
||||
|
||||
/**
|
||||
* @brief Setup various clocks on SoC at boot time.
|
||||
*
|
||||
* Setup Slow, Main, PLLA, Processor and Master clocks during the device boot.
|
||||
* It is assumed that the relevant registers are at their reset value.
|
||||
*/
|
||||
static ALWAYS_INLINE void clock_init(void)
|
||||
{
|
||||
/* Switch the main clock to the internal OSC with 12MHz */
|
||||
soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ);
|
||||
|
||||
/* Switch MCK (Master Clock) to the main clock */
|
||||
soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK);
|
||||
|
||||
EFC0->EEFC_FMR = EEFC_FMR_FWS(0);
|
||||
EFC1->EEFC_FMR = EEFC_FMR_FWS(0);
|
||||
|
||||
soc_pmc_enable_clock_failure_detector();
|
||||
|
||||
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) {
|
||||
soc_supc_slow_clock_select_crystal_osc();
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
|
||||
/*
|
||||
* Setup main external crystal oscillator.
|
||||
*/
|
||||
|
||||
/* We select maximum setup time.
|
||||
* While start up time could be shortened
|
||||
* this optimization is not deemed
|
||||
* critical now.
|
||||
*/
|
||||
soc_pmc_switch_mainck_to_xtal(false, 0xff);
|
||||
}
|
||||
|
||||
/*
|
||||
* Set FWS (Flash Wait State) value before increasing Master Clock
|
||||
* (MCK) frequency.
|
||||
* TODO: set FWS based on the actual MCK frequency and VDDCORE value
|
||||
* rather than maximum supported 84 MHz at standard VDDCORE=1.8V
|
||||
*/
|
||||
EFC0->EEFC_FMR = EEFC_FMR_FWS(4);
|
||||
EFC1->EEFC_FMR = EEFC_FMR_FWS(4);
|
||||
|
||||
/*
|
||||
* Setup PLLA
|
||||
*/
|
||||
|
||||
/*
|
||||
* PLL clock = Main * (MULA + 1) / DIVA
|
||||
*
|
||||
* By default, MULA == 6, DIVA == 1.
|
||||
* With main crystal running at 12 MHz,
|
||||
* PLL = 12 * (6 + 1) / 1 = 84 MHz
|
||||
*
|
||||
* With Processor Clock prescaler at 1
|
||||
* Processor Clock (HCLK) = 84 MHz.
|
||||
*/
|
||||
soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu,
|
||||
CONFIG_SOC_ATMEL_SAM_PLLA_DIVA);
|
||||
|
||||
/*
|
||||
* Final setup of the Master Clock
|
||||
*/
|
||||
|
||||
/* prescaler has to be set before PLL lock */
|
||||
soc_pmc_mck_set_prescaler(1);
|
||||
|
||||
/* Select PLL as Master Clock source. */
|
||||
soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK);
|
||||
|
||||
/* Disable internal fast RC if we have an external crystal oscillator */
|
||||
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
|
||||
soc_pmc_osc_disable_fastrc();
|
||||
}
|
||||
}
|
||||
|
||||
void z_arm_platform_init(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
|
||||
/*
|
||||
* Instruct CPU to enter Wait mode instead of Sleep mode to
|
||||
* keep Processor Clock (HCLK) and thus be able to debug
|
||||
* CPU using JTAG.
|
||||
*/
|
||||
soc_pmc_enable_waitmode();
|
||||
}
|
||||
/* Setup system clocks */
|
||||
clock_init();
|
||||
}
|
||||
52
soc/atmel/sam/sam3x/soc.h
Normal file
52
soc/atmel/sam/sam3x/soc.h
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2015 Wind River Systems, Inc.
|
||||
* Copyright (c) 2016 Intel Corporation.
|
||||
* Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/** @file
|
||||
* @brief Register access macros for the Atmel SAM3X MCU.
|
||||
*
|
||||
* This file provides register access macros for the Atmel SAM3X MCU, HAL
|
||||
* drivers for core peripherals as well as symbols specific to Atmel SAM family.
|
||||
*/
|
||||
|
||||
#ifndef _SOC_ATMEL_SAM_SAM3X_SOC_H_
|
||||
#define _SOC_ATMEL_SAM_SAM3X_SOC_H_
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#define DONT_USE_CMSIS_INIT
|
||||
#define DONT_USE_PREDEFINED_CORE_HANDLERS
|
||||
#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
|
||||
|
||||
#if defined(CONFIG_SOC_SAM3X4C)
|
||||
#include <sam3x4c.h>
|
||||
#elif defined(CONFIG_SOC_SAM3X4E)
|
||||
#include <sam3x4e.h>
|
||||
#elif defined(CONFIG_SOC_SAM3X8C)
|
||||
#include <sam3x8c.h>
|
||||
#elif defined(CONFIG_SOC_SAM3X8E)
|
||||
#include <sam3x8e.h>
|
||||
#elif defined(CONFIG_SOC_SAM3X8H)
|
||||
#include <sam3x8h.h>
|
||||
#else
|
||||
#error Library does not support the specified device.
|
||||
#endif
|
||||
|
||||
#include "../common/soc_pmc.h"
|
||||
#include "../common/soc_gpio.h"
|
||||
#include "../common/soc_supc.h"
|
||||
#include "../common/atmel_sam_dt.h"
|
||||
|
||||
/** Processor Clock (HCLK) Frequency */
|
||||
#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ
|
||||
|
||||
/** Master Clock (MCK) Frequency */
|
||||
#define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#endif /* _SOC_ATMEL_SAM_SAM3X_SOC_H_ */
|
||||
10
soc/atmel/sam/sam4e/CMakeLists.txt
Normal file
10
soc/atmel/sam/sam4e/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_include_directories(.)
|
||||
|
||||
zephyr_sources(
|
||||
soc.c
|
||||
)
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
|
||||
15
soc/atmel/sam/sam4e/Kconfig
Normal file
15
soc/atmel/sam/sam4e/Kconfig
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
# Atmel SAM4E MCU series
|
||||
|
||||
# Copyright (c) 2017 Justin Watson
|
||||
# Copyright (c) 2018 Vincent van der Locht
|
||||
# Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_SAM4E
|
||||
select ARM
|
||||
select CPU_CORTEX_M4
|
||||
select CPU_CORTEX_M_HAS_DWT
|
||||
select CPU_HAS_ARM_MPU
|
||||
select CPU_HAS_FPU
|
||||
select PLATFORM_SPECIFIC_INIT
|
||||
select HAS_POWEROFF
|
||||
13
soc/atmel/sam/sam4e/Kconfig.defconfig
Normal file
13
soc/atmel/sam/sam4e/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
# Atmel SAM4E MCU series configuration options
|
||||
|
||||
# Copyright (c) 2017 Justin Watson
|
||||
# Copyright (c) 2018 Vincent van der Locht
|
||||
# Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_SAM4E
|
||||
|
||||
config NUM_IRQS
|
||||
default 47
|
||||
|
||||
endif # SOC_SERIES_SAM4E
|
||||
37
soc/atmel/sam/sam4e/Kconfig.soc
Normal file
37
soc/atmel/sam/sam4e/Kconfig.soc
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
# Atmel SAM4E MCU series
|
||||
|
||||
# Copyright (c) 2017 Justin Watson
|
||||
# Copyright (c) 2018 Vincent van der Locht
|
||||
# Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_SAM4E
|
||||
bool
|
||||
select SOC_FAMILY_ATMEL_SAM
|
||||
help
|
||||
Enable support for Atmel SAM4E MCU series
|
||||
|
||||
config SOC_SERIES
|
||||
default "sam4e" if SOC_SERIES_SAM4E
|
||||
|
||||
config SOC_SAM4E16E
|
||||
bool
|
||||
select SOC_SERIES_SAM4E
|
||||
|
||||
config SOC_SAM4E16C
|
||||
bool
|
||||
select SOC_SERIES_SAM4E
|
||||
|
||||
config SOC_SAM4E8E
|
||||
bool
|
||||
select SOC_SERIES_SAM4E
|
||||
|
||||
config SOC_SAM4E8C
|
||||
bool
|
||||
select SOC_SERIES_SAM4E
|
||||
|
||||
config SOC
|
||||
default "sam4e16e" if SOC_SAM4E16E
|
||||
default "sam4e16c" if SOC_SAM4E16C
|
||||
default "sam4e8e" if SOC_SAM4E8E
|
||||
default "sam4e8c" if SOC_SAM4E8C
|
||||
104
soc/atmel/sam/sam4e/soc.c
Normal file
104
soc/atmel/sam/sam4e/soc.c
Normal file
|
|
@ -0,0 +1,104 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2015 Wind River Systems, Inc.
|
||||
* Copyright (c) 2016 Intel Corporation.
|
||||
* Copyright (c) 2017 Justin Watson
|
||||
* Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
* Copyright (c) 2023 Basalte bv
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Atmel SAM4E MCU series initialization code
|
||||
*
|
||||
* This module provides routines to initialize and support board-level hardware
|
||||
* for the Atmel SAM4E series processor.
|
||||
*/
|
||||
|
||||
#include <soc.h>
|
||||
#include <soc_pmc.h>
|
||||
#include <soc_supc.h>
|
||||
|
||||
/**
|
||||
* @brief Setup various clock on SoC at boot time.
|
||||
*
|
||||
* Setup the SoC clocks according to section 28.12 in datasheet.
|
||||
*
|
||||
* Setup Slow, Main, PLLA, Processor and Master clocks during the device boot.
|
||||
* It is assumed that the relevant registers are at their reset value.
|
||||
*/
|
||||
static ALWAYS_INLINE void clock_init(void)
|
||||
{
|
||||
/* Switch the main clock to the internal OSC with 12MHz */
|
||||
soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ);
|
||||
|
||||
/* Switch MCK (Master Clock) to the main clock */
|
||||
soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK);
|
||||
|
||||
EFC->EEFC_FMR = EEFC_FMR_FWS(0);
|
||||
|
||||
soc_pmc_enable_clock_failure_detector();
|
||||
|
||||
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) {
|
||||
soc_supc_slow_clock_select_crystal_osc();
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
|
||||
/*
|
||||
* Setup main external crystal oscillator.
|
||||
*/
|
||||
|
||||
/* We select maximum setup time.
|
||||
* While start up time could be shortened
|
||||
* this optimization is not deemed
|
||||
* critical now.
|
||||
*/
|
||||
soc_pmc_switch_mainck_to_xtal(false, 0xff);
|
||||
}
|
||||
|
||||
/*
|
||||
* Set FWS (Flash Wait State) value before increasing Master Clock
|
||||
* (MCK) frequency. Look at table 44.73 in the SAM4E datasheet.
|
||||
* This is set to the highest number of read cycles because it won't
|
||||
* hurt lower clock frequencies. However, a high frequency with too
|
||||
* few read cycles could cause flash read problems. FWS 5 (6 cycles)
|
||||
* is the safe setting for all of this SoCs usable frequencies.
|
||||
*/
|
||||
EFC->EEFC_FMR = EEFC_FMR_FWS(5);
|
||||
|
||||
/*
|
||||
* Setup PLLA
|
||||
*/
|
||||
soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu,
|
||||
CONFIG_SOC_ATMEL_SAM_PLLA_DIVA);
|
||||
|
||||
/*
|
||||
* Final setup of the Master Clock
|
||||
*/
|
||||
|
||||
/* prescaler has to be set before PLL lock */
|
||||
soc_pmc_mck_set_prescaler(1);
|
||||
|
||||
/* Select PLL as Master Clock source. */
|
||||
soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK);
|
||||
|
||||
/* Disable internal fast RC if we have an external crystal oscillator */
|
||||
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
|
||||
soc_pmc_osc_disable_fastrc();
|
||||
}
|
||||
}
|
||||
|
||||
void z_arm_platform_init(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
|
||||
/*
|
||||
* Instruct CPU to enter Wait mode instead of Sleep mode to
|
||||
* keep Processor Clock (HCLK) and thus be able to debug
|
||||
* CPU using JTAG.
|
||||
*/
|
||||
soc_pmc_enable_waitmode();
|
||||
}
|
||||
/* Setup system clocks. */
|
||||
clock_init();
|
||||
}
|
||||
51
soc/atmel/sam/sam4e/soc.h
Normal file
51
soc/atmel/sam/sam4e/soc.h
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2015 Wind River Systems, Inc.
|
||||
* Copyright (c) 2016 Intel Corporation.
|
||||
* Copyright (c) 2018 Vincent van der Locht
|
||||
* Copyright (c) 2017 Justin Watson
|
||||
* Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SoC configuration macros for the Atmel SAM4E family processors.
|
||||
*/
|
||||
|
||||
#ifndef _SOC_ATMEL_SAM_SAM4E_SOC_H_
|
||||
#define _SOC_ATMEL_SAM_SAM4E_SOC_H_
|
||||
|
||||
#include <zephyr/sys/util.h>
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#define DONT_USE_CMSIS_INIT
|
||||
#define DONT_USE_PREDEFINED_CORE_HANDLERS
|
||||
#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
|
||||
|
||||
#if defined(CONFIG_SOC_SAM4E16E)
|
||||
#include <sam4e16e.h>
|
||||
#elif defined(CONFIG_SOC_SAM4E16C)
|
||||
#include <sam4e16c.h>
|
||||
#elif defined(CONFIG_SOC_SAM4E8E)
|
||||
#include <sam4e8e.h>
|
||||
#elif defined(CONFIG_SOC_SAM4E8C)
|
||||
#include <sam4e8c.h>
|
||||
#else
|
||||
#error Library does not support the specified device.
|
||||
#endif
|
||||
|
||||
#include "../common/soc_pmc.h"
|
||||
#include "../common/soc_gpio.h"
|
||||
#include "../common/soc_supc.h"
|
||||
#include "../common/atmel_sam_dt.h"
|
||||
|
||||
/** Processor Clock (HCLK) Frequency */
|
||||
#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ
|
||||
|
||||
/** Master Clock (MCK) Frequency */
|
||||
#define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif /* _SOC_ATMEL_SAM_SAM4E_SOC_H_ */
|
||||
10
soc/atmel/sam/sam4l/CMakeLists.txt
Normal file
10
soc/atmel/sam/sam4l/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_include_directories(.)
|
||||
|
||||
zephyr_sources(
|
||||
soc.c
|
||||
)
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
|
||||
10
soc/atmel/sam/sam4l/Kconfig
Normal file
10
soc/atmel/sam/sam4l/Kconfig
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
# Copyright (c) 2020-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_SAM4L
|
||||
select ARM
|
||||
select CPU_CORTEX_M4
|
||||
select CPU_CORTEX_M_HAS_DWT
|
||||
select CPU_HAS_ARM_MPU
|
||||
select PLATFORM_SPECIFIC_INIT
|
||||
select HAS_POWEROFF
|
||||
9
soc/atmel/sam/sam4l/Kconfig.defconfig
Normal file
9
soc/atmel/sam/sam4l/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
# Copyright (c) 2020-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_SAM4L
|
||||
|
||||
config NUM_IRQS
|
||||
default 80
|
||||
|
||||
endif # SOC_SERIES_SAM4L
|
||||
107
soc/atmel/sam/sam4l/Kconfig.soc
Normal file
107
soc/atmel/sam/sam4l/Kconfig.soc
Normal file
|
|
@ -0,0 +1,107 @@
|
|||
# Copyright (c) 2020-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_SAM4L
|
||||
bool
|
||||
select SOC_FAMILY_ATMEL_SAM
|
||||
help
|
||||
Enable support for Atmel SAM4L Cortex-M4 microcontrollers.
|
||||
Part No.: SAM4LS8C, SAM4LS8B, SAM4LS8A, SAM4LS4C, SAM4LS4B,
|
||||
SAM4LS4A, SAM4LS2C, SAM4LS2B, SAM4LS2A, SAM4LC8C, SAM4LC8B,
|
||||
SAM4LC8A, SAM4LC4C, SAM4LC4B, SAM4LC4A SAM4LC2C, SAM4LC2B,
|
||||
SAM4LC2A
|
||||
|
||||
config SOC_SERIES
|
||||
default "sam4l" if SOC_SERIES_SAM4L
|
||||
|
||||
config SOC_SAM4LS2A
|
||||
bool
|
||||
select SOC_SERIES_SAM4L
|
||||
|
||||
config SOC_SAM4LS2B
|
||||
bool
|
||||
select SOC_SERIES_SAM4L
|
||||
|
||||
config SOC_SAM4LS2C
|
||||
bool
|
||||
select SOC_SERIES_SAM4L
|
||||
|
||||
config SOC_SAM4LS4A
|
||||
bool
|
||||
select SOC_SERIES_SAM4L
|
||||
|
||||
config SOC_SAM4LS4B
|
||||
bool
|
||||
select SOC_SERIES_SAM4L
|
||||
|
||||
config SOC_SAM4LS4C
|
||||
bool
|
||||
select SOC_SERIES_SAM4L
|
||||
|
||||
config SOC_SAM4LS8A
|
||||
bool
|
||||
select SOC_SERIES_SAM4L
|
||||
|
||||
config SOC_SAM4LS8B
|
||||
bool
|
||||
select SOC_SERIES_SAM4L
|
||||
|
||||
config SOC_SAM4LS8C
|
||||
bool
|
||||
select SOC_SERIES_SAM4L
|
||||
|
||||
config SOC_SAM4LC2A
|
||||
bool
|
||||
select SOC_SERIES_SAM4L
|
||||
|
||||
config SOC_SAM4LC2B
|
||||
bool
|
||||
select SOC_SERIES_SAM4L
|
||||
|
||||
config SOC_SAM4LC2C
|
||||
bool
|
||||
select SOC_SERIES_SAM4L
|
||||
|
||||
config SOC_SAM4LC4A
|
||||
bool
|
||||
select SOC_SERIES_SAM4L
|
||||
|
||||
config SOC_SAM4LC4B
|
||||
bool
|
||||
select SOC_SERIES_SAM4L
|
||||
|
||||
config SOC_SAM4LC4C
|
||||
bool
|
||||
select SOC_SERIES_SAM4L
|
||||
|
||||
config SOC_SAM4LC8A
|
||||
bool
|
||||
select SOC_SERIES_SAM4L
|
||||
|
||||
config SOC_SAM4LC8B
|
||||
bool
|
||||
select SOC_SERIES_SAM4L
|
||||
|
||||
config SOC_SAM4LC8C
|
||||
bool
|
||||
select SOC_SERIES_SAM4L
|
||||
|
||||
config SOC
|
||||
default "sam4ls2a" if SOC_SAM4LS2A
|
||||
default "sam4ls2b" if SOC_SAM4LS2B
|
||||
default "sam4ls2c" if SOC_SAM4LS2C
|
||||
default "sam4ls4a" if SOC_SAM4LS4A
|
||||
default "sam4ls4b" if SOC_SAM4LS4B
|
||||
default "sam4ls4c" if SOC_SAM4LS4C
|
||||
default "sam4ls8a" if SOC_SAM4LS8A
|
||||
default "sam4ls8b" if SOC_SAM4LS8B
|
||||
default "sam4ls8c" if SOC_SAM4LS8C
|
||||
default "sam4lc2a" if SOC_SAM4LC2A
|
||||
default "sam4lc2b" if SOC_SAM4LC2B
|
||||
default "sam4lc2c" if SOC_SAM4LC2C
|
||||
default "sam4lc4a" if SOC_SAM4LC4A
|
||||
default "sam4lc4b" if SOC_SAM4LC4B
|
||||
default "sam4lc4c" if SOC_SAM4LC4C
|
||||
default "sam4lc8a" if SOC_SAM4LC8A
|
||||
default "sam4lc8b" if SOC_SAM4LC8B
|
||||
default "sam4lc8c" if SOC_SAM4LC8C
|
||||
267
soc/atmel/sam/sam4l/soc.c
Normal file
267
soc/atmel/sam/sam4l/soc.c
Normal file
|
|
@ -0,0 +1,267 @@
|
|||
/*
|
||||
* Copyright (c) 2020-2023 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Atmel SAM4L MCU series initialization code
|
||||
*
|
||||
* This module provides routines to initialize and support board-level hardware
|
||||
* for the Atmel SAM4L series processor.
|
||||
*/
|
||||
|
||||
#include <zephyr/device.h>
|
||||
#include <zephyr/init.h>
|
||||
#include <soc.h>
|
||||
#include <zephyr/sys/util.h>
|
||||
|
||||
/** Watchdog control register first write keys */
|
||||
#define WDT_FIRST_KEY 0x55ul
|
||||
/** Watchdog control register second write keys */
|
||||
#define WDT_SECOND_KEY 0xAAul
|
||||
|
||||
/**
|
||||
* @brief Sets the WatchDog Timer Control register to the \a ctrl value thanks
|
||||
* to the WatchDog Timer key.
|
||||
*
|
||||
* @param ctrl Value to set the WatchDog Timer Control register to.
|
||||
*/
|
||||
static ALWAYS_INLINE void wdt_set_ctrl(uint32_t ctrl)
|
||||
{
|
||||
volatile uint32_t dly;
|
||||
|
||||
/** Calculate delay for internal synchronization
|
||||
* see 45.1.3 WDT errata
|
||||
*/
|
||||
dly = DIV_ROUND_UP(48000000 * 2, 115000);
|
||||
dly >>= 3; /* ~8 cycles for one while loop */
|
||||
while (dly--) {
|
||||
;
|
||||
}
|
||||
WDT->CTRL = ctrl | WDT_CTRL_KEY(WDT_FIRST_KEY);
|
||||
WDT->CTRL = ctrl | WDT_CTRL_KEY(WDT_SECOND_KEY);
|
||||
}
|
||||
|
||||
#define XTAL_FREQ 12000000
|
||||
#define NR_PLLS 1
|
||||
#define PLL_MAX_STARTUP_CYCLES (SCIF_PLL_PLLCOUNT_Msk >> SCIF_PLL_PLLCOUNT_Pos)
|
||||
|
||||
/**
|
||||
* Fcpu = 48MHz
|
||||
* Fpll = (Fclk * PLL_mul) / PLL_div
|
||||
*/
|
||||
#define PLL0_MUL (192000000 / XTAL_FREQ)
|
||||
#define PLL0_DIV 4
|
||||
|
||||
static inline bool pll_is_locked(uint32_t pll_id)
|
||||
{
|
||||
return !!(SCIF->PCLKSR & (1U << (6 + pll_id)));
|
||||
}
|
||||
|
||||
static inline bool osc_is_ready(uint8_t id)
|
||||
{
|
||||
switch (id) {
|
||||
case OSC_ID_OSC0:
|
||||
return !!(SCIF->PCLKSR & SCIF_PCLKSR_OSC0RDY);
|
||||
case OSC_ID_OSC32:
|
||||
return !!(BSCIF->PCLKSR & BSCIF_PCLKSR_OSC32RDY);
|
||||
case OSC_ID_RC32K:
|
||||
return !!(BSCIF->RC32KCR & (BSCIF_RC32KCR_EN));
|
||||
case OSC_ID_RC80M:
|
||||
return !!(SCIF->RC80MCR & (SCIF_RC80MCR_EN));
|
||||
case OSC_ID_RCFAST:
|
||||
return !!(SCIF->RCFASTCFG & (SCIF_RCFASTCFG_EN));
|
||||
case OSC_ID_RC1M:
|
||||
return !!(BSCIF->RC1MCR & (BSCIF_RC1MCR_CLKOE));
|
||||
case OSC_ID_RCSYS:
|
||||
/* RCSYS is always ready */
|
||||
return true;
|
||||
default:
|
||||
/* unhandled_case(id); */
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* The PLL options #PLL_OPT_VCO_RANGE_HIGH and #PLL_OPT_OUTPUT_DIV will
|
||||
* be set automatically based on the calculated target frequency.
|
||||
*/
|
||||
static inline uint32_t pll_config_init(uint32_t divide, uint32_t mul)
|
||||
{
|
||||
#define SCIF0_PLL_VCO_RANGE1_MAX_FREQ 240000000
|
||||
#define SCIF_PLL0_VCO_RANGE1_MIN_FREQ 160000000
|
||||
#define SCIF_PLL0_VCO_RANGE0_MAX_FREQ 180000000
|
||||
#define SCIF_PLL0_VCO_RANGE0_MIN_FREQ 80000000
|
||||
/* VCO frequency range is 160-240 MHz (80-180 MHz if unset) */
|
||||
#define PLL_OPT_VCO_RANGE_HIGH 0
|
||||
/* Divide output frequency by two */
|
||||
#define PLL_OPT_OUTPUT_DIV 1
|
||||
/* The threshold above which to set the #PLL_OPT_VCO_RANGE_HIGH option */
|
||||
#define PLL_VCO_LOW_THRESHOLD ((SCIF_PLL0_VCO_RANGE1_MIN_FREQ \
|
||||
+ SCIF_PLL0_VCO_RANGE0_MAX_FREQ) / 2)
|
||||
#define PLL_MIN_HZ 40000000
|
||||
#define PLL_MAX_HZ 240000000
|
||||
#define MUL_MIN 2
|
||||
#define MUL_MAX 16
|
||||
#define DIV_MIN 0
|
||||
#define DIV_MAX 15
|
||||
|
||||
uint32_t pll_value;
|
||||
uint32_t vco_hz;
|
||||
|
||||
/* Calculate internal VCO frequency */
|
||||
vco_hz = XTAL_FREQ * mul;
|
||||
vco_hz /= divide;
|
||||
|
||||
pll_value = 0;
|
||||
|
||||
/* Bring the internal VCO frequency up to the minimum value */
|
||||
if ((vco_hz < PLL_MIN_HZ * 2) && (mul <= 8)) {
|
||||
mul *= 2;
|
||||
vco_hz *= 2;
|
||||
pll_value |= (1U << (SCIF_PLL_PLLOPT_Pos +
|
||||
PLL_OPT_OUTPUT_DIV));
|
||||
}
|
||||
|
||||
/* Set VCO frequency range according to calculated value */
|
||||
if (vco_hz >= PLL_VCO_LOW_THRESHOLD) {
|
||||
pll_value |= 1U << (SCIF_PLL_PLLOPT_Pos +
|
||||
PLL_OPT_VCO_RANGE_HIGH);
|
||||
}
|
||||
|
||||
pll_value |= ((mul - 1) << SCIF_PLL_PLLMUL_Pos) |
|
||||
(divide << SCIF_PLL_PLLDIV_Pos) |
|
||||
(PLL_MAX_STARTUP_CYCLES << SCIF_PLL_PLLCOUNT_Pos);
|
||||
|
||||
return pll_value;
|
||||
}
|
||||
|
||||
static inline void flashcalw_set_wait_state(uint32_t wait_state)
|
||||
{
|
||||
HFLASHC->FCR = (HFLASHC->FCR & ~FLASHCALW_FCR_FWS) |
|
||||
(wait_state ?
|
||||
FLASHCALW_FCR_FWS_1 :
|
||||
FLASHCALW_FCR_FWS_0);
|
||||
}
|
||||
|
||||
static inline bool flashcalw_is_ready(void)
|
||||
{
|
||||
return ((HFLASHC->FSR & FLASHCALW_FSR_FRDY) != 0);
|
||||
}
|
||||
|
||||
static inline void flashcalw_issue_command(uint32_t command, int page_number)
|
||||
{
|
||||
uint32_t time;
|
||||
|
||||
flashcalw_is_ready();
|
||||
time = HFLASHC->FCMD;
|
||||
|
||||
/* Clear the command bitfield. */
|
||||
time &= ~FLASHCALW_FCMD_CMD_Msk;
|
||||
if (page_number >= 0) {
|
||||
time = (FLASHCALW_FCMD_KEY_KEY |
|
||||
FLASHCALW_FCMD_PAGEN(page_number) | command);
|
||||
} else {
|
||||
time |= (FLASHCALW_FCMD_KEY_KEY | command);
|
||||
}
|
||||
|
||||
HFLASHC->FCMD = time;
|
||||
flashcalw_is_ready();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Setup various clock on SoC at boot time.
|
||||
*
|
||||
* Setup the SoC clocks according to section 28.12 in datasheet.
|
||||
*
|
||||
* Setup Slow, Main, PLLA, Processor and Master clocks during the device boot.
|
||||
* It is assumed that the relevant registers are at their reset value.
|
||||
*/
|
||||
static ALWAYS_INLINE void clock_init(void)
|
||||
{
|
||||
/* Disable PicoCache and Enable HRAMC1 as extended RAM */
|
||||
soc_pmc_peripheral_enable(
|
||||
PM_CLOCK_MASK(PM_CLK_GRP_HSB, SYSCLK_HRAMC1_DATA));
|
||||
soc_pmc_peripheral_enable(
|
||||
PM_CLOCK_MASK(PM_CLK_GRP_PBB, SYSCLK_HRAMC1_REGS));
|
||||
|
||||
HCACHE->CTRL = HCACHE_CTRL_CEN_NO;
|
||||
|
||||
while (HCACHE->SR & HCACHE_SR_CSTS_EN) {
|
||||
;
|
||||
}
|
||||
|
||||
/* Enable PLL */
|
||||
if (!pll_is_locked(0)) {
|
||||
/* This assumes external 12MHz Crystal */
|
||||
SCIF->UNLOCK = SCIF_UNLOCK_KEY(0xAAu) |
|
||||
SCIF_UNLOCK_ADDR((uint32_t)&SCIF->OSCCTRL0 -
|
||||
(uint32_t)SCIF);
|
||||
SCIF->OSCCTRL0 = SCIF_OSCCTRL0_STARTUP(2) |
|
||||
SCIF_OSCCTRL0_GAIN(3) |
|
||||
SCIF_OSCCTRL0_MODE |
|
||||
SCIF_OSCCTRL0_OSCEN;
|
||||
|
||||
while (!osc_is_ready(OSC_ID_OSC0)) {
|
||||
;
|
||||
}
|
||||
uint32_t pll_config = pll_config_init(PLL0_DIV,
|
||||
PLL0_MUL);
|
||||
|
||||
SCIF->UNLOCK = SCIF_UNLOCK_KEY(0xAAu) |
|
||||
SCIF_UNLOCK_ADDR((uint32_t)&SCIF->PLL[0] -
|
||||
(uint32_t)SCIF);
|
||||
SCIF->PLL[0] = pll_config | SCIF_PLL_PLLEN;
|
||||
|
||||
while (!pll_is_locked(0)) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
/** Set a flash wait state depending on the new cpu frequency.
|
||||
*/
|
||||
flashcalw_set_wait_state(1);
|
||||
flashcalw_issue_command(FLASHCALW_FCMD_CMD_HSEN, -1);
|
||||
|
||||
/** Set Clock CPU/BUS dividers
|
||||
*/
|
||||
PM->UNLOCK = PM_UNLOCK_KEY(0xAAu) |
|
||||
PM_UNLOCK_ADDR((uint32_t)&PM->CPUSEL - (uint32_t)PM);
|
||||
PM->CPUSEL = PM_CPUSEL_CPUSEL(0);
|
||||
|
||||
PM->UNLOCK = PM_UNLOCK_KEY(0xAAu) |
|
||||
PM_UNLOCK_ADDR((uint32_t)&PM->PBASEL - (uint32_t)PM);
|
||||
PM->PBASEL = PM_PBASEL_PBSEL(0);
|
||||
|
||||
PM->UNLOCK = PM_UNLOCK_KEY(0xAAu) |
|
||||
PM_UNLOCK_ADDR((uint32_t)&PM->PBBSEL - (uint32_t)PM);
|
||||
PM->PBBSEL = PM_PBBSEL_PBSEL(0);
|
||||
|
||||
PM->UNLOCK = PM_UNLOCK_KEY(0xAAu) |
|
||||
PM_UNLOCK_ADDR((uint32_t)&PM->PBCSEL - (uint32_t)PM);
|
||||
PM->PBCSEL = PM_PBCSEL_PBSEL(0);
|
||||
|
||||
PM->UNLOCK = PM_UNLOCK_KEY(0xAAu) |
|
||||
PM_UNLOCK_ADDR((uint32_t)&PM->PBDSEL - (uint32_t)PM);
|
||||
PM->PBDSEL = PM_PBDSEL_PBSEL(0);
|
||||
|
||||
/** Set PLL0 as source clock
|
||||
*/
|
||||
PM->UNLOCK = PM_UNLOCK_KEY(0xAAu) |
|
||||
PM_UNLOCK_ADDR((uint32_t)&PM->MCCTRL - (uint32_t)PM);
|
||||
PM->MCCTRL = OSC_SRC_PLL0;
|
||||
}
|
||||
|
||||
void z_arm_platform_init(void)
|
||||
{
|
||||
#if defined(CONFIG_WDT_DISABLE_AT_BOOT)
|
||||
wdt_set_ctrl(WDT->CTRL & ~WDT_CTRL_EN);
|
||||
while (WDT->CTRL & WDT_CTRL_EN) {
|
||||
;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Setup system clocks. */
|
||||
clock_init();
|
||||
}
|
||||
223
soc/atmel/sam/sam4l/soc.h
Normal file
223
soc/atmel/sam/sam4l/soc.h
Normal file
|
|
@ -0,0 +1,223 @@
|
|||
/*
|
||||
* Copyright (c) 2020-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SoC configuration macros for the Atmel SAM4L family processors.
|
||||
*/
|
||||
|
||||
#ifndef _SOC_ATMEL_SAM_SAM4L_SOC_H_
|
||||
#define _SOC_ATMEL_SAM_SAM4L_SOC_H_
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#define DONT_USE_CMSIS_INIT
|
||||
#define DONT_USE_PREDEFINED_CORE_HANDLERS
|
||||
#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
|
||||
|
||||
#if defined(CONFIG_SOC_SAM4LS8C)
|
||||
#include <sam4ls8c.h>
|
||||
#elif defined(CONFIG_SOC_SAM4LS8B)
|
||||
#include <sam4ls8b.h>
|
||||
#elif defined(CONFIG_SOC_SAM4LS8A)
|
||||
#include <sam4ls8a.h>
|
||||
#elif defined(CONFIG_SOC_SAM4LS4C)
|
||||
#include <sam4ls4c.h>
|
||||
#elif defined(CONFIG_SOC_SAM4LS4B)
|
||||
#include <sam4ls4b.h>
|
||||
#elif defined(CONFIG_SOC_SAM4LS4A)
|
||||
#include <sam4ls4a.h>
|
||||
#elif defined(CONFIG_SOC_SAM4LS2C)
|
||||
#include <sam4ls2c.h>
|
||||
#elif defined(CONFIG_SOC_SAM4LS2B)
|
||||
#include <sam4ls2b.h>
|
||||
#elif defined(CONFIG_SOC_SAM4LS2A)
|
||||
#include <sam4ls2a.h>
|
||||
#elif defined(CONFIG_SOC_SAM4LC8C)
|
||||
#include <sam4lc8c.h>
|
||||
#elif defined(CONFIG_SOC_SAM4LC8B)
|
||||
#include <sam4lc8b.h>
|
||||
#elif defined(CONFIG_SOC_SAM4LC8A)
|
||||
#include <sam4lc8a.h>
|
||||
#elif defined(CONFIG_SOC_SAM4LC4C)
|
||||
#include <sam4lc4c.h>
|
||||
#elif defined(CONFIG_SOC_SAM4LC4B)
|
||||
#include <sam4lc4b.h>
|
||||
#elif defined(CONFIG_SOC_SAM4LC4A)
|
||||
#include <sam4lc4a.h>
|
||||
#elif defined(CONFIG_SOC_SAM4LC2C)
|
||||
#include <sam4lc2c.h>
|
||||
#elif defined(CONFIG_SOC_SAM4LC2B)
|
||||
#include <sam4lc2b.h>
|
||||
#elif defined(CONFIG_SOC_SAM4LC2A)
|
||||
#include <sam4lc2a.h>
|
||||
#else
|
||||
#error Library does not support the specified device.
|
||||
#endif
|
||||
|
||||
#include "../common/soc_pmc.h"
|
||||
#include "../common/soc_gpio.h"
|
||||
#include "../common/atmel_sam_dt.h"
|
||||
|
||||
/** Processor Clock (HCLK) Frequency */
|
||||
#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ
|
||||
|
||||
/** Master Clock (MCK) Frequency */
|
||||
#define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ
|
||||
|
||||
/** Oscillator identifiers
|
||||
* External Oscillator 0
|
||||
* External 32 kHz oscillator
|
||||
* Internal 32 kHz RC oscillator
|
||||
* Internal 80 MHz RC oscillator
|
||||
* Internal 4-8-12 MHz RCFAST oscillator
|
||||
* Internal 1 MHz RC oscillator
|
||||
* Internal System RC oscillator
|
||||
*/
|
||||
#define OSC_ID_OSC0 0
|
||||
#define OSC_ID_OSC32 1
|
||||
#define OSC_ID_RC32K 2
|
||||
#define OSC_ID_RC80M 3
|
||||
#define OSC_ID_RCFAST 4
|
||||
#define OSC_ID_RC1M 5
|
||||
#define OSC_ID_RCSYS 6
|
||||
|
||||
/** System clock source
|
||||
* System RC oscillator
|
||||
* Oscillator 0
|
||||
* Phase Locked Loop 0
|
||||
* Digital Frequency Locked Loop
|
||||
* 80 MHz RC oscillator
|
||||
* 4-8-12 MHz RC oscillator
|
||||
* 1 MHz RC oscillator
|
||||
*/
|
||||
#define OSC_SRC_RCSYS 0
|
||||
#define OSC_SRC_OSC0 1
|
||||
#define OSC_SRC_PLL0 2
|
||||
#define OSC_SRC_DFLL 3
|
||||
#define OSC_SRC_RC80M 4
|
||||
#define OSC_SRC_RCFAST 5
|
||||
#define OSC_SRC_RC1M 6
|
||||
|
||||
#define PM_CLOCK_MASK(bus, per) ((bus << 5) + per)
|
||||
|
||||
/** Bus index of maskable module clocks. Peripheral ids are defined out of
|
||||
* order. It start from PBA up to PBD, then move to HSB, and finally CPU.
|
||||
*/
|
||||
#define PM_CLK_GRP_CPU 5
|
||||
#define PM_CLK_GRP_HSB 4
|
||||
#define PM_CLK_GRP_PBA 0
|
||||
#define PM_CLK_GRP_PBB 1
|
||||
#define PM_CLK_GRP_PBC 2
|
||||
#define PM_CLK_GRP_PBD 3
|
||||
|
||||
/** Clocks derived from the CPU clock
|
||||
*/
|
||||
#define SYSCLK_OCD 0
|
||||
|
||||
/** Clocks derived from the HSB clock
|
||||
*/
|
||||
#define SYSCLK_PDCA_HSB 0
|
||||
#define SYSCLK_HFLASHC_DATA 1
|
||||
#define SYSCLK_HRAMC1_DATA 2
|
||||
#define SYSCLK_USBC_DATA 3
|
||||
#define SYSCLK_CRCCU_DATA 4
|
||||
#define SYSCLK_PBA_BRIDGE 5
|
||||
#define SYSCLK_PBB_BRIDGE 6
|
||||
#define SYSCLK_PBC_BRIDGE 7
|
||||
#define SYSCLK_PBD_BRIDGE 8
|
||||
#define SYSCLK_AESA_HSB 9
|
||||
|
||||
/** Clocks derived from the PBA clock
|
||||
*/
|
||||
#define SYSCLK_IISC 0
|
||||
#define SYSCLK_SPI 1
|
||||
#define SYSCLK_TC0 2
|
||||
#define SYSCLK_TC1 3
|
||||
#define SYSCLK_TWIM0 4
|
||||
#define SYSCLK_TWIS0 5
|
||||
#define SYSCLK_TWIM1 6
|
||||
#define SYSCLK_TWIS1 7
|
||||
#define SYSCLK_USART0 8
|
||||
#define SYSCLK_USART1 9
|
||||
#define SYSCLK_USART2 10
|
||||
#define SYSCLK_USART3 11
|
||||
#define SYSCLK_ADCIFE 12
|
||||
#define SYSCLK_DACC 13
|
||||
#define SYSCLK_ACIFC 14
|
||||
#define SYSCLK_GLOC 15
|
||||
#define SYSCLK_ABDACB 16
|
||||
#define SYSCLK_TRNG 17
|
||||
#define SYSCLK_PARC 18
|
||||
#define SYSCLK_CATB 19
|
||||
#define SYSCLK_TWIM2 21
|
||||
#define SYSCLK_TWIM3 22
|
||||
#define SYSCLK_LCDCA 23
|
||||
|
||||
/** Clocks derived from the PBB clock
|
||||
*/
|
||||
#define SYSCLK_HFLASHC_REGS 0
|
||||
#define SYSCLK_HRAMC1_REGS 1
|
||||
#define SYSCLK_HMATRIX 2
|
||||
#define SYSCLK_PDCA_PB 3
|
||||
#define SYSCLK_CRCCU_REGS 4
|
||||
#define SYSCLK_USBC_REGS 5
|
||||
#define SYSCLK_PEVC 6
|
||||
|
||||
/** Clocks derived from the PBC clock
|
||||
*/
|
||||
#define SYSCLK_PM 0
|
||||
#define SYSCLK_CHIPID 1
|
||||
#define SYSCLK_SCIF 2
|
||||
#define SYSCLK_FREQM 3
|
||||
#define SYSCLK_GPIO 4
|
||||
|
||||
/** Clocks derived from the PBD clock
|
||||
*/
|
||||
#define SYSCLK_BPM 0
|
||||
#define SYSCLK_BSCIF 1
|
||||
#define SYSCLK_AST 2
|
||||
#define SYSCLK_WDT 3
|
||||
#define SYSCLK_EIC 4
|
||||
#define SYSCLK_PICOUART 5
|
||||
|
||||
/** Divided clock mask derived from the PBA clock
|
||||
*/
|
||||
#define PBA_DIVMASK_TIMER_CLOCK2 (1u << 0)
|
||||
#define PBA_DIVMASK_TIMER_CLOCK3 (1u << 2)
|
||||
#define PBA_DIVMASK_CLK_USART (1u << 2)
|
||||
#define PBA_DIVMASK_TIMER_CLOCK4 (1u << 4)
|
||||
#define PBA_DIVMASK_TIMER_CLOCK5 (1u << 6)
|
||||
#define PBA_DIVMASK_Msk (0x7Fu << 0)
|
||||
|
||||
/** Generic Clock Instances
|
||||
* 0- DFLLIF main reference and GCLK0 pin (CLK_DFLLIF_REF)
|
||||
* 1- DFLLIF dithering and SSG reference and GCLK1 pin (CLK_DFLLIF_DITHER)
|
||||
* 2- AST and GCLK2 pin
|
||||
* 3- CATB and GCLK3 pin
|
||||
* 4- AESA
|
||||
* 5- GLOC, TC0 and RC32KIFB_REF
|
||||
* 6- ABDACB and IISC
|
||||
* 7- USBC
|
||||
* 8- TC1 and PEVC[0]
|
||||
* 9- PLL0 and PEVC[1]
|
||||
* 10- ADCIFE
|
||||
* 11- Master generic clock. Can be used as source for other generic clocks.
|
||||
*/
|
||||
#define GEN_CLK_DFLL_REF 0
|
||||
#define GEN_CLK_DFLL_DITHER 1
|
||||
#define GEN_CLK_AST 2
|
||||
#define GEN_CLK_CATB 3
|
||||
#define GEN_CLK_AESA 4
|
||||
#define GEN_CLK_GLOC 5
|
||||
#define GEN_CLK_ABDACB 6
|
||||
#define GEN_CLK_USBC 7
|
||||
#define GEN_CLK_TC1_PEVC0 8
|
||||
#define GEN_CLK_PLL0_PEVC1 9
|
||||
#define GEN_CLK_ADCIFE 10
|
||||
#define GEN_CLK_MASTER_GEN 11
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif /* _SOC_ATMEL_SAM_SAM4L_SOC_H_ */
|
||||
10
soc/atmel/sam/sam4s/CMakeLists.txt
Normal file
10
soc/atmel/sam/sam4s/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_include_directories(.)
|
||||
|
||||
zephyr_sources(
|
||||
soc.c
|
||||
)
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
|
||||
14
soc/atmel/sam/sam4s/Kconfig
Normal file
14
soc/atmel/sam/sam4s/Kconfig
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
# Atmel SAM4S MCU series
|
||||
|
||||
# Copyright (c) 2017 Justin Watson
|
||||
# Copyright (c) 2018 Vincent van der Locht
|
||||
# Copyright (c) 2020-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_SAM4S
|
||||
select ARM
|
||||
select CPU_CORTEX_M4
|
||||
select CPU_CORTEX_M_HAS_DWT
|
||||
select CPU_HAS_ARM_MPU
|
||||
select PLATFORM_SPECIFIC_INIT
|
||||
select HAS_POWEROFF
|
||||
13
soc/atmel/sam/sam4s/Kconfig.defconfig
Normal file
13
soc/atmel/sam/sam4s/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
# Atmel SAM4S MCU series configuration options
|
||||
|
||||
# Copyright (c) 2017 Justin Watson
|
||||
# Copyright (c) 2018 Vincent van der Locht
|
||||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_SAM4S
|
||||
|
||||
config NUM_IRQS
|
||||
default 35
|
||||
|
||||
endif # SOC_SERIES_SAM4S
|
||||
74
soc/atmel/sam/sam4s/Kconfig.soc
Normal file
74
soc/atmel/sam/sam4s/Kconfig.soc
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
# Atmel SAM4S MCU series
|
||||
|
||||
# Copyright (c) 2017 Justin Watson
|
||||
# Copyright (c) 2018 Vincent van der Locht
|
||||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_SAM4S
|
||||
bool
|
||||
select SOC_FAMILY_ATMEL_SAM
|
||||
help
|
||||
Enable support for Atmel SAM4S Cortex-M4 microcontrollers.
|
||||
Part No.: SAM4S16C, SAM4S16B, SAM4S8C, SAM4S8B,
|
||||
SAM4S4C, SAM4S4B, SAM4S4A, SAM4S2C, SAM4S2B, SAM4S2A
|
||||
|
||||
config SOC_SERIES
|
||||
default "sam4s" if SOC_SERIES_SAM4S
|
||||
|
||||
config SOC_SAM4S2A
|
||||
bool
|
||||
select SOC_SERIES_SAM4S
|
||||
|
||||
config SOC_SAM4S2B
|
||||
bool
|
||||
select SOC_SERIES_SAM4S
|
||||
|
||||
config SOC_SAM4S2C
|
||||
bool
|
||||
select SOC_SERIES_SAM4S
|
||||
|
||||
config SOC_SAM4S4A
|
||||
bool
|
||||
select SOC_SERIES_SAM4S
|
||||
|
||||
config SOC_SAM4S4B
|
||||
bool
|
||||
select SOC_SERIES_SAM4S
|
||||
|
||||
config SOC_SAM4S4C
|
||||
bool
|
||||
select SOC_SERIES_SAM4S
|
||||
|
||||
config SOC_SAM4S8B
|
||||
bool
|
||||
select SOC_SERIES_SAM4S
|
||||
|
||||
config SOC_SAM4S8C
|
||||
bool
|
||||
select SOC_SERIES_SAM4S
|
||||
|
||||
config SOC_SAM4S16B
|
||||
bool
|
||||
select SOC_SERIES_SAM4S
|
||||
|
||||
config SOC_SAM4S16C
|
||||
bool
|
||||
select SOC_SERIES_SAM4S
|
||||
|
||||
config SOC_SAM4SA16C
|
||||
bool
|
||||
select SOC_SERIES_SAM4S
|
||||
|
||||
config SOC
|
||||
default "sam4s2a" if SOC_SAM4S2A
|
||||
default "sam4s2b" if SOC_SAM4S2B
|
||||
default "sam4s2c" if SOC_SAM4S2C
|
||||
default "sam4s4a" if SOC_SAM4S4A
|
||||
default "sam4s4b" if SOC_SAM4S4B
|
||||
default "sam4s4c" if SOC_SAM4S4C
|
||||
default "sam4s8b" if SOC_SAM4S8B
|
||||
default "sam4s8c" if SOC_SAM4S8C
|
||||
default "sam4s16b" if SOC_SAM4S16B
|
||||
default "sam4s16c" if SOC_SAM4S16C
|
||||
default "sam4sa16c" if SOC_SAM4SA16C
|
||||
111
soc/atmel/sam/sam4s/soc.c
Normal file
111
soc/atmel/sam/sam4s/soc.c
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2015 Wind River Systems, Inc.
|
||||
* Copyright (c) 2016 Intel Corporation.
|
||||
* Copyright (c) 2017 Justin Watson
|
||||
* Copyright (c) 2023 Basalte bv
|
||||
* Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Atmel SAM4S MCU series initialization code
|
||||
*
|
||||
* This module provides routines to initialize and support board-level hardware
|
||||
* for the Atmel SAM4S series processor.
|
||||
*/
|
||||
|
||||
#include <soc.h>
|
||||
#include <soc_pmc.h>
|
||||
#include <soc_supc.h>
|
||||
|
||||
/**
|
||||
* @brief Setup various clock on SoC at boot time.
|
||||
*
|
||||
* Setup the SoC clocks according to section 28.12 in datasheet.
|
||||
*
|
||||
* Setup Slow, Main, PLLA, Processor and Master clocks during the device boot.
|
||||
* It is assumed that the relevant registers are at their reset value.
|
||||
*/
|
||||
static ALWAYS_INLINE void clock_init(void)
|
||||
{
|
||||
/* Switch the main clock to the internal OSC with 12MHz */
|
||||
soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ);
|
||||
|
||||
/* Switch MCK (Master Clock) to the main clock */
|
||||
soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK);
|
||||
|
||||
EFC0->EEFC_FMR = EEFC_FMR_FWS(0);
|
||||
#if defined(ID_EFC1)
|
||||
EFC1->EEFC_FMR = EEFC_FMR_FWS(0);
|
||||
#endif
|
||||
|
||||
soc_pmc_enable_clock_failure_detector();
|
||||
|
||||
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) {
|
||||
soc_supc_slow_clock_select_crystal_osc();
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
|
||||
/*
|
||||
* Setup main external crystal oscillator.
|
||||
*/
|
||||
|
||||
/* We select maximum setup time.
|
||||
* While start up time could be shortened
|
||||
* this optimization is not deemed
|
||||
* critical now.
|
||||
*/
|
||||
soc_pmc_switch_mainck_to_xtal(false, 0xff);
|
||||
}
|
||||
|
||||
/*
|
||||
* Set FWS (Flash Wait State) value before increasing Master Clock
|
||||
* (MCK) frequency. Look at table 44.73 in the SAM4S datasheet.
|
||||
* This is set to the highest number of read cycles because it won't
|
||||
* hurt lower clock frequencies. However, a high frequency with too
|
||||
* few read cycles could cause flash read problems. FWS 5 (6 cycles)
|
||||
* is the safe setting for all of this SoCs usable frequencies.
|
||||
*/
|
||||
EFC0->EEFC_FMR = EEFC_FMR_FWS(5);
|
||||
#if defined(ID_EFC1)
|
||||
EFC1->EEFC_FMR = EEFC_FMR_FWS(5);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Setup PLLA
|
||||
*/
|
||||
soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu,
|
||||
CONFIG_SOC_ATMEL_SAM_PLLA_DIVA);
|
||||
|
||||
/*
|
||||
* Final setup of the Master Clock
|
||||
*/
|
||||
|
||||
/* prescaler has to be set before PLL lock */
|
||||
soc_pmc_mck_set_prescaler(1);
|
||||
|
||||
/* Select PLL as Master Clock source. */
|
||||
soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK);
|
||||
|
||||
/* Disable internal fast RC if we have an external crystal oscillator */
|
||||
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
|
||||
soc_pmc_osc_disable_fastrc();
|
||||
}
|
||||
}
|
||||
|
||||
void z_arm_platform_init(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
|
||||
/*
|
||||
* Instruct CPU to enter Wait mode instead of Sleep mode to
|
||||
* keep Processor Clock (HCLK) and thus be able to debug
|
||||
* CPU using JTAG.
|
||||
*/
|
||||
soc_pmc_enable_waitmode();
|
||||
}
|
||||
|
||||
/* Setup system clocks. */
|
||||
clock_init();
|
||||
}
|
||||
65
soc/atmel/sam/sam4s/soc.h
Normal file
65
soc/atmel/sam/sam4s/soc.h
Normal file
|
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2015 Wind River Systems, Inc.
|
||||
* Copyright (c) 2016 Intel Corporation.
|
||||
* Copyright (c) 2017 Justin Watson
|
||||
* Copyright (c) 2018 Vincent van der Locht
|
||||
* Copyright (c) 2020-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SoC configuration macros for the Atmel SAM4S family processors.
|
||||
*/
|
||||
|
||||
#ifndef _SOC_ATMEL_SAM_SAM4S_SOC_H_
|
||||
#define _SOC_ATMEL_SAM_SAM4S_SOC_H_
|
||||
|
||||
#include <zephyr/sys/util.h>
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#define DONT_USE_CMSIS_INIT
|
||||
#define DONT_USE_PREDEFINED_CORE_HANDLERS
|
||||
#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
|
||||
|
||||
#if defined(CONFIG_SOC_SAM4S16C)
|
||||
#include <sam4s16c.h>
|
||||
#elif defined(CONFIG_SOC_SAM4SA16C)
|
||||
#include <sam4sa16c.h>
|
||||
#elif defined(CONFIG_SOC_SAM4S16B)
|
||||
#include <sam4s16b.h>
|
||||
#elif defined(CONFIG_SOC_SAM4S8C)
|
||||
#include <sam4s8c.h>
|
||||
#elif defined(CONFIG_SOC_SAM4S8B)
|
||||
#include <sam4s8b.h>
|
||||
#elif defined(CONFIG_SOC_SAM4S4C)
|
||||
#include <sam4s4c.h>
|
||||
#elif defined(CONFIG_SOC_SAM4S4B)
|
||||
#include <sam4s4b.h>
|
||||
#elif defined(CONFIG_SOC_SAM4S4A)
|
||||
#include <sam4s4a.h>
|
||||
#elif defined(CONFIG_SOC_SAM4S2C)
|
||||
#include <sam4s2c.h>
|
||||
#elif defined(CONFIG_SOC_SAM4S2B)
|
||||
#include <sam4s2b.h>
|
||||
#elif defined(CONFIG_SOC_SAM4S2A)
|
||||
#include <sam4s2a.h>
|
||||
#else
|
||||
#error Library does not support the specified device.
|
||||
#endif
|
||||
|
||||
#include "../common/soc_pmc.h"
|
||||
#include "../common/soc_gpio.h"
|
||||
#include "../common/soc_supc.h"
|
||||
#include "../common/atmel_sam_dt.h"
|
||||
|
||||
/** Processor Clock (HCLK) Frequency */
|
||||
#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ
|
||||
|
||||
/** Master Clock (MCK) Frequency */
|
||||
#define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif /* _SOC_ATMEL_SAM_SAM4S_SOC_H_ */
|
||||
11
soc/atmel/sam/same70/CMakeLists.txt
Normal file
11
soc/atmel/sam/same70/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_include_directories(.)
|
||||
|
||||
zephyr_sources(
|
||||
soc.c
|
||||
soc_config.c
|
||||
)
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
|
||||
19
soc/atmel/sam/same70/Kconfig
Normal file
19
soc/atmel/sam/same70/Kconfig
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
# Atmel SAM E70 MCU series
|
||||
|
||||
# Copyright (c) 2016 Piotr Mienkowski
|
||||
# Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_SAME70
|
||||
select ARM
|
||||
select CPU_CORTEX_M7
|
||||
select CPU_CORTEX_M_HAS_DWT
|
||||
select CPU_HAS_ARM_MPU
|
||||
select CPU_HAS_FPU_DOUBLE_PRECISION
|
||||
select CPU_HAS_ICACHE
|
||||
select CPU_HAS_DCACHE
|
||||
select INIT_ARCH_HW_AT_BOOT
|
||||
select PLATFORM_SPECIFIC_INIT
|
||||
select HAS_SWO
|
||||
select XIP
|
||||
select HAS_POWEROFF
|
||||
13
soc/atmel/sam/same70/Kconfig.defconfig
Normal file
13
soc/atmel/sam/same70/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
# Atmel SAM E70 MCU series configuration options
|
||||
|
||||
# Copyright (c) 2016 Piotr Mienkowski
|
||||
# Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_SAME70
|
||||
|
||||
config NUM_IRQS
|
||||
default 74 if SOC_ATMEL_SAME70_REVB
|
||||
default 71
|
||||
|
||||
endif # SOC_SERIES_SAME70
|
||||
122
soc/atmel/sam/same70/Kconfig.soc
Normal file
122
soc/atmel/sam/same70/Kconfig.soc
Normal file
|
|
@ -0,0 +1,122 @@
|
|||
# Atmel SAM E70 MCU series
|
||||
|
||||
# Copyright (c) 2016 Piotr Mienkowski
|
||||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_SAME70
|
||||
bool
|
||||
select SOC_FAMILY_ATMEL_SAM
|
||||
help
|
||||
Enable support for Atmel SAM E70 ARM Cortex-M7 Microcontrollers.
|
||||
Part No.: SAME70J19, SAME70J20, SAME70J21, SAME70N19, SAME70N20,
|
||||
SAME70N21, SAME70Q19, SAME70Q20, SAME70Q21, SAME70J19B, SAME70J20B,
|
||||
SAME70J21B, SAME70N19B, SAME70N20B, SAME70N21B, SAME70Q19B,
|
||||
SAME70Q20B, SAME70Q21B
|
||||
|
||||
config SOC_ATMEL_SAME70_REVB
|
||||
bool
|
||||
|
||||
config SOC_SERIES
|
||||
default "same70" if SOC_SERIES_SAME70
|
||||
|
||||
config SOC_SAME70J19
|
||||
bool
|
||||
select SOC_SERIES_SAME70
|
||||
|
||||
config SOC_SAME70J20
|
||||
bool
|
||||
select SOC_SERIES_SAME70
|
||||
|
||||
config SOC_SAME70J21
|
||||
bool
|
||||
select SOC_SERIES_SAME70
|
||||
|
||||
config SOC_SAME70N19
|
||||
bool
|
||||
select SOC_SERIES_SAME70
|
||||
|
||||
config SOC_SAME70N20
|
||||
bool
|
||||
select SOC_SERIES_SAME70
|
||||
|
||||
config SOC_SAME70N21
|
||||
bool
|
||||
select SOC_SERIES_SAME70
|
||||
|
||||
config SOC_SAME70Q19
|
||||
bool
|
||||
select SOC_SERIES_SAME70
|
||||
|
||||
config SOC_SAME70Q20
|
||||
bool
|
||||
select SOC_SERIES_SAME70
|
||||
|
||||
config SOC_SAME70Q21
|
||||
bool
|
||||
select SOC_SERIES_SAME70
|
||||
|
||||
config SOC_SAME70J19B
|
||||
bool
|
||||
select SOC_SERIES_SAME70
|
||||
select SOC_ATMEL_SAME70_REVB
|
||||
|
||||
config SOC_SAME70J20B
|
||||
bool
|
||||
select SOC_SERIES_SAME70
|
||||
select SOC_ATMEL_SAME70_REVB
|
||||
|
||||
config SOC_SAME70J21B
|
||||
bool
|
||||
select SOC_SERIES_SAME70
|
||||
select SOC_ATMEL_SAME70_REVB
|
||||
|
||||
config SOC_SAME70N19B
|
||||
bool
|
||||
select SOC_SERIES_SAME70
|
||||
select SOC_ATMEL_SAME70_REVB
|
||||
|
||||
config SOC_SAME70N20B
|
||||
bool
|
||||
select SOC_SERIES_SAME70
|
||||
select SOC_ATMEL_SAME70_REVB
|
||||
|
||||
config SOC_SAME70N21B
|
||||
bool
|
||||
select SOC_SERIES_SAME70
|
||||
select SOC_ATMEL_SAME70_REVB
|
||||
|
||||
config SOC_SAME70Q19B
|
||||
bool
|
||||
select SOC_SERIES_SAME70
|
||||
select SOC_ATMEL_SAME70_REVB
|
||||
|
||||
config SOC_SAME70Q20B
|
||||
bool
|
||||
select SOC_SERIES_SAME70
|
||||
select SOC_ATMEL_SAME70_REVB
|
||||
|
||||
config SOC_SAME70Q21B
|
||||
bool
|
||||
select SOC_SERIES_SAME70
|
||||
select SOC_ATMEL_SAME70_REVB
|
||||
|
||||
config SOC
|
||||
default "same70j19" if SOC_SAME70J19
|
||||
default "same70j20" if SOC_SAME70J20
|
||||
default "same70j21" if SOC_SAME70J21
|
||||
default "same70n19" if SOC_SAME70N19
|
||||
default "same70n20" if SOC_SAME70N20
|
||||
default "same70n21" if SOC_SAME70N21
|
||||
default "same70q19" if SOC_SAME70Q19
|
||||
default "same70q20" if SOC_SAME70Q20
|
||||
default "same70q21" if SOC_SAME70Q21
|
||||
default "same70j19b" if SOC_SAME70J19B
|
||||
default "same70j20b" if SOC_SAME70J20B
|
||||
default "same70j21b" if SOC_SAME70J21B
|
||||
default "same70n19b" if SOC_SAME70N19B
|
||||
default "same70n20b" if SOC_SAME70N20B
|
||||
default "same70n21b" if SOC_SAME70N21B
|
||||
default "same70q19b" if SOC_SAME70Q19B
|
||||
default "same70q20b" if SOC_SAME70Q20B
|
||||
default "same70q21b" if SOC_SAME70Q21B
|
||||
156
soc/atmel/sam/same70/soc.c
Normal file
156
soc/atmel/sam/same70/soc.c
Normal file
|
|
@ -0,0 +1,156 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Piotr Mienkowski
|
||||
* Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/** @file
|
||||
* @brief Atmel SAM E70 MCU initialization code
|
||||
*
|
||||
* This file provides routines to initialize and support board-level hardware
|
||||
* for the Atmel SAM E70 MCU.
|
||||
*/
|
||||
|
||||
#include <zephyr/kernel.h>
|
||||
#include <zephyr/device.h>
|
||||
#include <zephyr/init.h>
|
||||
#include <zephyr/cache.h>
|
||||
#include <zephyr/arch/cache.h>
|
||||
#include <soc.h>
|
||||
#include <soc_pmc.h>
|
||||
#include <soc_supc.h>
|
||||
#include <cmsis_core.h>
|
||||
#include <zephyr/logging/log.h>
|
||||
|
||||
#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
|
||||
LOG_MODULE_REGISTER(soc);
|
||||
|
||||
/**
|
||||
* @brief Setup various clocks on SoC at boot time.
|
||||
*
|
||||
* Setup Slow, Main, PLLA, Processor and Master clocks during the device boot.
|
||||
* It is assumed that the relevant registers are at their reset value.
|
||||
*/
|
||||
static ALWAYS_INLINE void clock_init(void)
|
||||
{
|
||||
/* Switch the main clock to the internal OSC with 12MHz */
|
||||
soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ);
|
||||
|
||||
/* Switch MCK (Master Clock) to the main clock */
|
||||
soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK);
|
||||
|
||||
EFC->EEFC_FMR = EEFC_FMR_FWS(0) | EEFC_FMR_CLOE;
|
||||
|
||||
soc_pmc_enable_clock_failure_detector();
|
||||
|
||||
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) {
|
||||
soc_supc_slow_clock_select_crystal_osc();
|
||||
}
|
||||
|
||||
|
||||
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
|
||||
/*
|
||||
* Setup main external crystal oscillator.
|
||||
*/
|
||||
|
||||
/* We select maximum setup time.
|
||||
* While start up time could be shortened
|
||||
* this optimization is not deemed
|
||||
* critical now.
|
||||
*/
|
||||
soc_pmc_switch_mainck_to_xtal(false, 0xff);
|
||||
}
|
||||
|
||||
/*
|
||||
* Set FWS (Flash Wait State) value before increasing Master Clock
|
||||
* (MCK) frequency.
|
||||
* TODO: set FWS based on the actual MCK frequency and VDDIO value
|
||||
* rather than maximum supported 150 MHz at standard VDDIO=2.7V
|
||||
*/
|
||||
EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE;
|
||||
|
||||
/*
|
||||
* Setup PLLA
|
||||
*/
|
||||
|
||||
/*
|
||||
* PLL clock = Main * (MULA + 1) / DIVA
|
||||
*
|
||||
* By default, MULA == 24, DIVA == 1.
|
||||
* With main crystal running at 12 MHz,
|
||||
* PLL = 12 * (24 + 1) / 1 = 300 MHz
|
||||
*
|
||||
* With Processor Clock prescaler at 1
|
||||
* Processor Clock (HCLK)=300 MHz.
|
||||
*/
|
||||
soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu,
|
||||
CONFIG_SOC_ATMEL_SAM_PLLA_DIVA);
|
||||
|
||||
|
||||
soc_pmc_enable_upllck(0x3Fu);
|
||||
|
||||
/*
|
||||
* Final setup of the Master Clock
|
||||
*/
|
||||
|
||||
/* Setting PLLA as MCK, first prescaler, then divider and source last */
|
||||
soc_pmc_mck_set_prescaler(1);
|
||||
soc_pmc_mck_set_divider(CONFIG_SOC_ATMEL_SAM_MDIV);
|
||||
soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK);
|
||||
|
||||
|
||||
/* Disable internal fast RC if we have an external crystal oscillator */
|
||||
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
|
||||
soc_pmc_osc_disable_fastrc();
|
||||
}
|
||||
}
|
||||
|
||||
void z_arm_platform_init(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
|
||||
/*
|
||||
* Instruct CPU to enter Wait mode instead of Sleep mode to
|
||||
* keep Processor Clock (HCLK) and thus be able to debug
|
||||
* CPU using JTAG.
|
||||
*/
|
||||
soc_pmc_enable_waitmode();
|
||||
}
|
||||
|
||||
/*
|
||||
* DTCM is enabled by default at reset, therefore we have to disable
|
||||
* it first to get the caches into a state where then the
|
||||
* sys_cache*-functions can enable them, if requested by the
|
||||
* configuration.
|
||||
*/
|
||||
SCB_DisableDCache();
|
||||
|
||||
/*
|
||||
* Enable the caches only if configured to do so.
|
||||
*/
|
||||
sys_cache_instr_enable();
|
||||
sys_cache_data_enable();
|
||||
|
||||
/* Setup system clocks */
|
||||
clock_init();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Perform basic hardware initialization at boot.
|
||||
*
|
||||
* This needs to be run at the very beginning.
|
||||
* So the init priority has to be 0 (zero).
|
||||
*
|
||||
* @return 0
|
||||
*/
|
||||
static int atmel_same70_init(void)
|
||||
{
|
||||
/* Check that the CHIP CIDR matches the HAL one */
|
||||
if (CHIPID->CHIPID_CIDR != CHIP_CIDR) {
|
||||
LOG_WRN("CIDR mismatch: chip = 0x%08x vs HAL = 0x%08x",
|
||||
(uint32_t)CHIPID->CHIPID_CIDR, (uint32_t)CHIP_CIDR);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(atmel_same70_init, PRE_KERNEL_1, 0);
|
||||
82
soc/atmel/sam/same70/soc.h
Normal file
82
soc/atmel/sam/same70/soc.h
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Piotr Mienkowski
|
||||
* Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/** @file
|
||||
* @brief Register access macros for the Atmel SAM E70 MCU.
|
||||
*
|
||||
* This file provides register access macros for the Atmel SAM E70 MCU, HAL
|
||||
* drivers for core peripherals as well as symbols specific to Atmel SAM family.
|
||||
*/
|
||||
|
||||
#ifndef _SOC_ATMEL_SAM_SAME70_SOC_H_
|
||||
#define _SOC_ATMEL_SAM_SAME70_SOC_H_
|
||||
|
||||
#include <zephyr/sys/util.h>
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#define DONT_USE_CMSIS_INIT
|
||||
#define DONT_USE_PREDEFINED_CORE_HANDLERS
|
||||
#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
|
||||
|
||||
#if defined(CONFIG_SOC_SAME70J19)
|
||||
#include <same70j19.h>
|
||||
#elif defined(CONFIG_SOC_SAME70J20)
|
||||
#include <same70j20.h>
|
||||
#elif defined(CONFIG_SOC_SAME70J21)
|
||||
#include <same70j21.h>
|
||||
#elif defined(CONFIG_SOC_SAME70N19)
|
||||
#include <same70n19.h>
|
||||
#elif defined(CONFIG_SOC_SAME70N20)
|
||||
#include <same70n20.h>
|
||||
#elif defined(CONFIG_SOC_SAME70N21)
|
||||
#include <same70n21.h>
|
||||
#elif defined(CONFIG_SOC_SAME70Q19)
|
||||
#include <same70q19.h>
|
||||
#elif defined(CONFIG_SOC_SAME70Q20)
|
||||
#include <same70q20.h>
|
||||
#elif defined(CONFIG_SOC_SAME70Q21)
|
||||
#include <same70q21.h>
|
||||
#elif defined(CONFIG_SOC_SAME70J19B)
|
||||
#include <same70j19b.h>
|
||||
#elif defined(CONFIG_SOC_SAME70J20B)
|
||||
#include <same70j20b.h>
|
||||
#elif defined(CONFIG_SOC_SAME70J21B)
|
||||
#include <same70j21b.h>
|
||||
#elif defined(CONFIG_SOC_SAME70N19B)
|
||||
#include <same70n19b.h>
|
||||
#elif defined(CONFIG_SOC_SAME70N20B)
|
||||
#include <same70n20b.h>
|
||||
#elif defined(CONFIG_SOC_SAME70N21B)
|
||||
#include <same70n21b.h>
|
||||
#elif defined(CONFIG_SOC_SAME70Q19B)
|
||||
#include <same70q19b.h>
|
||||
#elif defined(CONFIG_SOC_SAME70Q20B)
|
||||
#include <same70q20b.h>
|
||||
#elif defined(CONFIG_SOC_SAME70Q21B)
|
||||
#include <same70q21b.h>
|
||||
#else
|
||||
#error Library does not support the specified device.
|
||||
#endif
|
||||
|
||||
#include "../common/soc_pmc.h"
|
||||
#include "../common/soc_gpio.h"
|
||||
#include "../common/soc_supc.h"
|
||||
#include "../common/atmel_sam_dt.h"
|
||||
|
||||
/** Processor Clock (HCLK) Frequency */
|
||||
#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ
|
||||
|
||||
/** Master Clock (MCK) Frequency */
|
||||
#define SOC_ATMEL_SAM_MCK_FREQ_HZ \
|
||||
(SOC_ATMEL_SAM_HCLK_FREQ_HZ / CONFIG_SOC_ATMEL_SAM_MDIV)
|
||||
|
||||
/** UTMI PLL clock (UPLLCK) Frequency */
|
||||
#define SOC_ATMEL_SAM_UPLLCK_FREQ_HZ MHZ(480)
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#endif /* _SOC_ATMEL_SAM_SAME70_SOC_H_ */
|
||||
65
soc/atmel/sam/same70/soc_config.c
Normal file
65
soc/atmel/sam/same70/soc_config.c
Normal file
|
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Piotr Mienkowski
|
||||
* Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/** @file
|
||||
* @brief System module to support early Atmel SAM E70 MCU configuration
|
||||
*/
|
||||
|
||||
#include <zephyr/device.h>
|
||||
#include <zephyr/init.h>
|
||||
#include <soc.h>
|
||||
#include <zephyr/arch/cpu.h>
|
||||
|
||||
/**
|
||||
* @brief Perform SoC configuration at boot.
|
||||
*
|
||||
* This should be run early during the boot process but after basic hardware
|
||||
* initialization is done.
|
||||
*
|
||||
* @return 0
|
||||
*/
|
||||
static int atmel_same70_config(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_DISABLE_ERASE_PIN)) {
|
||||
/* Disable ERASE function on PB12 pin, this is controlled
|
||||
* by Bus Matrix
|
||||
*/
|
||||
MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12;
|
||||
}
|
||||
|
||||
/* In Cortex-M based SoCs JTAG interface can be used to perform
|
||||
* IEEE1149.1 JTAG Boundary scan only. It can not be used as a debug
|
||||
* interface therefore there is no harm done by disabling the JTAG TDI
|
||||
* pin by default.
|
||||
*/
|
||||
/* Disable TDI function on PB4 pin, this is controlled by Bus Matrix */
|
||||
MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4;
|
||||
|
||||
if (IS_ENABLED(CONFIG_LOG_BACKEND_SWO)) {
|
||||
/* Disable PCK3 clock used by ETM module */
|
||||
PMC->PMC_SCDR = PMC_SCDR_PCK3;
|
||||
while ((PMC->PMC_SCSR) & PMC_SCSR_PCK3) {
|
||||
;
|
||||
}
|
||||
/* Select PLLA clock as PCK3 clock */
|
||||
PMC->PMC_PCK[3] = PMC_MCKR_CSS_PLLA_CLK;
|
||||
/* Enable PCK3 clock */
|
||||
PMC->PMC_SCER = PMC_SCER_PCK3;
|
||||
/* Wait for PCK3 setup to complete */
|
||||
while (!((PMC->PMC_SR) & PMC_SR_PCKRDY3)) {
|
||||
;
|
||||
}
|
||||
/* Enable TDO/TRACESWO function on PB5 pin */
|
||||
MATRIX->CCFG_SYSIO &= ~CCFG_SYSIO_SYSIO5;
|
||||
} else {
|
||||
/* Disable TDO/TRACESWO function on PB5 pin */
|
||||
MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO5;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(atmel_same70_config, PRE_KERNEL_1, 1);
|
||||
11
soc/atmel/sam/samv71/CMakeLists.txt
Normal file
11
soc/atmel/sam/samv71/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_include_directories(.)
|
||||
|
||||
zephyr_sources(
|
||||
soc.c
|
||||
soc_config.c
|
||||
)
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
|
||||
19
soc/atmel/sam/samv71/Kconfig
Normal file
19
soc/atmel/sam/samv71/Kconfig
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
# Atmel SAM V71 MCU series
|
||||
|
||||
# Copyright (c) 2016 Piotr Mienkowski
|
||||
# Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_SAMV71
|
||||
select ARM
|
||||
select CPU_CORTEX_M7
|
||||
select CPU_CORTEX_M_HAS_DWT
|
||||
select CPU_HAS_ARM_MPU
|
||||
select CPU_HAS_FPU_DOUBLE_PRECISION
|
||||
select CPU_HAS_ICACHE
|
||||
select CPU_HAS_DCACHE
|
||||
select INIT_ARCH_HW_AT_BOOT
|
||||
select PLATFORM_SPECIFIC_INIT
|
||||
select HAS_SWO
|
||||
select XIP
|
||||
select HAS_POWEROFF
|
||||
13
soc/atmel/sam/samv71/Kconfig.defconfig
Normal file
13
soc/atmel/sam/samv71/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
# Atmel SAM V71 MCU series configuration options
|
||||
|
||||
# Copyright (c) 2016 Piotr Mienkowski
|
||||
# Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_SAMV71
|
||||
|
||||
config NUM_IRQS
|
||||
default 74 if SOC_ATMEL_SAMV71_REVB
|
||||
default 71
|
||||
|
||||
endif # SOC_SERIES_SAMV71
|
||||
122
soc/atmel/sam/samv71/Kconfig.soc
Normal file
122
soc/atmel/sam/samv71/Kconfig.soc
Normal file
|
|
@ -0,0 +1,122 @@
|
|||
# Atmel SAM V71 MCU series
|
||||
|
||||
# Copyright (c) 2016 Piotr Mienkowski
|
||||
# Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_SAMV71
|
||||
bool
|
||||
select SOC_FAMILY_ATMEL_SAM
|
||||
help
|
||||
Enable support for Atmel SAM V71 ARM Cortex-M7 Microcontrollers.
|
||||
Part No.: SAMV71J19, SAMV71J20, SAMV71J21, SAMV71N19, SAMV71N20,
|
||||
SAMV71N21, SAMV71Q19, SAMV71Q20, SAMV71Q21, SAMV71J19B, SAMV71J20B,
|
||||
SAMV71J21B, SAMV71N19B, SAMV71N20B, SAMV71N21B, SAMV71Q19B,
|
||||
SAMV71Q20B, SAMV71Q21B
|
||||
|
||||
config SOC_ATMEL_SAMV71_REVB
|
||||
bool
|
||||
|
||||
config SOC_SERIES
|
||||
default "samv71" if SOC_SERIES_SAMV71
|
||||
|
||||
config SOC_SAMV71J19
|
||||
bool
|
||||
select SOC_SERIES_SAMV71
|
||||
|
||||
config SOC_SAMV71J20
|
||||
bool
|
||||
select SOC_SERIES_SAMV71
|
||||
|
||||
config SOC_SAMV71J21
|
||||
bool
|
||||
select SOC_SERIES_SAMV71
|
||||
|
||||
config SOC_SAMV71N19
|
||||
bool
|
||||
select SOC_SERIES_SAMV71
|
||||
|
||||
config SOC_SAMV71N20
|
||||
bool
|
||||
select SOC_SERIES_SAMV71
|
||||
|
||||
config SOC_SAMV71N21
|
||||
bool
|
||||
select SOC_SERIES_SAMV71
|
||||
|
||||
config SOC_SAMV71Q19
|
||||
bool
|
||||
select SOC_SERIES_SAMV71
|
||||
|
||||
config SOC_SAMV71Q20
|
||||
bool
|
||||
select SOC_SERIES_SAMV71
|
||||
|
||||
config SOC_SAMV71Q21
|
||||
bool
|
||||
select SOC_SERIES_SAMV71
|
||||
|
||||
config SOC_SAMV71J19B
|
||||
bool
|
||||
select SOC_SERIES_SAMV71
|
||||
select SOC_ATMEL_SAMV71_REVB
|
||||
|
||||
config SOC_SAMV71J20B
|
||||
bool
|
||||
select SOC_SERIES_SAMV71
|
||||
select SOC_ATMEL_SAMV71_REVB
|
||||
|
||||
config SOC_SAMV71J21B
|
||||
bool
|
||||
select SOC_SERIES_SAMV71
|
||||
select SOC_ATMEL_SAMV71_REVB
|
||||
|
||||
config SOC_SAMV71N19B
|
||||
bool
|
||||
select SOC_SERIES_SAMV71
|
||||
select SOC_ATMEL_SAMV71_REVB
|
||||
|
||||
config SOC_SAMV71N20B
|
||||
bool
|
||||
select SOC_SERIES_SAMV71
|
||||
select SOC_ATMEL_SAMV71_REVB
|
||||
|
||||
config SOC_SAMV71N21B
|
||||
bool
|
||||
select SOC_SERIES_SAMV71
|
||||
select SOC_ATMEL_SAMV71_REVB
|
||||
|
||||
config SOC_SAMV71Q19B
|
||||
bool
|
||||
select SOC_SERIES_SAMV71
|
||||
select SOC_ATMEL_SAMV71_REVB
|
||||
|
||||
config SOC_SAMV71Q20B
|
||||
bool
|
||||
select SOC_SERIES_SAMV71
|
||||
select SOC_ATMEL_SAMV71_REVB
|
||||
|
||||
config SOC_SAMV71Q21B
|
||||
bool
|
||||
select SOC_SERIES_SAMV71
|
||||
select SOC_ATMEL_SAMV71_REVB
|
||||
|
||||
config SOC
|
||||
default "samv71j19" if SOC_SAMV71J19
|
||||
default "samv71j20" if SOC_SAMV71J20
|
||||
default "samv71j21" if SOC_SAMV71J21
|
||||
default "samv71n19" if SOC_SAMV71N19
|
||||
default "samv71n20" if SOC_SAMV71N20
|
||||
default "samv71n21" if SOC_SAMV71N21
|
||||
default "samv71q19" if SOC_SAMV71Q19
|
||||
default "samv71q20" if SOC_SAMV71Q20
|
||||
default "samv71q21" if SOC_SAMV71Q21
|
||||
default "samv71j19b" if SOC_SAMV71J19B
|
||||
default "samv71j20b" if SOC_SAMV71J20B
|
||||
default "samv71j21b" if SOC_SAMV71J21B
|
||||
default "samv71n19b" if SOC_SAMV71N19B
|
||||
default "samv71n20b" if SOC_SAMV71N20B
|
||||
default "samv71n21b" if SOC_SAMV71N21B
|
||||
default "samv71q19b" if SOC_SAMV71Q19B
|
||||
default "samv71q20b" if SOC_SAMV71Q20B
|
||||
default "samv71q21b" if SOC_SAMV71Q21B
|
||||
153
soc/atmel/sam/samv71/soc.c
Normal file
153
soc/atmel/sam/samv71/soc.c
Normal file
|
|
@ -0,0 +1,153 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Piotr Mienkowski
|
||||
* Copyright (c) 2019-2023 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/** @file
|
||||
* @brief Atmel SAM V71 MCU initialization code
|
||||
*
|
||||
* This file provides routines to initialize and support board-level hardware
|
||||
* for the Atmel SAM V71 MCU.
|
||||
*/
|
||||
|
||||
#include <zephyr/kernel.h>
|
||||
#include <zephyr/device.h>
|
||||
#include <zephyr/init.h>
|
||||
#include <zephyr/cache.h>
|
||||
#include <zephyr/arch/cache.h>
|
||||
#include <soc.h>
|
||||
#include <cmsis_core.h>
|
||||
#include <zephyr/logging/log.h>
|
||||
|
||||
#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
|
||||
LOG_MODULE_REGISTER(soc);
|
||||
|
||||
/**
|
||||
* @brief Setup various clocks on SoC at boot time.
|
||||
*
|
||||
* Setup Slow, Main, PLLA, Processor and Master clocks during the device boot.
|
||||
* It is assumed that the relevant registers are at their reset value.
|
||||
*/
|
||||
static ALWAYS_INLINE void clock_init(void)
|
||||
{
|
||||
/* Switch the main clock to the internal OSC with 12MHz */
|
||||
soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ);
|
||||
|
||||
/* Switch MCK (Master Clock) to the main clock */
|
||||
soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK);
|
||||
|
||||
EFC->EEFC_FMR = EEFC_FMR_FWS(0) | EEFC_FMR_CLOE;
|
||||
|
||||
soc_pmc_enable_clock_failure_detector();
|
||||
|
||||
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) {
|
||||
soc_supc_slow_clock_select_crystal_osc();
|
||||
}
|
||||
|
||||
|
||||
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
|
||||
/*
|
||||
* Setup main external crystal oscillator.
|
||||
*/
|
||||
|
||||
/* We select maximum setup time.
|
||||
* While start up time could be shortened
|
||||
* this optimization is not deemed
|
||||
* critical now.
|
||||
*/
|
||||
soc_pmc_switch_mainck_to_xtal(false, 0xff);
|
||||
}
|
||||
|
||||
/*
|
||||
* Set FWS (Flash Wait State) value before increasing Master Clock
|
||||
* (MCK) frequency.
|
||||
* TODO: set FWS based on the actual MCK frequency and VDDIO value
|
||||
* rather than maximum supported 150 MHz at standard VDDIO=2.7V
|
||||
*/
|
||||
EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE;
|
||||
|
||||
/*
|
||||
* Setup PLLA
|
||||
*/
|
||||
|
||||
/*
|
||||
* PLL clock = Main * (MULA + 1) / DIVA
|
||||
*
|
||||
* By default, MULA == 24, DIVA == 1.
|
||||
* With main crystal running at 12 MHz,
|
||||
* PLL = 12 * (24 + 1) / 1 = 300 MHz
|
||||
*
|
||||
* With Processor Clock prescaler at 1
|
||||
* Processor Clock (HCLK)=300 MHz.
|
||||
*/
|
||||
soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu,
|
||||
CONFIG_SOC_ATMEL_SAM_PLLA_DIVA);
|
||||
|
||||
|
||||
soc_pmc_enable_upllck(0x3Fu);
|
||||
|
||||
/*
|
||||
* Final setup of the Master Clock
|
||||
*/
|
||||
|
||||
/* Setting PLLA as MCK, first prescaler, then divider and source last */
|
||||
soc_pmc_mck_set_prescaler(1);
|
||||
soc_pmc_mck_set_divider(CONFIG_SOC_ATMEL_SAM_MDIV);
|
||||
soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK);
|
||||
|
||||
/* Disable internal fast RC if we have an external crystal oscillator */
|
||||
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
|
||||
soc_pmc_osc_disable_fastrc();
|
||||
}
|
||||
}
|
||||
|
||||
void z_arm_platform_init(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
|
||||
/*
|
||||
* Instruct CPU to enter Wait mode instead of Sleep mode to
|
||||
* keep Processor Clock (HCLK) and thus be able to debug
|
||||
* CPU using JTAG.
|
||||
*/
|
||||
soc_pmc_enable_waitmode();
|
||||
}
|
||||
|
||||
/*
|
||||
* DTCM is enabled by default at reset, therefore we have to disable
|
||||
* it first to get the caches into a state where then the
|
||||
* sys_cache*-functions can enable them, if requested by the
|
||||
* configuration.
|
||||
*/
|
||||
SCB_DisableDCache();
|
||||
|
||||
/*
|
||||
* Enable the caches only if configured to do so.
|
||||
*/
|
||||
sys_cache_instr_enable();
|
||||
sys_cache_data_enable();
|
||||
|
||||
/* Setup system clocks */
|
||||
clock_init();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Perform basic hardware initialization at boot.
|
||||
*
|
||||
* This needs to be run at the very beginning.
|
||||
* So the init priority has to be 0 (zero).
|
||||
*
|
||||
* @return 0
|
||||
*/
|
||||
static int atmel_samv71_init(void)
|
||||
{
|
||||
/* Check that the CHIP CIDR matches the HAL one */
|
||||
if (CHIPID->CHIPID_CIDR != CHIP_CIDR) {
|
||||
LOG_WRN("CIDR mismatch: chip = 0x%08x vs HAL = 0x%08x",
|
||||
(uint32_t)CHIPID->CHIPID_CIDR, (uint32_t)CHIP_CIDR);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(atmel_samv71_init, PRE_KERNEL_1, 0);
|
||||
84
soc/atmel/sam/samv71/soc.h
Normal file
84
soc/atmel/sam/samv71/soc.h
Normal file
|
|
@ -0,0 +1,84 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Piotr Mienkowski
|
||||
* Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/** @file
|
||||
* @brief Register access macros for the Atmel SAM V71 MCU.
|
||||
*
|
||||
* This file provides register access macros for the Atmel SAM V71 MCU, HAL
|
||||
* drivers for core peripherals as well as symbols specific to Atmel SAM family.
|
||||
*/
|
||||
|
||||
#ifndef _SOC_ATMEL_SAM_SAMV71_SOC_H_
|
||||
#define _SOC_ATMEL_SAM_SAMV71_SOC_H_
|
||||
|
||||
#include <zephyr/sys/util.h>
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#define DONT_USE_CMSIS_INIT
|
||||
#define DONT_USE_PREDEFINED_CORE_HANDLERS
|
||||
#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
|
||||
|
||||
#if defined(CONFIG_SOC_SAMV71J19)
|
||||
#include <samv71j19.h>
|
||||
#elif defined(CONFIG_SOC_SAMV71J20)
|
||||
#include <samv71j20.h>
|
||||
#elif defined(CONFIG_SOC_SAMV71J21)
|
||||
#include <samv71j21.h>
|
||||
#elif defined(CONFIG_SOC_SAMV71N19)
|
||||
#include <samv71n19.h>
|
||||
#elif defined(CONFIG_SOC_SAMV71N20)
|
||||
#include <samv71n20.h>
|
||||
#elif defined(CONFIG_SOC_SAMV71N21)
|
||||
#include <samv71n21.h>
|
||||
#elif defined(CONFIG_SOC_SAMV71Q19)
|
||||
#include <samv71q19.h>
|
||||
#elif defined(CONFIG_SOC_SAMV71Q20)
|
||||
#include <samv71q20.h>
|
||||
#elif defined(CONFIG_SOC_SAMV71Q21)
|
||||
#include <samv71q21.h>
|
||||
#elif defined(CONFIG_SOC_SAMV71J19B)
|
||||
#include <samv71j19b.h>
|
||||
#elif defined(CONFIG_SOC_SAMV71J20B)
|
||||
#include <samv71j20b.h>
|
||||
#elif defined(CONFIG_SOC_SAMV71J21B)
|
||||
#include <samv71j21b.h>
|
||||
#elif defined(CONFIG_SOC_SAMV71N19B)
|
||||
#include <samv71n19b.h>
|
||||
#elif defined(CONFIG_SOC_SAMV71N20B)
|
||||
#include <samv71n20b.h>
|
||||
#elif defined(CONFIG_SOC_SAMV71N21B)
|
||||
#include <samv71n21b.h>
|
||||
#elif defined(CONFIG_SOC_SAMV71Q19B)
|
||||
#include <samv71q19b.h>
|
||||
#elif defined(CONFIG_SOC_SAMV71Q20B)
|
||||
#include <samv71q20b.h>
|
||||
#elif defined(CONFIG_SOC_SAMV71Q21B)
|
||||
#include <samv71q21b.h>
|
||||
#else
|
||||
#error Library does not support the specified device.
|
||||
#endif
|
||||
|
||||
#include "../common/soc_pmc.h"
|
||||
#include "../common/soc_gpio.h"
|
||||
#include "../common/soc_supc.h"
|
||||
#include "../common/atmel_sam_dt.h"
|
||||
|
||||
/** Processor Clock (HCLK) Frequency */
|
||||
#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ
|
||||
|
||||
/** Master Clock (MCK) Frequency */
|
||||
#define SOC_ATMEL_SAM_MCK_FREQ_HZ \
|
||||
(SOC_ATMEL_SAM_HCLK_FREQ_HZ / CONFIG_SOC_ATMEL_SAM_MDIV)
|
||||
|
||||
/** UTMI PLL clock (UPLLCK) Frequency */
|
||||
#define SOC_ATMEL_SAM_UPLLCK_FREQ_HZ MHZ(480)
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#include "pwm_fixup.h"
|
||||
|
||||
#endif /* _SOC_ATMEL_SAM_SAMV71_SOC_H_ */
|
||||
66
soc/atmel/sam/samv71/soc_config.c
Normal file
66
soc/atmel/sam/samv71/soc_config.c
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Piotr Mienkowski
|
||||
* Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/** @file
|
||||
* @brief System module to support early Atmel SAM V71 MCU configuration
|
||||
*/
|
||||
|
||||
#include <zephyr/device.h>
|
||||
#include <zephyr/init.h>
|
||||
#include <soc.h>
|
||||
#include <zephyr/arch/cpu.h>
|
||||
|
||||
/**
|
||||
* @brief Perform SoC configuration at boot.
|
||||
*
|
||||
* This should be run early during the boot process but after basic hardware
|
||||
* initialization is done.
|
||||
*
|
||||
* @return 0
|
||||
*/
|
||||
static int atmel_samv71_config(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_DISABLE_ERASE_PIN)) {
|
||||
/* Disable ERASE function on PB12 pin, this is controlled
|
||||
* by Bus Matrix
|
||||
*/
|
||||
MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12;
|
||||
}
|
||||
|
||||
/* In Cortex-M based SoCs JTAG interface can be used to perform
|
||||
* IEEE1149.1 JTAG Boundary scan only. It can not be used as a debug
|
||||
* interface therefore there is no harm done by disabling the JTAG TDI
|
||||
* pin by default.
|
||||
*/
|
||||
/* Disable TDI function on PB4 pin, this is controlled by Bus Matrix
|
||||
*/
|
||||
MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4;
|
||||
|
||||
if (IS_ENABLED(CONFIG_LOG_BACKEND_SWO)) {
|
||||
/* Disable PCK3 clock used by ETM module */
|
||||
PMC->PMC_SCDR = PMC_SCDR_PCK3;
|
||||
while ((PMC->PMC_SCSR) & PMC_SCSR_PCK3) {
|
||||
;
|
||||
}
|
||||
/* Select PLLA clock as PCK3 clock */
|
||||
PMC->PMC_PCK[3] = PMC_MCKR_CSS_PLLA_CLK;
|
||||
/* Enable PCK3 clock */
|
||||
PMC->PMC_SCER = PMC_SCER_PCK3;
|
||||
/* Wait for PCK3 setup to complete */
|
||||
while (!((PMC->PMC_SR) & PMC_SR_PCKRDY3)) {
|
||||
;
|
||||
}
|
||||
/* Enable TDO/TRACESWO function on PB5 pin */
|
||||
MATRIX->CCFG_SYSIO &= ~CCFG_SYSIO_SYSIO5;
|
||||
} else {
|
||||
/* Disable TDO/TRACESWO function on PB5 pin */
|
||||
MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO5;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(atmel_samv71_config, PRE_KERNEL_1, 1);
|
||||
89
soc/atmel/sam/soc.yml
Normal file
89
soc/atmel/sam/soc.yml
Normal file
|
|
@ -0,0 +1,89 @@
|
|||
family:
|
||||
- name: atmel_sam
|
||||
series:
|
||||
- name: sam3x
|
||||
socs:
|
||||
- name: sam3x4c
|
||||
- name: sam3x4e
|
||||
- name: sam3x8c
|
||||
- name: sam3x8e
|
||||
- name: sam3x8h
|
||||
- name: sam4e
|
||||
socs:
|
||||
- name: sam4e8c
|
||||
- name: sam4e8e
|
||||
- name: sam4e16c
|
||||
- name: sam4e16e
|
||||
- name: sam4l
|
||||
socs:
|
||||
- name: sam4ls2a
|
||||
- name: sam4ls2b
|
||||
- name: sam4ls2c
|
||||
- name: sam4ls4a
|
||||
- name: sam4ls4b
|
||||
- name: sam4ls4c
|
||||
- name: sam4ls8a
|
||||
- name: sam4ls8b
|
||||
- name: sam4ls8c
|
||||
- name: sam4lc2a
|
||||
- name: sam4lc2b
|
||||
- name: sam4lc2c
|
||||
- name: sam4lc4a
|
||||
- name: sam4lc4b
|
||||
- name: sam4lc4c
|
||||
- name: sam4lc8a
|
||||
- name: sam4lc8b
|
||||
- name: sam4lc8c
|
||||
- name: sam4s
|
||||
socs:
|
||||
- name: sam4s2a
|
||||
- name: sam4s2b
|
||||
- name: sam4s2c
|
||||
- name: sam4s4a
|
||||
- name: sam4s4b
|
||||
- name: sam4s4c
|
||||
- name: sam4s8b
|
||||
- name: sam4s8c
|
||||
- name: sam4s16b
|
||||
- name: sam4s16c
|
||||
- name: sam4sa16c
|
||||
- name: same70
|
||||
socs:
|
||||
- name: same70j19
|
||||
- name: same70j20
|
||||
- name: same70j21
|
||||
- name: same70n19
|
||||
- name: same70n20
|
||||
- name: same70n21
|
||||
- name: same70q19
|
||||
- name: same70q20
|
||||
- name: same70q21
|
||||
- name: same70j19b
|
||||
- name: same70j20b
|
||||
- name: same70j21b
|
||||
- name: same70n19b
|
||||
- name: same70n20b
|
||||
- name: same70n21b
|
||||
- name: same70q19b
|
||||
- name: same70q20b
|
||||
- name: same70q21b
|
||||
- name: samv71
|
||||
socs:
|
||||
- name: samv71j19
|
||||
- name: samv71j20
|
||||
- name: samv71j21
|
||||
- name: samv71n19
|
||||
- name: samv71n20
|
||||
- name: samv71n21
|
||||
- name: samv71q19
|
||||
- name: samv71q20
|
||||
- name: samv71q21
|
||||
- name: samv71j19b
|
||||
- name: samv71j20b
|
||||
- name: samv71j21b
|
||||
- name: samv71n19b
|
||||
- name: samv71n20b
|
||||
- name: samv71n21b
|
||||
- name: samv71q19b
|
||||
- name: samv71q20b
|
||||
- name: samv71q21b
|
||||
10
soc/atmel/sam0/CMakeLists.txt
Normal file
10
soc/atmel/sam0/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
# Makefile - Atmel SAM0 MCU family
|
||||
#
|
||||
# Copyright (c) 2017 Google LLC.
|
||||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_include_directories(${ZEPHYR_BASE}/drivers)
|
||||
|
||||
add_subdirectory(common)
|
||||
add_subdirectory(${SOC_SERIES})
|
||||
16
soc/atmel/sam0/Kconfig
Normal file
16
soc/atmel/sam0/Kconfig
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
# Atmel SAM0 MCU family configuration options
|
||||
|
||||
# Copyright (c) 2017 Google LLC.
|
||||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_FAMILY_ATMEL_SAM0
|
||||
select ASF
|
||||
select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
|
||||
|
||||
if SOC_FAMILY_ATMEL_SAM0
|
||||
|
||||
rsource "common/Kconfig.sam*"
|
||||
rsource "*/Kconfig"
|
||||
|
||||
endif # SOC_FAMILY_ATMEL_SAM0
|
||||
30
soc/atmel/sam0/Kconfig.defconfig
Normal file
30
soc/atmel/sam0/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
# Atmel SAM0 MCU family default configuration options
|
||||
|
||||
# Copyright (c) 2017 Google LLC.
|
||||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_FAMILY_ATMEL_SAM0
|
||||
|
||||
rsource "*/Kconfig.defconfig"
|
||||
|
||||
config GPIO
|
||||
default y
|
||||
|
||||
config HWINFO_SAM0
|
||||
default HWINFO
|
||||
|
||||
config PINCTRL
|
||||
default y
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
|
||||
|
||||
if USB_DEVICE_DRIVER
|
||||
|
||||
config HEAP_MEM_POOL_ADD_SIZE_SOC
|
||||
def_int 1024
|
||||
|
||||
endif # USB_DEVICE_DRIVER
|
||||
|
||||
endif # SOC_FAMILY_ATMEL_SAM0
|
||||
21
soc/atmel/sam0/Kconfig.soc
Normal file
21
soc/atmel/sam0/Kconfig.soc
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
# Copyright (c) 2017 Google LLC.
|
||||
# Copyright (c) 2022-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_FAMILY_ATMEL_SAM0
|
||||
bool
|
||||
|
||||
config SOC_FAMILY
|
||||
default "atmel_sam0" if SOC_FAMILY_ATMEL_SAM0
|
||||
|
||||
config SOC_SERIES_REVISION_N
|
||||
bool
|
||||
depends on SOC_FAMILY_ATMEL_SAM0
|
||||
|
||||
config SOC_SERIES_REVISION
|
||||
string
|
||||
default "n" if SOC_SERIES_REVISION_N
|
||||
default ""
|
||||
depends on SOC_FAMILY_ATMEL_SAM0
|
||||
|
||||
rsource "*/Kconfig.soc"
|
||||
27
soc/atmel/sam0/common/CMakeLists.txt
Normal file
27
soc/atmel/sam0/common/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
# Makefile - Atmel SAM0 MCU family
|
||||
#
|
||||
# Copyright (c) 2019 ML!PA Consulting GmbH
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_sources(soc_port.c)
|
||||
|
||||
zephyr_sources_ifdef(CONFIG_BOOTLOADER_BOSSA bossa.c)
|
||||
|
||||
zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMC20 soc_samc2x.c)
|
||||
zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMC21 soc_samc2x.c)
|
||||
zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMD20 soc_samd2x.c)
|
||||
zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMD21 soc_samd2x.c)
|
||||
zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMR21 soc_samd2x.c)
|
||||
zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAML21 soc_saml2x.c)
|
||||
zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMR34 soc_saml2x.c)
|
||||
zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMR35 soc_saml2x.c)
|
||||
zephyr_sources_ifdef(CONFIG_SOC_ATMEL_SAMR3X_RADIO_OFF_SETUP soc_samr3x_radio_off.c)
|
||||
|
||||
zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMD51 soc_samd5x.c)
|
||||
zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAME51 soc_samd5x.c)
|
||||
zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAME53 soc_samd5x.c)
|
||||
zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAME54 soc_samd5x.c)
|
||||
|
||||
zephyr_include_directories(.)
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
|
||||
92
soc/atmel/sam0/common/Kconfig.samd2x
Normal file
92
soc/atmel/sam0/common/Kconfig.samd2x
Normal file
|
|
@ -0,0 +1,92 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_SAMD20 || SOC_SERIES_SAMD21 || SOC_SERIES_SAMR21
|
||||
|
||||
config SOC_ATMEL_SAMD_NVM_WAIT_STATES
|
||||
int "NVM wait states"
|
||||
default 1
|
||||
help
|
||||
Wait states to set for NVM. Consult the datasheet as these are highly
|
||||
dependent on the device operationg conditions.
|
||||
|
||||
config SOC_ATMEL_SAMD_OSC32K
|
||||
bool "Internal 32.768 kHz RC oscillator"
|
||||
help
|
||||
Enable the internal 32.768 kHz RC oscillator at startup.
|
||||
This can then be selected as the main clock reference for the SOC.
|
||||
|
||||
config SOC_ATMEL_SAMD_OSC8M
|
||||
bool "Internal 8 MHz RC oscillator"
|
||||
help
|
||||
Enable the internal 8 MHz RC oscillator at startup.
|
||||
This can then be selected as the main clock reference for the SOC.
|
||||
|
||||
config SOC_ATMEL_SAMD_XOSC32K
|
||||
bool "External 32.768 kHz clock source"
|
||||
help
|
||||
Enable the external 32.768 kHz clock source at startup.
|
||||
This can then be selected as the main clock reference for the SOC.
|
||||
|
||||
config SOC_ATMEL_SAMD_XOSC32K_CRYSTAL
|
||||
bool "External 32.768 kHz clock is a crystal oscillator"
|
||||
depends on SOC_ATMEL_SAMD_XOSC32K
|
||||
default y
|
||||
help
|
||||
Enable the crystal oscillator (if disabled, expect a clock signal on
|
||||
XIN32).
|
||||
|
||||
config SOC_ATMEL_SAMD_XOSC
|
||||
bool "External 0.4..32 MHz clock source"
|
||||
help
|
||||
Enable the external 0.4..32 MHz clock source at startup.
|
||||
This can then be selected as the main clock reference for the SOC.
|
||||
|
||||
config SOC_ATMEL_SAMD_XOSC_CRYSTAL
|
||||
bool "External 0.4..32 MHz clock is a crystal oscillator"
|
||||
depends on SOC_ATMEL_SAMD_XOSC
|
||||
default y
|
||||
help
|
||||
Enable the crystal oscillator (if disabled, expect a clock signal on
|
||||
XIN).
|
||||
|
||||
config SOC_ATMEL_SAMD_XOSC_FREQ_HZ
|
||||
int "External 0.4..32 MHz clock oscillator frequency"
|
||||
range 400000 32000000
|
||||
default 8000000
|
||||
depends on SOC_ATMEL_SAMD_XOSC
|
||||
help
|
||||
External 0.4..32 MHz clock oscillator reference frequency.
|
||||
|
||||
choice
|
||||
prompt "Main clock reference"
|
||||
default SOC_ATMEL_SAMD_DEFAULT_AS_MAIN
|
||||
help
|
||||
Selects the clock that will be used for the DFLL48M's reference.
|
||||
Main clocks, such as the CPU and AHB clocks will be derived from
|
||||
DFLL48M.
|
||||
|
||||
config SOC_ATMEL_SAMD_DEFAULT_AS_MAIN
|
||||
bool "DEFAULT"
|
||||
help
|
||||
This choice will leave all clocks to their current state.
|
||||
This can be the default reset state or a state set by a bootloader.
|
||||
|
||||
config SOC_ATMEL_SAMD_OSC32K_AS_MAIN
|
||||
bool "OSC32K"
|
||||
depends on SOC_ATMEL_SAMD_OSC32K
|
||||
|
||||
config SOC_ATMEL_SAMD_XOSC32K_AS_MAIN
|
||||
bool "XOSC32K"
|
||||
depends on SOC_ATMEL_SAMD_XOSC32K
|
||||
|
||||
config SOC_ATMEL_SAMD_OSC8M_AS_MAIN
|
||||
bool "OSC8M"
|
||||
depends on SOC_ATMEL_SAMD_OSC8M
|
||||
|
||||
config SOC_ATMEL_SAMD_XOSC_AS_MAIN
|
||||
bool "XOSC"
|
||||
depends on SOC_ATMEL_SAMD_XOSC
|
||||
|
||||
endchoice
|
||||
|
||||
endif # SOC_SERIES_SAMD20 || SOC_SERIES_SAMD21 || SOC_SERIES_SAMR21
|
||||
35
soc/atmel/sam0/common/Kconfig.samd5x
Normal file
35
soc/atmel/sam0/common/Kconfig.samd5x
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
# Copyright (c) 2019 ML!PA Consulting GmbH
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_SAMD51 || SOC_SERIES_SAME51 || SOC_SERIES_SAME53 || SOC_SERIES_SAME54
|
||||
|
||||
config SOC_ATMEL_SAMD5X_XOSC32K
|
||||
bool "The external 32 kHz crystal oscillator"
|
||||
help
|
||||
Say y to enable the external 32 kHZ crystal oscillator at
|
||||
startup. This can then be selected as the main clock source
|
||||
for the SOC.
|
||||
|
||||
choice
|
||||
prompt "Main clock source"
|
||||
default SOC_ATMEL_SAMD5X_DEFAULT_AS_MAIN
|
||||
help
|
||||
Selects the clock that the main clocks, such as the CPU
|
||||
clock and AHB clock, will be derived from.
|
||||
|
||||
config SOC_ATMEL_SAMD5X_DEFAULT_AS_MAIN
|
||||
bool "DEFAULT"
|
||||
help
|
||||
This choice will leave all clocks to their current state.
|
||||
This can be the default reset state or a state set by a bootloader.
|
||||
|
||||
config SOC_ATMEL_SAMD5X_XOSC32K_AS_MAIN
|
||||
depends on SOC_ATMEL_SAMD5X_XOSC32K
|
||||
bool "XOSC32K"
|
||||
|
||||
config SOC_ATMEL_SAMD5X_OSCULP32K_AS_MAIN
|
||||
bool "OSCULP32K"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
86
soc/atmel/sam0/common/Kconfig.saml2x
Normal file
86
soc/atmel/sam0/common/Kconfig.saml2x
Normal file
|
|
@ -0,0 +1,86 @@
|
|||
# Copyright (c) 2021 Argentum Systems Ltd.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_SAML21 || SOC_SERIES_SAMR34 || SOC_SERIES_SAMR35
|
||||
|
||||
config SOC_ATMEL_SAML_DEBUG_PAUSE
|
||||
bool "Insert a pause at boot, to allow a debugger to attach"
|
||||
default y
|
||||
help
|
||||
Issues have been observed while attempting to attach a debugger.
|
||||
These can be mitigated by inserting a small delay during the early boot
|
||||
sequence, before the system clock is configured.
|
||||
|
||||
If you ever intend to attach a debugger, say y.
|
||||
If you are confident that you will never attach a debugger to the
|
||||
resulting binary, or require the best possible boot time, say n.
|
||||
|
||||
config SOC_ATMEL_SAML_OSC32K
|
||||
bool "Internal 32.768 kHz RC oscillator"
|
||||
help
|
||||
Eable the internal 32.768 kHz RC oscillator at startup.
|
||||
This can then be selected as the main clock reference for the SOC.
|
||||
|
||||
config SOC_ATMEL_SAML_XOSC32K
|
||||
bool "External 32.768 kHz clock source"
|
||||
help
|
||||
Enable the external 32.768 kHz cloud source at startup.
|
||||
This can then be selected as the main clock reference for the SOC.
|
||||
|
||||
config SOC_ATMEL_SAML_XOSC32K_CRYSTAL
|
||||
bool "External 32.768 kHz clock is a crystal oscillator"
|
||||
depends on SOC_ATMEL_SAML_XOSC32K
|
||||
default y
|
||||
help
|
||||
Enable the crystal oscillator (if disabled, expect a clock signal on
|
||||
XIN32).
|
||||
|
||||
config SOC_ATMEL_SAML_OSC16M
|
||||
bool "Internal 16 MHz RC oscillator"
|
||||
help
|
||||
Enable the internal 16 MHz RC oscillator at startup.
|
||||
This can then be selected as the main clock reference for the SOC.
|
||||
|
||||
# NOTE: XOSC is not currently supported
|
||||
|
||||
|
||||
choice
|
||||
prompt "Main clock reference"
|
||||
default SOC_ATMEL_SAML_OPENLOOP_AS_MAIN
|
||||
help
|
||||
Selects the clock that will be used for the DFLL48M's reference.
|
||||
Main clocks, such as the CPU and AHB clocks will be derived from
|
||||
DFLL48M configured for 48 MHz.
|
||||
|
||||
config SOC_ATMEL_SAML_OPENLOOP_AS_MAIN
|
||||
bool "OPENLOOP"
|
||||
help
|
||||
Note, this mode can only be used with an LDO regulator.
|
||||
|
||||
config SOC_ATMEL_SAML_OSC32K_AS_MAIN
|
||||
bool "OSC32K"
|
||||
depends on SOC_ATMEL_SAML_OSC32K
|
||||
|
||||
config SOC_ATMEL_SAML_XOSC32K_AS_MAIN
|
||||
bool "XOSC32K"
|
||||
depends on SOC_ATMEL_SAML_XOSC32K
|
||||
|
||||
config SOC_ATMEL_SAML_OSC16M_AS_MAIN
|
||||
bool "OSC16M"
|
||||
depends on SOC_ATMEL_SAML_OSC16M
|
||||
|
||||
endchoice
|
||||
|
||||
config SOC_ATMEL_SAMR3X_RADIO_OFF_SETUP
|
||||
bool "Configure LoRa radio pins if not in use"
|
||||
default y if !LORA
|
||||
depends on SOC_SERIES_SAMR34 || SOC_SERIES_SAMR35
|
||||
help
|
||||
As detailed in DS70005356C, LoRa radio SPI pins do not have pull-ups,
|
||||
so when the radio is not in use, it's important that CS is kept high,
|
||||
to avoid unexpected behavior and increased current consumption. To
|
||||
further reduce power consumption, radio can be kept in reset state by
|
||||
keeping nRST pin low. When enabling this option, both CS and nRST will
|
||||
be configured high and low, respectively.
|
||||
|
||||
endif # SOC_SERIES_SAML21 || SOC_SERIES_SAMR34 || SOC_SERIES_SAMR35
|
||||
157
soc/atmel/sam0/common/adc_fixup_sam0.h
Normal file
157
soc/atmel/sam0/common/adc_fixup_sam0.h
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Argentum Systems Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _ATMEL_SAM_ADC_FIXUP_H_
|
||||
#define _ATMEL_SAM_ADC_FIXUP_H_
|
||||
|
||||
#if defined(ADC_SYNCBUSY_MASK)
|
||||
#define ADC_SYNC(adc) ((adc)->SYNCBUSY.reg)
|
||||
#define ADC_SYNC_MASK (ADC_SYNCBUSY_MASK)
|
||||
#elif defined(ADC_STATUS_SYNCBUSY)
|
||||
#define ADC_SYNC(adc) ((adc)->STATUS.reg)
|
||||
#define ADC_SYNC_MASK (ADC_STATUS_SYNCBUSY)
|
||||
#else
|
||||
#error ADC not supported...
|
||||
#endif
|
||||
|
||||
#if defined(ADC_INPUTCTRL_DIFFMODE)
|
||||
#define ADC_DIFF(adc) (inputctrl)
|
||||
#define ADC_DIFF_MASK (ADC_INPUTCTRL_DIFFMODE)
|
||||
#elif defined(ADC_CTRLB_DIFFMODE)
|
||||
#define ADC_DIFF(adc) ((adc)->CTRLB.reg)
|
||||
#define ADC_DIFF_MASK (ADC_CTRLB_DIFFMODE)
|
||||
#elif defined(ADC_CTRLC_DIFFMODE)
|
||||
#define ADC_DIFF(adc) ((adc)->CTRLC.reg)
|
||||
#define ADC_DIFF_MASK (ADC_CTRLC_DIFFMODE)
|
||||
#else
|
||||
#error ADC not supported...
|
||||
#endif
|
||||
|
||||
#if defined(ADC_CTRLB_RESSEL)
|
||||
#define ADC_RESSEL(adc) ((adc)->CTRLB.bit.RESSEL)
|
||||
#define ADC_RESSEL_8BIT ADC_CTRLB_RESSEL_8BIT_Val
|
||||
#define ADC_RESSEL_10BIT ADC_CTRLB_RESSEL_10BIT_Val
|
||||
#define ADC_RESSEL_12BIT ADC_CTRLB_RESSEL_12BIT_Val
|
||||
#define ADC_RESSEL_16BIT ADC_CTRLB_RESSEL_16BIT_Val
|
||||
#elif defined(ADC_CTRLC_RESSEL)
|
||||
#define ADC_RESSEL(adc) ((adc)->CTRLC.bit.RESSEL)
|
||||
#define ADC_RESSEL_8BIT ADC_CTRLC_RESSEL_8BIT_Val
|
||||
#define ADC_RESSEL_10BIT ADC_CTRLC_RESSEL_10BIT_Val
|
||||
#define ADC_RESSEL_12BIT ADC_CTRLC_RESSEL_12BIT_Val
|
||||
#define ADC_RESSEL_16BIT ADC_CTRLC_RESSEL_16BIT_Val
|
||||
#else
|
||||
#error ADC not supported...
|
||||
#endif
|
||||
|
||||
#if defined(ADC_CTRLA_PRESCALER)
|
||||
#define ADC_PRESCALER(adc) ((adc)->CTRLA.bit.PRESCALER)
|
||||
#define ADC_CTRLx_PRESCALER_DIV ADC_CTRLA_PRESCALER_DIV
|
||||
#elif defined(ADC_CTRLB_PRESCALER)
|
||||
#define ADC_PRESCALER(adc) ((adc)->CTRLB.bit.PRESCALER)
|
||||
#define ADC_CTRLx_PRESCALER_DIV ADC_CTRLB_PRESCALER_DIV
|
||||
#else
|
||||
#error ADC not supported...
|
||||
#endif
|
||||
|
||||
#if defined(SYSCTRL_VREF_TSEN)
|
||||
#define ADC_TSEN (SYSCTRL->VREF.bit.TSEN)
|
||||
#elif defined(SUPC_VREF_TSEN)
|
||||
#define ADC_TSEN (SUPC->VREF.bit.TSEN)
|
||||
#else
|
||||
#error ADC not supported...
|
||||
#endif
|
||||
|
||||
#if defined(SYSCTRL_VREF_BGOUTEN)
|
||||
#define ADC_BGEN (SYSCTRL->VREF.bit.BGOUTEN)
|
||||
#elif defined(SUPC_VREF_VREFOE)
|
||||
#define ADC_BGEN (SUPC->VREF.bit.VREFOE)
|
||||
#else
|
||||
#error ADC not supported...
|
||||
#endif
|
||||
|
||||
#if defined(MCLK)
|
||||
/* a trailing underscore and/or lumpy concatenation is used to prevent expansion */
|
||||
#define ADC_SAM0_CALIB(prefix, val) \
|
||||
UTIL_CAT(ADC_CALIB_, val)( \
|
||||
(((*(uint32_t *)UTIL_CAT(UTIL_CAT(UTIL_CAT(prefix, FUSES_), val), _ADDR)) \
|
||||
>> UTIL_CAT(UTIL_CAT(UTIL_CAT(prefix, FUSES_), val), _Pos)) \
|
||||
& UTIL_CAT(UTIL_CAT(UTIL_CAT(prefix, FUSES_), val), _Msk)) \
|
||||
)
|
||||
|
||||
#if ADC_INST_NUM == 1
|
||||
# define ADC_FUSES_PREFIX(n) ADC_
|
||||
#else
|
||||
# define ADC_FUSES_PREFIX(n) UTIL_CAT(AD, UTIL_CAT(C, UTIL_CAT(n, _)))
|
||||
#endif
|
||||
|
||||
#if defined(ADC_FUSES_BIASCOMP) || defined(ADC0_FUSES_BIASCOMP)
|
||||
# define ADC_SAM0_BIASCOMP(n) ADC_SAM0_CALIB(ADC_FUSES_PREFIX(n), BIASCOMP)
|
||||
#else
|
||||
# define ADC_SAM0_BIASCOMP(n) 0
|
||||
#endif
|
||||
|
||||
#if defined(ADC_FUSES_BIASR2R) || defined(ADC0_FUSES_BIASR2R)
|
||||
# define ADC_SAM0_BIASR2R(n) ADC_SAM0_CALIB(ADC_FUSES_PREFIX(n), BIASR2R)
|
||||
#else
|
||||
# define ADC_SAM0_BIASR2R(n) 0
|
||||
#endif
|
||||
|
||||
#if defined(ADC_FUSES_BIASREFBUF) || defined(ADC0_FUSES_BIASREFBUF)
|
||||
# define ADC_SAM0_BIASREFBUF(n) ADC_SAM0_CALIB(ADC_FUSES_PREFIX(n), BIASREFBUF)
|
||||
#else
|
||||
# define ADC_SAM0_BIASREFBUF(n) 0
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The following MCLK clock configuration fix-up symbols map to the applicable
|
||||
* APB-specific symbols, in order to accommodate different SoC series with the
|
||||
* ADC core connected to different APBs.
|
||||
*/
|
||||
#if defined(MCLK_APBDMASK_ADC) || defined(MCLK_APBDMASK_ADC0)
|
||||
# define MCLK_ADC (MCLK->APBDMASK.reg)
|
||||
#elif defined(MCLK_APBCMASK_ADC0)
|
||||
# define MCLK_ADC (MCLK->APBCMASK.reg)
|
||||
#else
|
||||
# error ADC not supported...
|
||||
#endif
|
||||
#endif /* MCLK */
|
||||
|
||||
/*
|
||||
* All SAM0 define the internal voltage reference as 1.0V by default.
|
||||
*/
|
||||
#ifndef ADC_REFCTRL_REFSEL_INTERNAL
|
||||
# ifdef ADC_REFCTRL_REFSEL_INTREF
|
||||
# define ADC_REFCTRL_REFSEL_INTERNAL ADC_REFCTRL_REFSEL_INTREF
|
||||
# else
|
||||
# define ADC_REFCTRL_REFSEL_INTERNAL ADC_REFCTRL_REFSEL_INT1V
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Some SAM0 devices can use VDDANA as a direct reference. For the devices
|
||||
* that not offer this option, the internal 1.0V reference will be used.
|
||||
*/
|
||||
#ifndef ADC_REFCTRL_REFSEL_VDD_1
|
||||
# if defined(ADC0_BANDGAP)
|
||||
# define ADC_REFCTRL_REFSEL_VDD_1 ADC_REFCTRL_REFSEL_INTVCC1
|
||||
# elif defined(ADC_REFCTRL_REFSEL_INTVCC2)
|
||||
# define ADC_REFCTRL_REFSEL_VDD_1 ADC_REFCTRL_REFSEL_INTVCC2
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* SAMD/E5x define ADC[0-1]_BANDGAP symbol. Only those devices use INTVCC0 to
|
||||
* implement VDDANA / 2.
|
||||
*/
|
||||
#ifndef ADC_REFCTRL_REFSEL_VDD_1_2
|
||||
# ifdef ADC0_BANDGAP
|
||||
# define ADC_REFCTRL_REFSEL_VDD_1_2 ADC_REFCTRL_REFSEL_INTVCC0
|
||||
# else
|
||||
# define ADC_REFCTRL_REFSEL_VDD_1_2 ADC_REFCTRL_REFSEL_INTVCC1
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#endif /* _ATMEL_SAM0_ADC_FIXUP_H_ */
|
||||
51
soc/atmel/sam0/common/atmel_sam0_dt.h
Normal file
51
soc/atmel/sam0/common/atmel_sam0_dt.h
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Linaro Ltd.
|
||||
* Copyright (c) 2021 Gerson Fernando Budke
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/** @file
|
||||
* @brief Atmel SAM0 MCU family devicetree helper macros
|
||||
*/
|
||||
|
||||
#ifndef _ATMEL_SAM0_DT_H_
|
||||
#define _ATMEL_SAM0_DT_H_
|
||||
|
||||
/* Helper macro to get MCLK register address for corresponding
|
||||
* that has corresponding clock enable bit.
|
||||
*/
|
||||
#define MCLK_MASK_DT_INT_REG_ADDR(n) \
|
||||
(DT_REG_ADDR(DT_INST_PHANDLE_BY_NAME(n, clocks, mclk)) + \
|
||||
DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, offset))
|
||||
|
||||
/* Helper macros for use with ATMEL SAM0 DMAC controller
|
||||
* return 0xff as default value if there is no 'dmas' property
|
||||
*/
|
||||
#define ATMEL_SAM0_DT_INST_DMA_CELL(n, name, cell) \
|
||||
COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), \
|
||||
(DT_INST_DMAS_CELL_BY_NAME(n, name, cell)), \
|
||||
(0xff))
|
||||
#define ATMEL_SAM0_DT_INST_DMA_TRIGSRC(n, name) \
|
||||
ATMEL_SAM0_DT_INST_DMA_CELL(n, name, trigsrc)
|
||||
#define ATMEL_SAM0_DT_INST_DMA_CHANNEL(n, name) \
|
||||
ATMEL_SAM0_DT_INST_DMA_CELL(n, name, channel)
|
||||
#define ATMEL_SAM0_DT_INST_DMA_CTLR(n, name) \
|
||||
COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), \
|
||||
(DT_INST_DMAS_CTLR_BY_NAME(n, name)), \
|
||||
(DT_INVALID_NODE))
|
||||
|
||||
|
||||
/* Use to check if a sercom 'n' is enabled for a given 'compat' */
|
||||
#define ATMEL_SAM0_DT_SERCOM_CHECK(n, compat) \
|
||||
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(sercom##n), compat, okay)
|
||||
|
||||
/* Use to check if TCC 'n' is enabled for a given 'compat' */
|
||||
#define ATMEL_SAM0_DT_TCC_CHECK(n, compat) \
|
||||
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(tcc##n), compat, okay)
|
||||
|
||||
/* Common macro for use to set HCLK_FREQ_HZ */
|
||||
#define ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ \
|
||||
DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
|
||||
|
||||
#endif /* _ATMEL_SAM0_SOC_DT_H_ */
|
||||
61
soc/atmel/sam0/common/bossa.c
Normal file
61
soc/atmel/sam0/common/bossa.c
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Google LLC.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <soc.h>
|
||||
#include <zephyr/drivers/uart/cdc_acm.h>
|
||||
#include <zephyr/drivers/usb/usb_dc.h>
|
||||
#include <zephyr/init.h>
|
||||
#include <zephyr/usb/class/usb_cdc.h>
|
||||
|
||||
/*
|
||||
* Magic value that causes the bootloader to stay in bootloader mode instead of
|
||||
* starting the application.
|
||||
*/
|
||||
#if CONFIG_BOOTLOADER_BOSSA_ADAFRUIT_UF2
|
||||
#define DOUBLE_TAP_MAGIC 0xf01669ef
|
||||
#elif CONFIG_BOOTLOADER_BOSSA_ARDUINO
|
||||
#define DOUBLE_TAP_MAGIC 0x07738135
|
||||
#else
|
||||
#error Unsupported BOSSA bootloader variant
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BOOTLOADER_BOSSA_DEVICE_NAME)
|
||||
|
||||
static void bossa_reset(const struct device *dev, uint32_t rate)
|
||||
{
|
||||
uint32_t *top;
|
||||
|
||||
if (rate != 1200) {
|
||||
return;
|
||||
}
|
||||
|
||||
/* The programmer set the baud rate to 1200 baud. Reset into the
|
||||
* bootloader.
|
||||
*/
|
||||
usb_dc_detach();
|
||||
|
||||
top = (uint32_t *)(DT_REG_ADDR(DT_NODELABEL(sram0)) +
|
||||
DT_REG_SIZE(DT_NODELABEL(sram0)));
|
||||
top[-1] = DOUBLE_TAP_MAGIC;
|
||||
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
|
||||
static int bossa_init(void)
|
||||
{
|
||||
const struct device *dev =
|
||||
device_get_binding(CONFIG_BOOTLOADER_BOSSA_DEVICE_NAME);
|
||||
|
||||
if (dev == NULL) {
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
return cdc_acm_dte_rate_callback_set(dev, bossa_reset);
|
||||
}
|
||||
|
||||
SYS_INIT(bossa_init, APPLICATION, 0);
|
||||
|
||||
#endif /* CONFIG_BOOTLOADER_BOSSA_DEVICE_NAME */
|
||||
27
soc/atmel/sam0/common/gmac_fixup_samd5x.h
Normal file
27
soc/atmel/sam0/common/gmac_fixup_samd5x.h
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/*
|
||||
* The following GMAC clock configuration fix-up symbols map to the applicable
|
||||
* APB-specific symbols, in order to accommodate different SoC series with the
|
||||
* GMAC core connected to different APBs.
|
||||
*/
|
||||
#ifdef MCLK_APBAMASK_GMAC
|
||||
#define MCLK_GMAC (&MCLK->APBAMASK.reg)
|
||||
#define MCLK_GMAC_MASK (MCLK_APBAMASK_GMAC)
|
||||
#endif
|
||||
#ifdef MCLK_APBBMASK_GMAC
|
||||
#define MCLK_GMAC (&MCLK->APBBMASK.reg)
|
||||
#define MCLK_GMAC_MASK (MCLK_APBBMASK_GMAC)
|
||||
#endif
|
||||
#ifdef MCLK_APBCMASK_GMAC
|
||||
#define MCLK_GMAC (&MCLK->APBCMASK.reg)
|
||||
#define MCLK_GMAC_MASK (MCLK_APBCMASK_GMAC)
|
||||
#endif
|
||||
#ifdef MCLK_APBDMASK_GMAC
|
||||
#define MCLK_GMAC (&MCLK->APBDMASK.reg)
|
||||
#define MCLK_GMAC_MASK (MCLK_APBDMASK_GMAC)
|
||||
#endif
|
||||
17
soc/atmel/sam0/common/pinctrl_soc.h
Normal file
17
soc/atmel/sam0/common/pinctrl_soc.h
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2022, Gerson Fernando Budke <nandojve@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* Atmel SAM SoC specific helpers for pinctrl driver
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_ARM_ATMEL_SAM_COMMON_PINCTRL_SOC_H_
|
||||
#define ZEPHYR_SOC_ARM_ATMEL_SAM_COMMON_PINCTRL_SOC_H_
|
||||
|
||||
#include <zephyr/drivers/pinctrl/pinctrl_soc_sam_common.h>
|
||||
|
||||
#endif /* ZEPHYR_SOC_ARM_ATMEL_SAM_COMMON_PINCTRL_SOC_H_ */
|
||||
141
soc/atmel/sam0/common/sercom_fixup_samd5x.h
Normal file
141
soc/atmel/sam0/common/sercom_fixup_samd5x.h
Normal file
|
|
@ -0,0 +1,141 @@
|
|||
/*
|
||||
* Copyright (c) 2019 ML!PA Consulting GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifdef MCLK_APBAMASK_SERCOM0
|
||||
#define MCLK_SERCOM0 (&MCLK->APBAMASK.reg)
|
||||
#define MCLK_SERCOM0_MASK (MCLK_APBAMASK_SERCOM0)
|
||||
#endif
|
||||
#ifdef MCLK_APBBMASK_SERCOM0
|
||||
#define MCLK_SERCOM0 (&MCLK->APBBMASK.reg)
|
||||
#define MCLK_SERCOM0_MASK (MCLK_APBBMASK_SERCOM0)
|
||||
#endif
|
||||
#ifdef MCLK_APBCMASK_SERCOM0
|
||||
#define MCLK_SERCOM0 (&MCLK->APBCMASK.reg)
|
||||
#define MCLK_SERCOM0_MASK (MCLK_APBCMASK_SERCOM0)
|
||||
#endif
|
||||
#ifdef MCLK_APBDMASK_SERCOM0
|
||||
#define MCLK_SERCOM0 (&MCLK->APBDMASK.reg)
|
||||
#define MCLK_SERCOM0_MASK (MCLK_APBDMASK_SERCOM0)
|
||||
#endif
|
||||
|
||||
#ifdef MCLK_APBAMASK_SERCOM1
|
||||
#define MCLK_SERCOM1 (&MCLK->APBAMASK.reg)
|
||||
#define MCLK_SERCOM1_MASK (MCLK_APBAMASK_SERCOM1)
|
||||
#endif
|
||||
#ifdef MCLK_APBBMASK_SERCOM1
|
||||
#define MCLK_SERCOM1 (&MCLK->APBBMASK.reg)
|
||||
#define MCLK_SERCOM1_MASK (MCLK_APBBMASK_SERCOM1)
|
||||
#endif
|
||||
#ifdef MCLK_APBCMASK_SERCOM1
|
||||
#define MCLK_SERCOM1 (&MCLK->APBCMASK.reg)
|
||||
#define MCLK_SERCOM1_MASK (MCLK_APBCMASK_SERCOM1)
|
||||
#endif
|
||||
#ifdef MCLK_APBDMASK_SERCOM1
|
||||
#define MCLK_SERCOM1 (&MCLK->APBDMASK.reg)
|
||||
#define MCLK_SERCOM1_MASK (MCLK_APBDMASK_SERCOM1)
|
||||
#endif
|
||||
|
||||
#ifdef MCLK_APBAMASK_SERCOM2
|
||||
#define MCLK_SERCOM2 (&MCLK->APBAMASK.reg)
|
||||
#define MCLK_SERCOM2_MASK (MCLK_APBAMASK_SERCOM2)
|
||||
#endif
|
||||
#ifdef MCLK_APBBMASK_SERCOM2
|
||||
#define MCLK_SERCOM2 (&MCLK->APBBMASK.reg)
|
||||
#define MCLK_SERCOM2_MASK (MCLK_APBBMASK_SERCOM2)
|
||||
#endif
|
||||
#ifdef MCLK_APBCMASK_SERCOM2
|
||||
#define MCLK_SERCOM2 (&MCLK->APBCMASK.reg)
|
||||
#define MCLK_SERCOM2_MASK (MCLK_APBCMASK_SERCOM2)
|
||||
#endif
|
||||
#ifdef MCLK_APBDMASK_SERCOM2
|
||||
#define MCLK_SERCOM2 (&MCLK->APBDMASK.reg)
|
||||
#define MCLK_SERCOM2_MASK (MCLK_APBDMASK_SERCOM2)
|
||||
#endif
|
||||
|
||||
#ifdef MCLK_APBAMASK_SERCOM3
|
||||
#define MCLK_SERCOM3 (&MCLK->APBAMASK.reg)
|
||||
#define MCLK_SERCOM3_MASK (MCLK_APBAMASK_SERCOM3)
|
||||
#endif
|
||||
#ifdef MCLK_APBBMASK_SERCOM3
|
||||
#define MCLK_SERCOM3 (&MCLK->APBBMASK.reg)
|
||||
#define MCLK_SERCOM3_MASK (MCLK_APBBMASK_SERCOM3)
|
||||
#endif
|
||||
#ifdef MCLK_APBCMASK_SERCOM3
|
||||
#define MCLK_SERCOM3 (&MCLK->APBCMASK.reg)
|
||||
#define MCLK_SERCOM3_MASK (MCLK_APBCMASK_SERCOM3)
|
||||
#endif
|
||||
#ifdef MCLK_APBDMASK_SERCOM3
|
||||
#define MCLK_SERCOM3 (&MCLK->APBDMASK.reg)
|
||||
#define MCLK_SERCOM3_MASK (MCLK_APBDMASK_SERCOM3)
|
||||
#endif
|
||||
|
||||
#ifdef MCLK_APBAMASK_SERCOM4
|
||||
#define MCLK_SERCOM4 (&MCLK->APBAMASK.reg)
|
||||
#define MCLK_SERCOM4_MASK (MCLK_APBAMASK_SERCOM4)
|
||||
#endif
|
||||
#ifdef MCLK_APBBMASK_SERCOM4
|
||||
#define MCLK_SERCOM4 (&MCLK->APBBMASK.reg)
|
||||
#define MCLK_SERCOM4_MASK (MCLK_APBBMASK_SERCOM4)
|
||||
#endif
|
||||
#ifdef MCLK_APBCMASK_SERCOM4
|
||||
#define MCLK_SERCOM4 (&MCLK->APBCMASK.reg)
|
||||
#define MCLK_SERCOM4_MASK (MCLK_APBCMASK_SERCOM4)
|
||||
#endif
|
||||
#ifdef MCLK_APBDMASK_SERCOM4
|
||||
#define MCLK_SERCOM4 (&MCLK->APBDMASK.reg)
|
||||
#define MCLK_SERCOM4_MASK (MCLK_APBDMASK_SERCOM4)
|
||||
#endif
|
||||
|
||||
#ifdef MCLK_APBAMASK_SERCOM5
|
||||
#define MCLK_SERCOM5 (&MCLK->APBAMASK.reg)
|
||||
#define MCLK_SERCOM5_MASK (MCLK_APBAMASK_SERCOM5)
|
||||
#endif
|
||||
#ifdef MCLK_APBBMASK_SERCOM5
|
||||
#define MCLK_SERCOM5 (&MCLK->APBBMASK.reg)
|
||||
#define MCLK_SERCOM5_MASK (MCLK_APBBMASK_SERCOM5)
|
||||
#endif
|
||||
#ifdef MCLK_APBCMASK_SERCOM5
|
||||
#define MCLK_SERCOM5 (&MCLK->APBCMASK.reg)
|
||||
#define MCLK_SERCOM5_MASK (MCLK_APBCMASK_SERCOM5)
|
||||
#endif
|
||||
#ifdef MCLK_APBDMASK_SERCOM5
|
||||
#define MCLK_SERCOM5 (&MCLK->APBDMASK.reg)
|
||||
#define MCLK_SERCOM5_MASK (MCLK_APBDMASK_SERCOM5)
|
||||
#endif
|
||||
|
||||
#ifdef MCLK_APBAMASK_SERCOM6
|
||||
#define MCLK_SERCOM6 (&MCLK->APBAMASK.reg)
|
||||
#define MCLK_SERCOM6_MASK (MCLK_APBAMASK_SERCOM6)
|
||||
#endif
|
||||
#ifdef MCLK_APBBMASK_SERCOM6
|
||||
#define MCLK_SERCOM6 (&MCLK->APBBMASK.reg)
|
||||
#define MCLK_SERCOM6_MASK (MCLK_APBBMASK_SERCOM6)
|
||||
#endif
|
||||
#ifdef MCLK_APBCMASK_SERCOM6
|
||||
#define MCLK_SERCOM6 (&MCLK->APBCMASK.reg)
|
||||
#define MCLK_SERCOM6_MASK (MCLK_APBCMASK_SERCOM6)
|
||||
#endif
|
||||
#ifdef MCLK_APBDMASK_SERCOM6
|
||||
#define MCLK_SERCOM6 (&MCLK->APBDMASK.reg)
|
||||
#define MCLK_SERCOM6_MASK (MCLK_APBDMASK_SERCOM6)
|
||||
#endif
|
||||
|
||||
#ifdef MCLK_APBAMASK_SERCOM7
|
||||
#define MCLK_SERCOM7 (&MCLK->APBAMASK.reg)
|
||||
#define MCLK_SERCOM7_MASK (MCLK_APBAMASK_SERCOM7)
|
||||
#endif
|
||||
#ifdef MCLK_APBBMASK_SERCOM7
|
||||
#define MCLK_SERCOM7 (&MCLK->APBBMASK.reg)
|
||||
#define MCLK_SERCOM7_MASK (MCLK_APBBMASK_SERCOM7)
|
||||
#endif
|
||||
#ifdef MCLK_APBCMASK_SERCOM7
|
||||
#define MCLK_SERCOM7 (&MCLK->APBCMASK.reg)
|
||||
#define MCLK_SERCOM7_MASK (MCLK_APBCMASK_SERCOM7)
|
||||
#endif
|
||||
#ifdef MCLK_APBDMASK_SERCOM7
|
||||
#define MCLK_SERCOM7 (&MCLK->APBDMASK.reg)
|
||||
#define MCLK_SERCOM7_MASK (MCLK_APBDMASK_SERCOM7)
|
||||
#endif
|
||||
81
soc/atmel/sam0/common/soc_port.c
Normal file
81
soc/atmel/sam0/common/soc_port.c
Normal file
|
|
@ -0,0 +1,81 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Piotr Mienkowski
|
||||
* Copyright (c) 2018 Google LLC.
|
||||
* Copyright (c) 2021 Gerson Fernando Budke
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/** @file
|
||||
* @brief Atmel SAM0 MCU family I/O Pin Controller (PORT)
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "soc_port.h"
|
||||
|
||||
int soc_port_pinmux_set(PortGroup *pg, uint32_t pin, uint32_t func)
|
||||
{
|
||||
bool is_odd = pin & 1;
|
||||
int idx = pin / 2U;
|
||||
|
||||
/* Each pinmux register holds the config for two pins. The
|
||||
* even numbered pin goes in the bits 0..3 and the odd
|
||||
* numbered pin in bits 4..7.
|
||||
*/
|
||||
if (is_odd) {
|
||||
pg->PMUX[idx].bit.PMUXO = func;
|
||||
} else {
|
||||
pg->PMUX[idx].bit.PMUXE = func;
|
||||
}
|
||||
pg->PINCFG[pin].bit.PMUXEN = 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void soc_port_configure(const struct soc_port_pin *pin)
|
||||
{
|
||||
PortGroup *pg = pin->regs;
|
||||
uint32_t flags = pin->flags;
|
||||
uint32_t func = (pin->flags & SOC_PORT_FUNC_MASK) >> SOC_PORT_FUNC_POS;
|
||||
PORT_PINCFG_Type pincfg = { .reg = 0 };
|
||||
|
||||
/* Reset or analog I/O: all digital disabled */
|
||||
pg->PINCFG[pin->pinum] = pincfg;
|
||||
pg->DIRCLR.reg = (1 << pin->pinum);
|
||||
pg->OUTCLR.reg = (1 << pin->pinum);
|
||||
|
||||
if (flags & SOC_PORT_PMUXEN_ENABLE) {
|
||||
soc_port_pinmux_set(pg, pin->pinum, func);
|
||||
return;
|
||||
}
|
||||
|
||||
if (flags & (SOC_PORT_PULLUP | SOC_PORT_PULLDOWN)) {
|
||||
if (flags & SOC_PORT_PULLUP) {
|
||||
pg->OUTSET.reg = (1 << pin->pinum);
|
||||
}
|
||||
|
||||
pincfg.bit.PULLEN = 1;
|
||||
}
|
||||
|
||||
if (flags & SOC_PORT_INPUT_ENABLE) {
|
||||
pincfg.bit.INEN = 1;
|
||||
}
|
||||
|
||||
if (flags & SOC_PORT_OUTPUT_ENABLE) {
|
||||
pg->DIRSET.reg = (1 << pin->pinum);
|
||||
}
|
||||
|
||||
if (flags & SOC_PORT_STRENGTH_STRONGER) {
|
||||
pincfg.bit.DRVSTR = 1;
|
||||
}
|
||||
|
||||
pg->PINCFG[pin->pinum] = pincfg;
|
||||
}
|
||||
|
||||
void soc_port_list_configure(const struct soc_port_pin pins[],
|
||||
unsigned int size)
|
||||
{
|
||||
for (int i = 0; i < size; i++) {
|
||||
soc_port_configure(&pins[i]);
|
||||
}
|
||||
}
|
||||
127
soc/atmel/sam0/common/soc_port.h
Normal file
127
soc/atmel/sam0/common/soc_port.h
Normal file
|
|
@ -0,0 +1,127 @@
|
|||
/*
|
||||
* Copyright (c) 2016-2017 Piotr Mienkowski
|
||||
* Copyright (c) 2020-2022 Gerson Fernando Budke
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/** @file
|
||||
* @brief Atmel SAM0 MCU family I/O Pin Controller (PORT)
|
||||
*/
|
||||
|
||||
#ifndef ATMEL_SAM0_SOC_PORT_H_
|
||||
#define ATMEL_SAM0_SOC_PORT_H_
|
||||
|
||||
#include <soc.h>
|
||||
|
||||
/*
|
||||
* Pin flags/attributes
|
||||
*/
|
||||
#define SOC_PORT_DEFAULT (0)
|
||||
|
||||
#define SOC_PORT_FLAGS_POS (0)
|
||||
#define SOC_PORT_FLAGS_MASK (0x7B << SOC_PORT_FLAGS_POS)
|
||||
#define SOC_PORT_PULLUP_POS (SOC_PORT_FLAGS_POS)
|
||||
#define SOC_PORT_PULLUP (1 << SOC_PORT_PULLUP_POS)
|
||||
#define SOC_PORT_PULLDOWN_POS (SOC_PORT_PULLUP_POS + 1U)
|
||||
#define SOC_PORT_PULLDOWN (1 << SOC_PORT_PULLDOWN_POS)
|
||||
/* Open-Drain is a reserved entry at pinctrl driver */
|
||||
#define SOC_GPIO_OPENDRAIN_POS (SOC_PORT_PULLDOWN_POS + 1U)
|
||||
/* Input-Enable means Input-Buffer, see dts/pinctrl/pincfg-node.yaml */
|
||||
#define SOC_PORT_INPUT_ENABLE_POS (SOC_GPIO_OPENDRAIN_POS + 1U)
|
||||
#define SOC_PORT_INPUT_ENABLE (1 << SOC_PORT_INPUT_ENABLE_POS)
|
||||
/* Output-Enable, see dts/pinctrl/pincfg-node.yaml */
|
||||
#define SOC_PORT_OUTPUT_ENABLE_POS (SOC_PORT_INPUT_ENABLE_POS + 1U)
|
||||
#define SOC_PORT_OUTPUT_ENABLE (1 << SOC_PORT_OUTPUT_ENABLE_POS)
|
||||
/* Drive-Strength, 0mA means normal, any other value means stronger */
|
||||
#define SOC_PORT_STRENGTH_STRONGER_POS (SOC_PORT_OUTPUT_ENABLE_POS + 1U)
|
||||
#define SOC_PORT_STRENGTH_STRONGER (1 << SOC_PORT_STRENGTH_STRONGER_POS)
|
||||
/* Peripheral Multiplexer Enable */
|
||||
#define SOC_PORT_PMUXEN_ENABLE_POS (SOC_PORT_STRENGTH_STRONGER_POS + 1U)
|
||||
#define SOC_PORT_PMUXEN_ENABLE (1 << SOC_PORT_PMUXEN_ENABLE_POS)
|
||||
|
||||
/* Bit field: SOC_PORT_FUNC */
|
||||
#define SOC_PORT_FUNC_POS (16U)
|
||||
#define SOC_PORT_FUNC_MASK (0xF << SOC_PORT_FUNC_POS)
|
||||
|
||||
/** Connect pin to peripheral A. */
|
||||
#define SOC_PORT_FUNC_A (0x0 << SOC_PORT_FUNC_POS)
|
||||
/** Connect pin to peripheral B. */
|
||||
#define SOC_PORT_FUNC_B (0x1 << SOC_PORT_FUNC_POS)
|
||||
/** Connect pin to peripheral C. */
|
||||
#define SOC_PORT_FUNC_C (0x2 << SOC_PORT_FUNC_POS)
|
||||
/** Connect pin to peripheral D. */
|
||||
#define SOC_PORT_FUNC_D (0x3 << SOC_PORT_FUNC_POS)
|
||||
/** Connect pin to peripheral E. */
|
||||
#define SOC_PORT_FUNC_E (0x4 << SOC_PORT_FUNC_POS)
|
||||
/** Connect pin to peripheral F. */
|
||||
#define SOC_PORT_FUNC_F (0x5 << SOC_PORT_FUNC_POS)
|
||||
/** Connect pin to peripheral G. */
|
||||
#define SOC_PORT_FUNC_G (0x6 << SOC_PORT_FUNC_POS)
|
||||
/** Connect pin to peripheral H. */
|
||||
#define SOC_PORT_FUNC_H (0x7 << SOC_PORT_FUNC_POS)
|
||||
/** Connect pin to peripheral I. */
|
||||
#define SOC_PORT_FUNC_I (0x8 << SOC_PORT_FUNC_POS)
|
||||
/** Connect pin to peripheral J. */
|
||||
#define SOC_PORT_FUNC_J (0x9 << SOC_PORT_FUNC_POS)
|
||||
/** Connect pin to peripheral K. */
|
||||
#define SOC_PORT_FUNC_K (0xa << SOC_PORT_FUNC_POS)
|
||||
/** Connect pin to peripheral L. */
|
||||
#define SOC_PORT_FUNC_L (0xb << SOC_PORT_FUNC_POS)
|
||||
/** Connect pin to peripheral M. */
|
||||
#define SOC_PORT_FUNC_M (0xc << SOC_PORT_FUNC_POS)
|
||||
/** Connect pin to peripheral N. */
|
||||
#define SOC_PORT_FUNC_N (0xd << SOC_PORT_FUNC_POS)
|
||||
|
||||
struct soc_port_pin {
|
||||
PortGroup *regs; /** pointer to registers of the I/O Pin Controller */
|
||||
uint32_t pinum; /** pin number */
|
||||
uint32_t flags; /** pin flags/attributes */
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Configure PORT pin muxing.
|
||||
*
|
||||
* Configure one pin muxing belonging to some PORT.
|
||||
*
|
||||
* @param pg PortGroup register
|
||||
* @param pin Pin number
|
||||
* @param func Pin Function
|
||||
*/
|
||||
int soc_port_pinmux_set(PortGroup *pg, uint32_t pin, uint32_t func);
|
||||
|
||||
/**
|
||||
* @brief Configure PORT pin.
|
||||
*
|
||||
* Configure one pin belonging to some PORT.
|
||||
* Example scenarios:
|
||||
* - configure pin(s) as input.
|
||||
* - connect pin(s) to a peripheral B and enable pull-up.
|
||||
*
|
||||
* @remark During Reset, all PORT lines are configured as inputs with input
|
||||
* buffers, output buffers and pull disabled. When the device is set to the
|
||||
* BACKUP sleep mode, even if the PORT configuration registers and input
|
||||
* synchronizers will lose their contents (these will not be restored when
|
||||
* PORT is powered up again), the latches in the pads will keep their current
|
||||
* configuration, such as the output value and pull settings. Refer to the
|
||||
* Power Manager documentation for more features related to the I/O lines
|
||||
* configuration in and out of BACKUP mode. The PORT peripheral will continue
|
||||
* operating in any Sleep mode where its source clock is running.
|
||||
*
|
||||
* @param pin pin's configuration data such as pin mask, pin attributes, etc.
|
||||
*/
|
||||
void soc_port_configure(const struct soc_port_pin *pin);
|
||||
|
||||
/**
|
||||
* @brief Configure a list of PORT pin(s).
|
||||
*
|
||||
* Configure an arbitrary amount of pins in an arbitrary way. Each
|
||||
* configuration entry is a single item in an array passed as an argument to
|
||||
* the function.
|
||||
*
|
||||
* @param pins an array where each item contains pin's configuration data.
|
||||
* @param size size of the pin list.
|
||||
*/
|
||||
void soc_port_list_configure(const struct soc_port_pin pins[],
|
||||
unsigned int size);
|
||||
|
||||
#endif /* ATMEL_SAM0_SOC_PORT_H_ */
|
||||
52
soc/atmel/sam0/common/soc_samc2x.c
Normal file
52
soc/atmel/sam0/common/soc_samc2x.c
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Kamil Serwus
|
||||
* Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Atmel SAMC MCU series initialization code
|
||||
*/
|
||||
|
||||
#include <zephyr/device.h>
|
||||
#include <zephyr/init.h>
|
||||
#include <zephyr/kernel.h>
|
||||
#include <soc.h>
|
||||
|
||||
static void flash_waitstates_init(void)
|
||||
{
|
||||
/* One wait state at 48 MHz. */
|
||||
NVMCTRL->CTRLB.bit.RWS = NVMCTRL_CTRLB_RWS_HALF_Val;
|
||||
}
|
||||
|
||||
static void osc48m_init(void)
|
||||
{
|
||||
/* Turn off the prescaler */
|
||||
OSCCTRL->OSC48MDIV.bit.DIV = 0;
|
||||
while (OSCCTRL->OSC48MSYNCBUSY.bit.OSC48MDIV) {
|
||||
}
|
||||
while (!OSCCTRL->STATUS.bit.OSC48MRDY) {
|
||||
}
|
||||
}
|
||||
|
||||
static void mclk_init(void)
|
||||
{
|
||||
MCLK->CPUDIV.reg = MCLK_CPUDIV_CPUDIV_DIV1_Val;
|
||||
}
|
||||
|
||||
static void gclks_init(void)
|
||||
{
|
||||
GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSC48M)
|
||||
| GCLK_GENCTRL_DIV(1)
|
||||
| GCLK_GENCTRL_GENEN;
|
||||
}
|
||||
|
||||
void z_arm_platform_init(void)
|
||||
{
|
||||
flash_waitstates_init();
|
||||
osc48m_init();
|
||||
mclk_init();
|
||||
gclks_init();
|
||||
}
|
||||
301
soc/atmel/sam0/common/soc_samd2x.c
Normal file
301
soc/atmel/sam0/common/soc_samd2x.c
Normal file
|
|
@ -0,0 +1,301 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Google LLC.
|
||||
* Copyright (c) 2023 Ionut Catalin Pavel <iocapa@iocapa.com>
|
||||
* Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Atmel SAMD MCU series initialization code
|
||||
*/
|
||||
|
||||
/* The CPU clock will be configured to the DT requested value,
|
||||
* and run via DFLL48M.
|
||||
*
|
||||
* Reference -> GCLK Gen 1 -> DFLL48M -> GCLK Gen 0 -> GCLK_MAIN
|
||||
*
|
||||
* GCLK Gen 0 -> GCLK_MAIN
|
||||
* GCLK Gen 1 -> DFLL48M (variable)
|
||||
* GCLK Gen 2 -> WDT @ 32768 Hz
|
||||
* GCLK Gen 3 -> ADC @ 8 MHz
|
||||
*/
|
||||
|
||||
#include <zephyr/device.h>
|
||||
#include <zephyr/init.h>
|
||||
#include <zephyr/kernel.h>
|
||||
|
||||
#include <soc.h>
|
||||
#include <cmsis_core.h>
|
||||
|
||||
/**
|
||||
* Fix different naming conventions for SAMD20
|
||||
*/
|
||||
#ifdef FUSES_OSC32KCAL_ADDR
|
||||
#define FUSES_OSC32K_CAL_ADDR FUSES_OSC32KCAL_ADDR
|
||||
#define FUSES_OSC32K_CAL_Pos FUSES_OSC32KCAL_Pos
|
||||
#define FUSES_OSC32K_CAL_Msk FUSES_OSC32KCAL_Msk
|
||||
#endif
|
||||
|
||||
static inline void osc8m_init(void)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
/* Save calibration */
|
||||
reg = SYSCTRL->OSC8M.reg
|
||||
& (SYSCTRL_OSC8M_FRANGE_Msk | SYSCTRL_OSC8M_CALIB_Msk);
|
||||
|
||||
SYSCTRL->OSC8M.reg = reg
|
||||
| SYSCTRL_OSC8M_RUNSTDBY
|
||||
| SYSCTRL_OSC8M_PRESC(0) /* 8MHz (/1) */
|
||||
| SYSCTRL_OSC8M_ENABLE;
|
||||
|
||||
while (!SYSCTRL->PCLKSR.bit.OSC8MRDY) {
|
||||
}
|
||||
|
||||
/* Use 8Mhz clock as gclk_main to allow switching between clocks
|
||||
* when using bootloaders
|
||||
*/
|
||||
GCLK->GENDIV.reg = GCLK_GENDIV_ID(0)
|
||||
| GCLK_GENDIV_DIV(0);
|
||||
|
||||
while (GCLK->STATUS.bit.SYNCBUSY) {
|
||||
}
|
||||
|
||||
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(0)
|
||||
| GCLK_GENCTRL_SRC_OSC8M
|
||||
| GCLK_GENCTRL_IDC
|
||||
| GCLK_GENCTRL_GENEN;
|
||||
|
||||
while (GCLK->STATUS.bit.SYNCBUSY) {
|
||||
}
|
||||
}
|
||||
|
||||
#if !CONFIG_SOC_ATMEL_SAMD_OSC32K || CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN
|
||||
#define osc32k_init()
|
||||
#else
|
||||
static inline void osc32k_init(void)
|
||||
{
|
||||
uint32_t cal;
|
||||
|
||||
/* Get calibration value */
|
||||
cal = (*((uint32_t *)FUSES_OSC32K_CAL_ADDR)
|
||||
& FUSES_OSC32K_CAL_Msk) >> FUSES_OSC32K_CAL_Pos;
|
||||
|
||||
SYSCTRL->OSC32K.reg = SYSCTRL_OSC32K_CALIB(cal)
|
||||
| SYSCTRL_OSC32K_STARTUP(0x5) /* 34 cycles / ~1ms */
|
||||
| SYSCTRL_OSC32K_RUNSTDBY
|
||||
| SYSCTRL_OSC32K_EN32K
|
||||
| SYSCTRL_OSC32K_ENABLE;
|
||||
|
||||
while (!SYSCTRL->PCLKSR.bit.OSC32KRDY) {
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !CONFIG_SOC_ATMEL_SAMD_XOSC || CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN
|
||||
#define xosc_init()
|
||||
#else
|
||||
static inline void xosc_init(void)
|
||||
{
|
||||
SYSCTRL->XOSC.reg = SYSCTRL_XOSC_STARTUP(0x5) /* 32 cycles / ~1ms */
|
||||
| SYSCTRL_XOSC_RUNSTDBY
|
||||
| SYSCTRL_XOSC_AMPGC
|
||||
#if CONFIG_SOC_ATMEL_SAMD_XOSC_FREQ_HZ <= 2000000
|
||||
| SYSCTRL_XOSC_GAIN(0x0)
|
||||
#elif CONFIG_SOC_ATMEL_SAMD_XOSC_FREQ_HZ <= 4000000
|
||||
| SYSCTRL_XOSC_GAIN(0x1)
|
||||
#elif CONFIG_SOC_ATMEL_SAMD_XOSC_FREQ_HZ <= 8000000
|
||||
| SYSCTRL_XOSC_GAIN(0x2)
|
||||
#elif CONFIG_SOC_ATMEL_SAMD_XOSC_FREQ_HZ <= 16000000
|
||||
| SYSCTRL_XOSC_GAIN(0x3)
|
||||
#elif CONFIG_SOC_ATMEL_SAMD_XOSC_FREQ_HZ <= 32000000
|
||||
| SYSCTRL_XOSC_GAIN(0x4)
|
||||
#endif
|
||||
#if CONFIG_SOC_ATMEL_SAMD_XOSC_CRYSTAL
|
||||
| SYSCTRL_XOSC_XTALEN
|
||||
#endif
|
||||
| SYSCTRL_XOSC_ENABLE;
|
||||
|
||||
while (!SYSCTRL->PCLKSR.bit.XOSCRDY) {
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !CONFIG_SOC_ATMEL_SAMD_XOSC32K || CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN
|
||||
#define xosc32k_init()
|
||||
#else
|
||||
static inline void xosc32k_init(void)
|
||||
{
|
||||
SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_STARTUP(0x1) /* 4096 cycles / ~0.13s */
|
||||
| SYSCTRL_XOSC32K_RUNSTDBY
|
||||
| SYSCTRL_XOSC32K_EN32K
|
||||
| SYSCTRL_XOSC32K_AAMPEN
|
||||
#if CONFIG_SOC_ATMEL_SAMD_XOSC32K_CRYSTAL
|
||||
| SYSCTRL_XOSC32K_XTALEN
|
||||
#endif
|
||||
| SYSCTRL_XOSC32K_ENABLE;
|
||||
|
||||
while (!SYSCTRL->PCLKSR.bit.XOSC32KRDY) {
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN
|
||||
#define dfll48m_init()
|
||||
#else
|
||||
static inline void dfll48m_init(void)
|
||||
{
|
||||
uint32_t fcal, ccal;
|
||||
|
||||
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(1)
|
||||
#if CONFIG_SOC_ATMEL_SAMD_OSC32K_AS_MAIN
|
||||
| GCLK_GENCTRL_SRC_OSC32K
|
||||
#elif CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN
|
||||
| GCLK_GENCTRL_SRC_XOSC32K
|
||||
#elif CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN
|
||||
| GCLK_GENCTRL_SRC_OSC8M
|
||||
#elif CONFIG_SOC_ATMEL_SAMD_XOSC_AS_MAIN
|
||||
| GCLK_GENCTRL_SRC_XOSC
|
||||
#endif
|
||||
| GCLK_GENCTRL_IDC
|
||||
| GCLK_GENCTRL_RUNSTDBY
|
||||
| GCLK_GENCTRL_GENEN;
|
||||
|
||||
while (GCLK->STATUS.bit.SYNCBUSY) {
|
||||
}
|
||||
|
||||
GCLK->GENDIV.reg = GCLK_GENDIV_ID(1)
|
||||
| GCLK_GENDIV_DIV(SOC_ATMEL_SAM0_GCLK1_DIV);
|
||||
|
||||
while (GCLK->STATUS.bit.SYNCBUSY) {
|
||||
}
|
||||
|
||||
/* Route multiplexer 0 to DFLL48M */
|
||||
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(0)
|
||||
| GCLK_CLKCTRL_GEN_GCLK1
|
||||
| GCLK_CLKCTRL_CLKEN;
|
||||
|
||||
|
||||
SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_MODE
|
||||
| SYSCTRL_DFLLCTRL_QLDIS
|
||||
| SYSCTRL_DFLLCTRL_RUNSTDBY;
|
||||
|
||||
/* Get calibration values */
|
||||
ccal = (*((uint32_t *)FUSES_DFLL48M_COARSE_CAL_ADDR)
|
||||
& FUSES_DFLL48M_COARSE_CAL_Msk) >> FUSES_DFLL48M_COARSE_CAL_Pos;
|
||||
|
||||
fcal = (*((uint32_t *)FUSES_DFLL48M_FINE_CAL_ADDR)
|
||||
& FUSES_DFLL48M_FINE_CAL_Msk) >> FUSES_DFLL48M_FINE_CAL_Pos;
|
||||
|
||||
SYSCTRL->DFLLVAL.reg = SYSCTRL_DFLLVAL_COARSE(ccal)
|
||||
| SYSCTRL_DFLLVAL_FINE(fcal);
|
||||
|
||||
/* Use half of maximum for both */
|
||||
SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP(31)
|
||||
| SYSCTRL_DFLLMUL_FSTEP(511)
|
||||
| SYSCTRL_DFLLMUL_MUL(SOC_ATMEL_SAM0_DFLL48M_MUL);
|
||||
|
||||
/* Enable */
|
||||
while (!SYSCTRL->PCLKSR.bit.DFLLRDY) {
|
||||
}
|
||||
SYSCTRL->DFLLCTRL.bit.ENABLE = 1;
|
||||
|
||||
/* Wait for synchronization. */
|
||||
while (!SYSCTRL->PCLKSR.bit.DFLLLCKC || !SYSCTRL->PCLKSR.bit.DFLLLCKF) {
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN
|
||||
#define flash_waitstates_init()
|
||||
#else
|
||||
static inline void flash_waitstates_init(void)
|
||||
{
|
||||
NVMCTRL->CTRLB.bit.RWS = NVMCTRL_CTRLB_RWS(CONFIG_SOC_ATMEL_SAMD_NVM_WAIT_STATES);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN
|
||||
#define gclk_main_configure()
|
||||
#else
|
||||
static inline void gclk_main_configure(void)
|
||||
{
|
||||
GCLK->GENDIV.reg = GCLK_GENDIV_ID(0)
|
||||
| GCLK_GENDIV_DIV(SOC_ATMEL_SAM0_GCLK0_DIV);
|
||||
|
||||
while (GCLK->STATUS.bit.SYNCBUSY) {
|
||||
}
|
||||
|
||||
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(0)
|
||||
| GCLK_GENCTRL_SRC_DFLL48M
|
||||
| GCLK_GENCTRL_IDC
|
||||
| GCLK_GENCTRL_GENEN;
|
||||
|
||||
while (GCLK->STATUS.bit.SYNCBUSY) {
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !CONFIG_ADC_SAM0 || CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN
|
||||
#define gclk_adc_configure()
|
||||
#else
|
||||
static inline void gclk_adc_configure(void)
|
||||
{
|
||||
GCLK->GENDIV.reg = GCLK_GENDIV_ID(3)
|
||||
| GCLK_GENDIV_DIV(SOC_ATMEL_SAM0_GCLK3_DIV);
|
||||
|
||||
while (GCLK->STATUS.bit.SYNCBUSY) {
|
||||
}
|
||||
|
||||
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(3)
|
||||
| GCLK_GENCTRL_SRC_DFLL48M
|
||||
| GCLK_GENCTRL_IDC
|
||||
| GCLK_GENCTRL_GENEN;
|
||||
|
||||
while (GCLK->STATUS.bit.SYNCBUSY) {
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !CONFIG_WDT_SAM0
|
||||
#define gclk_wdt_configure()
|
||||
#else
|
||||
static inline void gclk_wdt_configure(void)
|
||||
{
|
||||
GCLK->GENDIV.reg = GCLK_GENDIV_ID(2)
|
||||
| GCLK_GENDIV_DIV(4);
|
||||
|
||||
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(2)
|
||||
| GCLK_GENCTRL_GENEN
|
||||
| GCLK_GENCTRL_SRC_OSCULP32K
|
||||
| GCLK_GENCTRL_DIVSEL;
|
||||
|
||||
while (GCLK->STATUS.bit.SYNCBUSY) {
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if CONFIG_SOC_ATMEL_SAMD_OSC8M || CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN
|
||||
#define osc8m_disable()
|
||||
#else
|
||||
static inline void osc8m_disable(void)
|
||||
{
|
||||
SYSCTRL->OSC8M.bit.ENABLE = 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void z_arm_platform_init(void)
|
||||
{
|
||||
osc8m_init();
|
||||
osc32k_init();
|
||||
xosc_init();
|
||||
xosc32k_init();
|
||||
dfll48m_init();
|
||||
flash_waitstates_init();
|
||||
gclk_main_configure();
|
||||
gclk_adc_configure();
|
||||
gclk_wdt_configure();
|
||||
osc8m_disable();
|
||||
}
|
||||
139
soc/atmel/sam0/common/soc_samd5x.c
Normal file
139
soc/atmel/sam0/common/soc_samd5x.c
Normal file
|
|
@ -0,0 +1,139 @@
|
|||
/*
|
||||
* Copyright (c) 2019 ML!PA Consulting GmbH
|
||||
* Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Atmel SAMD MCU series initialization code
|
||||
*/
|
||||
|
||||
#include <zephyr/device.h>
|
||||
#include <zephyr/init.h>
|
||||
#include <zephyr/kernel.h>
|
||||
#include <soc.h>
|
||||
|
||||
#define SAM0_DFLL_FREQ_HZ (48000000U)
|
||||
#define SAM0_DPLL_FREQ_MIN_HZ (96000000U)
|
||||
#define SAM0_DPLL_FREQ_MAX_HZ (200000000U)
|
||||
|
||||
#if CONFIG_SOC_ATMEL_SAMD5X_XOSC32K_AS_MAIN
|
||||
static void osc32k_init(void)
|
||||
{
|
||||
OSC32KCTRL->XOSC32K.reg = OSC32KCTRL_XOSC32K_ENABLE | OSC32KCTRL_XOSC32K_XTALEN
|
||||
| OSC32KCTRL_XOSC32K_EN32K | OSC32KCTRL_XOSC32K_RUNSTDBY
|
||||
| OSC32KCTRL_XOSC32K_STARTUP(7);
|
||||
|
||||
while (!OSC32KCTRL->STATUS.bit.XOSC32KRDY) {
|
||||
}
|
||||
|
||||
GCLK->GENCTRL[1].reg = GCLK_GENCTRL_SRC(GCLK_SOURCE_XOSC32K)
|
||||
| GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN;
|
||||
|
||||
}
|
||||
#elif CONFIG_SOC_ATMEL_SAMD5X_OSCULP32K_AS_MAIN
|
||||
static void osc32k_init(void)
|
||||
{
|
||||
GCLK->GENCTRL[1].reg = GCLK_GENCTRL_SRC(GCLK_SOURCE_OSCULP32K)
|
||||
| GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN;
|
||||
}
|
||||
#else
|
||||
#error "No Clock Source selected."
|
||||
#endif
|
||||
|
||||
static void dpll_init(uint8_t n, uint32_t f_cpu)
|
||||
{
|
||||
/* We source the DPLL from 32kHz GCLK1 */
|
||||
const uint32_t LDR = ((f_cpu << 5) / SOC_ATMEL_SAM0_OSC32K_FREQ_HZ);
|
||||
|
||||
/* disable the DPLL before changing the configuration */
|
||||
OSCCTRL->Dpll[n].DPLLCTRLA.bit.ENABLE = 0;
|
||||
while (OSCCTRL->Dpll[n].DPLLSYNCBUSY.reg) {
|
||||
}
|
||||
|
||||
/* set DPLL clock source to 32kHz GCLK1 */
|
||||
GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0 + n].reg = GCLK_PCHCTRL_GEN(1) | GCLK_PCHCTRL_CHEN;
|
||||
while (!(GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0 + n].reg & GCLK_PCHCTRL_CHEN)) {
|
||||
}
|
||||
|
||||
OSCCTRL->Dpll[n].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(LDR & 0x1F)
|
||||
| OSCCTRL_DPLLRATIO_LDR((LDR >> 5) - 1);
|
||||
|
||||
/* Without LBYPASS, startup takes very long, see errata section 2.13. */
|
||||
OSCCTRL->Dpll[n].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK_GCLK
|
||||
| OSCCTRL_DPLLCTRLB_WUF
|
||||
| OSCCTRL_DPLLCTRLB_LBYPASS;
|
||||
|
||||
OSCCTRL->Dpll[n].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE;
|
||||
|
||||
while (OSCCTRL->Dpll[n].DPLLSYNCBUSY.reg) {
|
||||
}
|
||||
while (!(OSCCTRL->Dpll[n].DPLLSTATUS.bit.CLKRDY &&
|
||||
OSCCTRL->Dpll[n].DPLLSTATUS.bit.LOCK)) {
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static void dfll_init(void)
|
||||
{
|
||||
uint32_t reg = OSCCTRL_DFLLCTRLB_QLDIS
|
||||
#ifdef OSCCTRL_DFLLCTRLB_WAITLOCK
|
||||
| OSCCTRL_DFLLCTRLB_WAITLOCK
|
||||
#endif
|
||||
;
|
||||
|
||||
OSCCTRL->DFLLCTRLB.reg = reg;
|
||||
OSCCTRL->DFLLCTRLA.reg = OSCCTRL_DFLLCTRLA_ENABLE;
|
||||
|
||||
while (!OSCCTRL->STATUS.bit.DFLLRDY) {
|
||||
}
|
||||
}
|
||||
|
||||
static void gclk_reset(void)
|
||||
{
|
||||
GCLK->CTRLA.bit.SWRST = 1;
|
||||
while (GCLK->SYNCBUSY.bit.SWRST) {
|
||||
}
|
||||
}
|
||||
|
||||
static void gclk_connect(uint8_t gclk, uint8_t src, uint8_t div)
|
||||
{
|
||||
GCLK->GENCTRL[gclk].reg = GCLK_GENCTRL_SRC(src)
|
||||
| GCLK_GENCTRL_DIV(div)
|
||||
| GCLK_GENCTRL_GENEN;
|
||||
}
|
||||
|
||||
void z_arm_platform_init(void)
|
||||
{
|
||||
uint8_t dfll_div;
|
||||
|
||||
if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC < SAM0_DFLL_FREQ_HZ) {
|
||||
dfll_div = 3;
|
||||
} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC < SAM0_DPLL_FREQ_MIN_HZ) {
|
||||
dfll_div = 2;
|
||||
} else {
|
||||
dfll_div = 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Force Cortex M Cache Controller disabled
|
||||
*
|
||||
* It is not clear if regular Cortex-M instructions can be used to
|
||||
* perform cache maintenance or this is a proprietary cache controller
|
||||
* that require special SoC support.
|
||||
*/
|
||||
CMCC->CTRL.bit.CEN = 0;
|
||||
|
||||
gclk_reset();
|
||||
osc32k_init();
|
||||
dfll_init();
|
||||
dpll_init(0, dfll_div * CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
|
||||
|
||||
/* use DPLL for main clock */
|
||||
gclk_connect(0, GCLK_SOURCE_DPLL0, dfll_div);
|
||||
|
||||
/* connect GCLK2 to 48 MHz DFLL for USB */
|
||||
gclk_connect(2, GCLK_SOURCE_DFLL48M, 0);
|
||||
}
|
||||
272
soc/atmel/sam0/common/soc_saml2x.c
Normal file
272
soc/atmel/sam0/common/soc_saml2x.c
Normal file
|
|
@ -0,0 +1,272 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Argentum Systems Ltd.
|
||||
* Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Atmel SAML MCU series initialization code
|
||||
*/
|
||||
|
||||
#include <zephyr/device.h>
|
||||
#include <zephyr/init.h>
|
||||
#include <zephyr/kernel.h>
|
||||
#include <soc.h>
|
||||
#include <cmsis_core.h>
|
||||
|
||||
/* the SAML21 currently operates only in Performance Level 2... sleep
|
||||
* and low-power operation are not currently supported by the BSP
|
||||
*
|
||||
* the CPU clock will be configured to 48 MHz, and run via DFLL48M.
|
||||
*
|
||||
* Reference -> GCLK Gen 1 -> DFLL48M -> GCLK Gen 0 -> GCLK_MAIN
|
||||
*
|
||||
* GCLK Gen 0 -> GCLK_MAIN @ 48 Mhz
|
||||
* GCLK Gen 1 -> DFLL48M (variable)
|
||||
* GCLK Gen 2 -> USB @ 48 MHz
|
||||
* GCLK Gen 3 -> ADC @ 24 MHz (further /2 in the ADC peripheral)
|
||||
*/
|
||||
|
||||
static inline void gclk_reset(void)
|
||||
{
|
||||
GCLK->CTRLA.bit.SWRST = 1;
|
||||
while (GCLK->SYNCBUSY.bit.SWRST) {
|
||||
}
|
||||
|
||||
/* by default, OSC16M will be enabled at 4 MHz, and the CPU will
|
||||
* run from it. to permit initialization, the CPU is temporarily
|
||||
* clocked from OSCULP32K, and OSC16M is disabled
|
||||
*/
|
||||
GCLK->GENCTRL[0].bit.SRC = GCLK_GENCTRL_SRC_OSCULP32K_Val;
|
||||
OSCCTRL->OSC16MCTRL.bit.ENABLE = 0;
|
||||
}
|
||||
|
||||
#if !CONFIG_SOC_ATMEL_SAML_OSC32K
|
||||
#define osc32k_init()
|
||||
#else
|
||||
static inline void osc32k_init(void)
|
||||
{
|
||||
uint32_t cal;
|
||||
|
||||
/* OSC32KCAL is in NVMCTRL_OTP5[12:6] */
|
||||
cal = *((uint32_t *)NVMCTRL_OTP5);
|
||||
cal >>= 6;
|
||||
cal &= (1 << 7) - 1;
|
||||
|
||||
OSC32KCTRL->OSC32K.reg = 0
|
||||
| OSC32KCTRL_OSC32K_CALIB(cal)
|
||||
| OSC32KCTRL_OSC32K_STARTUP(0x5) /* 34 cycles / ~1.038ms */
|
||||
| !OSC32KCTRL_OSC32K_ONDEMAND
|
||||
| OSC32KCTRL_OSC32K_RUNSTDBY
|
||||
| OSC32KCTRL_OSC32K_EN32K
|
||||
| OSC32KCTRL_OSC32K_ENABLE;
|
||||
|
||||
/* wait for ready */
|
||||
while (!OSC32KCTRL->STATUS.bit.OSC32KRDY) {
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !CONFIG_SOC_ATMEL_SAML_XOSC32K
|
||||
#define xosc32k_init()
|
||||
#else
|
||||
static inline void xosc32k_init(void)
|
||||
{
|
||||
OSC32KCTRL->XOSC32K.reg = 0
|
||||
| OSC32KCTRL_XOSC32K_STARTUP(0x1) /* 4096 cycles / ~0.13s */
|
||||
| !OSC32KCTRL_XOSC32K_ONDEMAND
|
||||
| OSC32KCTRL_XOSC32K_RUNSTDBY
|
||||
| OSC32KCTRL_XOSC32K_EN32K
|
||||
#if CONFIG_SOC_ATMEL_SAML_XOSC32K_CRYSTAL
|
||||
| OSC32KCTRL_XOSC32K_XTALEN
|
||||
#endif
|
||||
| OSC32KCTRL_XOSC32K_ENABLE;
|
||||
|
||||
/* wait for ready */
|
||||
while (!OSC32KCTRL->STATUS.bit.XOSC32KRDY) {
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !CONFIG_SOC_ATMEL_SAML_OSC16M
|
||||
#define osc16m_init()
|
||||
#else
|
||||
static inline void osc16m_init(void)
|
||||
{
|
||||
OSCCTRL->OSC16MCTRL.reg = 0
|
||||
| !OSCCTRL_OSC16MCTRL_ONDEMAND
|
||||
| OSCCTRL_OSC16MCTRL_RUNSTDBY
|
||||
| OSCCTRL_OSC16MCTRL_FSEL_16
|
||||
| OSCCTRL_OSC16MCTRL_ENABLE;
|
||||
|
||||
/* wait for ready */
|
||||
while (!OSCCTRL->STATUS.bit.OSC16MRDY) {
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/* TODO: use CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC ?? */
|
||||
static inline void dfll48m_init(void)
|
||||
{
|
||||
uint32_t cal;
|
||||
|
||||
/* setup the reference clock (if any) */
|
||||
GCLK->GENCTRL[1].reg = 0
|
||||
#if CONFIG_SOC_ATMEL_SAML_OSC32K_AS_MAIN
|
||||
| GCLK_GENCTRL_SRC_OSC32K
|
||||
#elif CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN
|
||||
| GCLK_GENCTRL_SRC_XOSC32K
|
||||
#elif CONFIG_SOC_ATMEL_SAML_OSC16M_AS_MAIN
|
||||
/* configure Fout = Fin / 2^(DIV+1) = 31.25 kHz
|
||||
* Fgclk_dfll48m_ref max is 33 kHz
|
||||
*/
|
||||
| GCLK_GENCTRL_DIV(8)
|
||||
| GCLK_GENCTRL_DIVSEL
|
||||
| GCLK_GENCTRL_SRC_OSC16M
|
||||
#endif
|
||||
#if !CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN
|
||||
| GCLK_GENCTRL_RUNSTDBY
|
||||
| GCLK_GENCTRL_GENEN
|
||||
#endif
|
||||
;
|
||||
|
||||
#if !CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN
|
||||
/* configure and enable the generator & peripheral channel */
|
||||
GCLK->PCHCTRL[0].reg = 0
|
||||
| GCLK_PCHCTRL_CHEN
|
||||
| GCLK_PCHCTRL_GEN_GCLK1;
|
||||
#endif
|
||||
|
||||
/* --- */
|
||||
|
||||
/* if the target frequency is 48 MHz, then the calibration value can be used to
|
||||
* decrease the time until the coarse lock is acquired. this is loaded from
|
||||
* NVMCTRL_OTP5[31:26]
|
||||
*/
|
||||
cal = *((uint32_t *)NVMCTRL_OTP5);
|
||||
cal >>= 26;
|
||||
cal &= (1 << 6) - 1;
|
||||
|
||||
OSCCTRL->DFLLCTRL.reg = 0
|
||||
| OSCCTRL_DFLLCTRL_QLDIS
|
||||
| !OSCCTRL_DFLLCTRL_ONDEMAND
|
||||
| OSCCTRL_DFLLCTRL_RUNSTDBY
|
||||
#if !CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN
|
||||
| OSCCTRL_DFLLCTRL_MODE
|
||||
#endif
|
||||
;
|
||||
|
||||
OSCCTRL->DFLLVAL.reg = 0
|
||||
| OSCCTRL_DFLLVAL_COARSE(cal)
|
||||
| OSCCTRL_DFLLVAL_FINE(512) /* use 50% */
|
||||
;
|
||||
|
||||
OSCCTRL->DFLLMUL.reg = 0
|
||||
/* use 25% of maximum value for the coarse and fine step
|
||||
* ... I couldn't find details on the inner workings of the DFLL, or any
|
||||
* example values for these - I have seen others using ~50%. hopefully these
|
||||
* values will provide a good balance between startup time and overshoot
|
||||
*/
|
||||
| OSCCTRL_DFLLMUL_CSTEP(16)
|
||||
| OSCCTRL_DFLLMUL_FSTEP(256)
|
||||
#if CONFIG_SOC_ATMEL_SAML_OSC32K_AS_MAIN || CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN
|
||||
/* use a 32.768 kHz reference ... 48e6 / 32,768 = 1,464.843... */
|
||||
| OSCCTRL_DFLLMUL_MUL(1465)
|
||||
#elif CONFIG_SOC_ATMEL_SAML_OSC16M_AS_MAIN
|
||||
/* use a 16 MHz -> 31.25 kHz reference... 48e6 / 31,250 = 1,536
|
||||
* a small value can make the DFLL unstable, hence not using the
|
||||
* 16 MHz source directly
|
||||
*/
|
||||
| OSCCTRL_DFLLMUL_MUL(1536)
|
||||
#endif
|
||||
;
|
||||
|
||||
/* --- */
|
||||
|
||||
/* enable */
|
||||
while (!OSCCTRL->STATUS.bit.DFLLRDY) {
|
||||
}
|
||||
OSCCTRL->DFLLCTRL.bit.ENABLE = 1;
|
||||
|
||||
#if !CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN
|
||||
/* wait for ready... note in open loop mode, we won't get a lock */
|
||||
while (!OSCCTRL->STATUS.bit.DFLLLCKC || !OSCCTRL->STATUS.bit.DFLLLCKF) {
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void flash_waitstates_init(void)
|
||||
{
|
||||
/* PL2, >= 2.7v, 48MHz = 2 wait states */
|
||||
NVMCTRL->CTRLB.bit.RWS = 2;
|
||||
}
|
||||
|
||||
static inline void pm_init(void)
|
||||
{
|
||||
PM->PLCFG.bit.PLDIS = 0;
|
||||
PM->PLCFG.bit.PLSEL = 2;
|
||||
}
|
||||
|
||||
static inline void gclk_main_configure(void)
|
||||
{
|
||||
/* finally, switch the CPU over to run from DFLL48M */
|
||||
GCLK->GENCTRL[0].bit.SRC = GCLK_GENCTRL_SRC_DFLL48M_Val;
|
||||
}
|
||||
|
||||
#if !CONFIG_USB_DC_SAM0
|
||||
#define gclk_usb_configure()
|
||||
#else
|
||||
static inline void gclk_usb_configure(void)
|
||||
{
|
||||
GCLK->GENCTRL[2].reg = 0
|
||||
| GCLK_GENCTRL_SRC_DFLL48M
|
||||
| GCLK_GENCTRL_DIV(1)
|
||||
| GCLK_GENCTRL_GENEN;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !CONFIG_ADC_SAM0
|
||||
#define gclk_adc_configure()
|
||||
#else
|
||||
static inline void gclk_adc_configure(void)
|
||||
{
|
||||
GCLK->GENCTRL[3].reg = 0
|
||||
| GCLK_GENCTRL_SRC_DFLL48M
|
||||
| GCLK_GENCTRL_DIV(2)
|
||||
| GCLK_GENCTRL_GENEN;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if CONFIG_SOC_ATMEL_SAML_DEBUG_PAUSE
|
||||
static inline void pause_for_debug(void)
|
||||
{
|
||||
/* for some reason, when attempting to flash / debug the target, the operations
|
||||
* will time out... I suspect this is due to clock configuration, so instead of
|
||||
* doing this immediately, we defer startup for a while to permit the debugger
|
||||
* to jump in and interrupt us. ick
|
||||
*/
|
||||
for (uint32_t i = 0; i < 10000; i += 1) {
|
||||
__asm__ volatile ("nop\n");
|
||||
}
|
||||
}
|
||||
#else
|
||||
static inline void pause_for_debug(void) {}
|
||||
#endif
|
||||
|
||||
void z_arm_platform_init(void)
|
||||
{
|
||||
pause_for_debug();
|
||||
|
||||
gclk_reset();
|
||||
osc32k_init();
|
||||
xosc32k_init();
|
||||
osc16m_init();
|
||||
dfll48m_init();
|
||||
flash_waitstates_init();
|
||||
pm_init();
|
||||
gclk_main_configure();
|
||||
gclk_usb_configure();
|
||||
gclk_adc_configure();
|
||||
}
|
||||
34
soc/atmel/sam0/common/soc_samr3x_radio_off.c
Normal file
34
soc/atmel/sam0/common/soc_samr3x_radio_off.c
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Argentum Systems Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/drivers/gpio.h>
|
||||
#include <zephyr/init.h>
|
||||
|
||||
static int radio_off_setup(void)
|
||||
{
|
||||
int ret;
|
||||
const struct gpio_dt_spec reset = GPIO_DT_SPEC_GET(DT_NODELABEL(lora), reset_gpios);
|
||||
const struct gpio_dt_spec cs = GPIO_DT_SPEC_GET(DT_NODELABEL(sercom4), cs_gpios);
|
||||
|
||||
if (!gpio_is_ready_dt(&reset) || !gpio_is_ready_dt(&cs)) {
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ret = gpio_pin_configure_dt(&reset, GPIO_OUTPUT_ACTIVE);
|
||||
if (ret < 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = gpio_pin_configure_dt(&cs, GPIO_OUTPUT_INACTIVE);
|
||||
if (ret < 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(radio_off_setup, PRE_KERNEL_1, 99);
|
||||
73
soc/atmel/sam0/common/tc_fixup_samd5x.h
Normal file
73
soc/atmel/sam0/common/tc_fixup_samd5x.h
Normal file
|
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* Copyright (c) 2019 ML!PA Consulting GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifdef MCLK_APBAMASK_TC0
|
||||
#define MCLK_TC0 (&MCLK->APBAMASK.reg)
|
||||
#define MCLK_TC0_MASK ((1 << MCLK_APBAMASK_TC0_Pos) | (1 << MCLK_APBAMASK_TC1_Pos))
|
||||
#endif
|
||||
#ifdef MCLK_APBBMASK_TC0
|
||||
#define MCLK_TC0 (&MCLK->APBBMASK.reg)
|
||||
#define MCLK_TC0_MASK ((1 << MCLK_APBBMASK_TC0_Pos) | (1 << MCLK_APBBMASK_TC1_Pos))
|
||||
#endif
|
||||
#ifdef MCLK_APBCMASK_TC0
|
||||
#define MCLK_TC0 (&MCLK->APBCMASK.reg)
|
||||
#define MCLK_TC0_MASK ((1 << MCLK_APBCMASK_TC0_Pos) | (1 << MCLK_APBCMASK_TC1_Pos))
|
||||
#endif
|
||||
#ifdef MCLK_APBDMASK_TC0
|
||||
#define MCLK_TC0 (&MCLK->APBDMASK.reg)
|
||||
#define MCLK_TC0_MASK ((1 << MCLK_APBDMASK_TC0_Pos) | (1 << MCLK_APBDMASK_TC1_Pos))
|
||||
#endif
|
||||
|
||||
#ifdef MCLK_APBAMASK_TC2
|
||||
#define MCLK_TC2 (&MCLK->APBAMASK.reg)
|
||||
#define MCLK_TC2_MASK ((1 << MCLK_APBAMASK_TC2_Pos) | (1 << MCLK_APBAMASK_TC3_Pos))
|
||||
#endif
|
||||
#ifdef MCLK_APBBMASK_TC2
|
||||
#define MCLK_TC2 (&MCLK->APBBMASK.reg)
|
||||
#define MCLK_TC2_MASK ((1 << MCLK_APBBMASK_TC2_Pos) | (1 << MCLK_APBBMASK_TC3_Pos))
|
||||
#endif
|
||||
#ifdef MCLK_APBCMASK_TC2
|
||||
#define MCLK_TC2 (&MCLK->APBCMASK.reg)
|
||||
#define MCLK_TC2_MASK ((1 << MCLK_APBCMASK_TC2_Pos) | (1 << MCLK_APBCMASK_TC3_Pos))
|
||||
#endif
|
||||
#ifdef MCLK_APBDMASK_TC2
|
||||
#define MCLK_TC2 (&MCLK->APBDMASK.reg)
|
||||
#define MCLK_TC2_MASK ((1 << MCLK_APBDMASK_TC2_Pos) | (1 << MCLK_APBDMASK_TC3_Pos))
|
||||
#endif
|
||||
|
||||
#ifdef MCLK_APBAMASK_TC4
|
||||
#define MCLK_TC4 (&MCLK->APBAMASK.reg)
|
||||
#define MCLK_TC4_MASK ((1 << MCLK_APBAMASK_TC4_Pos) | (1 << MCLK_APBAMASK_TC5_Pos))
|
||||
#endif
|
||||
#ifdef MCLK_APBBMASK_TC4
|
||||
#define MCLK_TC4 (&MCLK->APBBMASK.reg)
|
||||
#define MCLK_TC4_MASK ((1 << MCLK_APBBMASK_TC4_Pos) | (1 << MCLK_APBBMASK_TC5_Pos))
|
||||
#endif
|
||||
#ifdef MCLK_APBCMASK_TC4
|
||||
#define MCLK_TC4 (&MCLK->APBCMASK.reg)
|
||||
#define MCLK_TC4_MASK ((1 << MCLK_APBCMASK_TC4_Pos) | (1 << MCLK_APBCMASK_TC5_Pos))
|
||||
#endif
|
||||
#ifdef MCLK_APBDMASK_TC4
|
||||
#define MCLK_TC4 (&MCLK->APBDMASK.reg)
|
||||
#define MCLK_TC4_MASK ((1 << MCLK_APBDMASK_TC4_Pos) | (1 << MCLK_APBDMASK_TC5_Pos))
|
||||
#endif
|
||||
|
||||
#ifdef MCLK_APBAMASK_TC6
|
||||
#define MCLK_TC6 (&MCLK->APBAMASK.reg)
|
||||
#define MCLK_TC6_MASK ((1 << MCLK_APBAMASK_TC6_Pos) | (1 << MCLK_APBAMASK_TC7_Pos))
|
||||
#endif
|
||||
#ifdef MCLK_APBBMASK_TC6
|
||||
#define MCLK_TC6 (&MCLK->APBBMASK.reg)
|
||||
#define MCLK_TC6_MASK ((1 << MCLK_APBBMASK_TC6_Pos) | (1 << MCLK_APBBMASK_TC7_Pos))
|
||||
#endif
|
||||
#ifdef MCLK_APBCMASK_TC6
|
||||
#define MCLK_TC6 (&MCLK->APBCMASK.reg)
|
||||
#define MCLK_TC6_MASK ((1 << MCLK_APBCMASK_TC6_Pos) | (1 << MCLK_APBCMASK_TC7_Pos))
|
||||
#endif
|
||||
#ifdef MCLK_APBDMASK_TC6
|
||||
#define MCLK_TC6 (&MCLK->APBDMASK.reg)
|
||||
#define MCLK_TC6_MASK ((1 << MCLK_APBDMASK_TC6_Pos) | (1 << MCLK_APBDMASK_TC7_Pos))
|
||||
#endif
|
||||
4
soc/atmel/sam0/samc20/CMakeLists.txt
Normal file
4
soc/atmel/sam0/samc20/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_include_directories(.)
|
||||
12
soc/atmel/sam0/samc20/Kconfig
Normal file
12
soc/atmel/sam0/samc20/Kconfig
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
# Atmel SAMC20 MCU series
|
||||
|
||||
# Copyright (c) 2022 Kamil Serwus
|
||||
# Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_SAMC20
|
||||
select ARM
|
||||
select CPU_CORTEX_M0PLUS
|
||||
select CPU_CORTEX_M_HAS_SYSTICK
|
||||
select CPU_CORTEX_M_HAS_VTOR
|
||||
select PLATFORM_SPECIFIC_INIT
|
||||
12
soc/atmel/sam0/samc20/Kconfig.defconfig
Normal file
12
soc/atmel/sam0/samc20/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
# Atmel SAMC20 MCU series configuration options
|
||||
|
||||
# Copyright (c) 2022 Kamil Serwus
|
||||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_SAMC20
|
||||
|
||||
config NUM_IRQS
|
||||
default 32
|
||||
|
||||
endif # SOC_SERIES_SAMC20
|
||||
98
soc/atmel/sam0/samc20/Kconfig.soc
Normal file
98
soc/atmel/sam0/samc20/Kconfig.soc
Normal file
|
|
@ -0,0 +1,98 @@
|
|||
# Atmel SAMC20 MCU series
|
||||
|
||||
# Copyright (c) 2022 Kamil Serwus
|
||||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_SAMC20
|
||||
bool
|
||||
select SOC_FAMILY_ATMEL_SAM0
|
||||
help
|
||||
Enable support for Atmel SAMC20 Cortex-M0+ microcontrollers.
|
||||
|
||||
config SOC_SERIES
|
||||
default "samc20" if SOC_SERIES_SAMC20
|
||||
|
||||
config SOC_SAMC20E15A
|
||||
bool
|
||||
select SOC_SERIES_SAMC20
|
||||
|
||||
config SOC_SAMC20E16A
|
||||
bool
|
||||
select SOC_SERIES_SAMC20
|
||||
|
||||
config SOC_SAMC20E17A
|
||||
bool
|
||||
select SOC_SERIES_SAMC20
|
||||
|
||||
config SOC_SAMC20E18A
|
||||
bool
|
||||
select SOC_SERIES_SAMC20
|
||||
|
||||
config SOC_SAMC20G15A
|
||||
bool
|
||||
select SOC_SERIES_SAMC20
|
||||
|
||||
config SOC_SAMC20G16A
|
||||
bool
|
||||
select SOC_SERIES_SAMC20
|
||||
|
||||
config SOC_SAMC20G17A
|
||||
bool
|
||||
select SOC_SERIES_SAMC20
|
||||
|
||||
config SOC_SAMC20G18A
|
||||
bool
|
||||
select SOC_SERIES_SAMC20
|
||||
|
||||
config SOC_SAMC20J15A
|
||||
bool
|
||||
select SOC_SERIES_SAMC20
|
||||
|
||||
config SOC_SAMC20J16A
|
||||
bool
|
||||
select SOC_SERIES_SAMC20
|
||||
|
||||
config SOC_SAMC20J17A
|
||||
bool
|
||||
select SOC_SERIES_SAMC20
|
||||
|
||||
config SOC_SAMC20J18A
|
||||
bool
|
||||
select SOC_SERIES_SAMC20
|
||||
|
||||
config SOC_SAMC20J17AU
|
||||
bool
|
||||
select SOC_SERIES_SAMC20
|
||||
|
||||
config SOC_SAMC20J18AU
|
||||
bool
|
||||
select SOC_SERIES_SAMC20
|
||||
|
||||
config SOC_SAMC20N17A
|
||||
bool
|
||||
select SOC_SERIES_SAMC20
|
||||
select SOC_SERIES_REVISION_N
|
||||
|
||||
config SOC_SAMC20N18A
|
||||
bool
|
||||
select SOC_SERIES_SAMC20
|
||||
select SOC_SERIES_REVISION_N
|
||||
|
||||
config SOC
|
||||
default "samc20e15a" if SOC_SAMC20E15A
|
||||
default "samc20e16a" if SOC_SAMC20E16A
|
||||
default "samc20e17a" if SOC_SAMC20E17A
|
||||
default "samc20e18a" if SOC_SAMC20E18A
|
||||
default "samc20g15a" if SOC_SAMC20G15A
|
||||
default "samc20g16a" if SOC_SAMC20G16A
|
||||
default "samc20g17a" if SOC_SAMC20G17A
|
||||
default "samc20g18a" if SOC_SAMC20G18A
|
||||
default "samc20j15a" if SOC_SAMC20J15A
|
||||
default "samc20j16a" if SOC_SAMC20J16A
|
||||
default "samc20j17a" if SOC_SAMC20J17A
|
||||
default "samc20j18a" if SOC_SAMC20J18A
|
||||
default "samc20j17au" if SOC_SAMC20J17AU
|
||||
default "samc20j18au" if SOC_SAMC20J18AU
|
||||
default "samc20n17a" if SOC_SAMC20N17A
|
||||
default "samc20n18a" if SOC_SAMC20N18A
|
||||
70
soc/atmel/sam0/samc20/soc.h
Normal file
70
soc/atmel/sam0/samc20/soc.h
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Kamil Serwus
|
||||
* Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _SOC_ATMEL_SAM0_SAMC20_SOC_H_
|
||||
#define _SOC_ATMEL_SAM0_SAMC20_SOC_H_
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#define DONT_USE_CMSIS_INIT
|
||||
|
||||
#include <zephyr/types.h>
|
||||
|
||||
#if defined(CONFIG_SOC_SAMC20E15A)
|
||||
#include <samc20e15a.h>
|
||||
#elif defined(CONFIG_SOC_SAMC20E16A)
|
||||
#include <samc20e16a.h>
|
||||
#elif defined(CONFIG_SOC_SAMC20E17A)
|
||||
#include <samc20e17a.h>
|
||||
#elif defined(CONFIG_SOC_SAMC20E18A)
|
||||
#include <samc20e18a.h>
|
||||
#elif defined(CONFIG_SOC_SAMC20G15A)
|
||||
#include <samc20g15a.h>
|
||||
#elif defined(CONFIG_SOC_SAMC20G16A)
|
||||
#include <samc20g16a.h>
|
||||
#elif defined(CONFIG_SOC_SAMC20G17A)
|
||||
#include <samc20g17a.h>
|
||||
#elif defined(CONFIG_SOC_SAMC20G18A)
|
||||
#include <samc20g18a.h>
|
||||
#elif defined(CONFIG_SOC_SAMC20J15A)
|
||||
#include <samc20j15a.h>
|
||||
#elif defined(CONFIG_SOC_SAMC20J16A)
|
||||
#include <samc20j16a.h>
|
||||
#elif defined(CONFIG_SOC_SAMC20J17A)
|
||||
#include <samc20j17a.h>
|
||||
#elif defined(CONFIG_SOC_SAMC20J18A)
|
||||
#include <samc20j18a.h>
|
||||
#elif defined(CONFIG_SOC_SAMC20J17AU)
|
||||
#include <samc20j17au.h>
|
||||
#elif defined(CONFIG_SOC_SAMC20J18AU)
|
||||
#include <samc20j18au.h>
|
||||
#elif defined(CONFIG_SOC_SAMC20N17A)
|
||||
#include <samc20n17a.h>
|
||||
#elif defined(CONFIG_SOC_SAMC20N18A)
|
||||
#include <samc20n18a.h>
|
||||
#else
|
||||
#error Library does not support the specified device.
|
||||
#endif
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#define ADC_SAM0_REFERENCE_ENABLE_PROTECTED
|
||||
|
||||
#include "adc_fixup_sam0.h"
|
||||
#include "../common/soc_port.h"
|
||||
#include "../common/atmel_sam0_dt.h"
|
||||
|
||||
#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768
|
||||
#define SOC_ATMEL_SAM0_OSC48M_FREQ_HZ 48000000
|
||||
|
||||
/** Processor Clock (HCLK) Frequency */
|
||||
#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
/** Master Clock (MCK) Frequency */
|
||||
#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ
|
||||
#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
|
||||
|
||||
#endif /* _SOC_ATMEL_SAM0_SAMC20_SOC_H_ */
|
||||
4
soc/atmel/sam0/samc21/CMakeLists.txt
Normal file
4
soc/atmel/sam0/samc21/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_include_directories(.)
|
||||
13
soc/atmel/sam0/samc21/Kconfig
Normal file
13
soc/atmel/sam0/samc21/Kconfig
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
# Atmel SAMC21 MCU series
|
||||
|
||||
# Copyright (c) 2022 Kamil Serwus
|
||||
# Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_SAMC21
|
||||
select ARM
|
||||
select CPU_CORTEX_M0PLUS
|
||||
select CPU_CORTEX_M_HAS_SYSTICK
|
||||
select CPU_CORTEX_M_HAS_VTOR
|
||||
select CPU_HAS_ARM_MPU
|
||||
select PLATFORM_SPECIFIC_INIT
|
||||
12
soc/atmel/sam0/samc21/Kconfig.defconfig
Normal file
12
soc/atmel/sam0/samc21/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
# Atmel SAMC21 MCU series configuration options
|
||||
|
||||
# Copyright (c) 2022 Kamil Serwus
|
||||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_SAMC21
|
||||
|
||||
config NUM_IRQS
|
||||
default 32
|
||||
|
||||
endif # SOC_SERIES_SAMC21
|
||||
98
soc/atmel/sam0/samc21/Kconfig.soc
Normal file
98
soc/atmel/sam0/samc21/Kconfig.soc
Normal file
|
|
@ -0,0 +1,98 @@
|
|||
# Atmel SAMC21 MCU series
|
||||
|
||||
# Copyright (c) 2022 Kamil Serwus
|
||||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_SAMC21
|
||||
bool
|
||||
select SOC_FAMILY_ATMEL_SAM0
|
||||
help
|
||||
Enable support for Atmel SAMC21 Cortex-M0+ microcontrollers.
|
||||
|
||||
config SOC_SERIES
|
||||
default "samc21" if SOC_SERIES_SAMC21
|
||||
|
||||
config SOC_SAMC21E15A
|
||||
bool
|
||||
select SOC_SERIES_SAMC21
|
||||
|
||||
config SOC_SAMC21E16A
|
||||
bool
|
||||
select SOC_SERIES_SAMC21
|
||||
|
||||
config SOC_SAMC21E17A
|
||||
bool
|
||||
select SOC_SERIES_SAMC21
|
||||
|
||||
config SOC_SAMC21E18A
|
||||
bool
|
||||
select SOC_SERIES_SAMC21
|
||||
|
||||
config SOC_SAMC21G15A
|
||||
bool
|
||||
select SOC_SERIES_SAMC21
|
||||
|
||||
config SOC_SAMC21G16A
|
||||
bool
|
||||
select SOC_SERIES_SAMC21
|
||||
|
||||
config SOC_SAMC21G17A
|
||||
bool
|
||||
select SOC_SERIES_SAMC21
|
||||
|
||||
config SOC_SAMC21G18A
|
||||
bool
|
||||
select SOC_SERIES_SAMC21
|
||||
|
||||
config SOC_SAMC21J15A
|
||||
bool
|
||||
select SOC_SERIES_SAMC21
|
||||
|
||||
config SOC_SAMC21J16A
|
||||
bool
|
||||
select SOC_SERIES_SAMC21
|
||||
|
||||
config SOC_SAMC21J17A
|
||||
bool
|
||||
select SOC_SERIES_SAMC21
|
||||
|
||||
config SOC_SAMC21J18A
|
||||
bool
|
||||
select SOC_SERIES_SAMC21
|
||||
|
||||
config SOC_SAMC21J17AU
|
||||
bool
|
||||
select SOC_SERIES_SAMC21
|
||||
|
||||
config SOC_SAMC21J18AU
|
||||
bool
|
||||
select SOC_SERIES_SAMC21
|
||||
|
||||
config SOC_SAMC21N17A
|
||||
bool
|
||||
select SOC_SERIES_SAMC21
|
||||
select SOC_SERIES_REVISION_N
|
||||
|
||||
config SOC_SAMC21N18A
|
||||
bool
|
||||
select SOC_SERIES_SAMC21
|
||||
select SOC_SERIES_REVISION_N
|
||||
|
||||
config SOC
|
||||
default "samc21e15a" if SOC_SAMC21E15A
|
||||
default "samc21e16a" if SOC_SAMC21E16A
|
||||
default "samc21e17a" if SOC_SAMC21E17A
|
||||
default "samc21e18a" if SOC_SAMC21E18A
|
||||
default "samc21g15a" if SOC_SAMC21G15A
|
||||
default "samc21g16a" if SOC_SAMC21G16A
|
||||
default "samc21g17a" if SOC_SAMC21G17A
|
||||
default "samc21g18a" if SOC_SAMC21G18A
|
||||
default "samc21j15a" if SOC_SAMC21J15A
|
||||
default "samc21j16a" if SOC_SAMC21J16A
|
||||
default "samc21j17a" if SOC_SAMC21J17A
|
||||
default "samc21j18a" if SOC_SAMC21J18A
|
||||
default "samc21j17au" if SOC_SAMC21J17AU
|
||||
default "samc21j18au" if SOC_SAMC21J18AU
|
||||
default "samc21n17a" if SOC_SAMC21N17A
|
||||
default "samc21n18a" if SOC_SAMC21N18A
|
||||
70
soc/atmel/sam0/samc21/soc.h
Normal file
70
soc/atmel/sam0/samc21/soc.h
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Kamil Serwus
|
||||
* Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _SOC_ATMEL_SAM0_SAMC21_SOC_H_
|
||||
#define _SOC_ATMEL_SAM0_SAMC21_SOC_H_
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#define DONT_USE_CMSIS_INIT
|
||||
|
||||
#include <zephyr/types.h>
|
||||
|
||||
#if defined(CONFIG_SOC_SAMC21E15A)
|
||||
#include <samc21e15a.h>
|
||||
#elif defined(CONFIG_SOC_SAMC21E16A)
|
||||
#include <samc21e16a.h>
|
||||
#elif defined(CONFIG_SOC_SAMC21E17A)
|
||||
#include <samc21e17a.h>
|
||||
#elif defined(CONFIG_SOC_SAMC21E18A)
|
||||
#include <samc21e18a.h>
|
||||
#elif defined(CONFIG_SOC_SAMC21G15A)
|
||||
#include <samc21g15a.h>
|
||||
#elif defined(CONFIG_SOC_SAMC21G16A)
|
||||
#include <samc21g16a.h>
|
||||
#elif defined(CONFIG_SOC_SAMC21G17A)
|
||||
#include <samc21g17a.h>
|
||||
#elif defined(CONFIG_SOC_SAMC21G18A)
|
||||
#include <samc21g18a.h>
|
||||
#elif defined(CONFIG_SOC_SAMC21J15A)
|
||||
#include <samc21j15a.h>
|
||||
#elif defined(CONFIG_SOC_SAMC21J16A)
|
||||
#include <samc21j16a.h>
|
||||
#elif defined(CONFIG_SOC_SAMC21J17A)
|
||||
#include <samc21j17a.h>
|
||||
#elif defined(CONFIG_SOC_SAMC21J18A)
|
||||
#include <samc21j18a.h>
|
||||
#elif defined(CONFIG_SOC_SAMC21J17AU)
|
||||
#include <samc21j17au.h>
|
||||
#elif defined(CONFIG_SOC_SAMC21J18AU)
|
||||
#include <samc21j18au.h>
|
||||
#elif defined(CONFIG_SOC_SAMC21N17A)
|
||||
#include <samc21n17a.h>
|
||||
#elif defined(CONFIG_SOC_SAMC21N18A)
|
||||
#include <samc21n18a.h>
|
||||
#else
|
||||
#error Library does not support the specified device.
|
||||
#endif
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#define ADC_SAM0_REFERENCE_ENABLE_PROTECTED
|
||||
|
||||
#include "adc_fixup_sam0.h"
|
||||
#include "../common/soc_port.h"
|
||||
#include "../common/atmel_sam0_dt.h"
|
||||
|
||||
#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768
|
||||
#define SOC_ATMEL_SAM0_OSC48M_FREQ_HZ 48000000
|
||||
|
||||
/** Processor Clock (HCLK) Frequency */
|
||||
#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
/** Master Clock (MCK) Frequency */
|
||||
#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ
|
||||
#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
|
||||
|
||||
#endif /* _SOC_ATMEL_SAM0_SAMC21_SOC_H_ */
|
||||
4
soc/atmel/sam0/samd20/CMakeLists.txt
Normal file
4
soc/atmel/sam0/samd20/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_include_directories(.)
|
||||
12
soc/atmel/sam0/samd20/Kconfig
Normal file
12
soc/atmel/sam0/samd20/Kconfig
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
# Atmel SAMD20 MCU series
|
||||
|
||||
# Copyright (c) 2018 Sean Nyekjaer
|
||||
# Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_SAMD20
|
||||
select ARM
|
||||
select CPU_CORTEX_M0PLUS
|
||||
select CPU_CORTEX_M_HAS_SYSTICK
|
||||
select CPU_CORTEX_M_HAS_VTOR
|
||||
select PLATFORM_SPECIFIC_INIT
|
||||
12
soc/atmel/sam0/samd20/Kconfig.defconfig
Normal file
12
soc/atmel/sam0/samd20/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
# Atmel SAMD20 MCU series configuration options
|
||||
|
||||
# Copyright (c) 2018 Sean Nyekjaer
|
||||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_SAMD20
|
||||
|
||||
config NUM_IRQS
|
||||
default 25
|
||||
|
||||
endif # SOC_SERIES_SAMD20
|
||||
100
soc/atmel/sam0/samd20/Kconfig.soc
Normal file
100
soc/atmel/sam0/samd20/Kconfig.soc
Normal file
|
|
@ -0,0 +1,100 @@
|
|||
# Atmel SAMD20 MCU series
|
||||
|
||||
# Copyright (c) 2018 Sean Nyekjaer
|
||||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_SAMD20
|
||||
bool
|
||||
select SOC_FAMILY_ATMEL_SAM0
|
||||
help
|
||||
Enable support for Atmel SAMD20 Cortex-M0+ microcontrollers.
|
||||
|
||||
config SOC_SERIES
|
||||
default "samd20" if SOC_SERIES_SAMD20
|
||||
|
||||
config SOC_SAMD20E14
|
||||
bool
|
||||
select SOC_SERIES_SAMD20
|
||||
|
||||
config SOC_SAMD20E15
|
||||
bool
|
||||
select SOC_SERIES_SAMD20
|
||||
|
||||
config SOC_SAMD20E16
|
||||
bool
|
||||
select SOC_SERIES_SAMD20
|
||||
|
||||
config SOC_SAMD20E17
|
||||
bool
|
||||
select SOC_SERIES_SAMD20
|
||||
|
||||
config SOC_SAMD20E18
|
||||
bool
|
||||
select SOC_SERIES_SAMD20
|
||||
|
||||
config SOC_SAMD20G14
|
||||
bool
|
||||
select SOC_SERIES_SAMD20
|
||||
|
||||
config SOC_SAMD20G15
|
||||
bool
|
||||
select SOC_SERIES_SAMD20
|
||||
|
||||
config SOC_SAMD20G16
|
||||
bool
|
||||
select SOC_SERIES_SAMD20
|
||||
|
||||
config SOC_SAMD20G17
|
||||
bool
|
||||
|
||||
config SOC_SAMD20G18
|
||||
bool
|
||||
select SOC_SERIES_SAMD20
|
||||
|
||||
config SOC_SAMD20G17U
|
||||
bool
|
||||
select SOC_SERIES_SAMD20
|
||||
|
||||
config SOC_SAMD20G18U
|
||||
bool
|
||||
select SOC_SERIES_SAMD20
|
||||
|
||||
config SOC_SAMD20J14
|
||||
bool
|
||||
select SOC_SERIES_SAMD20
|
||||
|
||||
config SOC_SAMD20J15
|
||||
bool
|
||||
select SOC_SERIES_SAMD20
|
||||
|
||||
config SOC_SAMD20J16
|
||||
bool
|
||||
select SOC_SERIES_SAMD20
|
||||
|
||||
config SOC_SAMD20J17
|
||||
bool
|
||||
select SOC_SERIES_SAMD20
|
||||
|
||||
config SOC_SAMD20J18
|
||||
bool
|
||||
select SOC_SERIES_SAMD20
|
||||
|
||||
config SOC
|
||||
default "samd20e14" if SOC_SAMD20E14
|
||||
default "samd20e15" if SOC_SAMD20E15
|
||||
default "samd20e16" if SOC_SAMD20E16
|
||||
default "samd20e17" if SOC_SAMD20E17
|
||||
default "samd20e18" if SOC_SAMD20E18
|
||||
default "samd20g14" if SOC_SAMD20G14
|
||||
default "samd20g15" if SOC_SAMD20G15
|
||||
default "samd20g16" if SOC_SAMD20G16
|
||||
default "samd20g17" if SOC_SAMD20G17
|
||||
default "samd20g18" if SOC_SAMD20G18
|
||||
default "samd20g17u" if SOC_SAMD20G17U
|
||||
default "samd20g18u" if SOC_SAMD20G18U
|
||||
default "samd20j14" if SOC_SAMD20J14
|
||||
default "samd20j15" if SOC_SAMD20J15
|
||||
default "samd20j16" if SOC_SAMD20J16
|
||||
default "samd20j17" if SOC_SAMD20J17
|
||||
default "samd20j18" if SOC_SAMD20J18
|
||||
122
soc/atmel/sam0/samd20/soc.h
Normal file
122
soc/atmel/sam0/samd20/soc.h
Normal file
|
|
@ -0,0 +1,122 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Sean Nyekjaer
|
||||
* Copyright (c) 2023 Ionut Catalin Pavel <iocapa@iocapa.com>
|
||||
* Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _SOC_ATMEL_SAM0_SAMD20_SOC_H_
|
||||
#define _SOC_ATMEL_SAM0_SAMD20_SOC_H_
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#define DONT_USE_CMSIS_INIT
|
||||
|
||||
#include <zephyr/types.h>
|
||||
|
||||
#if defined(CONFIG_SOC_SAMD20E14)
|
||||
#include <samd20e14.h>
|
||||
#elif defined(CONFIG_SOC_SAMD20E15)
|
||||
#include <samd20e15.h>
|
||||
#elif defined(CONFIG_SOC_SAMD20E16)
|
||||
#include <samd20e16.h>
|
||||
#elif defined(CONFIG_SOC_SAMD20E17)
|
||||
#include <samd20e17.h>
|
||||
#elif defined(CONFIG_SOC_SAMD20E18)
|
||||
#include <samd20e18.h>
|
||||
#elif defined(CONFIG_SOC_SAMD20G14)
|
||||
#include <samd20g14.h>
|
||||
#elif defined(CONFIG_SOC_SAMD20G15)
|
||||
#include <samd20g15.h>
|
||||
#elif defined(CONFIG_SOC_SAMD20G16)
|
||||
#include <samd20g16.h>
|
||||
#elif defined(CONFIG_SOC_SAMD20G17)
|
||||
#include <samd20g17.h>
|
||||
#elif defined(CONFIG_SOC_SAMD20G18)
|
||||
#include <samd20g18.h>
|
||||
#elif defined(CONFIG_SOC_SAMD20G17U)
|
||||
#include <samd20g17u.h>
|
||||
#elif defined(CONFIG_SOC_SAMD20G18U)
|
||||
#include <samd20g18u.h>
|
||||
#elif defined(CONFIG_SOC_SAMD20J14)
|
||||
#include <samd20j14.h>
|
||||
#elif defined(CONFIG_SOC_SAMD20J15)
|
||||
#include <samd20j15.h>
|
||||
#elif defined(CONFIG_SOC_SAMD20J16)
|
||||
#include <samd20j16.h>
|
||||
#elif defined(CONFIG_SOC_SAMD20J17)
|
||||
#include <samd20j17.h>
|
||||
#elif defined(CONFIG_SOC_SAMD20J18)
|
||||
#include <samd20j18.h>
|
||||
#else
|
||||
#error Library does not support the specified device.
|
||||
#endif
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#include "adc_fixup_sam0.h"
|
||||
#include "../common/soc_port.h"
|
||||
#include "../common/atmel_sam0_dt.h"
|
||||
|
||||
/** Processor Clock (HCLK) Frequency */
|
||||
#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ
|
||||
|
||||
/** Master Clock (MCK) Frequency */
|
||||
#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ
|
||||
|
||||
/** Known values */
|
||||
#define SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ 48000000
|
||||
#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768
|
||||
#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768
|
||||
#define SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 8000000
|
||||
#define SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ 32768
|
||||
#define SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ 31250
|
||||
|
||||
/** GCLK1 source frequency selector */
|
||||
#if defined(CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN)
|
||||
#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ
|
||||
#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC32K_AS_MAIN)
|
||||
#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ
|
||||
#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN)
|
||||
#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ
|
||||
#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN)
|
||||
#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ
|
||||
#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC_AS_MAIN)
|
||||
#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ CONFIG_SOC_ATMEL_SAMD_XOSC_FREQ_HZ
|
||||
#else
|
||||
#error Unsupported GCLK1 clock source.
|
||||
#endif
|
||||
|
||||
/** Dividers and frequency for GCLK0 */
|
||||
#define SOC_ATMEL_SAM0_GCLK0_DIV \
|
||||
(SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ / SOC_ATMEL_SAM0_MCK_FREQ_HZ)
|
||||
#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
|
||||
|
||||
/** DFLL48M output frequency */
|
||||
#define SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ \
|
||||
(SOC_ATMEL_SAM0_MCK_FREQ_HZ * SOC_ATMEL_SAM0_GCLK0_DIV)
|
||||
|
||||
/** Dividers and frequency for GCLK1 */
|
||||
#define SOC_ATMEL_SAM0_GCLK1_DIV \
|
||||
(SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ)
|
||||
#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ \
|
||||
(SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_DIV)
|
||||
|
||||
/** DFLL48M output multiplier */
|
||||
#define SOC_ATMEL_SAM0_DFLL48M_MUL \
|
||||
(SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_FREQ_HZ)
|
||||
|
||||
/** Frequency for GCLK2 */
|
||||
#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ
|
||||
|
||||
/** Dividers and frequency for GCLK3 */
|
||||
#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ
|
||||
#define SOC_ATMEL_SAM0_GCLK3_DIV \
|
||||
(SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK3_FREQ_HZ)
|
||||
|
||||
#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
|
||||
#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
|
||||
#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
|
||||
|
||||
#endif /* _SOC_ATMEL_SAM0_SAMD20_SOC_H_ */
|
||||
4
soc/atmel/sam0/samd21/CMakeLists.txt
Normal file
4
soc/atmel/sam0/samd21/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_include_directories(.)
|
||||
12
soc/atmel/sam0/samd21/Kconfig
Normal file
12
soc/atmel/sam0/samd21/Kconfig
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
# Atmel SAMD21 MCU series
|
||||
|
||||
# Copyright (c) 2017 Google LLC.
|
||||
# Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_SAMD21
|
||||
select ARM
|
||||
select CPU_CORTEX_M0PLUS
|
||||
select CPU_CORTEX_M_HAS_SYSTICK
|
||||
select CPU_CORTEX_M_HAS_VTOR
|
||||
select PLATFORM_SPECIFIC_INIT
|
||||
12
soc/atmel/sam0/samd21/Kconfig.defconfig
Normal file
12
soc/atmel/sam0/samd21/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
# Atmel SAMD21 MCU series configuration options
|
||||
|
||||
# Copyright (c) 2017 Google LLC.
|
||||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_SAMD21
|
||||
|
||||
config NUM_IRQS
|
||||
default 28
|
||||
|
||||
endif # SOC_SERIES_SAMD21
|
||||
90
soc/atmel/sam0/samd21/Kconfig.soc
Normal file
90
soc/atmel/sam0/samd21/Kconfig.soc
Normal file
|
|
@ -0,0 +1,90 @@
|
|||
# Atmel SAMD21 MCU series
|
||||
|
||||
# Copyright (c) 2017 Google LLC.
|
||||
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_SAMD21
|
||||
bool
|
||||
select SOC_FAMILY_ATMEL_SAM0
|
||||
help
|
||||
Enable support for Atmel SAMD21 Cortex-M0+ microcontrollers.
|
||||
|
||||
config SOC_SERIES
|
||||
default "samd21" if SOC_SERIES_SAMD21
|
||||
|
||||
config SOC_SAMD21E15A
|
||||
bool
|
||||
select SOC_SERIES_SAMD21
|
||||
|
||||
config SOC_SAMD21E16A
|
||||
bool
|
||||
select SOC_SERIES_SAMD21
|
||||
|
||||
config SOC_SAMD21E17A
|
||||
bool
|
||||
select SOC_SERIES_SAMD21
|
||||
|
||||
config SOC_SAMD21E18A
|
||||
bool
|
||||
select SOC_SERIES_SAMD21
|
||||
|
||||
config SOC_SAMD21E19A
|
||||
bool
|
||||
select SOC_SERIES_SAMD21
|
||||
|
||||
config SOC_SAMD21G15A
|
||||
bool
|
||||
select SOC_SERIES_SAMD21
|
||||
|
||||
config SOC_SAMD21G16A
|
||||
bool
|
||||
select SOC_SERIES_SAMD21
|
||||
|
||||
config SOC_SAMD21G17A
|
||||
bool
|
||||
select SOC_SERIES_SAMD21
|
||||
|
||||
config SOC_SAMD21G18A
|
||||
bool
|
||||
select SOC_SERIES_SAMD21
|
||||
|
||||
config SOC_SAMD21G17AU
|
||||
bool
|
||||
select SOC_SERIES_SAMD21
|
||||
|
||||
config SOC_SAMD21G18AU
|
||||
bool
|
||||
select SOC_SERIES_SAMD21
|
||||
|
||||
config SOC_SAMD21J15A
|
||||
bool
|
||||
select SOC_SERIES_SAMD21
|
||||
|
||||
config SOC_SAMD21J16A
|
||||
bool
|
||||
select SOC_SERIES_SAMD21
|
||||
|
||||
config SOC_SAMD21J17A
|
||||
bool
|
||||
select SOC_SERIES_SAMD21
|
||||
|
||||
config SOC_SAMD21J18A
|
||||
bool
|
||||
select SOC_SERIES_SAMD21
|
||||
|
||||
config SOC
|
||||
default "samd21e15a" if SOC_SAMD21E15A
|
||||
default "samd21e16a" if SOC_SAMD21E16A
|
||||
default "samd21e17a" if SOC_SAMD21E17A
|
||||
default "samd21e18a" if SOC_SAMD21E18A
|
||||
default "samd21g15a" if SOC_SAMD21G15A
|
||||
default "samd21g16a" if SOC_SAMD21G16A
|
||||
default "samd21g17a" if SOC_SAMD21G17A
|
||||
default "samd21g18a" if SOC_SAMD21G18A
|
||||
default "samd21g17au" if SOC_SAMD21G17AU
|
||||
default "samd21g18au" if SOC_SAMD21G18AU
|
||||
default "samd21j15a" if SOC_SAMD21J15A
|
||||
default "samd21j16a" if SOC_SAMD21J16A
|
||||
default "samd21j17a" if SOC_SAMD21J17A
|
||||
default "samd21j18a" if SOC_SAMD21J18A
|
||||
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Reference in a new issue