michaelh/zephyr
1
0
Fork 0
Code Releases Activity

arch: riscv: improve exception messages

Browse source 
Add exception descriptions of mcause id 6~15. Also print mtval CSR for
memory access fault & illegal instruction exceptions.

Signed-off-by: Jim Shu <cwshu@andestech.com>
This commit is contained in:
Jim Shu 2021-03-14 02:08:49 +08:00 • committed by Anas Nashif
commit 8db3683820
1 changed files with 19 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

20
arch/riscv/core/fatal.c
View file

@ -65,6 +65,22 @@ static char *cause_str(ulong_t cause)
return "Load address misaligned"; return "Load address misaligned";
case 5: case 5:
return "Load access fault"; return "Load access fault";
case 6:
return "Store/AMO address misaligned";
case 7:
return "Store/AMO access fault";
case 8:
return "Environment call from U-mode";
case 9:
return "Environment call from S-mode";
case 11:
return "Environment call from M-mode";
case 12:
return "Instruction page fault";
case 13:
return "Load page fault";
case 15:
return "Store/AMO page fault";
default: default:
return "unknown"; return "unknown";
} }
@ -87,13 +103,15 @@ void _Fault(z_arch_esf_t *esf)
} }
} }
#endif /* CONFIG_USERSPACE */ #endif /* CONFIG_USERSPACE */
ulong_t mcause; ulong_t mcause, mtval;
__asm__ volatile("csrr %0, mcause" : "=r" (mcause)); __asm__ volatile("csrr %0, mcause" : "=r" (mcause));
__asm__ volatile("csrr %0, mtval" : "=r" (mtval));
mcause &= SOC_MCAUSE_EXP_MASK; mcause &= SOC_MCAUSE_EXP_MASK;
LOG_ERR(""); LOG_ERR("");
LOG_ERR(" mcause: %ld, %s", mcause, cause_str(mcause)); LOG_ERR(" mcause: %ld, %s", mcause, cause_str(mcause));
LOG_ERR(" mtval: %lx", mtval);
z_riscv_fatal_error(K_ERR_CPU_EXCEPTION, esf); z_riscv_fatal_error(K_ERR_CPU_EXCEPTION, esf);
} }