diff --git a/soc/ite/ec/common/chip_chipregs.h b/soc/ite/ec/common/chip_chipregs.h
index 08e15aeebba..929f9bde9ae 100644
--- a/soc/ite/ec/common/chip_chipregs.h
+++ b/soc/ite/ec/common/chip_chipregs.h
@@ -191,6 +191,8 @@
  */
 /* GPIO control register */
 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
+#define IT8XXX2_GPIO_GPCRB3     ECREG(EC_REG_BASE_ADDR + 0x161B)
+#define IT8XXX2_GPIO_GPCRB4     ECREG(EC_REG_BASE_ADDR + 0x161C)
 #define GPCRF4			ECREG(EC_REG_BASE_ADDR + 0x163C)
 #define GPCRF5			ECREG(EC_REG_BASE_ADDR + 0x163D)
 #define GPCRH1			ECREG(EC_REG_BASE_ADDR + 0x1649)
diff --git a/soc/ite/ec/it8xxx2/Kconfig b/soc/ite/ec/it8xxx2/Kconfig
index 739278e97f9..c959e886d27 100644
--- a/soc/ite/ec/it8xxx2/Kconfig
+++ b/soc/ite/ec/it8xxx2/Kconfig
@@ -7,6 +7,7 @@ config SOC_SERIES_IT8XXX2
 	select ARCH_HAS_CUSTOM_CPU_IDLE
 	select ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE
 	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
+	select SOC_PREP_HOOK
 
 if SOC_SERIES_IT8XXX2
 
diff --git a/soc/ite/ec/it8xxx2/soc.c b/soc/ite/ec/it8xxx2/soc.c
index 73768c7ab83..e8a9b7fb3d7 100644
--- a/soc/ite/ec/it8xxx2/soc.c
+++ b/soc/ite/ec/it8xxx2/soc.c
@@ -369,6 +369,18 @@ void arch_cpu_atomic_idle(unsigned int key)
 	riscv_idle(CHIP_PLL_DOZE, key);
 }
 
+void soc_prep_hook(void)
+{
+#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
+	/*
+	 * Disables the I2C0 alternate function before executing the PLL sequence change
+	 * to ensure that the EC can enter sleep mode successfully.
+	 */
+	IT8XXX2_GPIO_GPCRB3 = GPCR_PORT_PIN_MODE_INPUT;
+	IT8XXX2_GPIO_GPCRB4 = GPCR_PORT_PIN_MODE_INPUT;
+#endif
+}
+
 static int ite_it8xxx2_init(void)
 {
 	struct gpio_it8xxx2_regs *const gpio_regs = GPIO_IT8XXX2_REG_BASE;