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i2c: adds driver for Atmel SAM3

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Adds the driver to utilize the I2C/TWI interface on Atmel SAM3
family processors for I2C communication.

Note that this currently only supports master mode. Limited
testing has been done using the Fujitsu FRAM sample app.

Change-Id: Ibdb8277e47dd9450b49a66a95421eb1ffb1c4eb4
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung 2016-02-03 13:28:31 -08:00 • committed by Anas Nashif
commit 8d48828b3c
8 changed files with 877 additions and 0 deletions
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10
arch/arm/soc/atmel_sam3/Kconfig
View file

@ -171,4 +171,14 @@ config GPIO_ATMEL_SAM3_PORTD
endif # GPIO_ATMEL_SAM3
if I2C_ATMEL_SAM3
config I2C_ATMEL_SAM3_0
default y
config I2C_ATMEL_SAM3_1
default y
endif # I2C_ATMEL_SAM3
endif # SOC_ATMEL_SAM3

8
arch/arm/soc/atmel_sam3/soc.h
View file

@ -205,6 +205,10 @@
#define SUPC_SR_OSCSEL (1 << 7)
/* Two-wire Interface (TWI) */
#define TWI0_ADDR 0x4008C000
#define TWI1_ADDR 0x40090000
#ifndef _ASMLANGUAGE
#include <device.h>
@ -234,6 +238,10 @@
/* Supply Controller Register struct */
#define __SUPC ((volatile struct __supc *)SUPC_ADDR)
/* Two-wire Interface (TWI) */
#define __TWI0 ((volatile struct __twi *)TWI0_ADDR)
#define __TWI1 ((volatile struct __twi *)TWI1_ADDR)
#endif /* !_ASMLANGUAGE */
#endif /* _ATMEL_SAM3_SOC_H_ */

23
arch/arm/soc/atmel_sam3/soc_registers.h
View file

@ -211,5 +211,28 @@ struct __supc {
uint32_t sr; /* 0x14 Status */
};
/* Two-wire Interface (TWI), aka I2C */
struct __twi {
uint32_t cr; /* 0x00 Control */
uint32_t mmr; /* 0x04 Master Mode */
uint32_t smr; /* 0x08 Slave Mode */
uint32_t iadr; /* 0x0C Internal Address */
uint32_t cwgr; /* 0x10 Clock Waveform Generator */
uint32_t rev0[3]; /* 0x14-0x1C reserved */
uint32_t sr; /* 0x20 Status */
uint32_t ier; /* 0x24 Interrupt Enable */
uint32_t idr; /* 0x28 Interrupt Disable */
uint32_t imr; /* 0x2C Interrupt Mask */
uint32_t rhr; /* 0x30 Receive Holding */
uint32_t thr; /* 0x34 Transmit Holding */
uint32_t rev1[50]; /* 0x38-0xFC Reserved */
struct __pdc pdc; /* 0x100 - 0x124 PDC */
};
#endif /* _ATMEL_SAM3_SOC_REGS_H_ */