drivers: gpio: sifive: use Kconfig to convert between levels
The number of IRQ first level bits is not necessarily 8 bits now, so use `CONFIG_1ST_LEVEL_INTERRUPT_BITS` instead of hardcoded value. Signed-off-by: Yong Cong Sin <ycsin@meta.com>
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1 changed files with 3 additions and 2 deletions
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@ -77,7 +77,7 @@ static inline unsigned int gpio_sifive_pin_irq(unsigned int base_irq, int pin)
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if (level == 1) {
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pin_irq = base_irq + pin;
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} else if (level == 2) {
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pin_irq = base_irq + (pin << 8);
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pin_irq = base_irq + (pin << CONFIG_1ST_LEVEL_INTERRUPT_BITS);
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}
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return pin_irq;
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@ -104,7 +104,8 @@ static void gpio_sifive_irq_handler(const struct device *dev)
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const struct gpio_sifive_config *cfg = DEV_GPIO_CFG(dev);
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/* Calculate pin and mask from base level 2 line */
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uint8_t pin = 1 + (riscv_plic_get_irq() - (uint8_t)(cfg->gpio_irq_base >> 8));
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uint8_t pin = 1 + (riscv_plic_get_irq() -
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(uint8_t)(cfg->gpio_irq_base >> CONFIG_1ST_LEVEL_INTERRUPT_BITS));
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/* This peripheral tracks each condition separately: a
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* transition from low to high will mark the pending bit for
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