From 8c9b226900b1162727f9b4b3bb27821ad077c315 Mon Sep 17 00:00:00 2001 From: Ruijia Wang Date: Mon, 2 Dec 2024 23:07:38 +0800 Subject: [PATCH] mcux: soc: rt1180 unmask reset event when rtwdog is using RT1180 takes reset event mask feature which should be unmasked when watch dog is enabled. Signed-off-by: Ruijia Wang --- soc/nxp/imxrt/imxrt118x/soc.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/soc/nxp/imxrt/imxrt118x/soc.c b/soc/nxp/imxrt/imxrt118x/soc.c index 4705c54795a..df277164807 100644 --- a/soc/nxp/imxrt/imxrt118x/soc.c +++ b/soc/nxp/imxrt/imxrt118x/soc.c @@ -17,6 +17,9 @@ #include #include #include +#if defined(CONFIG_WDT_MCUX_RTWDOG) +#include +#endif #include #include @@ -53,6 +56,14 @@ static const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = { }; #endif +#if defined(CONFIG_WDT_MCUX_RTWDOG) +#define RTWDOG_IF_SET_SRC(n, i) \ + if (IS_ENABLED(DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rtwdog##n), nxp_rtwdog, okay))) { \ + SRC_SetGlobalSystemResetMode(SRC_GENERAL_REG, kSRC_Wdog##i##Reset, \ + kSRC_ResetSystem); \ + } +#endif + const clock_sys_pll1_config_t sysPll1Config_BOARD_BootClockRUN = { /* Enable Sys Pll1 divide-by-2 clock or not */ .pllDiv2En = 1, @@ -625,6 +636,19 @@ void soc_early_init_hook(void) clock_init(); /* Get trdc and enable all access modes for MBC and MRC of TRDCA and TRDCW */ trdc_enable_all_access(); +#if defined(CONFIG_WDT_MCUX_RTWDOG) + /* Unmask the watchdog reset channel */ + RTWDOG_IF_SET_SRC(0, 1) + RTWDOG_IF_SET_SRC(1, 2) + RTWDOG_IF_SET_SRC(2, 3) + RTWDOG_IF_SET_SRC(3, 4) + RTWDOG_IF_SET_SRC(4, 5) + + /* Clear the reset status otherwise TCM memory will reload in next reset */ + uint32_t mask = SRC_GetResetStatusFlags(SRC_GENERAL_REG); + + SRC_ClearGlobalSystemResetStatus(SRC_GENERAL_REG, mask); +#endif /* Enable data cache */ sys_cache_data_enable();