boards: imx943_evk: add i.MX 943 EVK board support for A55

The IMX943 EVK board is a design and evaluation platform based on the
NXP i.MX 943 processor.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>

boards/nxp/imx943_evk/Kconfig.defconfig

@@ -0,0 +1,8 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config INTC_INIT_PRIORITY
+	default 2
+
+config MBOX_INIT_PRIORITY
+	default 3

boards/nxp/imx943_evk/Kconfig.imx943_evk

@@ -0,0 +1,6 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_IMX943_EVK
+	select SOC_MIMX94398_A55 if BOARD_IMX943_EVK_MIMX94398_A55
+	select SOC_PART_NUMBER_MIMX94398AVKM

boards/nxp/imx943_evk/board.yml

@@ -0,0 +1,6 @@
+board:
+  name: imx943_evk
+  full_name: i.MX943 EVK
+  vendor: nxp
+  socs:
+  - name: mimx94398

boards/nxp/imx943_evk/doc/index.rst

@@ -0,0 +1,124 @@
+.. zephyr:board:: imx943_evk
+
+Overview
+********
+
+The IMX943LP5EVK-19 board is a design and evaluation platform based on the
+NXP i.MX 943 processor. The i.MX 943 processor integrates up to four Arm
+Cortex-A55 cores, along with two Arm Cortex-M33 cores and two Arm Cortex-M7
+cores for functional safety. With PLCs, I/O controllers, V2X accelerators,
+ML acceleration, energy management, and advanced security, the i.MX 943
+processor provides optimized performance and power efficiency for industrial,
+IoT, and automotive devices. The i.MX943 device on the board comes in a
+compact 19 x 19 mm package.
+
+Hardware
+********
+
+- i.MX 943 automotive applications processor
+
+  - The processor integrates up to four Arm Cortex-A55 cores, and supports
+    functional safety with built-in Arm Cortex-M33 and -M7 cores
+
+- DRAM memory: 8-Gbit LPDDR5 DRAM
+- XSPI interface: 64 MB octal SPI NOR flash memory
+- eMMC: 32 GB eMMC NAND flash memory
+- uSDHC interface: an SD card slot
+- USB interface: Two USB Type-C ports
+- Ethernet interface: seven Ethernet ports
+- PCIe interface: one M.2 slot and one PCIe x4 slot.
+- FlexCAN interface: four CAN controller with four CAN connector.
+- LPUART interface
+- LPSPI interface
+- LPI2C interface
+- SAI interface
+- MQS interface
+- MICFIL interface
+- LVDS interface
+- ADC interface
+- SINC interface
+- Debug interface
+  - One USB-to-UART/MPSSE device, FT4232H
+  - One USB 3.2 Type-C connector (J15) for FT4232H provides quad serial ports
+  - JTAG header J16
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+System Clock
+------------
+
+This board configuration uses a system clock frequency of 24 MHz for Cortex-A55.
+Cortex-A55 Core runs up to 1.7 GHz.
+
+Serial Port
+-----------
+
+This board configuration uses a single serial communication channel with the
+CPU's UART1 for Cortex-A55.
+
+Programming and Debugging (A55)
+*******************************
+
+.. zephyr:board-supported-runners::
+
+Boot Zephyr by Using U-Boot Command
+===================================
+
+U-Boot "go" command can be used to start Zephyr on A55 Core0.
+
+Dependency
+----------
+
+Need to disable all watchdog in U-Boot, otherwise, watchdog will reset the board
+after Zephyr start up from the same A55 Core.
+
+Step 1: Build Zephyr application
+--------------------------------
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :host-os: unix
+   :board: imx943_evk/mimx94398/a55
+   :goals: build
+
+Step 2: Download Zephyr Image into DDR Memory
+---------------------------------------------
+
+Firstly need to download Zephyr binary image into DDR memory, it can use tftp:
+
+.. code-block:: console
+
+    tftp 0xd0000000 zephyr.bin
+
+Or copy the Zephyr image ``zephyr.bin`` SD card and plug the card into the board, for example
+if copy to the FAT partition of the SD card, use the following U-Boot command to load the image
+into DDR memory (assuming the SD card is dev 1, fat partition ID is 1, they could be changed
+based on actual setup):
+
+.. code-block:: console
+
+    fatload mmc 1:1 0xd0000000 zephyr.bin;
+
+Step 3: Boot Zephyr
+-------------------
+
+Use the following command to boot Zephyr on the core0:
+
+.. code-block:: console
+
+    dcache off; icache flush; go 0xd0000000;
+
+Then the following log could be found on UART1 console:
+
+.. code-block:: console
+
+    *** Booting Zephyr OS build v4.1.0-3650-gdb71736adb68 ***
+    Hello World! imx943_evk/mimx94398/a55
+
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer

boards/nxp/imx943_evk/imx943_evk-pinctrl.dtsi

@@ -0,0 +1,18 @@
+/*
+ * Copyright 2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nxp/nxp_imx/mimx94398avkm-pinctrl.dtsi>
+
+&pinctrl {
+	lpuart1_default: lpuart1_default {
+		group0 {
+			pinmux = <&iomuxc_uart1_rxd_lpuart_rx_lpuart1_rx>,
+				<&iomuxc_uart1_txd_lpuart_tx_lpuart1_tx>;
+			bias-pull-up;
+			slew-rate = "slightly_fast";
+			drive-strength = "x4";
+		};
+	};
+};

boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.dts

@@ -0,0 +1,47 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_mimx943_a55.dtsi>
+#include "imx943_evk-pinctrl.dtsi"
+
+/ {
+	model = "NXP i.MX943 A55";
+	compatible = "fsl,mimx943";
+
+	chosen {
+		zephyr,console = &lpuart1;
+		zephyr,shell-uart = &lpuart1;
+		/* sram node actually locates at DDR DRAM */
+		zephyr,sram = &dram;
+	};
+
+	cpus {
+		cpu@0 {
+			status = "disabled";
+		};
+
+		cpu@100 {
+			status = "disabled";
+		};
+
+		cpu@200 {
+			status = "disabled";
+		};
+	};
+
+	dram: memory@d0000000 {
+		reg = <0xd0000000 DT_SIZE_M(1)>;
+	};
+};
+
+&lpuart1 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&lpuart1_default>;
+	pinctrl-names = "default";
+};

boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.yaml

@@ -0,0 +1,17 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: imx943_evk/mimx94398/a55
+name: NXP i.MX943 EVK A55
+type: mcu
+arch: arm64
+toolchain:
+  - zephyr
+  - cross-compile
+ram: 1024
+supported:
+  - uart
+vendor: nxp

boards/nxp/imx943_evk/imx943_evk_mimx94398_a55_defconfig

@@ -0,0 +1,33 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# ARM Options
+CONFIG_AARCH64_IMAGE_HEADER=y
+CONFIG_ARMV8_A_NS=y
+
+# MMU Options
+CONFIG_MAX_XLAT_TABLES=24
+
+# Cache Options
+CONFIG_CACHE_MANAGEMENT=y
+CONFIG_DCACHE_LINE_SIZE_DETECT=y
+CONFIG_ICACHE_LINE_SIZE_DETECT=y
+
+# Zephyr Kernel Configuration
+CONFIG_XIP=n
+CONFIG_KERNEL_DIRECT_MAP=y
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+CONFIG_CLOCK_CONTROL=y
+
+CONFIG_MBOX=y
+CONFIG_ARM_SCMI=y