serial: Provide STM32Cube based serial driver on stm32f1, stm32f4
STM32Cube based implementation allows single driver file for all stm32 based SoCs. By maximizing code reuse, use of STM32Cube eases new SoCs porting into Zephyr and provides better maintanability and maturity. Change-Id: Ief4b723add3dfc8b2a839683559c5a4c5d5eb837 Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou
Kumar Gala
parent
c899cd0d12
commit
8c079e91c9
5 changed files with 135 additions and 258 deletions
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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* Copyright (c) 2016 Linaro Limited.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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@ -43,89 +44,43 @@
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#define DEV_DATA(dev) \
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((struct uart_stm32_data * const)(dev)->driver_data)
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#define UART_STRUCT(dev) \
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((volatile struct uart_stm32 *)(DEV_CFG(dev))->uconf.base)
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((USART_TypeDef *)(DEV_CFG(dev))->uconf.base)
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/**
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* @brief set baud rate
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*
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*/
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static void set_baud_rate(struct device *dev, uint32_t rate)
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{
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volatile struct uart_stm32 *uart = UART_STRUCT(dev);
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struct uart_stm32_data *data = DEV_DATA(dev);
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const struct uart_stm32_config *cfg = DEV_CFG(dev);
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uint32_t div, mantissa, fraction;
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uint32_t clock;
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/* Baud rate is controlled through BRR register. The values
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* written into the register depend on the clock driving the
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* peripheral. Ask clock_control for the current clock rate of
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* our peripheral.
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*/
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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clock_control_get_rate(data->clock, cfg->clock_subsys, &clock);
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#elif CONFIG_SOC_SERIES_STM32F4X
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clock_control_get_rate(data->clock,
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(clock_control_subsys_t *)&cfg->pclken, &clock);
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#endif
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/* baud rate calculation:
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*
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* baud rate = f_clk / (16 * usartdiv)
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*
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* Example (STM32F10x, USART1, PCLK2 @ 36MHz, 9600bps):
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*
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* f_clk == PCLK2,
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* usartdiv = 234.375,
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* mantissa = 234,
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* fraction = 6 (0.375 * 16)
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*/
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div = clock / rate;
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mantissa = div >> 4;
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fraction = div & 0xf;
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uart->brr.bit.mantissa = mantissa;
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uart->brr.bit.fraction = fraction;
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}
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#define TIMEOUT 1000
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static int uart_stm32_poll_in(struct device *dev, unsigned char *c)
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{
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volatile struct uart_stm32 *uart = UART_STRUCT(dev);
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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/* check if RXNE is set */
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if (!uart->sr.bit.rxne) {
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if (HAL_UART_Receive(UartHandle, (uint8_t *)c, 1, TIMEOUT) == HAL_OK) {
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return 0;
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} else {
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return -1;
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}
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/* read character */
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*c = (unsigned char)uart->dr.bit.dr;
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return 0;
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}
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static unsigned char uart_stm32_poll_out(struct device *dev,
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unsigned char c)
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{
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volatile struct uart_stm32 *uart = UART_STRUCT(dev);
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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/* wait for TXE to be set */
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while (!uart->sr.bit.txe) {
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}
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HAL_UART_Transmit(UartHandle, (uint8_t *)&c, 1, TIMEOUT);
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uart->dr.bit.dr = c;
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return c;
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}
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static inline void __uart_stm32_get_clock(struct device *dev)
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{
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struct uart_stm32_data *ddata = dev->driver_data;
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struct uart_stm32_data *data = DEV_DATA(dev);
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struct device *clk =
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device_get_binding(STM32_CLOCK_CONTROL_NAME);
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__ASSERT_NO_MSG(clk);
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ddata->clock = clk;
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data->clock = clk;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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@ -133,12 +88,24 @@ static inline void __uart_stm32_get_clock(struct device *dev)
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static int uart_stm32_fifo_fill(struct device *dev, const uint8_t *tx_data,
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int size)
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{
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volatile struct uart_stm32 *uart = UART_STRUCT(dev);
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size_t num_tx = 0;
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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uint8_t num_tx = 0;
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/* FIXME: DMA maybe? */
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while ((size - num_tx > 0) && (uart->sr.bit.txe)) {
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uart->dr.bit.dr = tx_data[num_tx++];
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while ((size - num_tx > 0) && __HAL_UART_GET_FLAG(UartHandle,
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UART_FLAG_TXE)) {
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/* TXE flag will be cleared with byte write to DR register */
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/* Send a character (8bit , parity none) */
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#if defined(CONFIG_SOC_SERIES_STM32F1X) || defined(CONFIG_SOC_SERIES_STM32F4X)
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/* Use direct access for F1, F4 until Low Level API is available
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* Once it is we can remove the if/else
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*/
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UartHandle->Instance->DR = (tx_data[num_tx++] &
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(uint8_t)0x00FF);
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#else
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LL_USART_TransmitData8(UartHandle->Instance, tx_data[num_tx++]);
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#endif
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}
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return num_tx;
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@ -147,92 +114,131 @@ static int uart_stm32_fifo_fill(struct device *dev, const uint8_t *tx_data,
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static int uart_stm32_fifo_read(struct device *dev, uint8_t *rx_data,
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const int size)
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{
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volatile struct uart_stm32 *uart = UART_STRUCT(dev);
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size_t num_rx = 0;
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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uint8_t num_rx = 0;
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while ((size - num_rx > 0) && (uart->sr.bit.rxne)) {
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rx_data[num_rx++] = (uint8_t) uart->dr.bit.dr;
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while ((size - num_rx > 0) && __HAL_UART_GET_FLAG(UartHandle,
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UART_FLAG_RXNE)) {
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/* Clear the interrupt */
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__HAL_UART_CLEAR_FLAG(UartHandle, UART_FLAG_RXNE);
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/* Receive a character (8bit , parity none) */
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#if defined(CONFIG_SOC_SERIES_STM32F1X) || defined(CONFIG_SOC_SERIES_STM32F4X)
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/* Use direct access for F1, F4 until Low Level API is available
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* Once it is we can remove the if/else
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*/
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rx_data[num_rx++] = (uint8_t)(UartHandle->Instance->DR &
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(uint8_t)0x00FF);
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#else
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rx_data[num_rx++] = LL_USART_ReceiveData8(UartHandle->Instance);
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#endif
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}
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return num_rx;
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}
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static void uart_stm32_irq_tx_enable(struct device *dev)
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{
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volatile struct uart_stm32 *uart = UART_STRUCT(dev);
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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uart->cr1.bit.txeie = 1;
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__HAL_UART_ENABLE_IT(UartHandle, UART_IT_TC);
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}
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static void uart_stm32_irq_tx_disable(struct device *dev)
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{
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volatile struct uart_stm32 *uart = UART_STRUCT(dev);
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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uart->cr1.bit.txeie = 0;
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__HAL_UART_DISABLE_IT(UartHandle, UART_IT_TC);
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}
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static int uart_stm32_irq_tx_ready(struct device *dev)
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{
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volatile struct uart_stm32 *uart = UART_STRUCT(dev);
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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return uart->sr.bit.txe;
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return __HAL_UART_GET_FLAG(UartHandle, UART_FLAG_TXE);
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}
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static int uart_stm32_irq_tx_empty(struct device *dev)
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{
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volatile struct uart_stm32 *uart = UART_STRUCT(dev);
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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return uart->sr.bit.txe;
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return __HAL_UART_GET_FLAG(UartHandle, UART_FLAG_TXE);
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}
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static void uart_stm32_irq_rx_enable(struct device *dev)
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{
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volatile struct uart_stm32 *uart = UART_STRUCT(dev);
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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uart->cr1.bit.rxneie = 1;
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__HAL_UART_ENABLE_IT(UartHandle, UART_IT_RXNE);
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}
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static void uart_stm32_irq_rx_disable(struct device *dev)
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{
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volatile struct uart_stm32 *uart = UART_STRUCT(dev);
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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uart->cr1.bit.rxneie = 0;
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__HAL_UART_DISABLE_IT(UartHandle, UART_IT_RXNE);
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}
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static int uart_stm32_irq_rx_ready(struct device *dev)
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{
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volatile struct uart_stm32 *uart = UART_STRUCT(dev);
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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return uart->sr.bit.rxne;
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return __HAL_UART_GET_FLAG(UartHandle, UART_FLAG_RXNE);
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}
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static void uart_stm32_irq_err_enable(struct device *dev)
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{
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volatile struct uart_stm32 *uart = UART_STRUCT(dev);
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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uart->cr3.bit.eie = 1;
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/* Enable FE, ORE interruptions */
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__HAL_UART_ENABLE_IT(UartHandle, UART_IT_ERR);
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/* Enable Line break detection */
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__HAL_UART_ENABLE_IT(UartHandle, UART_IT_LBD);
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/* Enable parity error interruption */
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__HAL_UART_ENABLE_IT(UartHandle, UART_IT_PE);
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}
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static void uart_stm32_irq_err_disable(struct device *dev)
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{
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volatile struct uart_stm32 *uart = UART_STRUCT(dev);
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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uart->cr3.bit.eie = 0;
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/* Disable FE, ORE interruptions */
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__HAL_UART_DISABLE_IT(UartHandle, UART_IT_ERR);
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/* Disable Line break detection */
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__HAL_UART_DISABLE_IT(UartHandle, UART_IT_LBD);
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/* Disable parity error interruption */
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__HAL_UART_DISABLE_IT(UartHandle, UART_IT_PE);
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}
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static int uart_stm32_irq_is_pending(struct device *dev)
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{
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volatile struct uart_stm32 *uart = UART_STRUCT(dev);
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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return uart->sr.bit.rxne || uart->sr.bit.txe;
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return __HAL_UART_GET_FLAG(UartHandle, UART_FLAG_TXE | UART_FLAG_RXNE);
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}
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static int uart_stm32_irq_update(struct device *dev)
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{
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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__HAL_UART_CLEAR_FLAG(UartHandle, UART_FLAG_TC);
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return 1;
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}
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static void uart_stm32_irq_callback_set(struct device *dev,
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uart_irq_callback_t cb)
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uart_irq_callback_t cb)
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{
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struct uart_stm32_data *data = DEV_DATA(dev);
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@ -284,42 +290,31 @@ static const struct uart_driver_api uart_stm32_driver_api = {
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*/
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static int uart_stm32_init(struct device *dev)
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{
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volatile struct uart_stm32 *uart = UART_STRUCT(dev);
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const struct uart_stm32_config *config = DEV_CFG(dev);
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struct uart_stm32_data *data = DEV_DATA(dev);
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const struct uart_stm32_config *cfg = DEV_CFG(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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__uart_stm32_get_clock(dev);
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/* enable clock */
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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clock_control_on(data->clock, cfg->clock_subsys);
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clock_control_on(data->clock, config->clock_subsys);
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#elif CONFIG_SOC_SERIES_STM32F4X
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clock_control_on(data->clock, (clock_control_subsys_t *)&cfg->pclken);
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clock_control_on(data->clock,
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(clock_control_subsys_t *)&config->pclken);
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#endif
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/* FIXME: hardcoded, clear stop bits */
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uart->cr2.bit.stop = 0;
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UartHandle->Instance = UART_STRUCT(dev);
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UartHandle->Init.WordLength = UART_WORDLENGTH_8B;
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UartHandle->Init.StopBits = UART_STOPBITS_1;
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UartHandle->Init.Parity = UART_PARITY_NONE;
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UartHandle->Init.HwFlowCtl = UART_HWCONTROL_NONE;
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UartHandle->Init.Mode = UART_MODE_TX_RX;
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UartHandle->Init.OverSampling = UART_OVERSAMPLING_16;
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uart->cr1.val = 0;
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/* FIXME: hardcoded, 8n1 */
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uart->cr1.bit.m = 0;
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uart->cr1.bit.pce = 0;
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/* FIXME: hardcoded, disable hardware flow control */
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uart->cr3.bit.ctse = 0;
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uart->cr3.bit.rtse = 0;
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set_baud_rate(dev, data->baud_rate);
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/* enable TX/RX */
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uart->cr1.bit.te = 1;
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uart->cr1.bit.re = 1;
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/* enable */
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uart->cr1.bit.ue = 1;
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HAL_UART_Init(UartHandle);
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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cfg->uconf.irq_config_func(dev);
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config->uconf.irq_config_func(dev);
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#endif
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return 0;
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}
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@ -332,7 +327,7 @@ static void uart_stm32_irq_config_func_0(struct device *dev);
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static const struct uart_stm32_config uart_stm32_dev_cfg_0 = {
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.uconf = {
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.base = (uint8_t *)USART1_ADDR,
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.base = (uint8_t *)USART1_BASE,
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.irq_config_func = uart_stm32_irq_config_func_0,
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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@ -346,7 +341,9 @@ static const struct uart_stm32_config uart_stm32_dev_cfg_0 = {
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};
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static struct uart_stm32_data uart_stm32_dev_data_0 = {
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.baud_rate = CONFIG_UART_STM32_PORT_0_BAUD_RATE,
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.huart = {
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.Init = {
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.BaudRate = CONFIG_UART_STM32_PORT_0_BAUD_RATE} }
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};
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DEVICE_AND_API_INIT(uart_stm32_0, CONFIG_UART_STM32_PORT_0_NAME,
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@ -373,6 +370,7 @@ static void uart_stm32_irq_config_func_0(struct device *dev)
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#endif /* CONFIG_UART_STM32_PORT_0 */
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#ifdef CONFIG_UART_STM32_PORT_1
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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@ -381,7 +379,7 @@ static void uart_stm32_irq_config_func_1(struct device *dev);
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static const struct uart_stm32_config uart_stm32_dev_cfg_1 = {
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.uconf = {
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.base = (uint8_t *)USART2_ADDR,
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.base = (uint8_t *)USART2_BASE,
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.irq_config_func = uart_stm32_irq_config_func_1,
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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@ -395,7 +393,9 @@ static const struct uart_stm32_config uart_stm32_dev_cfg_1 = {
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};
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static struct uart_stm32_data uart_stm32_dev_data_1 = {
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.baud_rate = CONFIG_UART_STM32_PORT_1_BAUD_RATE,
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.huart = {
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.Init = {
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.BaudRate = CONFIG_UART_STM32_PORT_1_BAUD_RATE} }
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};
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DEVICE_AND_API_INIT(uart_stm32_1, CONFIG_UART_STM32_PORT_1_NAME,
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@ -422,6 +422,7 @@ static void uart_stm32_irq_config_func_1(struct device *dev)
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#endif /* CONFIG_UART_STM32_PORT_1 */
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#ifdef CONFIG_UART_STM32_PORT_2
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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@ -430,7 +431,7 @@ static void uart_stm32_irq_config_func_2(struct device *dev);
|
|||
|
||||
static const struct uart_stm32_config uart_stm32_dev_cfg_2 = {
|
||||
.uconf = {
|
||||
.base = (uint8_t *)USART3_ADDR,
|
||||
.base = (uint8_t *)USART3_BASE,
|
||||
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
||||
.irq_config_func = uart_stm32_irq_config_func_2,
|
||||
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
|
||||
|
|
@ -443,7 +444,9 @@ static const struct uart_stm32_config uart_stm32_dev_cfg_2 = {
|
|||
};
|
||||
|
||||
static struct uart_stm32_data uart_stm32_dev_data_2 = {
|
||||
.baud_rate = CONFIG_UART_STM32_PORT_2_BAUD_RATE,
|
||||
.huart = {
|
||||
.Init = {
|
||||
.BaudRate = CONFIG_UART_STM32_PORT_2_BAUD_RATE} }
|
||||
};
|
||||
|
||||
DEVICE_AND_API_INIT(uart_stm32_2, CONFIG_UART_STM32_PORT_2_NAME,
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue