boards: nxp: add mimxrt700_evk board
add files related to mimxrt700_evk board add gpio/uart function support on board Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
This commit is contained in:
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commit
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13 changed files with 928 additions and 0 deletions
28
boards/nxp/mimxrt700_evk/CMakeLists.txt
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28
boards/nxp/mimxrt700_evk/CMakeLists.txt
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#
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# Copyright 2024 NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if(CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU0 OR CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU1)
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zephyr_library()
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zephyr_library_sources(board.c)
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endif()
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if(CONFIG_NXP_IMXRT_BOOT_HEADER)
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if(NOT ((DEFINED CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU0)
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OR (DEFINED CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU1)))
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message(WARNING "It appears you are using the board definition for "
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"the MIMXRT7xx-EVK, but targeting a custom board. You may need to "
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"update your flash configuration block data")
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endif()
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# Include flash configuration block for RT7xx EVK from NXP's HAL.
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# This configuration block may need modification if another flash chip is
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# used on your custom board. See NXP AN13304 for more information.
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zephyr_compile_definitions(BOOT_HEADER_ENABLE=1)
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zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024)
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set(RT7XX_BOARD_DIR
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"${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/mimxrt700evk")
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zephyr_library_sources(${RT7XX_BOARD_DIR}/flash_config/flash_config.c)
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zephyr_library_include_directories(${RT7XX_BOARD_DIR}/flash_config)
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endif()
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7
boards/nxp/mimxrt700_evk/Kconfig.mimxrt700_evk
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7
boards/nxp/mimxrt700_evk/Kconfig.mimxrt700_evk
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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_MIMXRT700_EVK
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select SOC_MIMXRT798S_CM33_CPU0 if BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU0
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select SOC_MIMXRT798S_CM33_CPU1 if BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU1
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select SOC_PART_NUMBER_MIMXRT798SGFOA
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389
boards/nxp/mimxrt700_evk/board.c
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boards/nxp/mimxrt700_evk/board.c
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/*
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* Copyright 2024 NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/init.h>
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#include <zephyr/device.h>
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#include "fsl_power.h"
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#include "fsl_clock.h"
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#include <soc.h>
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#include <fsl_glikey.h>
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/*!< System oscillator settling time in us */
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#define SYSOSC_SETTLING_US 220U
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/*!< xtal frequency in Hz */
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#define XTAL_SYS_CLK_HZ 24000000U
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#define SET_UP_FLEXCOMM_CLOCK(x) \
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do { \
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CLOCK_AttachClk(kFCCLK0_to_FLEXCOMM##x); \
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RESET_ClearPeripheralReset(kFC##x##_RST_SHIFT_RSTn); \
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CLOCK_EnableClock(kCLOCK_LPFlexComm##x); \
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} while (0)
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const clock_main_pll_config_t g_mainPllConfig_clock_init = {
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.main_pll_src = kCLOCK_MainPllOscClk, /* OSC clock */
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.numerator = 0, /* Numerator of the SYSPLL0 fractional loop divider is 0 */
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.denominator = 1, /* Denominator of the SYSPLL0 fractional loop divider is 1 */
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.main_pll_mult = kCLOCK_MainPllMult22 /* Divide by 22 */
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};
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const clock_audio_pll_config_t g_audioPllConfig_clock_init = {
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.audio_pll_src = kCLOCK_AudioPllOscClk, /* OSC clock */
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.numerator = 5040, /* Numerator of the Audio PLL fractional loop divider is 0 */
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.denominator = 27000, /* Denominator of the Audio PLL fractional loop divider is 1 */
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.audio_pll_mult = kCLOCK_AudioPllMult22, /* Divide by 22 */
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.enableVcoOut = true};
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static void BOARD_InitAHBSC(void);
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void board_early_init_hook(void)
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{
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#if CONFIG_SOC_MIMXRT798S_CM33_CPU0
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const clock_fro_config_t froAutotrimCfg = {
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.targetFreq = 300000000U,
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.range = 50U,
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.trim1DelayUs = 15U,
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.trim2DelayUs = 15U,
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.refDiv = 1U,
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.enableInt = 0U,
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.coarseTrimEn = true,
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};
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#ifndef CONFIG_IMXRT7XX_CODE_CACHE
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CACHE64_DisableCache(CACHE64_CTRL0);
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#endif
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POWER_DisablePD(kPDRUNCFG_PD_LPOSC);
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/* Power up OSC */
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POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL);
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/* Enable system OSC */
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CLOCK_EnableSysOscClk(true, true, SYSOSC_SETTLING_US);
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/* Sets external XTAL OSC freq */
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CLOCK_SetXtalFreq(XTAL_SYS_CLK_HZ);
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/* Make sure FRO1 is enabled. */
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POWER_DisablePD(kPDRUNCFG_PD_FRO1);
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/* Switch to FRO1 for safe configure. */
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CLOCK_AttachClk(kFRO1_DIV1_to_COMPUTE_BASE);
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CLOCK_AttachClk(kCOMPUTE_BASE_to_COMPUTE_MAIN);
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CLOCK_SetClkDiv(kCLOCK_DivCmptMainClk, 1U);
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CLOCK_AttachClk(kFRO1_DIV1_to_RAM);
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CLOCK_SetClkDiv(kCLOCK_DivComputeRamClk, 1U);
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CLOCK_AttachClk(kFRO1_DIV1_to_COMMON_BASE);
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CLOCK_AttachClk(kCOMMON_BASE_to_COMMON_VDDN);
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CLOCK_SetClkDiv(kCLOCK_DivCommonVddnClk, 1U);
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#if CONFIG_FLASH_MCUX_XSPI_XIP
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/* Change to common_base clock(Sourced by FRO1). */
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xspi_clock_safe_config();
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#endif
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/* Ungate all FRO clock. */
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POWER_DisablePD(kPDRUNCFG_GATE_FRO0);
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/* Use close loop mode. */
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CLOCK_EnableFroClkFreqCloseLoop(FRO0, &froAutotrimCfg, kCLOCK_FroAllOutEn);
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/* Enable FRO0 MAX clock for all domains.*/
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CLOCK_EnableFro0ClkForDomain(kCLOCK_AllDomainEnable);
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CLOCK_InitMainPll(&g_mainPllConfig_clock_init);
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CLOCK_InitMainPfd(kCLOCK_Pfd0, 20U); /* 475 MHz */
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CLOCK_InitMainPfd(kCLOCK_Pfd1, 24U); /* 396 MHz */
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CLOCK_InitMainPfd(kCLOCK_Pfd2, 18U); /* 528 MHz */
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/* Main PLL kCLOCK_Pfd3 (528 * 18 / 19) = 500 MHz -need 2 div -> 250 MHz*/
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CLOCK_InitMainPfd(kCLOCK_Pfd3, 19U);
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CLOCK_EnableMainPllPfdClkForDomain(kCLOCK_Pfd0, kCLOCK_AllDomainEnable);
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CLOCK_EnableMainPllPfdClkForDomain(kCLOCK_Pfd1, kCLOCK_AllDomainEnable);
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CLOCK_EnableMainPllPfdClkForDomain(kCLOCK_Pfd2, kCLOCK_AllDomainEnable);
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CLOCK_EnableMainPllPfdClkForDomain(kCLOCK_Pfd3, kCLOCK_AllDomainEnable);
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CLOCK_SetClkDiv(kCLOCK_DivCmptMainClk, 2U);
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CLOCK_AttachClk(kMAIN_PLL_PFD0_to_COMPUTE_MAIN); /* Switch to PLL 237.5 MHz */
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CLOCK_SetClkDiv(kCLOCK_DivMediaMainClk, 2U);
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CLOCK_AttachClk(kMAIN_PLL_PFD0_to_MEDIA_MAIN); /* Switch to PLL 237.5 MHz */
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CLOCK_SetClkDiv(kCLOCK_DivMediaVddnClk, 2U);
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CLOCK_AttachClk(kMAIN_PLL_PFD0_to_MEDIA_VDDN); /* Switch to PLL 237.5 MHz */
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CLOCK_SetClkDiv(kCLOCK_DivComputeRamClk, 2U);
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CLOCK_AttachClk(kMAIN_PLL_PFD0_to_RAM); /* Switch to PLL 237.5 MHz */
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CLOCK_SetClkDiv(kCLOCK_DivCommonVddnClk, 2U);
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CLOCK_AttachClk(kMAIN_PLL_PFD3_to_COMMON_VDDN); /* Switch to 250MHZ */
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/* Configure Audio PLL clock source. */
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CLOCK_InitAudioPll(&g_audioPllConfig_clock_init); /* 532.48MHZ */
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CLOCK_InitAudioPfd(kCLOCK_Pfd1, 24U); /* 399.36MHz */
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CLOCK_InitAudioPfd(kCLOCK_Pfd3, 26U); /* Enable Audio PLL PFD3 clock to 368.64MHZ */
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CLOCK_EnableAudioPllPfdClkForDomain(kCLOCK_Pfd1, kCLOCK_AllDomainEnable);
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CLOCK_EnableAudioPllPfdClkForDomain(kCLOCK_Pfd3, kCLOCK_AllDomainEnable);
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#if CONFIG_FLASH_MCUX_XSPI_XIP
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/* Call function xspi_setup_clock() to set user configured clock for XSPI. */
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xspi_setup_clock(XSPI0, 3U, 1U); /* Main PLL PDF1 DIV1. */
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#endif /* CONFIG_FLASH_MCUX_XSPI_XIP */
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#elif CONFIG_SOC_MIMXRT798S_CM33_CPU1
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/* Power up OSC in case it's not enabled. */
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POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL);
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/* Enable system OSC */
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CLOCK_EnableSysOscClk(true, true, SYSOSC_SETTLING_US);
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/* Sets external XTAL OSC freq */
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CLOCK_SetXtalFreq(XTAL_SYS_CLK_HZ);
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CLOCK_AttachClk(kFRO1_DIV3_to_SENSE_BASE);
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CLOCK_SetClkDiv(kCLOCK_DivSenseMainClk, 1);
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CLOCK_AttachClk(kSENSE_BASE_to_SENSE_MAIN);
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POWER_DisablePD(kPDRUNCFG_GATE_FRO2);
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CLOCK_EnableFroClkFreq(FRO2, 300000000U, kCLOCK_FroAllOutEn);
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CLOCK_EnableFro2ClkForDomain(kCLOCK_AllDomainEnable);
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CLOCK_AttachClk(kFRO2_DIV3_to_SENSE_BASE);
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CLOCK_SetClkDiv(kCLOCK_DivSenseMainClk, 1);
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CLOCK_AttachClk(kSENSE_BASE_to_SENSE_MAIN);
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#endif /* CONFIG_SOC_MIMXRT798S_CM33_CPU0 */
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BOARD_InitAHBSC();
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(iocon), okay)
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RESET_ClearPeripheralReset(kIOPCTL0_RST_SHIFT_RSTn);
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CLOCK_EnableClock(kCLOCK_Iopctl0);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(iocon1), okay)
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RESET_ClearPeripheralReset(kIOPCTL1_RST_SHIFT_RSTn);
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CLOCK_EnableClock(kCLOCK_Iopctl1);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(iocon2), okay)
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RESET_ClearPeripheralReset(kIOPCTL2_RST_SHIFT_RSTn);
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CLOCK_EnableClock(kCLOCK_Iopctl2);
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#endif
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#ifdef CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU0
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CLOCK_AttachClk(kOSC_CLK_to_FCCLK0);
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CLOCK_SetClkDiv(kCLOCK_DivFcclk0Clk, 1U);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm0), okay)
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SET_UP_FLEXCOMM_CLOCK(0);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm1), okay)
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SET_UP_FLEXCOMM_CLOCK(1);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm2), okay)
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SET_UP_FLEXCOMM_CLOCK(2);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm3), okay)
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SET_UP_FLEXCOMM_CLOCK(3);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm4), okay)
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SET_UP_FLEXCOMM_CLOCK(4);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm5), okay)
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SET_UP_FLEXCOMM_CLOCK(5);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm6), okay)
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SET_UP_FLEXCOMM_CLOCK(6);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm7), okay)
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SET_UP_FLEXCOMM_CLOCK(7);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm8), okay)
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SET_UP_FLEXCOMM_CLOCK(8);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm9), okay)
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SET_UP_FLEXCOMM_CLOCK(9);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm10), okay)
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SET_UP_FLEXCOMM_CLOCK(10);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm11), okay)
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SET_UP_FLEXCOMM_CLOCK(11);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm12), okay)
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SET_UP_FLEXCOMM_CLOCK(12);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm13), okay)
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SET_UP_FLEXCOMM_CLOCK(13);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi14), okay)
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CLOCK_EnableClock(kCLOCK_LPSpi14);
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RESET_ClearPeripheralReset(kLPSPI14_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c15), okay)
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CLOCK_EnableClock(kCLOCK_LPI2c15);
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RESET_ClearPeripheralReset(kLPI2C15_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi16), okay)
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CLOCK_AttachClk(kFRO0_DIV1_to_LPSPI16);
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CLOCK_SetClkDiv(kCLOCK_DivLpspi16Clk, 1U);
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CLOCK_EnableClock(kCLOCK_LPSpi16);
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RESET_ClearPeripheralReset(kLPSPI16_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm17), okay)
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CLOCK_AttachClk(kSENSE_BASE_to_FLEXCOMM17);
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CLOCK_SetClkDiv(kCLOCK_DivLPFlexComm17Clk, 4U);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm18), okay)
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CLOCK_AttachClk(kSENSE_BASE_to_FLEXCOMM18);
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CLOCK_SetClkDiv(kCLOCK_DivLPFlexComm18Clk, 4U);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm19), okay)
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CLOCK_AttachClk(kSENSE_BASE_to_FLEXCOMM19);
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CLOCK_SetClkDiv(kCLOCK_DivLPFlexComm19Clk, 4U);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm20), okay)
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CLOCK_AttachClk(kSENSE_BASE_to_FLEXCOMM20);
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CLOCK_SetClkDiv(kCLOCK_DivLPFlexComm20Clk, 4U);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio0), okay)
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CLOCK_EnableClock(kCLOCK_Gpio0);
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RESET_ClearPeripheralReset(kGPIO0_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
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CLOCK_EnableClock(kCLOCK_Gpio1);
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RESET_ClearPeripheralReset(kGPIO1_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay)
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CLOCK_EnableClock(kCLOCK_Gpio2);
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RESET_ClearPeripheralReset(kGPIO2_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio3), okay)
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CLOCK_EnableClock(kCLOCK_Gpio3);
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RESET_ClearPeripheralReset(kGPIO3_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio4), okay)
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CLOCK_EnableClock(kCLOCK_Gpio4);
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RESET_ClearPeripheralReset(kGPIO4_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio5), okay)
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CLOCK_EnableClock(kCLOCK_Gpio5);
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RESET_ClearPeripheralReset(kGPIO5_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio6), okay)
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CLOCK_EnableClock(kCLOCK_Gpio6);
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RESET_ClearPeripheralReset(kGPIO6_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio7), okay)
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CLOCK_EnableClock(kCLOCK_Gpio7);
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RESET_ClearPeripheralReset(kGPIO7_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio8), okay)
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CLOCK_EnableClock(kCLOCK_Gpio8);
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RESET_ClearPeripheralReset(kGPIO8_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio9), okay)
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CLOCK_EnableClock(kCLOCK_Gpio9);
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RESET_ClearPeripheralReset(kGPIO9_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio10), okay)
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CLOCK_EnableClock(kCLOCK_Gpio10);
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RESET_ClearPeripheralReset(kGPIO10_RST_SHIFT_RSTn);
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#endif
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}
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static void GlikeyWriteEnable(GLIKEY_Type *base, uint8_t idx)
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{
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(void)GLIKEY_SyncReset(base);
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(void)GLIKEY_StartEnable(base, idx);
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(void)GLIKEY_ContinueEnable(base, GLIKEY_CODEWORD_STEP1);
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(void)GLIKEY_ContinueEnable(base, GLIKEY_CODEWORD_STEP2);
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(void)GLIKEY_ContinueEnable(base, GLIKEY_CODEWORD_STEP3);
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(void)GLIKEY_ContinueEnable(base, GLIKEY_CODEWORD_STEP_EN);
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}
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static void GlikeyClearConfig(GLIKEY_Type *base)
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{
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(void)GLIKEY_SyncReset(base);
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}
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|
||||
/* Disable the secure check for AHBSC and enable periperhals/sram access for masters */
|
||||
static void BOARD_InitAHBSC(void)
|
||||
{
|
||||
#if defined(CONFIG_SOC_MIMXRT798S_CM33_CPU0)
|
||||
GlikeyWriteEnable(GLIKEY0, 1U);
|
||||
AHBSC0->MISC_CTRL_DP_REG = 0x000086aa;
|
||||
/* AHBSC0 MISC_CTRL_REG, disable Privilege & Secure checking. */
|
||||
AHBSC0->MISC_CTRL_REG = 0x000086aa;
|
||||
|
||||
GlikeyWriteEnable(GLIKEY0, 7U);
|
||||
/* Enable arbiter0 accessing SRAM */
|
||||
AHBSC0->COMPUTE_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF;
|
||||
AHBSC0->SENSE_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF;
|
||||
AHBSC0->MEDIA_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF;
|
||||
AHBSC0->NPU_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF;
|
||||
AHBSC0->HIFI4_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF;
|
||||
#endif
|
||||
|
||||
GlikeyWriteEnable(GLIKEY1, 1U);
|
||||
AHBSC3->MISC_CTRL_DP_REG = 0x000086aa;
|
||||
/* AHBSC3 MISC_CTRL_REG, disable Privilege & Secure checking.*/
|
||||
AHBSC3->MISC_CTRL_REG = 0x000086aa;
|
||||
|
||||
GlikeyWriteEnable(GLIKEY1, 9U);
|
||||
/* Enable arbiter1 accessing SRAM */
|
||||
AHBSC3->COMPUTE_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
|
||||
AHBSC3->SENSE_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
|
||||
AHBSC3->MEDIA_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
|
||||
AHBSC3->NPU_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
|
||||
AHBSC3->HIFI4_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
|
||||
AHBSC3->HIFI1_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
|
||||
|
||||
GlikeyWriteEnable(GLIKEY1, 8U);
|
||||
/* Access enable for COMPUTE domain masters to common APB peripherals.*/
|
||||
AHBSC3->COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE = 0xffffffff;
|
||||
AHBSC3->SENSE_APB_PERIPHERAL_ACCESS_ENABLE = 0xffffffff;
|
||||
GlikeyWriteEnable(GLIKEY1, 7U);
|
||||
AHBSC3->COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE = 0xffffffff;
|
||||
AHBSC3->SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE = 0xffffffff;
|
||||
|
||||
GlikeyWriteEnable(GLIKEY2, 1U);
|
||||
/*Disable secure and secure privilege checking. */
|
||||
AHBSC4->MISC_CTRL_DP_REG = 0x000086aa;
|
||||
AHBSC4->MISC_CTRL_REG = 0x000086aa;
|
||||
|
||||
#if defined(CONFIG_SOC_MIMXRT798S_CM33_CPU0)
|
||||
GlikeyClearConfig(GLIKEY0);
|
||||
#endif
|
||||
GlikeyClearConfig(GLIKEY1);
|
||||
GlikeyClearConfig(GLIKEY2);
|
||||
}
|
21
boards/nxp/mimxrt700_evk/board.cmake
Normal file
21
boards/nxp/mimxrt700_evk/board.cmake
Normal file
|
@ -0,0 +1,21 @@
|
|||
#
|
||||
# Copyright 2024 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
if(CONFIG_SOC_MIMXRT798S_CM33_CPU0)
|
||||
board_runner_args(jlink "--device=MIMXRT798S_M33_0" "--reset-after-load")
|
||||
board_runner_args(linkserver "--device=MIMXRT798S:MIMXRT700-EVK")
|
||||
board_runner_args(linkserver "--override=/device/memory/4=")
|
||||
board_runner_args(linkserver "--core=cm33_core0")
|
||||
elseif(CONFIG_SOC_MIMXRT798S_CM33_CPU1)
|
||||
board_runner_args(jlink "--device=MIMXRT798S_M33_1")
|
||||
board_runner_args(linkserver "--device=MIMXRT798S:MIMXRT700-EVK")
|
||||
board_runner_args(linkserver "--core=cm33_core1")
|
||||
else()
|
||||
message(FATAL_ERROR "Requested core is not supported")
|
||||
endif()
|
||||
|
||||
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
|
||||
include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
|
6
boards/nxp/mimxrt700_evk/board.yml
Normal file
6
boards/nxp/mimxrt700_evk/board.yml
Normal file
|
@ -0,0 +1,6 @@
|
|||
board:
|
||||
name: mimxrt700_evk
|
||||
full_name: MIMXRT700-EVK
|
||||
vendor: nxp
|
||||
socs:
|
||||
- name: mimxrt798s
|
194
boards/nxp/mimxrt700_evk/doc/index.rst
Normal file
194
boards/nxp/mimxrt700_evk/doc/index.rst
Normal file
|
@ -0,0 +1,194 @@
|
|||
.. zephyr:board:: mimxrt700_evk
|
||||
|
||||
Overview
|
||||
********
|
||||
|
||||
The new i.MX RT700 CPU architecture is composed of a high-performance main compute subsystem,
|
||||
a secondary “always-on” sense-compute subsystem and specialized coprocessors.
|
||||
|
||||
The main compute subsystem uses a 325 MHz capable Arm® Cortex®-M33 (CM33).
|
||||
Similar to the i.MX RT600 crossover MCU, the i.MX RT700 includes a Cadence Tensilica® HiFi 4 DSP.
|
||||
The HiFi 4 is a high performance DSP core based upon a Very Long Instruction Word (VLIW) architecture,
|
||||
which is capable of processing up to eight 32x16 MACs per instruction cycle. It can be used for offloading
|
||||
high-performance numerical tasks such as audio and image processing and supports both fixed-point and
|
||||
floating-point operations.
|
||||
|
||||
Hardware
|
||||
********
|
||||
|
||||
- Main Compute Subsystem:
|
||||
|
||||
- Arm Cortex-M33 up to 325 MHz
|
||||
- HiFi 4 DSP up to 325 MHz
|
||||
- eIQ Neutron NPU up to 325 MHz
|
||||
- Sense Compute Subsystem:
|
||||
|
||||
- Arm Cortex-M33 up to 250 MHz
|
||||
- HiFi 1 DSP up to 250 MHz
|
||||
- 7.5 MB on-chip SRAM
|
||||
- Three xSPI interfaces for off-chip memory expansion, supporting up to 16b wide external memories up to 250 MHz DDR
|
||||
- eUSB support with integrated PHY
|
||||
- Two SD/eMMC memory card interfaces—one supporting eMMC 5.0 with HS400/DDR operation
|
||||
- USB high-speed host/device controller with on-chip PHY
|
||||
- A digital microphone interface supporting up to 8 channels
|
||||
- Serial peripherals (UART/I²C/I3C/SPI/HSPI/SAI)
|
||||
- 2.5D GPU with vector graphics acceleration and frame buffer compression
|
||||
- EZH-V using RISC-V core with additional SIMD/DSP instructions
|
||||
- Full openVG 1.1 support
|
||||
- Up to 720p@60FPS from on-chip SRAM
|
||||
- LCD Interface + MIPI DSI
|
||||
- Integrated JPEG and PNG support
|
||||
- CSI 8/10/16-bit parallel (via FlexIO)
|
||||
|
||||
For more information about the MIMXRT798 SoC and MIMXRT700-EVK board, see
|
||||
these references:
|
||||
|
||||
- `i.MX RT700 Website`_
|
||||
|
||||
Supported Features
|
||||
==================
|
||||
|
||||
NXP considers the MIMXRT700-EVK as a superset board for the i.MX RT7xx
|
||||
family of MCUs. This board is a focus for NXP's Full Platform Support for
|
||||
Zephyr, to better enable the entire RT7xx family. NXP prioritizes enabling
|
||||
this board with new support for Zephyr features. The ``mimxrt700_evk/mimxrt798s
|
||||
/cm33_cpu0`` and ``mimxrt700_evk/mimxrt798s/cm33_cpu1`` board targets support
|
||||
the hardware features below.
|
||||
|
||||
+-----------+------------+-------------------------------------+
|
||||
| Interface | Controller | Driver/Component |
|
||||
+===========+============+=====================================+
|
||||
| NVIC | on-chip | nested vector interrupt controller |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| SYSTICK | on-chip | systick |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| IOCON | on-chip | pinmux |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| GPIO | on-chip | gpio |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| UART | on-chip | serial port-polling; |
|
||||
| | | serial port-interrupt |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| CLOCK | on-chip | clock_control |
|
||||
+-----------+------------+-------------------------------------+
|
||||
|
||||
The default configuration can be found in the defconfig file:
|
||||
|
||||
:zephyr_file:`boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0_defconfig`
|
||||
:zephyr_file:`boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1_defconfig`
|
||||
|
||||
Other hardware features are not currently supported by the port.
|
||||
|
||||
Connections and IOs
|
||||
===================
|
||||
|
||||
The MIMXRT798 SoC has IOCON registers, which can be used to configure the
|
||||
functionality of a pin.
|
||||
|
||||
+---------+-----------------+----------------------------+
|
||||
| Name | Function | Usage |
|
||||
+=========+=================+============================+
|
||||
| PIO0_31 | UART0 | UART RX |
|
||||
+---------+-----------------+----------------------------+
|
||||
| PIO1_0 | UART0 | UART TX |
|
||||
+---------+-----------------+----------------------------+
|
||||
| PIO0_18 | GPIO | GREEN LED |
|
||||
+---------+-----------------+----------------------------+
|
||||
| PIO0_9 | GPIO | SW5 |
|
||||
+---------+-----------------+----------------------------+
|
||||
| PIO8_14 | UART19 | UART TX |
|
||||
+---------+-----------------+----------------------------+
|
||||
| PIO8_15 | UART19 | UART RX |
|
||||
+---------+-----------------+----------------------------+
|
||||
|
||||
System Clock
|
||||
============
|
||||
|
||||
The MIMXRT700 EVK is configured to use the Systick
|
||||
as a source for the system clock.
|
||||
|
||||
Programming and Debugging
|
||||
*************************
|
||||
|
||||
Build and flash applications as usual (see :ref:`build_an_application` and
|
||||
:ref:`application_run` for more details).
|
||||
|
||||
Configuring a Debug Probe
|
||||
=========================
|
||||
|
||||
A debug probe is used for both flashing and debugging the board. This board is
|
||||
configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.
|
||||
|
||||
.. tabs::
|
||||
.. group-tab:: LinkServer
|
||||
|
||||
|
||||
1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path.
|
||||
2. To put the board in ``DFU mode`` to program the firmware, short jumper J20.
|
||||
3. To update the debug firmware, please follow the instructions on `MIMXRT700-EVK Debug Firmware`
|
||||
|
||||
.. group-tab:: JLink External
|
||||
|
||||
|
||||
1. Install the :ref:`jlink-debug-host-tools` and make sure they are in your search path.
|
||||
|
||||
2. To disconnect the SWD signals from onboard debug circuit, **short** jumpers JP18.
|
||||
|
||||
3. Connect the J-Link probe to J18 20-pin header.
|
||||
|
||||
See :ref:`jlink-external-debug-probe` for more information.
|
||||
|
||||
Configuring a Console
|
||||
=====================
|
||||
|
||||
Connect a USB cable from your PC to J54, and use the serial terminal of your choice
|
||||
(minicom, putty, etc.) with the following settings:
|
||||
|
||||
- Speed: 115200
|
||||
- Data: 8 bits
|
||||
- Parity: None
|
||||
- Stop bits: 1
|
||||
|
||||
Flashing
|
||||
========
|
||||
|
||||
Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the
|
||||
:ref:`jlink-debug-host-tools` as default.
|
||||
|
||||
.. zephyr-app-commands::
|
||||
:zephyr-app: samples/hello_world
|
||||
:board: mimxrt700_evk/mimxrt798s/cm33_cpu0
|
||||
:goals: flash
|
||||
|
||||
Open a serial terminal, reset the board (press the RESET button), and you should
|
||||
see the following message in the terminal:
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
*** Booting Zephyr OS v3.7.0 ***
|
||||
Hello World! mimxrt700_evk/mimxrt798s/cm33_cpu0
|
||||
|
||||
Debugging
|
||||
=========
|
||||
|
||||
Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the
|
||||
:ref:`jlink-debug-host-tools` as default.
|
||||
|
||||
.. zephyr-app-commands::
|
||||
:zephyr-app: samples/hello_world
|
||||
:board: mimxrt700_evk/mimxrt798s/cm33_cpu0
|
||||
:goals: debug
|
||||
|
||||
Open a serial terminal, step through the application in your debugger, and you
|
||||
should see the following message in the terminal:
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
*** Booting Zephyr OS v3.7.0 ***
|
||||
Hello World! mimxrt700_evk/mimxrt798s/cm33_cpu0
|
||||
|
||||
.. _i.MX RT700 Website:
|
||||
https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt700-crossover-mcu-with-arm-cortex-m33-npu-dsp-and-gpu-cores:i.MX-RT700
|
||||
|
||||
.. _MIMXRT700-EVK Debug Firmware:
|
||||
https://www.nxp.com/docs/en/application-note/AN13206.pdf
|
36
boards/nxp/mimxrt700_evk/mimxrt700_evk-pinctrl.dtsi
Normal file
36
boards/nxp/mimxrt700_evk/mimxrt700_evk-pinctrl.dtsi
Normal file
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* Copyright 2024 NXP
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <nxp/nxp_imx/rt/MIMXRT798SGFOA-pinctrl.h>
|
||||
|
||||
&pinctrl {
|
||||
pinmux_flexcomm0_lpuart: pinmux_flexcomm0_lpuart {
|
||||
group0 {
|
||||
pinmux = <LP_FLEXCOMM0_P0_PIO0_31>;
|
||||
input-enable;
|
||||
slew-rate = "normal";
|
||||
drive-strength = "normal";
|
||||
};
|
||||
group1 {
|
||||
pinmux = <LP_FLEXCOMM0_P1_PIO1_0>;
|
||||
slew-rate = "normal";
|
||||
drive-strength = "normal";
|
||||
};
|
||||
};
|
||||
|
||||
pinmux_flexcomm19_lpuart: pinmux_flexcomm19_lpuart {
|
||||
group0 {
|
||||
pinmux = <LP_FLEXCOMM19_P0_PIO8_14>;
|
||||
input-enable;
|
||||
slew-rate = "normal";
|
||||
drive-strength = "normal";
|
||||
};
|
||||
group1 {
|
||||
pinmux = <LP_FLEXCOMM19_P1_PIO8_15>;
|
||||
slew-rate = "normal";
|
||||
drive-strength = "normal";
|
||||
};
|
||||
};
|
||||
};
|
104
boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.dts
Normal file
104
boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.dts
Normal file
|
@ -0,0 +1,104 @@
|
|||
/*
|
||||
* Copyright 2024 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <nxp/nxp_rt7xx_cm33_cpu0.dtsi>
|
||||
#include <zephyr/dt-bindings/input/input-event-codes.h>
|
||||
#include "mimxrt700_evk-pinctrl.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NXP MIMXRT700-EVK board";
|
||||
compatible = "nxp,mimxrt798s";
|
||||
|
||||
aliases {
|
||||
led0 = &green_led;
|
||||
led1 = &blue_led;
|
||||
sw0 = &user_button_1;
|
||||
sw1 = &user_button_2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
zephyr,flash-controller = &mx25um51345g;
|
||||
zephyr,flash = &mx25um51345g;
|
||||
zephyr,sram = &sram0;
|
||||
zephyr,console = &flexcomm0_lpuart0;
|
||||
zephyr,shell-uart = &flexcomm0_lpuart0;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
green_led: led_0 {
|
||||
gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
|
||||
label = "User LED_GREEN";
|
||||
};
|
||||
blue_led: led_1 {
|
||||
gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
|
||||
label = "User LED_BLUE";
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
user_button_1: button_0 {
|
||||
label = "User SW5";
|
||||
gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
|
||||
zephyr,code = <INPUT_KEY_0>;
|
||||
};
|
||||
user_button_2: button_1 {
|
||||
label = "User SW7";
|
||||
gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
|
||||
zephyr,code = <INPUT_KEY_1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&systick {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&flexcomm0{
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&flexcomm0_lpuart0 {
|
||||
status = "okay";
|
||||
current-speed = <115200>;
|
||||
pinctrl-0 = <&pinmux_flexcomm0_lpuart>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&green_led {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blue_led {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&xspi0 {
|
||||
status = "okay";
|
||||
|
||||
mx25um51345g: mx25um51345g@0 {
|
||||
compatible = "nxp,xspi-mx25um51345g";
|
||||
/* MX25UM51245G is 64MB, 512MBit flash part */
|
||||
size = <DT_SIZE_M(64 * 8)>;
|
||||
reg = <0>;
|
||||
spi-max-frequency = <200000000>;
|
||||
status = "okay";
|
||||
jedec-id = [c2 81 3a];
|
||||
erase-block-size = <4096>;
|
||||
write-block-size = <2>;
|
||||
};
|
||||
};
|
|
@ -0,0 +1,20 @@
|
|||
#
|
||||
# Copyright 2024 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
identifier: mimxrt700_evk/mimxrt798s/cm33_cpu0
|
||||
name: NXP MIMXRT700-EVK (CM33_CPU0)
|
||||
type: mcu
|
||||
arch: arm
|
||||
ram: 512
|
||||
flash: 65536
|
||||
toolchain:
|
||||
- zephyr
|
||||
- gnuarmemb
|
||||
- xtools
|
||||
supported:
|
||||
- gpio
|
||||
- uart
|
||||
vendor: nxp
|
|
@ -0,0 +1,18 @@
|
|||
#
|
||||
# Copyright 2024 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
CONFIG_CONSOLE=y
|
||||
CONFIG_UART_CONSOLE=y
|
||||
CONFIG_SERIAL=y
|
||||
CONFIG_UART_INTERRUPT_DRIVEN=y
|
||||
CONFIG_GPIO=y
|
||||
|
||||
CONFIG_ARM_MPU=y
|
||||
CONFIG_HW_STACK_PROTECTION=y
|
||||
CONFIG_BOARD_EARLY_INIT_HOOK=y
|
||||
|
||||
# Enable TrustZone-M
|
||||
CONFIG_TRUSTED_EXECUTION_SECURE=y
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* Copyright 2024 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <nxp/nxp_rt7xx_cm33_cpu1.dtsi>
|
||||
#include <zephyr/dt-bindings/input/input-event-codes.h>
|
||||
#include "mimxrt700_evk-pinctrl.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NXP MIMXRT700-EVK board";
|
||||
compatible = "nxp,mimxrt798s";
|
||||
|
||||
aliases {
|
||||
led0 = &red_led;
|
||||
sw0 = &user_button_1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
zephyr,flash = &sram_code;
|
||||
zephyr,sram = &sram0;
|
||||
zephyr,console = &flexcomm19_lpuart19;
|
||||
zephyr,shell-uart = &flexcomm19_lpuart19;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
red_led: led_0 {
|
||||
status = "okay";
|
||||
gpios = <&gpio8 6 GPIO_ACTIVE_HIGH>;
|
||||
label = "User LED_RED";
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
user_button_1: button_0 {
|
||||
label = "User SW6";
|
||||
gpios = <&gpio8 5 (GPIO_ACTIVE_LOW)>;
|
||||
zephyr,code = <INPUT_KEY_0>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&systick {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&flexcomm19{
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&flexcomm19_lpuart19 {
|
||||
status = "okay";
|
||||
current-speed = <115200>;
|
||||
pinctrl-0 = <&pinmux_flexcomm19_lpuart>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&gpio8 {
|
||||
status = "okay";
|
||||
};
|
|
@ -0,0 +1,20 @@
|
|||
#
|
||||
# Copyright 2024 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
identifier: mimxrt700_evk/mimxrt798s/cm33_cpu1
|
||||
name: NXP MIMXRT700-EVK (CM33_CPU1)
|
||||
type: mcu
|
||||
arch: arm
|
||||
ram: 256
|
||||
flash: 512
|
||||
toolchain:
|
||||
- zephyr
|
||||
- gnuarmemb
|
||||
- xtools
|
||||
supported:
|
||||
- gpio
|
||||
- uart
|
||||
vendor: nxp
|
|
@ -0,0 +1,19 @@
|
|||
#
|
||||
# Copyright 2024 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
CONFIG_CONSOLE=y
|
||||
CONFIG_UART_CONSOLE=y
|
||||
CONFIG_SERIAL=y
|
||||
CONFIG_UART_INTERRUPT_DRIVEN=y
|
||||
CONFIG_GPIO=y
|
||||
|
||||
CONFIG_ARM_MPU=y
|
||||
CONFIG_HW_STACK_PROTECTION=y
|
||||
CONFIG_BOARD_EARLY_INIT_HOOK=y
|
||||
|
||||
# Enable TrustZone-M
|
||||
CONFIG_TRUSTED_EXECUTION_SECURE=y
|
||||
CONFIG_NXP_IMXRT_BOOT_HEADER=n
|
Loading…
Add table
Add a link
Reference in a new issue