diff --git a/arch/arm/core/aarch32/irq_manage.c b/arch/arm/core/aarch32/irq_manage.c
index 1576c072088..477a3f411da 100644
--- a/arch/arm/core/aarch32/irq_manage.c
+++ b/arch/arm/core/aarch32/irq_manage.c
@@ -69,29 +69,25 @@ void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
 	 * of priority levels reserved by the kernel.
 	 */
 
-#if defined(CONFIG_ZERO_LATENCY_IRQS)
 	/* If we have zero latency interrupts, those interrupts will
 	 * run at a priority level which is not masked by irq_lock().
 	 * Our policy is to express priority levels with special properties
 	 * via flags
 	 */
-	if (flags & IRQ_ZERO_LATENCY) {
+	if (IS_ENABLED(CONFIG_ZERO_LATENCY_IRQS) && (flags & IRQ_ZERO_LATENCY)) {
 		prio = _EXC_ZERO_LATENCY_IRQS_PRIO;
 	} else {
 		prio += _IRQ_PRIO_OFFSET;
 	}
-#else
-	ARG_UNUSED(flags);
-	prio += _IRQ_PRIO_OFFSET;
-#endif
+
 	/* The last priority level is also used by PendSV exception, but
 	 * allow other interrupts to use the same level, even if it ends up
 	 * affecting performance (can still be useful on systems with a
 	 * reduced set of priorities, like Cortex-M0/M0+).
 	 */
 	__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
-		 "invalid priority %d! values must be less than %lu\n",
-		 prio - _IRQ_PRIO_OFFSET,
+		 "invalid priority %d for %d irq! values must be less than %lu\n",
+		 prio - _IRQ_PRIO_OFFSET, irq,
 		 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
 	NVIC_SetPriority((IRQn_Type)irq, prio);
 }
diff --git a/include/arch/arm/aarch32/exc.h b/include/arch/arm/aarch32/exc.h
index bc6cc8bf97d..e095c61ebb6 100644
--- a/include/arch/arm/aarch32/exc.h
+++ b/include/arch/arm/aarch32/exc.h
@@ -48,14 +48,9 @@
 #endif
 
 #define _EXC_FAULT_PRIO 0
-#ifdef CONFIG_ZERO_LATENCY_IRQS
 #define _EXC_ZERO_LATENCY_IRQS_PRIO 0
-#define _EXC_SVC_PRIO 1
-#define _IRQ_PRIO_OFFSET (_EXCEPTION_RESERVED_PRIO + 1)
-#else
-#define _EXC_SVC_PRIO 0
-#define _IRQ_PRIO_OFFSET (_EXCEPTION_RESERVED_PRIO)
-#endif
+#define _EXC_SVC_PRIO COND_CODE_1(CONFIG_ZERO_LATENCY_IRQS, (1), (0))
+#define _IRQ_PRIO_OFFSET (_EXCEPTION_RESERVED_PRIO + _EXC_SVC_PRIO)
 
 #define _EXC_IRQ_DEFAULT_PRIO Z_EXC_PRIO(_IRQ_PRIO_OFFSET)
 
diff --git a/include/arch/arm/aarch32/irq.h b/include/arch/arm/aarch32/irq.h
index 06b7681afc5..518aa4993c3 100644
--- a/include/arch/arm/aarch32/irq.h
+++ b/include/arch/arm/aarch32/irq.h
@@ -85,14 +85,12 @@ extern void z_arm_interrupt_init(void);
 #define CONCAT(x, y) DO_CONCAT(x, y)
 
 /* Flags for use with IRQ_CONNECT() */
-#ifdef CONFIG_ZERO_LATENCY_IRQS
 /**
  * Set this interrupt up as a zero-latency IRQ. It has a fixed hardware
  * priority level (discarding what was supplied in the interrupt's priority
  * argument), and will run even if irq_lock() is active. Be careful!
  */
 #define IRQ_ZERO_LATENCY	BIT(0)
-#endif
 
 
 /* All arguments must be computable by the compiler at build time.
@@ -107,12 +105,16 @@ extern void z_arm_interrupt_init(void);
  */
 #define ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
 { \
+	BUILD_ASSERT(IS_ENABLED(CONFIG_ZERO_LATENCY_IRQS) || !(flags_p & IRQ_ZERO_LATENCY), \
+			"ZLI interrupt registered but feature is disabled"); \
 	Z_ISR_DECLARE(irq_p, 0, isr_p, isr_param_p); \
 	z_arm_irq_priority_set(irq_p, priority_p, flags_p); \
 }
 
 #define ARCH_IRQ_DIRECT_CONNECT(irq_p, priority_p, isr_p, flags_p) \
 { \
+	BUILD_ASSERT(IS_ENABLED(CONFIG_ZERO_LATENCY_IRQS) || !(flags_p & IRQ_ZERO_LATENCY), \
+			"ZLI interrupt registered but feature is disabled"); \
 	Z_ISR_DECLARE(irq_p, ISR_FLAG_DIRECT, isr_p, NULL); \
 	z_arm_irq_priority_set(irq_p, priority_p, flags_p); \
 }
diff --git a/tests/arch/arm/arm_irq_advanced_features/src/arm_zero_latency_irqs.c b/tests/arch/arm/arm_irq_advanced_features/src/arm_zero_latency_irqs.c
index ff36a5afd38..0bcc6694b32 100644
--- a/tests/arch/arm/arm_irq_advanced_features/src/arm_zero_latency_irqs.c
+++ b/tests/arch/arm/arm_irq_advanced_features/src/arm_zero_latency_irqs.c
@@ -8,8 +8,6 @@
 #include <arch/cpu.h>
 #include <arch/arm/aarch32/cortex_m/cmsis.h>
 
-#if defined(CONFIG_ZERO_LATENCY_IRQS)
-
 static volatile int test_flag;
 
 void arm_zero_latency_isr_handler(const void *args)
@@ -21,6 +19,13 @@ void arm_zero_latency_isr_handler(const void *args)
 
 void test_arm_zero_latency_irqs(void)
 {
+
+	if (!IS_ENABLED(CONFIG_ZERO_LATENCY_IRQS)) {
+		TC_PRINT("Skipped (Cortex-M Mainline only)\n");
+
+		return;
+	}
+
 	/* Determine an NVIC IRQ line that is not currently in use. */
 	int i, key;
 	int init_flag, post_flag;
@@ -98,12 +103,7 @@ void test_arm_zero_latency_irqs(void)
 
 	irq_unlock(key);
 }
-#else
-void test_arm_zero_latency_irqs(void)
-{
-	TC_PRINT("Skipped (Cortex-M Mainline only)\n");
-}
-#endif /* CONFIG_ZERO_LATENCY_IRQS */
+
 /**
  * @}
  */
diff --git a/tests/drivers/timer/nrf_rtc_timer/src/main.c b/tests/drivers/timer/nrf_rtc_timer/src/main.c
index 2dd0c4e956d..c33541276e7 100644
--- a/tests/drivers/timer/nrf_rtc_timer/src/main.c
+++ b/tests/drivers/timer/nrf_rtc_timer/src/main.c
@@ -38,8 +38,8 @@ static void init_zli_timer0(void)
 
 	IRQ_DIRECT_CONNECT(TIMER0_IRQn, 0,
 			   timer0_isr_wrapper,
-			   COND_CODE_1(CONFIG_ZERO_LATENCY_IRQS,
-				   (IRQ_ZERO_LATENCY), (0)));
+			   IS_ENABLED(CONFIG_ZERO_LATENCY_IRQS) ?
+			   IRQ_ZERO_LATENCY : 0);
 	irq_enable(TIMER0_IRQn);
 }