michaelh/zephyr
1
0
Fork 0
Code Releases Activity

soc: arm: replace DT_CPU_CLOCK_FREQUENCY with new dt macros

Browse source 
Replace DT_CPU_CLOCK_FREQUENCY with a PATH based reference to cpu@0
(DT_PATH(cpus, cpu_0)) and than getting the clock_frequency property:

DT_CPU_CLOCK_FREQUENCY -> DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)

This lets us remove DT_CPU_CLOCK_FREQUENCY from dts_fixup.h.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2020-04-22 07:06:40 -05:00 • committed by Kumar Gala
commit 8b6acb5e91
13 changed files with 14 additions and 36 deletions
Download patch file Download diff file Expand all files Collapse all files

4
drivers/i2c/i2c_cc13xx_cc26xx.c
View file

@ -241,6 +241,7 @@ static int i2c_cc13xx_cc26xx_transfer(struct device *dev, struct i2c_msg *msgs,
return ret;
}
#define CPU_FREQ DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
static int i2c_cc13xx_cc26xx_configure(struct device *dev, u32_t dev_config)
{
bool fast;
@ -270,8 +271,7 @@ static int i2c_cc13xx_cc26xx_configure(struct device *dev, u32_t dev_config)
}
/* Enables and configures I2C master */
I2CMasterInitExpClk(get_dev_config(dev)->base,
DT_CPU_CLOCK_FREQUENCY, fast);
I2CMasterInitExpClk(get_dev_config(dev)->base, CPU_FREQ, fast);
#ifdef CONFIG_SYS_POWER_MANAGEMENT
get_dev_data(dev)->dev_config = dev_config;

6
drivers/spi/spi_cc13xx_cc26xx.c
View file

@ -37,6 +37,8 @@ struct spi_cc13xx_cc26xx_data {
#endif
};
#define CPU_FREQ DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
static inline struct spi_cc13xx_cc26xx_data *get_dev_data(struct device *dev)
{
return dev->driver_data;
@ -91,7 +93,7 @@ static int spi_cc13xx_cc26xx_configure(struct device *dev,
return -EINVAL;
}
if (2 * config->frequency > DT_CPU_CLOCK_FREQUENCY) {
if (2 * config->frequency > CPU_FREQ) {
LOG_ERR("Frequency greater than supported in master mode");
return -EINVAL;
}
@ -121,7 +123,7 @@ static int spi_cc13xx_cc26xx_configure(struct device *dev,
SSIDisable(cfg->base);
/* Configure SSI */
SSIConfigSetExpClk(cfg->base, DT_CPU_CLOCK_FREQUENCY, prot,
SSIConfigSetExpClk(cfg->base, CPU_FREQ, prot,
SSI_MODE_MASTER, config->frequency, 8);
if (SPI_MODE_GET(config->operation) & SPI_MODE_LOOP) {

2
soc/arm/atmel_sam/same70/dts_fixup.h
View file

@ -8,8 +8,6 @@
/* SoC level DTS fixup file */
#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M7_0_CLOCK_FREQUENCY
#define DT_SPI_0_BASE_ADDRESS DT_ATMEL_SAM_SPI_40008000_BASE_ADDRESS
#define DT_SPI_0_NAME DT_ATMEL_SAM_SPI_40008000_LABEL
#define DT_SPI_0_IRQ DT_ATMEL_SAM_SPI_40008000_IRQ_0

2
soc/arm/atmel_sam/samv71/dts_fixup.h
View file

@ -12,8 +12,6 @@
/* SoC level DTS fixup file */
#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M7_0_CLOCK_FREQUENCY
#define DT_SPI_0_BASE_ADDRESS DT_ATMEL_SAM_SPI_40008000_BASE_ADDRESS
#define DT_SPI_0_NAME DT_ATMEL_SAM_SPI_40008000_LABEL
#define DT_SPI_0_IRQ DT_ATMEL_SAM_SPI_40008000_IRQ_0

2
soc/arm/silabs_exx32/efm32hg/dts_fixup.h
View file

@ -8,8 +8,6 @@
/* SoC level DTS fixup file */
#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M0PLUS_0_CLOCK_FREQUENCY
#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_LABEL

2
soc/arm/silabs_exx32/efm32jg12b/dts_fixup.h
View file

@ -6,8 +6,6 @@
/* SoC level DTS fixup file */
#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY
#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL

2
soc/arm/silabs_exx32/efm32pg12b/dts_fixup.h
View file

@ -6,8 +6,6 @@
/* SoC level DTS fixup file */
#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY
#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL

2
soc/arm/silabs_exx32/efm32wg/dts_fixup.h
View file

@ -8,8 +8,6 @@
/* SoC level DTS fixup file */
#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY
#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_LABEL

2
soc/arm/silabs_exx32/efr32bg13p/dts_fixup.h
View file

@ -12,8 +12,6 @@
/* SoC level DTS fixup file */
#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY
#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL

2
soc/arm/silabs_exx32/efr32fg1p/dts_fixup.h
View file

@ -8,8 +8,6 @@
/* SoC level DTS fixup file */
#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY
#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL

2
soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h
View file

@ -8,8 +8,6 @@
/* SoC level DTS fixup file */
#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY
#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL

11
soc/arm/ti_simplelink/cc13x2_cc26x2/dts_fixup.h
View file

@ -1,11 +0,0 @@
/*
* Copyright (c) 2019 Brett Witherspoon
*
* SPDX-License-Identifier: Apache-2.0
*/
/* SoC level DTS fixup file */
#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4_0_CLOCK_FREQUENCY
/* End of SoC Level DTS fixup file */

11
subsys/logging/log_backend_swo.c
View file

@ -18,8 +18,8 @@
* this frequency should much the one set by the SWO viewer program.
*
* The initialization code assumes that SWO core frequency is equal to HCLK
* as defined by DT_CPU_CLOCK_FREQUENCY. This may require additional,
* vendor specific configuration.
* as defined by the clock-frequency property in the CPU node. This may require
* additional, vendor specific configuration.
*/
#include <logging/log_backend.h>
@ -36,7 +36,12 @@
#if CONFIG_LOG_BACKEND_SWO_FREQ_HZ == 0
#define SWO_FREQ_DIV 1
#else
#define SWO_FREQ (DT_CPU_CLOCK_FREQUENCY + (CONFIG_LOG_BACKEND_SWO_FREQ_HZ / 2))
#if DT_NODE_HAS_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
#define CPU_FREQ DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
#else
#error "Missing DT 'clock-frequency' property on cpu@0 node"
#endif
#define SWO_FREQ (CPU_FREQ + (CONFIG_LOG_BACKEND_SWO_FREQ_HZ / 2))
#define SWO_FREQ_DIV (SWO_FREQ / CONFIG_LOG_BACKEND_SWO_FREQ_HZ)
#if SWO_FREQ_DIV > 0xFFFF
#error CONFIG_LOG_BACKEND_SWO_FREQ_HZ is too low. SWO clock divider is 16-bit. \