arch/xtensa: Enable code relocation

Besides adding ARCH_HAS_CODE_DATA_RELOCATION, this patch also adds
support for the "sample_controller" SoC (used by qemu_xtensa) as
demonstration.

As Xtensa lacks a common linker script at the arch level, enabling it
for each platform will be a piecemeal effort. This patch adds it to the
`soc/xtensa/sample_controller` SoC. Basically, default RAMABLE_REGION is
set to be called "RAM", and hooks are inserted so that
gen_relocate_app.py can add the relevant linker bits.

Also, `tests/application_developent/code_relocation` was tweaked to
support the qemu_xtensa platform. Basically, add the relevant linker
script and ensure that relevant memory regions have their program header
(PHDR) associated.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>

arch/Kconfig

@@ -124,6 +124,7 @@ config XTENSA
 	select USE_SWITCH
 	select USE_SWITCH_SUPPORTED
 	select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD
+	select ARCH_HAS_CODE_DATA_RELOCATION
 	select ARCH_HAS_TIMING_FUNCTIONS
 	imply ATOMIC_OPERATIONS_ARCH
 	help

soc/xtensa/sample_controller/include/xtensa-sample-controller.ld

@@ -16,7 +16,7 @@
 #include <zephyr/linker/linker-defs.h>
 #include <zephyr/linker/linker-tool.h>
 
-#define RAMABLE_REGION sram0_seg :sram0_phdr
+#define RAMABLE_REGION RAM :sram0_phdr
 #define ROMABLE_REGION srom1_seg :srom1_phdr
 
 MEMORY
@@ -45,7 +45,7 @@ MEMORY
   iram0_19_seg :                      	org = 0x40000400, len = 0x1FC00
   srom0_seg :                         	org = 0x50000000, len = 0x300
   srom1_seg :                         	org = 0x50000300, len = 0xFFFD00
-  sram0_seg :                         	org = 0x60000000, len = 0x4000000
+  RAM :                         	org = 0x60000000, len = 0x4000000
 #ifdef CONFIG_GEN_ISR_TABLES
   IDT_LIST : org = 0x3ffbe000, len = 0x2000
 #endif
@@ -408,6 +408,10 @@ SECTIONS
     _memmap_seg_srom0_end = ALIGN(0x8);
   } >srom0_seg :srom0_phdr
 
+#ifdef CONFIG_CODE_DATA_RELOCATION
+#include <linker_relocate.ld>
+#endif
+
   .srom.rodata : ALIGN(4)
   {
     _srom_rodata_start = ABSOLUTE(.);
@@ -430,7 +434,7 @@ SECTIONS
     _sram_rodata_start = ABSOLUTE(.);
     *(.sram.rodata)
     _sram_rodata_end = ABSOLUTE(.);
-  } >sram0_seg :sram0_phdr
+  } >RAM :sram0_phdr
 
 #include <zephyr/linker/common-rom.ld>
 
@@ -479,14 +483,14 @@ SECTIONS
     LONG(_bss_end)
     _bss_table_end = ABSOLUTE(.);
     _rodata_end = ABSOLUTE(.);
-  } >sram0_seg :sram0_phdr
+  } >RAM :sram0_phdr
 
   .sram.text : ALIGN(4)
   {
     _sram_text_start = ABSOLUTE(.);
     *(.sram.literal .sram.text)
     _sram_text_end = ABSOLUTE(.);
-  } >sram0_seg :sram0_phdr
+  } >RAM :sram0_phdr
 
   __text_region_start =  ALIGN(4);
   .text : ALIGN(4)
@@ -502,7 +506,7 @@ SECTIONS
     *(.gnu.version)
     _text_end = ABSOLUTE(.);
     _etext = .;
-  } >sram0_seg :sram0_phdr
+  } >RAM :sram0_phdr
   __text_region_end = .;
 
   .sram.data : ALIGN(4)
@@ -510,19 +514,19 @@ SECTIONS
     _sram_data_start = ABSOLUTE(.);
     *(.sram.data)
     _sram_data_end = ABSOLUTE(.);
-  } >sram0_seg :sram0_phdr
+  } >RAM :sram0_phdr
 
   .noinit :  ALIGN(4)
   {
     *(.noinit)
     *(.noinit.*)
-  } >sram0_seg :sram0_phdr
+  } >RAM :sram0_phdr
 
 #include <snippets-sections.ld>
 
   .data : ALIGN(4)
   {
-    _data_start = ABSOLUTE(.);
+    __data_start = ABSOLUTE(.);
     *(.data)
     *(.data.*)
     *(.gnu.linkonce.d.*)
@@ -540,8 +544,13 @@ SECTIONS
     #include <snippets-rwdata.ld>
     . = ALIGN(4);
 
-    _data_end = ABSOLUTE(.);
+#ifdef CONFIG_CODE_DATA_RELOCATION
-  } >sram0_seg :sram0_phdr
+#include <linker_sram_data_relocate.ld>
+#endif
+    . = ALIGN(4);
+
+    __data_end = ABSOLUTE(.);
+  } >RAM :sram0_phdr
 
 #include <snippets-data-sections.ld>
 
@@ -550,7 +559,7 @@ SECTIONS
   .tm_clone_table :
   {
     *(.tm_clone_table)
-  } >sram0_seg :sram0_phdr
+  } >RAM :sram0_phdr
 
 #include <snippets-ram-sections.ld>
 
@@ -572,6 +581,9 @@ SECTIONS
     *(.gnu.linkonce.b.*)
     *(COMMON)
     *(.sram.bss)
+#ifdef CONFIG_CODE_DATA_RELOCATION
+#include <linker_sram_bss_relocate.ld>
+#endif
     . = ALIGN (8);
     _bss_end = ABSOLUTE(.);
     _end = ALIGN(0x8);
@@ -579,7 +591,7 @@ SECTIONS
     PROVIDE(end = ALIGN(0x8));
     _stack_sentry = ALIGN(0x8);
     _memmap_seg_sram0_end = ALIGN(0x8);
-  } >sram0_seg :sram0_bss_phdr
+  } >RAM :sram0_bss_phdr
   __stack = 0x64000000;
   _heap_sentry = 0x64000000;
   .comment  0 :  { *(.comment) }

tests/application_development/code_relocation/CMakeLists.txt

@@ -8,16 +8,22 @@ project(code_relocation)
 FILE(GLOB app_sources src/*.c)
 target_sources(app PRIVATE ${app_sources})
 
+if (CONFIG_BOARD_QEMU_XTENSA)
+    set(RAM_PHDR :sram0_phdr)
+    set(SRAM2_PHDR :sram2_phdr)
+endif()
+
 # Code relocation feature
-zephyr_code_relocate(src/test_file1.c SRAM2)
+zephyr_code_relocate(src/test_file1.c "SRAM2 ${SRAM2_PHDR}")
 
-zephyr_code_relocate(src/test_file2.c RAM)
+zephyr_code_relocate(src/test_file2.c "RAM ${RAM_PHDR}")
 
+zephyr_code_relocate(src/test_file3.c SRAM2_LITERAL)
 zephyr_code_relocate(src/test_file3.c SRAM2_TEXT)
 zephyr_code_relocate(src/test_file3.c RAM_DATA)
 zephyr_code_relocate(src/test_file3.c SRAM2_BSS)
 
-zephyr_code_relocate(../../../kernel/sem.c RAM)
+zephyr_code_relocate(../../../kernel/sem.c "RAM ${RAM_PHDR}")
 
 if (CONFIG_RELOCATE_TO_ITCM)
 zephyr_code_relocate(../../../lib/libc/minimal/source/string/string.c ITCM_TEXT)

tests/application_development/code_relocation/linker_xtensa_qemu_sram2.ld

@@ -0,0 +1,29 @@
+/*
+ * Copyright 2022 The Chromium OS Authors
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/linker/sections.h>
+#include <zephyr/devicetree.h>
+
+#include <zephyr/linker/linker-defs.h>
+#include <zephyr/linker/linker-tool.h>
+
+#define SRAM2_ADDR  (CONFIG_SRAM_BASE_ADDRESS + RAM_SIZE2)
+#define RAM_SIZE2 (0x4000000)
+
+MEMORY
+{
+    SRAM2      (wx) : ORIGIN = (CONFIG_SRAM_BASE_ADDRESS + RAM_SIZE2), LENGTH = RAM_SIZE2
+}
+
+PHDRS
+{
+    sram2_phdr PT_LOAD;
+}
+
+#define MPU_ALIGN(region_size) \
+    . = ALIGN(4)
+
+#include <xtensa-sample-controller.ld>

tests/application_development/code_relocation/prj_xtensa.conf

@@ -0,0 +1,5 @@
+CONFIG_CODE_DATA_RELOCATION=y
+CONFIG_ZTEST=y
+CONFIG_ZTEST_NEW_API=y
+CONFIG_HAVE_CUSTOM_LINKER_SCRIPT=y
+CONFIG_CUSTOM_LINKER_SCRIPT="linker_xtensa_qemu_sram2.ld"

tests/application_development/code_relocation/testcase.yaml

@@ -20,3 +20,6 @@ tests:
   tests.application_development.code_relocation.riscv:
     extra_args: CONF_FILE="prj_riscv.conf"
     platform_allow: qemu_riscv32 qemu_riscv64
+  tests.application_development.code_relocation.xtensa:
+    extra_args: CONF_FILE="prj_xtensa.conf"
+    platform_allow: qemu_xtensa