michaelh/zephyr
1
0
Fork 0
Code Releases Activity

arch/xtensa: Enable code relocation

Browse source 
Besides adding ARCH_HAS_CODE_DATA_RELOCATION, this patch also adds
support for the "sample_controller" SoC (used by qemu_xtensa) as
demonstration.

As Xtensa lacks a common linker script at the arch level, enabling it
for each platform will be a piecemeal effort. This patch adds it to the
`soc/xtensa/sample_controller` SoC. Basically, default RAMABLE_REGION is
set to be called "RAM", and hooks are inserted so that
gen_relocate_app.py can add the relevant linker bits.

Also, `tests/application_developent/code_relocation` was tweaked to
support the qemu_xtensa platform. Basically, add the relevant linker
script and ensure that relevant memory regions have their program header
(PHDR) associated.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
This commit is contained in:
Ederson de Souza 2022-10-19 12:25:12 -07:00 • committed by Carles Cufí
commit 8ac6f74a7d
6 changed files with 72 additions and 16 deletions
Download patch file Download diff file Expand all files Collapse all files

12
tests/application_development/code_relocation/CMakeLists.txt
View file

@ -8,16 +8,22 @@ project(code_relocation)
FILE(GLOB app_sources src/*.c)
target_sources(app PRIVATE ${app_sources})
if (CONFIG_BOARD_QEMU_XTENSA)
set(RAM_PHDR :sram0_phdr)
set(SRAM2_PHDR :sram2_phdr)
endif()
# Code relocation feature
zephyr_code_relocate(src/test_file1.c SRAM2)
zephyr_code_relocate(src/test_file1.c "SRAM2 ${SRAM2_PHDR}")
zephyr_code_relocate(src/test_file2.c RAM)
zephyr_code_relocate(src/test_file2.c "RAM ${RAM_PHDR}")
zephyr_code_relocate(src/test_file3.c SRAM2_LITERAL)
zephyr_code_relocate(src/test_file3.c SRAM2_TEXT)
zephyr_code_relocate(src/test_file3.c RAM_DATA)
zephyr_code_relocate(src/test_file3.c SRAM2_BSS)
zephyr_code_relocate(../../../kernel/sem.c RAM)
zephyr_code_relocate(../../../kernel/sem.c "RAM ${RAM_PHDR}")
if (CONFIG_RELOCATE_TO_ITCM)
zephyr_code_relocate(../../../lib/libc/minimal/source/string/string.c ITCM_TEXT)

29
tests/application_development/code_relocation/linker_xtensa_qemu_sram2.ld Normal file
View file

@ -0,0 +1,29 @@
/*
* Copyright 2022 The Chromium OS Authors
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/linker/sections.h>
#include <zephyr/devicetree.h>
#include <zephyr/linker/linker-defs.h>
#include <zephyr/linker/linker-tool.h>
#define SRAM2_ADDR (CONFIG_SRAM_BASE_ADDRESS + RAM_SIZE2)
#define RAM_SIZE2 (0x4000000)
MEMORY
{
SRAM2 (wx) : ORIGIN = (CONFIG_SRAM_BASE_ADDRESS + RAM_SIZE2), LENGTH = RAM_SIZE2
}
PHDRS
{
sram2_phdr PT_LOAD;
}
#define MPU_ALIGN(region_size) \
. = ALIGN(4)
#include <xtensa-sample-controller.ld>

5
tests/application_development/code_relocation/prj_xtensa.conf Normal file
View file

@ -0,0 +1,5 @@
CONFIG_CODE_DATA_RELOCATION=y
CONFIG_ZTEST=y
CONFIG_ZTEST_NEW_API=y
CONFIG_HAVE_CUSTOM_LINKER_SCRIPT=y
CONFIG_CUSTOM_LINKER_SCRIPT="linker_xtensa_qemu_sram2.ld"

3
tests/application_development/code_relocation/testcase.yaml
View file

@ -20,3 +20,6 @@ tests:
tests.application_development.code_relocation.riscv:
extra_args: CONF_FILE="prj_riscv.conf"
platform_allow: qemu_riscv32 qemu_riscv64
tests.application_development.code_relocation.xtensa:
extra_args: CONF_FILE="prj_xtensa.conf"
platform_allow: qemu_xtensa