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soc: lowrisc: move init code from SYS_INIT to hooks

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Replace SYS_INIT with SoC hooks and adapt SoC init code

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2024-09-10 09:42:37 -04:00 • committed by Henrik Brix Andersen
commit 8a16c72023
2 changed files with 2 additions and 3 deletions
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1
soc/lowrisc/opentitan/Kconfig
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@ -20,3 +20,4 @@ config SOC_OPENTITAN
select RISCV_VECTORED_MODE select RISCV_VECTORED_MODE
select GEN_IRQ_VECTOR_TABLE select GEN_IRQ_VECTOR_TABLE
imply XIP imply XIP
select SOC_EARLY_INIT_HOOK

4
soc/lowrisc/opentitan/soc.c
View file

@ -26,7 +26,7 @@
#define RV_TIMER_LOWER0_OFFSET 0x110 #define RV_TIMER_LOWER0_OFFSET 0x110
#define RV_TIMER_COMPARE_LOWER0_OFFSET 0x118 #define RV_TIMER_COMPARE_LOWER0_OFFSET 0x118
static int soc_opentitan_init(void) void soc_early_init_hook(void)
{ {
/* Enable the watchdog reset (bit 1). */ /* Enable the watchdog reset (bit 1). */
sys_write32(2u, PWRMGR_BASE + PWRMGR_RESET_EN_REG_OFFSET); sys_write32(2u, PWRMGR_BASE + PWRMGR_RESET_EN_REG_OFFSET);
@ -40,6 +40,4 @@ static int soc_opentitan_init(void)
sys_write32(1u, RV_TIMER_BASE + RV_TIMER_CTRL_REG_OFFSET); sys_write32(1u, RV_TIMER_BASE + RV_TIMER_CTRL_REG_OFFSET);
/* Enable timer interrupts. */ /* Enable timer interrupts. */
sys_write32(1u, RV_TIMER_BASE + RV_TIMER_INTR_ENABLE_REG_OFFSET); sys_write32(1u, RV_TIMER_BASE + RV_TIMER_INTR_ENABLE_REG_OFFSET);
return 0;
} }
SYS_INIT(soc_opentitan_init, PRE_KERNEL_1, 0);