arm: Add support for Nordic Semiconductor's nRF52 series of ICs

Add SoC support for the Nordic Semiconductor nRF52 series.

JIRA: ZEP-377
Change-Id: Idb476f43d7ca35f87c73910dd9bd1c50032ccdbe
Signed-off-by: Glenn Ruben Bakke <glenn.ruben.bakke@nordicsemi.no>
Signed-off-by: Vinayak Kariappa Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Signed-off-by: Håkon Alseth <haakon.alseth@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>

arch/arm/soc/nordic_nrf5/Kbuild

@@ -0,0 +1,2 @@
+
+obj-y += $(SOC_SERIES)/

arch/arm/soc/nordic_nrf5/Kconfig

@@ -0,0 +1,29 @@
+# Kconfig - Nordic Semiconductor nRF5 MCU line
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+config SOC_NRF5
+	bool
+	# omit prompt to signify a "hidden" option
+	default n
+
+if SOC_FAMILY_NRF5
+config SOC_FAMILY
+	string
+	default nordic_nrf5
+endif
+
+source "arch/arm/soc/nordic_nrf5/*/Kconfig.soc"

arch/arm/soc/nordic_nrf5/Kconfig.defconfig

@@ -0,0 +1,18 @@
+# Kconfig.defconfig - Nordic Semiconductor nRF5 MCU line
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+source "arch/arm/soc/nordic_nrf5/*/Kconfig.defconfig.series"

arch/arm/soc/nordic_nrf5/Kconfig.soc

@@ -0,0 +1,19 @@
+# Kconfig.soc - Nordic Semiconductor nRF5 MCU line
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+source "arch/arm/soc/nordic_nrf5/*/Kconfig.series"
+

arch/arm/soc/nordic_nrf5/nrf52/Kbuild

@@ -0,0 +1 @@
+obj-y += soc.o

arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.nrf52832

@@ -0,0 +1,40 @@
+# Kconfig.defconfig.nrf52832 - Nordic Semiconductor nRF52832 MCU
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+
+if SOC_NRF52832
+
+config SOC
+	string
+	default nRF52832
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	int
+	default 64000000
+
+config SRAM_SIZE
+	default 64
+
+config FLASH_SIZE
+	default 512
+
+config NUM_IRQS
+	int
+	default 38
+
+endif # SOC_NRF52832
+

arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.series

@@ -0,0 +1,35 @@
+# Kconfig.defconfig.series - Nordic Semiconductor nRF5 MCU line
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+if SOC_SERIES_NRF52X
+
+source "arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.nrf52*"
+
+config SOC_SERIES
+	default nordic_nrf5/nrf52
+
+config SRAM_BASE_ADDRESS
+	default 0x20000000
+
+config FLASH_BASE_ADDRESS
+	default 0x00000000
+
+config NUM_IRQ_PRIO_BITS
+	int
+	default 3
+
+endif # SOC_SERIES_NRF52X

arch/arm/soc/nordic_nrf5/nrf52/Kconfig.series

@@ -0,0 +1,28 @@
+# Kconfig.series - Nordic Semiconductor nRF5 MCU line
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+config  SOC_SERIES_NRF52X
+	bool "Nordic Semiconductor nRF52 series MCU"
+	select CPU_CORTEX_M
+	select CPU_CORTEX_M4
+	select SOC_FAMILY_NRF5
+	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	select XIP
+	select HAS_CMSIS
+	select HAS_NORDIC_MDK
+	help
+	 Enable support for NRF52 MCU series

arch/arm/soc/nordic_nrf5/nrf52/Kconfig.soc

@@ -0,0 +1,25 @@
+# Kconfig.soc - Nordic Semiconductor nRF52 MCU line
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+choice
+prompt "nRF52x MCU Selection"
+depends on SOC_SERIES_NRF52X
+
+config SOC_NRF52832
+       bool "NRF52832"
+
+endchoice

arch/arm/soc/nordic_nrf5/nrf52/Makefile

@@ -0,0 +1,10 @@
+arch-cflags += $(call cc-option,-mthumb -mcpu=cortex-m4) \
+		$(call cc-option,-march=armv7e-m) \
+		$(call cc-option,-mabi=aapcs) \
+
+_CROSS_COMPILE_arm_isa = armv7e-m
+export _CROSS_COMPILE_arm_isa
+
+KBUILD_CFLAGS += $(arch-cflags)
+KBUILD_CXXFLAGS += $(arch-cflags)
+KBUILD_AFLAGS += $(arch-cflags)

arch/arm/soc/nordic_nrf5/nrf52/linker.ld

@@ -0,0 +1,19 @@
+/* linker.ld - Linker command/script file */
+
+/*
+ * Copyright (c) 2014 Wind River Systems, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <arch/arm/cortex_m/scripts/linker.ld>

arch/arm/soc/nordic_nrf5/nrf52/soc.c

@@ -0,0 +1,250 @@
+/*
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Nordic Semiconductor nRF52 family processor
+ *
+ * This module provides routines to initialize and support board-level hardware
+ * for the Nordic Semiconductor nRF52 family processor.
+ */
+
+#include <nanokernel.h>
+#include <device.h>
+#include <init.h>
+#include <soc.h>
+
+#ifdef CONFIG_RUNTIME_NMI
+extern void _NmiInit(void);
+#define NMI_INIT() _NmiInit()
+#else
+#define NMI_INIT()
+#endif
+
+#include "system_nrf52.h"
+
+#define __SYSTEM_CLOCK_64M (64000000UL)
+
+static bool ftpan_32(void);
+static bool ftpan_37(void);
+static bool ftpan_36(void);
+
+uint32_t SystemCoreClock __used = __SYSTEM_CLOCK_64M;
+
+static void clock_init(void)
+{
+	SystemCoreClock = __SYSTEM_CLOCK_64M;
+}
+
+static int nordicsemi_nrf52_init(struct device *arg)
+{
+	uint32_t key;
+
+	ARG_UNUSED(arg);
+
+	/* Note:
+	* Magic numbers below are obtained by reading the registers
+	* when the SoC was running the SAM-BA bootloader
+	* (with reserved bits set to 0).
+	*/
+
+	key = irq_lock();
+
+	/* Setup the vector table offset register (VTOR),
+	* which is located at the beginning of flash area.
+	*/
+	_scs_relocate_vector_table((void *)CONFIG_FLASH_BASE_ADDRESS);
+
+	/* Workaround for FTPAN-32 "DIF: Debug session automatically
+	* enables TracePort pins" found at Product Anomaly document
+	* for your device located at https://www.nordicsemi.com/
+	*/
+	if (ftpan_32()) {
+		CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
+	}
+
+	/* Workaround for FTPAN-37 "AMLI: EasyDMA is slow with Radio,
+	* ECB, AAR and CCM." found at Product Anomaly document
+	* for your device located at https://www.nordicsemi.com/
+	*/
+	if (ftpan_37()) {
+		*(volatile uint32_t *)0x400005A0 = 0x3;
+	}
+
+	/* Workaround for FTPAN-36 "CLOCK: Some registers are not
+	* reset when expected." found at Product Anomaly document
+	* for your device located at https://www.nordicsemi.com/
+	*/
+	if (ftpan_36()) {
+		NRF_CLOCK->EVENTS_DONE = 0;
+		NRF_CLOCK->EVENTS_CTTO = 0;
+	}
+
+	/* Enable the FPU if the compiler used floating point unit
+	* instructions. __FPU_USED is a MACRO defined by the
+	* compiler. Since the FPU consumes energy, remember to
+	* disable FPU use in the compiler if floating point unit
+	* operations are not used in your code.
+	*/
+	#if (__FPU_USED == 1)
+
+	SCB->CPACR |= (3UL << 20) | (3UL << 22);
+	__DSB();
+	__ISB();
+
+	#endif
+
+	/* Configure NFCT pins as GPIOs if NFCT is not to be used in
+	* your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
+	* two GPIOs (see Product Specification to see which ones)
+	* will be reserved for NFC and will not be available as
+	* normal GPIOs.
+	*/
+	#if defined(CONFIG_NFCT_PINS_AS_GPIOS)
+
+	if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) ==
+	    (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)) {
+
+		NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NVIC_SystemReset();
+	}
+
+	#endif
+
+	/* Configure GPIO pads as pPin Reset pin if Pin Reset
+	* capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
+	* defined, pin reset will not be available. One GPIO (see
+	* Product Specification to see which one) will then be
+	* reserved for PinReset and not available as normal GPIO.
+	*/
+	#if defined(CONFIG_GPIO_AS_PINRESET)
+	if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) !=
+	     (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
+	    ((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) !=
+	     (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))) {
+
+		NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NRF_UICR->PSELRESET[0] = 21;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NRF_UICR->PSELRESET[1] = 21;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NVIC_SystemReset();
+	}
+	#endif
+
+	/* Enable SWO trace functionality. If ENABLE_SWO is not
+	* defined, SWO pin will be used as GPIO (see Product
+	* Specification to see which one).
+	*/
+	#if defined(ENABLE_SWO)
+
+	CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+	NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial <<
+				  CLOCK_TRACECONFIG_TRACEMUX_Pos;
+	#endif
+
+	/* Enable Trace functionality. If ENABLE_TRACE is not
+	* defined, TRACE pins will be used as GPIOs (see Product
+	* Specification to see which ones).
+	*/
+	#if defined(ENABLE_TRACE)
+	CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+	NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel <<
+				  CLOCK_TRACECONFIG_TRACEMUX_Pos;
+	#endif
+
+	/* Clear all faults */
+	_ScbMemFaultAllFaultsReset();
+	_ScbBusFaultAllFaultsReset();
+	_ScbUsageFaultAllFaultsReset();
+
+	_ScbHardFaultAllFaultsReset();
+
+	/* Setup master clock */
+	clock_init();
+
+	/* Install default handler that simply resets the CPU
+	* if configured in the kernel, NOP otherwise
+	*/
+	NMI_INIT();
+
+	irq_unlock(key);
+
+	return 0;
+}
+
+static bool ftpan_32(void)
+{
+	if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
+	    (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
+		if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
+		    (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
+			return true;
+		}
+	}
+
+	return false;
+}
+
+static bool ftpan_37(void)
+{
+	if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
+	    (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
+		if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
+		    (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
+			return true;
+		}
+	}
+
+	return false;
+}
+
+static bool ftpan_36(void)
+{
+	if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
+	    (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
+		if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
+		    (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
+			return true;
+		}
+	}
+
+	return false;
+}
+
+SYS_INIT(nordicsemi_nrf52_init, PRIMARY, 0);

arch/arm/soc/nordic_nrf5/nrf52/soc.h

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file SoC configuration macros for the Nordic Semiconductor nRF52 family processors.
+ */
+
+#ifndef _NORDICSEMI_NRF52_SOC_H_
+#define _NORDICSEMI_NRF52_SOC_H_
+
+#ifndef _ASMLANGUAGE
+
+#include "soc_irq.h"
+#include <nrf52.h>
+#include <nrf52_bitfields.h>
+#include <device.h>
+#include <misc/util.h>
+#include <drivers/rand32.h>
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _NORDICSEMI_NRF52_SOC_H_ */

arch/arm/soc/nordic_nrf5/nrf52/soc_irq.h

@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Interrupt numbers for NRF52 family processors.
+ *
+ * Based on Nordic MDK included header file: nrf52.h
+ */
+
+
+#ifndef _NRF52_SOC_IRQ_H_
+#define _NRF52_SOC_IRQ_H_
+
+#define NRF52_IRQ_POWER_CLOCK_IRQn			 0
+#define NRF52_IRQ_RADIO_IRQn				 1
+#define NRF52_IRQ_UARTE0_UART0_IRQn			 2
+#define NRF52_IRQ_SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn 3
+#define NRF52_IRQ_SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn 4
+#define NRF52_IRQ_NFCT_IRQn				 5
+#define NRF52_IRQ_GPIOTE_IRQn				 6
+#define NRF52_IRQ_SAADC_IRQn				 7
+#define NRF52_IRQ_TIMER0_IRQn				 8
+#define NRF52_IRQ_TIMER1_IRQn				 9
+#define NRF52_IRQ_TIMER2_IRQn				 10
+#define NRF52_IRQ_RTC0_IRQn				 11
+#define NRF52_IRQ_TEMP_IRQn				 12
+#define NRF52_IRQ_RNG_IRQn				 13
+#define NRF52_IRQ_ECB_IRQn				 14
+#define NRF52_IRQ_CCM_AAR_IRQn				 15
+#define NRF52_IRQ_WDT_IRQn				 16
+#define NRF52_IRQ_RTC1_IRQn				 17
+#define NRF52_IRQ_QDEC_IRQn				 18
+#define NRF52_IRQ_COMP_LPCOMP_IRQn			 19
+#define NRF52_IRQ_SWI0_EGU0_IRQn			 20
+#define NRF52_IRQ_SWI1_EGU1_IRQn			 21
+#define NRF52_IRQ_SWI2_EGU2_IRQn			 22
+#define NRF52_IRQ_SWI3_EGU3_IRQn			 23
+#define NRF52_IRQ_SWI4_EGU4_IRQn			 24
+#define NRF52_IRQ_SWI5_EGU5_IRQn			 25
+#define NRF52_IRQ_TIMER3_IRQn				 26
+#define NRF52_IRQ_TIMER4_IRQn				 27
+#define NRF52_IRQ_PWM0_IRQn				 28
+#define NRF52_IRQ_PDM_IRQn				 29
+#define NRF52_IRQ_MWU_IRQn				 32
+#define NRF52_IRQ_PWM1_IRQn				 33
+#define NRF52_IRQ_PWM2_IRQn				 34
+#define NRF52_IRQ_SPIM2_SPIS2_SPI2_IRQn			 35
+#define NRF52_IRQ_RTC2_IRQn				 36
+#define NRF52_IRQ_I2S_IRQn				 37
+#define NRF52_IRQ_FPU_IRQn				 38
+
+#endif /* _NRF52_SOC_IRQ_H_ */