From 8922afb0f8debcf034e4c1ed0622304f19de8955 Mon Sep 17 00:00:00 2001 From: Evgeniy Didin Date: Tue, 12 Nov 2019 11:00:51 +0300 Subject: [PATCH] arc: hsdk: Set SRAM_BASE_ADDRESS in defconfig On power-on boot-ROM is mapped to address 0 in HSDK board. Normally later when U-Boot gets started by boot-ROM we change mappings so that real DDR is mapped to entire address space including 0: https://elixir.bootlin.com/u-boot/latest/source/board/synopsys/hsdk/hsdk.c#L474 But if U-Boot is not started (which is controlled by the BIM dip-switch on the board) boot-ROM remains mapped to 0, and essentially any attempt to write to that location fails, thus we cannot upload contents of our target Elf there even with JTAG. The next logical option is to use beginning of the non-translated memory region 0x8000_0000 which we typically use for loading U-Boot & Linux kernel on ARC boards. But in case of HSDK we have DCCM (Data Closely-Coupled MEmory - fast on-chip SRAM) mapped there and since we cannot execute code from DCCM we need to skip that region as well which gives us the next option being 0x9000_0000 . That's because DCCM owns entire 256 MiB "aperture" even though it may have much smaller size up-to 8 MiB. We are mapping only 5 apertures because the last two (0xe000_0000-0xffff_ffff) are used for peripherals and AXI. Signed-off-by: Evgeniy Didin Signed-off-by: Alexey Brodkin --- dts/arc/arc_hsdk.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/dts/arc/arc_hsdk.dtsi b/dts/arc/arc_hsdk.dtsi index 4fb12a1d997..3d556f316f7 100644 --- a/dts/arc/arc_hsdk.dtsi +++ b/dts/arc/arc_hsdk.dtsi @@ -61,10 +61,10 @@ interrupt-parent = <&idu_intc>; ranges; - ddr0: memory@0 { + ddr0: memory@90000000 { device_type = "memory"; compatible = "mmio-sram"; - reg = <0x0 0x80000000>; + reg = <0x90000000 0x50000000>; }; uart0: uart@f0005000 { @@ -186,4 +186,4 @@ }; }; -}; \ No newline at end of file +};