From 8907c09fee1d77dc523b7ba188f31e1c26e8d528 Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Fri, 30 Nov 2018 15:16:00 -0800 Subject: [PATCH] soc/miv: Use DTS to generate PLIC addresses Describe the MMIO register regions for the PLIC in the DTS instead of hardcoded in soc.h. Signed-off-by: Nathaniel Graff --- dts/riscv32/microsemi-miv.dtsi | 6 ++++-- soc/riscv32/riscv-privilege/miv/dts_fixup.h | 10 ++++++++++ soc/riscv32/riscv-privilege/miv/soc.h | 8 -------- 3 files changed, 14 insertions(+), 10 deletions(-) diff --git a/dts/riscv32/microsemi-miv.dtsi b/dts/riscv32/microsemi-miv.dtsi index dd78d43edfc..bcd7f5139e5 100644 --- a/dts/riscv32/microsemi-miv.dtsi +++ b/dts/riscv32/microsemi-miv.dtsi @@ -36,8 +36,10 @@ compatible = "riscv,plic0"; interrupt-controller; interrupts-extended = <&hlic 11>; - reg = <0x40000000 0x4000000>; - reg-names = "control"; + reg = <0x40000000 0x2000 + 0x40002000 0x1fe000 + 0x40200000 0x2000000>; + reg-names = "prio", "irq_en", "reg"; riscv,max-priority = <1>; }; diff --git a/soc/riscv32/riscv-privilege/miv/dts_fixup.h b/soc/riscv32/riscv-privilege/miv/dts_fixup.h index 872173c0ad8..69d1d42280a 100644 --- a/soc/riscv32/riscv-privilege/miv/dts_fixup.h +++ b/soc/riscv32/riscv-privilege/miv/dts_fixup.h @@ -1,4 +1,14 @@ +/* PLIC */ +#define DT_PLIC_MAX_PRIORITY \ + DT_RISCV_PLIC0_40000000_RISCV_MAX_PRIORITY +#define DT_PLIC_PRIO_BASE_ADDR \ + DT_RISCV_PLIC0_40000000_PRIO_BASE_ADDRESS +#define DT_PLIC_IRQ_EN_BASE_ADDR \ + DT_RISCV_PLIC0_40000000_IRQ_EN_BASE_ADDRESS +#define DT_PLIC_REG_BASE_ADDR \ + DT_RISCV_PLIC0_40000000_REG_BASE_ADDRESS + /* UART 0 */ #define DT_MIV_UART_0_BASE_ADDR DT_MICROSEMI_COREUART_70001000_BASE_ADDRESS #define DT_MIV_UART_0_CLOCK_FREQUENCY DT_MICROSEMI_COREUART_70001000_CLOCK_FREQUENCY diff --git a/soc/riscv32/riscv-privilege/miv/soc.h b/soc/riscv32/riscv-privilege/miv/soc.h index 68076dc8960..636df020af5 100644 --- a/soc/riscv32/riscv-privilege/miv/soc.h +++ b/soc/riscv32/riscv-privilege/miv/soc.h @@ -43,14 +43,6 @@ /* GPIO Configuration */ #define MIV_GPIO_0_BASE_ADDR 0x70002000 -/* Platform Level Interrupt Controller Configuration */ -#define MIV_PLIC_BASE_ADDR 0x40000000 -#define MIV_PLIC_PRIO_BASE_ADDR MIV_PLIC_BASE_ADDR -#define MIV_PLIC_IRQ_EN_BASE_ADDR (MIV_PLIC_BASE_ADDR + 0x2000) -#define MIV_PLIC_REG_BASE_ADDR (MIV_PLIC_BASE_ADDR + 0x200000) - -#define MIV_PLIC_MAX_PRIORITY 7 - /* Clock controller. */ #define PRCI_BASE_ADDR 0x44000000