boards: stm32: Add nucleo_h755zi_q support

Add support for the ST nucleo h755zi_q board which
uses an stm32h755 in the st nucleo-144 board
format.

Signed-off-by: Mike Banducci <michael.banducci@sandc.com>

boards/st/nucleo_h755zi_q/Kconfig.defconfig

@@ -0,0 +1,15 @@
+# STM32H755ZI Nucleo board configuration
+
+# Copyright (c) 2024 S&C Electric Company <Michael.Banducci@sandc.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_NUCLEO_H755ZI_Q
+
+if NETWORKING
+
+config NET_L2_ETHERNET
+	default y
+
+endif # NETWORKING
+
+endif # BOARD_NUCLEO_H755ZI_Q

boards/st/nucleo_h755zi_q/Kconfig.nucleo_h755zi_q

@@ -0,0 +1,8 @@
+# STM32H755ZI Nucleo board configuration
+
+# Copyright (c) 2024 S&C Electric Company <Michael.Banducci@sandc.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_NUCLEO_H755ZI_Q
+	select SOC_STM32H755XX_M7 if BOARD_NUCLEO_H755ZI_Q_STM32H755XX_M7
+	select SOC_STM32H755XX_M4 if BOARD_NUCLEO_H755ZI_Q_STM32H755XX_M4

boards/st/nucleo_h755zi_q/arduino_r3_connector.dtsi

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2024 S&C Electric Company <Michael.Banducci@sandc.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	arduino_header: connector {
+		compatible = "arduino-header-r3";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <0 0 &gpioa 3 0>,	/* A0 */
+			   <1 0 &gpioc 0 0>,	/* A1 */
+			   <2 0 &gpioc 3 0>,	/* A2 */
+			   <3 0 &gpiob 1 0>,	/* A3 */
+			   <4 0 &gpioc 2 0>,	/* A4 */
+			   <5 0 &gpiof 11 0>,	/* A5 */
+			   <6 0 &gpiob 7 0>,	/* D0 */
+			   <7 0 &gpiob 6 0>,	/* D1 */
+			   <8 0 &gpiog 14 0>,	/* D2 */
+			   <9 0 &gpioe 13 0>,	/* D3 */
+			   <10 0 &gpioe 14 0>,	/* D4 */
+			   <11 0 &gpioe 11 0>,	/* D5 */
+			   <12 0 &gpioa 8 0>,	/* D6 */
+			   <13 0 &gpiog 12 0>,	/* D7 */
+			   <14 0 &gpiog 9 0>,	/* D8 */
+			   <15 0 &gpiod 15 0>,	/* D9 */
+			   <16 0 &gpiod 14 0>,	/* D10 */
+			   <17 0 &gpiob 5 0>,	/* D11 */
+			   <18 0 &gpioa 6 0>,	/* D12 */
+			   <19 0 &gpioa 5 0>,	/* D13 */
+			   <20 0 &gpiob 9 0>,	/* D14 */
+			   <21 0 &gpiob 8 0>;	/* D15 */
+	};
+};
+
+arduino_i2c: &i2c1 {};
+
+arduino_serial: &uart8 {};

boards/st/nucleo_h755zi_q/board.cmake

@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
+board_runner_args(jlink "--device=STM32H755ZI" "--speed=3300")
+if(CONFIG_BOARD_NUCLEO_H755ZI_Q_STM32H755XX_M7)
+  board_runner_args(openocd --target-handle=_CHIPNAME.cpu0)
+elseif(CONFIG_BOARD_NUCLEO_H755ZI_Q_STM32H755XX_M4)
+  board_runner_args(openocd --target-handle=_CHIPNAME.cpu1)
+endif()
+
+include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/st/nucleo_h755zi_q/board.yml

@@ -0,0 +1,5 @@
+board:
+  name: nucleo_h755zi_q
+  vendor: st
+  socs:
+    - name: stm32h755xx

boards/st/nucleo_h755zi_q/doc/index.rst

@@ -0,0 +1,295 @@
+.. _nucleo_h755zi_q_board:
+
+ST Nucleo H755ZI-Q
+###################
+
+Overview
+********
+
+The NUCLEO-H755ZI-Q board, based on the MB1363 reference board, provides an affordable and
+flexible way for users to try out new concepts and build prototypes on the STM32H755ZIT6
+microcontroller.
+
+The ST Zio connector, which extends the ARDUINO® Uno V3 connectivity, and
+the ST morpho headers provide an easy means of expanding the functionality of the Nucleo
+open development platform with a wide choice of specialized shields.
+The NUCLEO-H755ZI-Q board does not require any separate probe as it integrates
+the ST-LINK V3 debugger/programmer.
+
+Key Features
+
+- STM32H755ZIT6 microcontroller in LQFP144 package
+- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support)
+- USB OTG or full-speed device (depending on STM32 support)
+- 3 user LEDs
+- 2 user and reset push-buttons
+- 32.768 kHz crystal oscillator
+- Board connectors:
+
+ - USB with Micro-AB
+ - Ethernet RJ45 (depending on STM32 support)
+ - SWDST Zio connector including Arduino* Uno V3ST
+ - ST morpho expansion
+
+- Flexible power-supply options: ST-LINK USB VBUS or external sources
+- External or internal SMPS to generate Vcore logic supply
+- On-board ST-LINK/V3 debugger/programmer with USB re-enumeration
+- capability: mass storage, virtual COM port and debug port
+- USB OTG full speed or device only
+
+.. image:: img/nucleo_h755zi_q.webp
+   :align: center
+   :alt: Nucleo H755ZI-Q
+
+More information about the board can be found at the `Nucleo H755ZI-Q website`_.
+
+Hardware
+********
+
+Nucleo H755ZI-Q provides the following hardware components:
+
+- STM32H755ZI in LQFP144 package
+- ARM 32-bit Cortex-M7 CPU with FPU
+- ARM 32-bit Cortex-M4 CPU with FPU
+- Chrom-ART Accelerator
+- Hardware JPEG Codec
+- 480 MHz max CPU frequency
+- VDD from 1.62 V to 3.6 V
+- 2 MB Flash
+- 1 MB SRAM
+- High-resolution timer (2.1 ns)
+- 32-bit timers(2)
+- 16-bit timers(12)
+- SPI(6)
+- I2C(4)
+- I2S (3)
+- USART(4)
+- UART(4)
+- USB OTG Full Speed and High Speed(1)
+- USB OTG Full Speed(1)
+- CAN-FD(2)
+- SAI(2)
+- SPDIF_Rx(4)
+- HDMI_CEC(1)
+- Dual Mode Quad SPI(1)
+- Camera Interface
+- GPIO (up to 114) with external interrupt capability
+- 16-bit ADC(3) with 36 channels / 3.6 MSPS
+- 12-bit DAC with 2 channels(2)
+- True Random Number Generator (RNG)
+- 16-channel DMA
+- LCD-TFT Controller with XGA resolution
+- CRYPT and HASH peripherals
+
+Supported Features
+==================
+
+The Zephyr nucleo_h755zi_q board configuration supports the following hardware
+features:
+
++-------------+------------+-------------------------------------+
+| Interface   | Controller | Driver/Component                    |
++=============+============+=====================================+
+| NVIC        | on-chip    | nested vector interrupt controller  |
++-------------+------------+-------------------------------------+
+| UART/USART  | on-chip    | serial port                         |
++-------------+------------+-------------------------------------+
+| PINMUX      | on-chip    | pinmux                              |
++-------------+------------+-------------------------------------+
+| GPIO        | on-chip    | gpio                                |
++-------------+------------+-------------------------------------+
+| RTC         | on-chip    | counter                             |
++-------------+------------+-------------------------------------+
+| I2C         | on-chip    | i2c                                 |
++-------------+------------+-------------------------------------+
+| PWM         | on-chip    | pwm                                 |
++-------------+------------+-------------------------------------+
+| ETHERNET    | on-chip    | ethernet                            |
++-------------+------------+-------------------------------------+
+| RNG         | on-chip    | True Random number generator        |
++-------------+------------+-------------------------------------+
+| USB OTG FS  | on-chip    | USB device                          |
++-------------+------------+-------------------------------------+
+
+Other hardware features are not yet supported on this Zephyr port.
+
+The default configuration per core can be found in the defconfig files:
+:zephyr_file:`boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7_defconfig` and
+:zephyr_file:`boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m4_defconfig`
+
+For mode details please refer to `STM32 Nucleo-144 board User Manual`_.
+
+Default Zephyr Peripheral Mapping:
+----------------------------------
+
+The Nucleo H755ZI board features a ST Zio connector (extended Arduino Uno V3)
+and a ST morpho connector. Board is configured as follows:
+
+- USART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com)
+- USER_PB : PC13
+- LD1 : PA5
+- LD2 : PE1
+- LD3 : PB14
+- I2C : PB8, PB9
+
+System Clock
+------------
+
+Nucleo H755ZI-Q System Clock can be driven by an internal or external
+oscillator, as well as the main PLL clock. By default, the System clock is
+driven by the PLL clock at 480MHz, driven by an 8MHz high-speed external clock.
+
+Serial Port
+-----------
+
+Nucleo H755ZI-Q board has 4 UARTs and 4 USARTs. The Zephyr console output is
+assigned to USART3. Default settings are 115200 8N1.
+
+Resources sharing
+-----------------
+
+The dual core nature of STM32H755 SoC requires sharing HW resources between the
+two cores. This is done in 3 ways:
+
+- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only
+  has access to bus clock activation and deactivation.
+- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in
+  devicetree before compilation. The user must ensure peripherals are not assigned
+  to both cores at the same time.
+- **Run time protection**: Interrupt-controller and GPIO configurations could be
+  accessed by both cores at run time. Accesses are protected by a hardware semaphore
+  to avoid potential concurrent access issues.
+
+Programming and Debugging
+*************************
+
+Applications for the ``nucleo_h755zi_q`` board should be built per core target,
+using either ``nucleo_h755zi_q/stm32h755xx/m7`` or ``nucleo_h755zi_q/stm32h755xx/m4``
+as the target (see :ref:`build_an_application` and :ref:`application_run` for more
+details).
+
+.. note::
+
+   Check if the board's ST-LINK V3 has the newest firmware version. It can be
+   updated with `STM32CubeIDE`_
+
+Flashing
+========
+
+Nucleo H755ZI-Q board includes an ST-LINK/V3 embedded debug tool interface.
+
+The board is configured to be flashed using west `STM32CubeProgrammer`_ runner
+for both cores, so its installation is required to be able to flash the board.
+The target core is detected automatically.
+
+It is advised to use `STM32CubeProgrammer`_ to check and update option bytes
+configuration and flash ``nucleo_h755zi_q/stm32h755xx/m7`` and
+``nucleo_h755zi_q/stm32h755xx/m4`` board targets.
+
+By default:
+
+  - CPU0 (Cortex-M7) boot address is set to 0x08000000 (OB: BOOT_CM7_ADD0)
+  - CPU1 (Cortex-M4) boot address is set to 0x08100000 (OB: BOOT_CM4_ADD0)
+
+Also, default out of the box board configuration enables CM7 and CM4 boot when
+board is powered (Option bytes BCM7 and BCM4 are checked).
+In that configuration, Kconfig boot option ``STM32H7_BOOT_CM4_CM7`` should be selected.
+Zephyr flash configuration has been set to meet these default settings.
+
+Alternatively, openocd or JLink can also be used to flash the board using
+the ``--runner`` (or ``-r``) option:
+
+.. code-block:: console
+
+   $ west flash --runner openocd
+   $ west flash --runner jlink
+
+Flashing an application to STM32H755ZI M7 Core
+----------------------------------------------
+First, connect the NUCLEO-H755ZI-Q to your host computer using
+the USB port to prepare it for flashing. Then build and flash your application.
+
+Here is an example for the :ref:`hello_world` application.
+
+Run a serial host program to connect with your NUCLEO-H755ZI-Q board.
+
+.. code-block:: console
+
+   $ minicom -b 115200 -D /dev/ttyACM0
+
+or use screen:
+
+.. code-block:: console
+
+   $ screen /dev/ttyACM0 115200
+
+Build and flash the application:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: nucleo_h755zi_q/stm32h755xx/m7
+   :goals: build flash
+
+You should see the following message on the console:
+
+.. code-block:: console
+
+   $ Hello World! nucleo_h755zi_q/stm32h755xx/m7
+
+.. note::
+  Sometimes, flashing via OpenOCD does not work. It is necessary to erase the flash
+  (with STM32CubeProgrammer for example) to make it work again.
+
+Similarly, you can build and flash samples on the M4 target. For this, please
+take care of the resource sharing (UART port used for console for instance).
+
+Here is an example for the :zephyr:code-sample:`blinky` application on M4 core.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: nucleo_h755zi_q/stm32h755xx/m4
+   :goals: build flash
+
+.. note::
+
+   Flashing both M4 and M7 and pushing RESTART button on the board leads
+   to LD1 and LD2 flashing simultaneously.
+
+Debugging
+=========
+
+You can debug an application on the Cortex M7 core in the usual way.
+Here is an example for the :ref:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: nucleo_h755zi_q/stm32h755xx/m7
+   :maybe-skip-config:
+   :goals: debug
+
+Debugging a Zephyr application on Cortex M4 side with west is currently not
+available. As a workaround, `STM32CubeIDE`_ can be used.
+
+.. _Nucleo H755ZI-Q website:
+   https://www.st.com/en/evaluation-tools/nucleo-h755zi-q.html
+
+.. _STM32 Nucleo-144 board User Manual:
+   https://www.st.com/resource/en/user_manual/dm00499171-stm32h7-nucleo144-boards-mb1363-stmicroelectronics.pdf
+
+.. _STM32H755ZI on www.st.com:
+   https://www.st.com/en/microcontrollers-microprocessors/stm32h755zi.html
+
+.. _STM32H755 reference manual:
+   https://www.st.com/resource/en/reference_manual/dm00176879-stm32h745755-and-stm32h747757-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
+
+.. _OpenOCD installing Debug Version:
+   https://github.com/zephyrproject-rtos/openocd
+
+.. _OpenOCD installing with ST-LINK V3 support:
+   https://mbd.kleier.net/integrating-st-link-v3.html
+
+.. _STM32CubeIDE:
+   https://www.st.com/en/development-tools/stm32cubeide.html
+
+.. _STM32CubeProgrammer:
+   https://www.st.com/en/development-tools/stm32cubeprog.html

boards/st/nucleo_h755zi_q/nucleo_h755zi_q.dtsi

@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2024 S&C Electric Company <Michael.Banducci@sandc.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/h7/stm32h755zitx-pinctrl.dtsi>
+#include "arduino_r3_connector.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	leds: leds {
+		compatible = "gpio-leds";
+		green_led: led_1 {
+			gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>;
+			label = "User LD1";
+		};
+		yellow_led: led_2 {
+			gpios = <&gpioe 1 GPIO_ACTIVE_HIGH>;
+			label = "User LD2";
+		};
+		red_led: led_3 {
+			gpios = <&gpiob 14 GPIO_ACTIVE_HIGH>;
+			label = "User LD3";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		user_button: button_0 {
+			gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
+			label = "User SB1";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+};
+
+&rcc {
+	d1cpre = <1>;
+	hpre = <2>;
+	d1ppre = <2>;
+	d2ppre1 = <2>;
+	d2ppre2 = <2>;
+	d3ppre = <2>;
+};
+
+&mailbox {
+	status = "okay";
+};

boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m4.dts

@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2024 S&C Electric Company <Michael.Banducci@sandc.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/h7/stm32h755Xi_m4.dtsi>
+#include "nucleo_h755zi_q.dtsi"
+
+/ {
+	model = "STMicroelectronics STM32H755ZI-Q-NUCLEO board";
+	compatible = "st,stm32h755zi-q-nucleo";
+
+	/* HW resources belonging to CM4 */
+	chosen {
+		zephyr,console = &uart8;
+		zephyr,shell-uart = &uart8;
+		zephyr,sram = &sram1;
+		zephyr,flash = &flash1;
+	};
+
+	aliases {
+		led0 = &yellow_led;
+	};
+};
+
+&uart8 {
+	pinctrl-0 = <&uart8_tx_pe1 &uart8_rx_pe0>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&rcc {
+	clock-frequency = <DT_FREQ_M(240)>;
+};

boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m4.yaml

@@ -0,0 +1,18 @@
+identifier: nucleo_h755zi_q/stm32h755xx/m4
+name: ST Nucleo H755ZI-Q (M4)
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+ram: 288
+flash: 1024
+supported:
+  - arduino_gpio
+  - gpio
+  - netif:eth
+testing:
+  ignore_tags:
+    - mpu
+    - nfc
+vendor: st

boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m4_defconfig

@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2024 S&C Electric Company <Michael.Banducci@sandc.com>
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable clock
+CONFIG_CLOCK_CONTROL=y
+
+# By default SERIAL peripherals are assigned to m7
+
+# Enable uart driver
+#CONFIG_SERIAL=y
+
+# Console
+#CONFIG_CONSOLE=y
+#CONFIG_UART_CONSOLE=y
+
+# Enable pin controller
+CONFIG_PINCTRL=y

boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.dts

@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2024 S&C Electric Company <Michael.Banducci@sandc.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/h7/stm32h755Xi_m7.dtsi>
+#include "nucleo_h755zi_q.dtsi"
+
+/*
+ * WARNING:
+ * Possible pin conflicts: The pins PA2 and PB13 may conflict on selection of
+ * ETH_STM32_HAL, since they are used in ST Zio or ST morpho connectors. To
+ * avoid conflicting states the jumpers JP6 and JP7 must be in ON state.
+ */
+
+/ {
+	model = "STMicroelectronics STM32H755ZI-Q-NUCLEO board";
+	compatible = "st,stm32h755zi-q-nucleo";
+
+	/* HW resources belonging to CM7 */
+	chosen {
+		zephyr,console = &usart3;
+		zephyr,shell-uart = &usart3;
+		zephyr,dtcm = &dtcm;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		red_pwm_led: red_pwm_led {
+			pwms = <&pwm12 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
+			label = "User LD3 - PWM12";
+		};
+	};
+
+	aliases {
+		led0 = &green_led;
+		pwm-led0 = &red_pwm_led;
+		sw0 = &user_button;
+	};
+};
+
+&clk_lsi {
+	status = "okay";
+};
+
+&clk_hsi48 {
+	status = "okay";
+};
+
+&clk_hse {
+	hse-bypass;
+	clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
+	status = "okay";
+};
+
+&pll {
+	div-m = <1>;
+	mul-n = <120>;
+	div-p = <2>;
+	div-q = <8>;
+	div-r = <2>;
+	clocks = <&clk_hse>;
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(480)>;
+};
+
+&usart3 {
+	pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&rtc {
+	clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>,
+		 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
+	status = "okay";
+};
+
+&i2c1 {
+	pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
+	pinctrl-names = "default";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&timers12 {
+	st,prescaler = <10000>;
+	status = "okay";
+
+	pwm12: pwm {
+		status = "okay";
+		pinctrl-0 = <&tim12_ch1_pb14>;
+		pinctrl-names = "default";
+	};
+};
+
+&mac {
+	status = "okay";
+	pinctrl-0 = <&eth_ref_clk_pa1
+		     &eth_crs_dv_pa7
+		     &eth_rxd0_pc4
+		     &eth_rxd1_pc5
+		     &eth_tx_en_pg11
+		     &eth_txd0_pg13
+		     &eth_txd1_pb13>;
+	pinctrl-names = "default";
+};
+
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
+	pinctrl-names = "default";
+
+	ethernet-phy@0 {
+		compatible = "ethernet-phy";
+		reg = <0x00>;
+		status = "okay";
+	};
+};
+
+&rng {
+	status = "okay";
+};
+
+zephyr_udc0: &usbotg_fs {
+	pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
+	pinctrl-names = "default";
+	status = "okay";
+};

boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.yaml

@@ -0,0 +1,20 @@
+identifier: nucleo_h755zi_q/stm32h755xx/m7
+name: ST Nucleo H755ZI-Q (M7)
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+ram: 512
+flash: 1024
+supported:
+  - arduino_gpio
+  - arduino_i2c
+  - uart
+  - gpio
+  - counter
+  - i2c
+  - pwm
+  - netif:eth
+  - usb_device
+vendor: st

boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7_defconfig

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+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2024 S&C Electric Company <Michael.Banducci@sandc.com>
+
+# Enable the internal SMPS regulator
+CONFIG_POWER_SUPPLY_DIRECT_SMPS=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable HW stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable UART (disable to assign to M4 core)
+CONFIG_SERIAL=y
+
+# Console (disable to assign to M4 core)
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable Clock
+CONFIG_CLOCK_CONTROL=y
+
+# Enable pin controller
+CONFIG_PINCTRL=y

boards/st/nucleo_h755zi_q/support/openocd.cfg

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+# STM32H745ZI Nucleo board OpenOCD ST-LINK V3 configuration
+#
+# Copyright (c) 2024 S&C Electric Company <Michael.Banducci@sandc.com>
+# SPDX-License-Identifier: Apache-2.0
+#
+
+# Borrow the nucleo_h745zi openocd configuration as no config exists for the h755 yet.
+source [find board/st_nucleo_h745zi.cfg]
+
+# Use connect_assert_srst here to be able to program
+# even when core is in sleep mode
+reset_config srst_only srst_nogate connect_assert_srst
+
+$_CHIPNAME.cpu0 configure -event gdb-attach {
+        echo "Debugger attaching: halting execution"
+        gdb_breakpoint_override hard
+}
+
+$_CHIPNAME.cpu0 configure -event gdb-detach {
+        echo "Debugger detaching: resuming execution"
+        resume
+}
+
+# Due to the use of connect_assert_srst, running gdb requires
+# to reset halt just after openocd init.
+rename init old_init
+proc init {} {
+        old_init
+        reset halt
+}