From 888607d550709c5338b1dc0970878faa5ae9b268 Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Wed, 21 Dec 2022 15:53:44 +0100 Subject: [PATCH] tests: clock_control: stm32h7: pll2: Fix test configuration In test spi1_pll2p_1, pll2 should be enabled instead of pll3. Signed-off-by: Erwan Gouriou --- .../stm32h7_devices/boards/spi1_pll2p_1.overlay | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/spi1_pll2p_1.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/spi1_pll2p_1.overlay index 9bc58581118..9526921dde9 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/spi1_pll2p_1.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/spi1_pll2p_1.overlay @@ -9,7 +9,7 @@ * It is assumed that it is applied after core_init.overlay file. */ -&pll3 { +&pll2 { clocks = <&clk_hse>; div-m = <1>; mul-n = <24>;