soc: arm: mps2: Add configuration for CMSDK Driver
This patch adds the configuration parametes required to enable CMSDK (Cortex-M System Design Kit) Drivers at MPS2 soc level. It provides as well the definitions for the MPS2 System Control registers. Change-Id: I06181dcfeb4fb887425b85ec9a99c268c857a34e Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
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3 changed files with 96 additions and 6 deletions
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@ -10,7 +10,20 @@
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#include <soc_memory_map.h>
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#include <soc_irq.h>
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#if defined(CONFIG_GPIO)
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/* CMSDK AHB General Purpose Input/Output (GPIO) */
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#define CMSDK_AHB_GPIO0 GPIO_0_BASE_ADDR
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#define IRQ_PORT0_ALL IRQ_GPIO_0_COMBINED
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#define CMSDK_AHB_GPIO1 GPIO_1_BASE_ADDR
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#define IRQ_PORT1_ALL IRQ_GPIO_1_COMBINED
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#define CMSDK_AHB_GPIO2 GPIO_2_BASE_ADDR
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#define IRQ_PORT2_ALL IRQ_GPIO_2_COMBINED
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#define CMSDK_AHB_GPIO3 GPIO_3_BASE_ADDR
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#define IRQ_PORT3_ALL IRQ_GPIO_3_COMBINED
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#endif /* CONFIG_GPIO */
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#if defined(CONFIG_UART_CMSDK_APB)
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/* CMSDK APB Universal Asynchronous Receiver-Transmitter (UART) */
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#define CMSDK_APB_UART0 UART_0_BASE_ADDR
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#define CMSDK_APB_UART_0_IRQ_TX IRQ_UART_0_TX
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#define CMSDK_APB_UART_0_IRQ_RX IRQ_UART_0_RX
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#define CMSDK_APB_UART4 UART_4_BASE_ADDR
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#define CMSDK_APB_UART_4_IRQ_TX IRQ_UART_4_TX
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#define CMSDK_APB_UART_4_IRQ_RX IRQ_UART_4_RX
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#endif
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#endif /* CONFIG_UART_CMSDK_APB */
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#if defined(CONFIG_WATCHDOG)
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/* CMSDK APB Watchdog */
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#define CMSDK_APB_WDOG WDOG_BASE_ADDR
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#endif /* CONFIG_WATCHDOG */
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#if defined(CONFIG_COUNTER)
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/* CMSDK APB Timers */
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#define CMSDK_APB_TIMER0 TIMER_0_BASE_ADDR
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#define CMSDK_APB_TIMER_0_IRQ IRQ_TIMER_0
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#define CMSDK_APB_TIMER1 TIMER_1_BASE_ADDR
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#define CMSDK_APB_TIMER_1_IRQ IRQ_TIMER_1
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/* CMSDK APB Dual Timer */
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#define CMSDK_APB_DTIMER DTIMER_BASE_ADDR
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#define CMSDK_APB_DUALTIMER_IRQ IRQ_DUAL_TIMER
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#endif /* CONFIG_COUNTER */
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#ifndef _ASMLANGUAGE
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#include "soc_registers.h"
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/* System Control Register (SYSCON) */
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#define __MPS2_SYSCON ((volatile struct mps2_syscon *)SYSCON_BASE_ADDR)
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#endif /* !_ASMLANGUAGE */
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#endif /* _SOC_DEVICES_H_ */
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#ifndef _SOC_MEMORY_MAP_H_
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#define _SOC_MEMORY_MAP_H_
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#define UART_0_BASE_ADDR 0x40004000
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#define UART_1_BASE_ADDR 0x40005000
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#define UART_2_BASE_ADDR 0x40006000
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#define UART_3_BASE_ADDR 0x40007000
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#define UART_4_BASE_ADDR 0x40009000
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/*
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* Address space definitions
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*/
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/* MPS2 Address space definition */
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#define MPS2_APB_BASE_ADDR 0x40000000
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#define MPS2_AHB_BASE_ADDR 0x40010000
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/* MPS2 AHB peripherals */
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#define GPIO_0_BASE_ADDR (MPS2_AHB_BASE_ADDR + 0x0000)
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#define GPIO_1_BASE_ADDR (MPS2_AHB_BASE_ADDR + 0x1000)
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#define GPIO_2_BASE_ADDR (MPS2_AHB_BASE_ADDR + 0x2000)
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#define GPIO_3_BASE_ADDR (MPS2_AHB_BASE_ADDR + 0x3000)
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#define SYSCON_BASE_ADDR (MPS2_AHB_BASE_ADDR + 0xF000)
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/* MPS2 APB peripherals */
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#define TIMER_0_BASE_ADDR (MPS2_APB_BASE_ADDR + 0x0000)
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#define TIMER_1_BASE_ADDR (MPS2_APB_BASE_ADDR + 0x1000)
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#define DTIMER_BASE_ADDR (MPS2_APB_BASE_ADDR + 0x2000)
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#define UART_0_BASE_ADDR (MPS2_APB_BASE_ADDR + 0x4000)
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#define UART_1_BASE_ADDR (MPS2_APB_BASE_ADDR + 0x5000)
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#define UART_2_BASE_ADDR (MPS2_APB_BASE_ADDR + 0x6000)
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#define UART_3_BASE_ADDR (MPS2_APB_BASE_ADDR + 0x7000)
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#define WDOG_BASE_ADDR (MPS2_APB_BASE_ADDR + 0x8000)
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#define UART_4_BASE_ADDR (MPS2_APB_BASE_ADDR + 0xB000)
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#endif /* _SOC_MEMORY_MAP_H_ */
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31
arch/arm/soc/arm/mps2/soc_registers.h
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31
arch/arm/soc/arm/mps2/soc_registers.h
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/*
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* Copyright (c) 2017 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file SoC configuration macros for the ARM Ltd MPS2.
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*
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*/
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#ifndef _ARM_MPS2_REGS_H_
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#define _ARM_MPS2_REGS_H_
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#include <stdint.h>
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/* System Control Register (SYSCON) */
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struct mps2_syscon {
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/* Offset: 0x000 (r/w) remap control register */
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volatile uint32_t remap;
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/* Offset: 0x004 (r/w) pmu control register */
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volatile uint32_t pmuctrl;
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/* Offset: 0x008 (r/w) reset option register */
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volatile uint32_t resetop;
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/* Offset: 0x00c (r/w) emi control register */
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volatile uint32_t emictrl;
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/* Offset: 0x010 (r/w) reset information register */
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volatile uint32_t rstinfo;
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};
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#endif /* _ARM_MPS2_REGS_H_ */
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