arch: arm: cortex-r: Add compiler tuning for Cortex-R82
Change the GCC toolchain configuration to make use of the Cortex-R82 target. When Cortex-R82 was added as a GCC toolchain option, the GCC version of the Zephyr SDK did not support Cortex-R82 tuning. Zephyr was therefore compiled compiled for the Armv8.4-A architecture. Since Zephyr SDK 0.15.0 (which updated GCC from 10.3.0 to 12.1.0) coupled with Zephyr 3.2, the Cortex-R82 target is supported. The Armv8-R AArch64 architecture does not support the EL3 exception level. EL3 support is therefore made conditional on Armv8-R vs Armv8-A. Signed-off-by: Debbie Martin <Debbie.Martin@arm.com>
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22c83f0f97
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5 changed files with 16 additions and 2 deletions
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@ -313,11 +313,13 @@ void z_arm64_fatal_error(unsigned int reason, z_arch_esf_t *esf)
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far = read_far_el1();
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elr = read_elr_el1();
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break;
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#if !defined(CONFIG_ARMV8_R)
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case MODE_EL3:
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esr = read_esr_el3();
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far = read_far_el3();
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elr = read_elr_el3();
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break;
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#endif /* CONFIG_ARMV8_R */
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}
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#ifdef CONFIG_ARM64_STACK_PROTECTION
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@ -43,6 +43,7 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__reset_prep_c)
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switch_el x0, 3f, 2f, 1f
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3:
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#if !defined(CONFIG_ARMV8_R)
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/* Reinitialize SCTLR from scratch in EL3 */
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ldr w0, =(SCTLR_EL3_RES1 | SCTLR_I_BIT | SCTLR_SA_BIT)
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msr sctlr_el3, x0
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@ -55,6 +56,7 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__reset_prep_c)
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msr sp_el1, x24
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b out
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#endif /* CONFIG_ARMV8_R */
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2:
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/* Disable alignment fault checking */
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mrs x0, sctlr_el2
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@ -216,7 +218,9 @@ stack_init_done:
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switch_el:
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switch_el x0, 3f, 2f, 1f
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3:
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#if !defined(CONFIG_ARMV8_R)
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/* EL3 init */
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bl z_arm64_el3_init
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@ -224,6 +228,7 @@ switch_el:
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adr x0, switch_el
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bl z_arm64_el3_get_next_el
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eret
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#endif /* CONFIG_ARMV8_R */
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2:
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/* EL2 init */
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@ -41,6 +41,8 @@ void z_arm64_el_highest_init(void)
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barrier_isync_fence_full();
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}
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#if !defined(CONFIG_ARMV8_R)
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enum el3_next_el {
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EL3_TO_EL2,
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EL3_TO_EL1_NO_EL2,
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@ -113,6 +115,7 @@ void z_arm64_el3_init(void)
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z_arm64_el2_init();
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}
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}
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#endif /* CONFIG_ARMV8_R */
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void z_arm64_el2_init(void)
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{
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@ -195,6 +198,7 @@ void z_arm64_el1_init(void)
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barrier_isync_fence_full();
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}
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#if !defined(CONFIG_ARMV8_R)
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void z_arm64_el3_get_next_el(uint64_t switch_addr)
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{
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uint64_t spsr;
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@ -214,3 +218,4 @@ void z_arm64_el3_get_next_el(uint64_t switch_addr)
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write_spsr_el3(spsr);
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}
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#endif /* CONFIG_ARMV8_R */
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@ -83,7 +83,7 @@ elseif("${ARCH}" STREQUAL "arm64")
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elseif(CONFIG_CPU_CORTEX_A72)
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set(GCC_M_CPU cortex-a72)
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elseif(CONFIG_CPU_CORTEX_R82)
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set(GCC_M_ARCH armv8.4-a+nolse)
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set(GCC_M_CPU cortex-r82)
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endif()
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elseif("${ARCH}" STREQUAL "arc")
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if(CONFIG_CPU_EM4_FPUS)
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@ -70,8 +70,10 @@ MAKE_REG_HELPER(hcr_el2);
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MAKE_REG_HELPER(id_aa64pfr0_el1);
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MAKE_REG_HELPER(id_aa64mmfr0_el1);
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MAKE_REG_HELPER(mpidr_el1);
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MAKE_REG_HELPER(par_el1)
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MAKE_REG_HELPER(par_el1);
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#if !defined(CONFIG_ARMV8_R)
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MAKE_REG_HELPER(scr_el3);
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#endif /* CONFIG_ARMV8_R */
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MAKE_REG_HELPER(tpidrro_el0);
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MAKE_REG_HELPER(vmpidr_el2);
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MAKE_REG_HELPER(sp_el0);
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