drivers: gpio: update gpio_mcux.c driver
update gpio driver to adapt rt7xx gpio model: 1. There is no PORT_Type on RT7xx,so set PORT_Type as void 2. Add port_no parameter in gpio_mcux_config to adapt IOPCTL driver 3. Add gpio-port-offest parameter in blinding, it will help map the relation between index n and gpio port when some soc have domain access attribution. 3. Splite gpio_mcux_configure function into two functions( gpio_mcux_iopctl_configure and gpio_mcux_port_configure) according to CONFIG_PINCTRL_NXP_IOCON macro 4. Add code to adapt RT700 GPIO attribute configuration Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
This commit is contained in:
Lucien Zhao
Benjamin Cabé
parent
7f64d8f214
commit
87e4db9b86
2 changed files with 118 additions and 17 deletions
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@ -17,12 +17,22 @@
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#if defined(CONFIG_PINCTRL_NXP_IOCON)
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#include <fsl_iopctl.h>
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#include <fsl_reset.h>
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#include <fsl_clock.h>
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#include <fsl_gpio.h>
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/* Use IOCON to configure electrical characteristic, set PORT_Type as void. */
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#define PORT_Type void
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#endif
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struct gpio_mcux_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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GPIO_Type *gpio_base;
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PORT_Type *port_base;
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unsigned int flags;
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uint32_t port_no;
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};
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struct gpio_mcux_data {
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@ -32,7 +42,80 @@ struct gpio_mcux_data {
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sys_slist_t callbacks;
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};
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static int gpio_mcux_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
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#if defined(CONFIG_PINCTRL_NXP_IOCON)
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static int gpio_mcux_iopctl_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
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{
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const struct gpio_mcux_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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uint32_t port_no = config->port_no;
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volatile uint32_t pinconfig = 0;
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if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
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return -ENOTSUP;
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}
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if ((flags & GPIO_SINGLE_ENDED) != 0) {
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return -ENOTSUP;
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}
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/* The flags contain options that require touching registers in the
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* GPIO module and the corresponding PORT module.
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*
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* Start with the GPIO module and set up the pin direction register.
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* 0 - pin is input, 1 - pin is output
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*/
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switch (flags & GPIO_DIR_MASK) {
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case GPIO_INPUT:
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gpio_base->PDDR &= ~BIT(pin);
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/* Enable input buffer for input pins */
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pinconfig |= IOPCTL_INBUF_EN;
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break;
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case GPIO_OUTPUT:
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if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
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gpio_base->PSOR = BIT(pin);
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} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
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gpio_base->PCOR = BIT(pin);
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}
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gpio_base->PDDR |= BIT(pin);
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break;
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default:
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return -ENOTSUP;
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}
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/* Select GPIO mux for this pin (func 0 is always GPIO) */
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pinconfig |= IOPCTL_FUNC0;
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if ((flags & GPIO_PULL_UP) != 0) {
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/* Enable and select pull up. */
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pinconfig |= (IOPCTL_PUPD_EN | IOPCTL_PULLUP_EN);
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} else if ((flags & GPIO_PULL_DOWN) != 0) {
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/* Enable and select pull down. */
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pinconfig |= (IOPCTL_PUPD_EN | IOPCTL_PULLDOWN_EN);
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}
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#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
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/* Determine the drive strength */
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switch (flags & KINETIS_GPIO_DS_MASK) {
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case KINETIS_GPIO_DS_DFLT:
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/* Default is low drive strength */
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pinconfig |= IOPCTL_DRIVE_100OHM;
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break;
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case KINETIS_GPIO_DS_ALT:
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/* Alternate is high drive strength */
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pinconfig |= IOPCTL_DRIVE_33OHM;
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break;
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default:
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return -ENOTSUP;
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}
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#endif /* defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */
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IOPCTL_PinMuxSet(port_no, pin, pinconfig);
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return 0;
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}
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#else
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static int gpio_mcux_port_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
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{
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const struct gpio_mcux_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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@ -122,6 +205,7 @@ static int gpio_mcux_configure(const struct device *dev, gpio_pin_t pin, gpio_fl
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return 0;
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}
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#endif /* defined(CONFIG_PINCTRL_NXP_IOCON) */
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static int gpio_mcux_port_get_raw(const struct device *dev, uint32_t *value)
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{
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@ -173,6 +257,7 @@ static int gpio_mcux_port_toggle_bits(const struct device *dev, uint32_t mask)
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return 0;
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}
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#if !(defined(CONFIG_PINCTRL_NXP_IOCON))
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#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
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static uint32_t get_port_pcr_irqc_value_from_flags(const struct device *dev, uint32_t pin,
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enum gpio_int_mode mode, enum gpio_int_trig trig)
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@ -208,6 +293,7 @@ static uint32_t get_port_pcr_irqc_value_from_flags(const struct device *dev, uin
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return PORT_PCR_IRQC(port_interrupt);
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}
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#endif /* !defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT */
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#endif /* !(defined(CONFIG_PINCTRL_NXP_IOCON)) */
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#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && \
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FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
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@ -259,12 +345,14 @@ static int gpio_mcux_pin_interrupt_configure(const struct device *dev, gpio_pin_
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{
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const struct gpio_mcux_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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#if !(defined(CONFIG_PINCTRL_NXP_IOCON))
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PORT_Type *port_base = config->port_base;
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/* Check for an invalid pin number */
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if (pin >= ARRAY_SIZE(port_base->PCR)) {
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return -EINVAL;
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}
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#endif
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/* Check for an invalid pin configuration */
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if ((mode != GPIO_INT_MODE_DISABLED) && ((gpio_base->PDDR & BIT(pin)) != 0)) {
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@ -276,15 +364,15 @@ static int gpio_mcux_pin_interrupt_configure(const struct device *dev, gpio_pin_
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return -ENOTSUP;
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}
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#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
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uint32_t pcr = get_port_pcr_irqc_value_from_flags(dev, pin, mode, trig);
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port_base->PCR[pin] = (port_base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | pcr;
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#elif (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && \
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#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && \
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FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
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uint32_t icr = get_gpio_icr_irqc_value_from_flags(dev, pin, mode, trig);
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gpio_base->ICR[pin] = (gpio_base->ICR[pin] & ~GPIO_ICR_IRQC_MASK) | icr;
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#elif !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
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uint32_t pcr = get_port_pcr_irqc_value_from_flags(dev, pin, mode, trig);
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port_base->PCR[pin] = (port_base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | pcr;
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#endif /* !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) */
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return 0;
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@ -304,17 +392,17 @@ static void gpio_mcux_port_isr(const struct device *dev)
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struct gpio_mcux_data *data = dev->data;
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uint32_t int_status;
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#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
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int_status = config->port_base->ISFR;
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/* Clear the port interrupts */
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config->port_base->ISFR = int_status;
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#elif (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && \
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#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && \
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FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
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int_status = config->gpio_base->ISFR[0];
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/* Clear the gpio interrupts */
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config->gpio_base->ISFR[0] = int_status;
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#elif !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
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int_status = config->port_base->ISFR;
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/* Clear the port interrupts */
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config->port_base->ISFR = int_status;
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#else
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int_status = 0U;
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ARG_UNUSED(config);
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@ -377,7 +465,11 @@ static int gpio_mcux_port_get_direction(const struct device *dev, gpio_port_pins
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#endif /* CONFIG_GPIO_GET_DIRECTION */
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static DEVICE_API(gpio, gpio_mcux_driver_api) = {
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.pin_configure = gpio_mcux_configure,
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#if defined(CONFIG_PINCTRL_NXP_IOCON)
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.pin_configure = gpio_mcux_iopctl_configure,
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#else
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.pin_configure = gpio_mcux_port_configure,
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#endif
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.port_get_raw = gpio_mcux_port_get_raw,
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.port_set_masked_raw = gpio_mcux_port_set_masked_raw,
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.port_set_bits_raw = gpio_mcux_port_set_bits_raw,
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@ -399,6 +491,8 @@ static DEVICE_API(gpio, gpio_mcux_driver_api) = {
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} while (false)
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#define GPIO_PORT_BASE_ADDR(n) DT_REG_ADDR(DT_INST_PHANDLE(n, nxp_kinetis_port))
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#define GPIO_PORT_NUMBER(n) COND_CODE_1(DT_INST_NODE_HAS_PROP(n, gpio_port_offest), \
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(DT_INST_PROP(n, gpio_port_offest) + n), (n)) \
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#define GPIO_DEVICE_INIT_MCUX(n) \
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static int gpio_mcux_port##n##_init(const struct device *dev); \
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@ -412,6 +506,7 @@ static DEVICE_API(gpio, gpio_mcux_driver_api) = {
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.port_base = (PORT_Type *)GPIO_PORT_BASE_ADDR(n), \
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.flags = UTIL_AND(UTIL_OR(DT_INST_IRQ_HAS_IDX(n, 0), GPIO_HAS_SHARED_IRQ), \
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GPIO_INT_ENABLE), \
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.port_no = GPIO_PORT_NUMBER(n), \
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}; \
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\
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static struct gpio_mcux_data gpio_mcux_port##n##_data; \
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@ -18,6 +18,12 @@ properties:
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A phandle reference to the device tree node that contains the pinmux
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port associated with this GPIO controller.
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gpio-port-offest:
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type: int
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default: 0
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description: |
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Describes an offset between inst index and actual GPIO port number.
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gpio-cells:
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- pin
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- flags
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