ioapic_intr: remove dead code
XIOAPIC_DIRECT_ADDRESSING and IOAPIC_MSI_REDIRECT are never set and not tied to any config options. Change-Id: Ib64cd198c99fe670eb5bcd946ce93f616c03d12a Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
Andrew Boie
Anas Nashif
parent
0452ab7463
commit
876c86e1a8
1 changed files with 0 additions and 168 deletions
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@ -78,61 +78,6 @@
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#define IOAPIC_IRQPA 0x20 /* IRQ Pin Assertion Register */
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#define IOAPIC_EOI 0x40 /* EOI Register */
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#ifdef IOAPIC_MSI_REDIRECT
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/* direct addressing of the RTEs; including the "configuration register" */
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#define IOAPIC_RTE0_LOW 0x1000
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#define IOAPIC_RTE0_HIGH 0x1004
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#define IOAPIC_RTE0_CONFIG 0x1008
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#define IOAPIC_RTE1_LOW 0x1010
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#define IOAPIC_RTE1_HIGH 0x1014
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#define IOAPIC_RTE1_CONFIG 0x1018
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#define IOAPIC_RTE2_LOW 0x1020
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#define IOAPIC_RTE2_HIGH 0x1024
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#define IOAPIC_RTE2_CONFIG 0x1028
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/*
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* etc., etc. until IOAPIC_RTE63_LOW/IOAPIC_RTE63_HIGH/IOAPIC_RTE63_CONFIG
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*
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* rteLowOffset = IOAPIC_RTE0_LOW + (irq * 0x10)
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* rteHighOffset = IOAPIC_RTE0_HIGH + (irq * 0x10)
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* rteConfigOffset = IOAPIC_RTE0_CONFIG + (irq * 0x10)
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*/
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/*
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* An extention to the "standard" IOAPIC design supports a redirection
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* capability that allows each RTE to specify which of the 8 "redirection
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* registers" to use for determining the MSI address.
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*/
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#define IOAPIC_REDIR_ADDR0 0x2000 /* Dummy entry; reads return all 0's */
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#define IOAPIC_REDIR_ADDR1 0x2004 /* MSI redirection selection reg 1 */
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#define IOAPIC_REDIR_ADDR2 0x2008 /* MSI redirection selection reg 2 */
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#define IOAPIC_REDIR_ADDR3 0x200c /* MSI redirection selection reg 3 */
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#define IOAPIC_REDIR_ADDR4 0x2010 /* MSI redirection selection reg 4 */
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#define IOAPIC_REDIR_ADDR5 0x2014 /* MSI redirection selection reg 5 */
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#define IOAPIC_REDIR_ADDR6 0x2018 /* MSI redirection selection reg 6 */
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#define IOAPIC_REDIR_ADDR7 0x201c /* MSI redirection selection reg 7 */
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/* interrupt status for line interrupts generated via RTE0 through RTE31 */
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#define IOAPIC_LINE_INT_STAT0 0x2040
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/* interrupt status for line interrupts generated via RTE32 through RTE64 */
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#define IOAPIC_LINE_INT_STAT1 0x2044
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/* interrupt mask for line interrupts generated via RTE0 to RTE31 */
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#define IOAPIC_LINE_INT_MASK0 0x2048
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/* interrupt mask for line interrupts generated via RTE32 to RTE63 */
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#define IOAPIC_LINE_INT_MASK1 0x204c
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#endif /* IOAPIC_MSI_REDIRECT */
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/* IO APIC indirect register offset */
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#define IOAPIC_ID 0x00 /* IOAPIC ID */
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@ -164,24 +109,8 @@
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#define IOAPIC_VEC_MASK 0x000000ff
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#ifdef IOAPIC_MSI_REDIRECT
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/* RTE configuration register bits */
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#define IOAPIC_RTE_CONFIG_REDIR_SEL 0x7
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#define IOAPIC_RTE_CONFIG_LI0EN 0x8
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#define IOAPIC_RTE_CONFIG_LI1EN 0x10
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#define IOAPIC_RTE_CONFIG_LI2EN 0x20
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#define IOAPIC_RTE_CONFIG_BYPASS_MSI_DISABLE 0x40
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#define IOAPIC_RTE_CONFIG_DISABLE_INT_EXT 0x80
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#endif /* IOAPIC_MSI_REDIRECT */
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#ifndef XIOAPIC_DIRECT_ADDRESSING
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static uint32_t __IoApicGet(int32_t offset);
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static void __IoApicSet(int32_t offset, uint32_t value);
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#endif
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static void ioApicRedSetHi(unsigned int irq, uint32_t upper32);
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static void ioApicRedSetLo(unsigned int irq, uint32_t lower32);
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static uint32_t ioApicRedGetLo(unsigned int irq);
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@ -208,10 +137,6 @@ int _ioapic_init(struct device *unused)
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int32_t ix; /* redirection table index */
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uint32_t rteValue; /* value to copy into redirection table entry */
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#ifdef IOAPIC_MSI_REDIRECT
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_IoApicRedirRegSet(MSI_REDIRECT_SELECT_ID, MSI_REDIRECT_TARGET_ADDR);
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#endif
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/*
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* The platform must set the Kconfig option IOAPIC_NUM_RTES to indicate
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* the number of redirection table entries supported by the IOAPIC.
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@ -305,8 +230,6 @@ void _ioapic_int_vec_set(unsigned int irq, unsigned int vector)
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_IoApicRedUpdateLo(irq, vector, IOAPIC_VEC_MASK);
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}
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#ifndef XIOAPIC_DIRECT_ADDRESSING
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/**
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*
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* @brief Read a 32 bit IO APIC register
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@ -358,8 +281,6 @@ static void __IoApicSet(int32_t offset, uint32_t value)
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irq_unlock(key);
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}
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#endif
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/**
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*
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* @brief Get low 32 bits of Redirection Table entry
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@ -371,18 +292,9 @@ static void __IoApicSet(int32_t offset, uint32_t value)
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*/
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static uint32_t ioApicRedGetLo(unsigned int irq)
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{
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#ifdef XIOAPIC_DIRECT_ADDRESSING
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volatile uint32_t *pEntry; /* pointer to redirection table entry */
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pEntry = (volatile uint32_t *)(CONFIG_IOAPIC_BASE_ADDRESS + (irq * 0x10) +
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IOAPIC_RTE0_LOW);
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return *pEntry;
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#else
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int32_t offset = IOAPIC_REDTBL + (irq << 1); /* register offset */
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return __IoApicGet(offset);
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#endif
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}
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/**
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@ -397,18 +309,9 @@ static uint32_t ioApicRedGetLo(unsigned int irq)
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*/
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static void ioApicRedSetLo(unsigned int irq, uint32_t lower32)
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{
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#ifdef XIOAPIC_DIRECT_ADDRESSING
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volatile uint32_t *pEntry; /* pointer to redirection table entry */
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pEntry = (volatile uint32_t *)(CONFIG_IOAPIC_BASE_ADDRESS + (irq * 0x10) +
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IOAPIC_RTE0_LOW);
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*pEntry = lower32;
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#else
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int32_t offset = IOAPIC_REDTBL + (irq << 1); /* register offset */
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__IoApicSet(offset, lower32);
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#endif
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}
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/**
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@ -423,18 +326,9 @@ static void ioApicRedSetLo(unsigned int irq, uint32_t lower32)
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*/
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static void ioApicRedSetHi(unsigned int irq, uint32_t upper32)
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{
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#ifdef XIOAPIC_DIRECT_ADDRESSING
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volatile uint32_t *pEntry; /* pointer to redirection table entry */
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pEntry = (volatile uint32_t *)(CONFIG_IOAPIC_BASE_ADDRESS + (irq * 0x10) +
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IOAPIC_RTE0_HIGH);
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*pEntry = upper32;
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#else
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int32_t offset = IOAPIC_REDTBL + (irq << 1) + 1; /* register offset */
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__IoApicSet(offset, upper32);
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#endif
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}
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/**
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@ -456,65 +350,3 @@ static void _IoApicRedUpdateLo(unsigned int irq,
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ioApicRedSetLo(irq, (ioApicRedGetLo(irq) & ~mask) | (value & mask));
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}
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#ifdef IOAPIC_MSI_REDIRECT
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/*
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* The platform is responsible for defining the IOAPIC_MSI_REDIRECT
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* macro if the I/O APIC supports the MSI redirect capability.
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*/
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/**
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*
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* @brief Write to the RTE config register for specified IRQ
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*
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* This routine writes the specified 32-bit <value> into the RTE configuration
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* register for the specified <irq> (0 to (CONFIG_IOAPIC_NUM_RTES - 1))
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*
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* @param irq INTIN number
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* @param value Value to be written
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* @return N/A
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*/
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static void _IoApicRteConfigSet(unsigned int irq, uint32_t value)
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{
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unsigned int offset; /* register offset */
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#ifdef CONFIG_IOAPIC_DEBUG
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if (irq >= CONFIG_IOAPIC_NUM_RTES)
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return; /* do nothing if <irq> is invalid */
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#endif
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offset = IOAPIC_RTE0_CONFIG + (irq * 0x10);
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/* use direct addressing when writing to RTE config register */
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*((volatile uint32_t *)(CONFIG_IOAPIC_BASE_ADDRESS + offset)) = value;
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}
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/**
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*
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* @brief Write to the specified MSI redirection register
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*
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* This routine writes the 32-bit <value> into the redirection register
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* specified by <reg>.
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* @param reg Register
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* @param value Value to be written
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*
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* @return N/A
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*/
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static void _IoApicRedirRegSet(unsigned int reg, uint32_t value)
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{
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unsigned int offset; /* register offset */
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#ifdef CONFIG_IOAPIC_DEBUG
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if ((reg > 7) || (reg == 0))
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return; /* do nothing if <reg> is invalid */
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#endif
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offset = IOAPIC_REDIR_ADDR0 + (reg * 4);
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/* use direct addressing when writing to RTE config register */
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*((volatile uint32_t *)(CONFIG_IOAPIC_BASE_ADDRESS + offset)) = value;
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}
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#endif /* IOAPIC_MSI_REDIRECT */
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