spi: k64: Remove the k64 spi driver
Now that we have a more generic mcux spi driver that can be used across multiple Kinetis SoCs, remove the specific k64 spi driver. Jira: ZEP-1374 Change-Id: Ifc324374f305837f5e3d2cfd7ad30d3608865b5b Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
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6 changed files with 0 additions and 1406 deletions
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@ -146,31 +146,6 @@ extern "C" {
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#define PWM_K64_FTM_2_REG_BASE 0x4003A000
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#define PWM_K64_FTM_3_REG_BASE 0x400B9000
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/*
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* SPI configuration settings
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*/
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#if defined(CONFIG_SPI_K64)
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#define SPI_K64_0_BASE_ADDR 0x4002C000
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#define SPI_K64_0_IRQ IRQ_SPI0
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#define SPI_K64_0_PCS_NUM 6
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#define SPI_K64_0_CLK_GATE_REG_ADDR 0x4004803C
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#define SPI_K64_0_CLK_GATE_REG_BIT 12
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#define SPI_K64_1_BASE_ADDR 0x4002D000
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#define SPI_K64_1_IRQ IRQ_SPI1
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#define SPI_K64_1_PCS_NUM 4
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#define SPI_K64_1_CLK_GATE_REG_ADDR 0x4004803C
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#define SPI_K64_1_CLK_GATE_REG_BIT 13
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#define SPI_K64_2_BASE_ADDR 0x400AC000
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#define SPI_K64_2_IRQ IRQ_SPI2
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#define SPI_K64_2_PCS_NUM 2
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#define SPI_K64_2_CLK_GATE_REG_ADDR 0x40048030
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#define SPI_K64_2_CLK_GATE_REG_BIT 12
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#endif /* CONFIG_SPI_K64 */
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#endif /* !_ASMLANGUAGE */
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#ifdef __cplusplus
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@ -33,14 +33,6 @@ config SPI_QMSI_SS
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SPI driver implementation using QMSI library. This instance is
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for the Sensor Subsystem.
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config SPI_K64
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bool
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prompt "Freescale K64-based SPI controller driver"
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depends on SPI && SOC_MK64F12
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default n
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help
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Enable support for Freescale K64-based SPI controllers.
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config SPI_INTEL
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bool
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prompt "Intel SPI controller driver"
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@ -3,4 +3,3 @@ obj-$(CONFIG_SPI_DW) += spi_dw.o
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obj-$(CONFIG_SPI_MCUX) += spi_mcux.o
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obj-$(CONFIG_SPI_QMSI) += spi_qmsi.o
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obj-$(CONFIG_SPI_QMSI_SS) += spi_qmsi_ss.o
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obj-$(CONFIG_SPI_K64) += spi_k64.o
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File diff suppressed because it is too large
Load diff
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@ -1,166 +0,0 @@
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/* spi_k64_priv.h - Freescale K64 SPI driver private definitions */
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/*
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* Copyright (c) 2015-2016 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __SPI_K64_PRIV_H__
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#define __SPI_K64_PRIV_H__
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typedef void (*spi_k64_config_t)(void);
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struct spi_k64_config {
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uint32_t regs; /* base address of SPI module registers */
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uint32_t clk_gate_reg; /* SPI module's clock gate register addr. */
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uint32_t clk_gate_bit; /* SPI module's clock gate bit position */
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uint32_t irq; /* SPI module IRQ number */
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spi_k64_config_t config_func; /* IRQ configuration function pointer */
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};
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struct spi_k64_data {
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uint8_t frame_sz; /* frame/word size, in bits */
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uint8_t cont_pcs_sel; /* continuous slave/PCS selection enable */
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uint8_t pcs; /* slave/PCS selection */
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const uint8_t *tx_buf;
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uint32_t tx_buf_len;
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uint8_t *rx_buf;
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uint32_t rx_buf_len;
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uint32_t xfer_len;
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struct k_sem device_sync_sem; /* sync call information */
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uint8_t error; /* error condition */
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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uint32_t device_power_state;
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#endif
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};
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/* Data transfer signal timing delays */
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enum spi_k64_delay_id {
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DELAY_PCS_TO_SCK,
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DELAY_AFTER_SCK,
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DELAY_AFTER_XFER
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};
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/* Register offsets */
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#define SPI_K64_REG_MCR (0x00)
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#define SPI_K64_REG_TCR (0x08)
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#define SPI_K64_REG_CTAR0 (0x0C)
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#define SPI_K64_REG_CTAR1 (0x10)
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#define SPI_K64_REG_SR (0x2C)
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#define SPI_K64_REG_RSER (0x30)
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#define SPI_K64_REG_PUSHR (0x34)
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#define SPI_K64_REG_POPR (0x38)
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#define SPI_K64_REG_TXFR0 (0x3C)
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#define SPI_K64_REG_RXFR0 (0x7C)
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/* Module Control Register (MCR) settings */
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#define SPI_K64_MCR_HALT (0x1)
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#define SPI_K64_MCR_HALT_BIT (0)
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#define SPI_K64_MCR_SMPL_PT_MSK (0x3 << 8)
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#define SPI_K64_MCR_CLR_RXF (0x1 << 10)
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#define SPI_K64_MCR_CLR_TXF (0x1 << 11)
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#define SPI_K64_MCR_DIS_RXF (0x1 << 12)
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#define SPI_K64_MCR_DIS_TXF (0x1 << 13)
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#define SPI_K64_MCR_MDIS (0x1 << 14)
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#define SPI_K64_MCR_MDIS_BIT (14)
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#define SPI_K64_MCR_DOZE (0x1 << 15)
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#define SPI_K64_MCR_PCSIS_MSK (0x3F << 16)
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#define SPI_K64_MCR_PCSIS_SET(pcsis) ((pcsis) << 16)
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#define SPI_K64_MCR_ROOE (0x1 << 24)
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#define SPI_K64_MCR_PCSSE (0x1 << 25)
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#define SPI_K64_MCR_MTFE (0x1 << 26)
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#define SPI_K64_MCR_FRZ (0x1 << 27)
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#define SPI_K64_MCR_DCONF_MSK (0x3 << 28)
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#define SPI_K64_MCR_CONT_SCKE (0x1 << 30)
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#define SPI_K64_MCR_CONT_SCKE_SET(cont) ((cont) << 30)
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#define SPI_K64_MCR_MSTR (0x1 << 31)
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/* Clock and Transfer Attributes Register (CTAR) settings */
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#define SPI_K64_CTAR_BR_MSK (0xF)
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#define SPI_K64_CTAR_DT_MSK (0xF << 4)
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#define SPI_K64_CTAR_DT_SET(dt) ((dt) << 4)
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#define SPI_K64_CTAR_ASC_MSK (0xF << 8)
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#define SPI_K64_CTAR_ASC_SET(asc) ((asc) << 8)
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#define SPI_K64_CTAR_CSSCK_MSK (0xF << 12)
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#define SPI_K64_CTAR_CSSCK_SET(cssck) ((cssck) << 12)
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#define SPI_K64_CTAR_PBR_MSK (0x3 << 16)
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#define SPI_K64_CTAR_PBR_SET(pbr) ((pbr) << 16)
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#define SPI_K64_CTAR_PDT_MSK (0xF << 18)
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#define SPI_K64_CTAR_PDT_SET(pdt) ((pdt) << 18)
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#define SPI_K64_CTAR_PASC_MSK (0xF << 20)
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#define SPI_K64_CTAR_PASC_SET(pasc) ((pasc) << 20)
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#define SPI_K64_CTAR_PCSSCK_MSK (0xF << 22)
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#define SPI_K64_CTAR_PCSSCK_SET(pcssck) ((pcssck) << 22)
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#define SPI_K64_CTAR_LSBFE (0x1 << 24)
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#define SPI_K64_CTAR_CPHA (0x1 << 25)
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#define SPI_K64_CTAR_CPOL (0x1 << 26)
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#define SPI_K64_CTAR_FRMSZ_MSK (0xF << 27)
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#define SPI_K64_CTAR_FRMSZ_SET(sz) ((sz) << 27)
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#define SPI_K64_CTAR_DBR (0x1 << 31)
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#define SPI_K64_CTAR_DBR_SET(dbr) ((dbr) << 31)
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/* Status Register (SR) settings */
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#define SPI_K64_SR_POPNXTPTR_MSK (0xF)
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#define SPI_K64_SR_RXCTR_MSK (0xF << 4)
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#define SPI_K64_SR_TXNXTPTR_MSK (0xF << 8)
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#define SPI_K64_SR_TXCTR_MSK (0xF << 12)
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#define SPI_K64_SR_RFDF (0x1 << 17)
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#define SPI_K64_SR_RFOF (0x1 << 19)
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#define SPI_K64_SR_TFFF (0x1 << 25)
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#define SPI_K64_SR_TFUF (0x1 << 27)
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#define SPI_K64_SR_EOQF (0x1 << 28)
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#define SPI_K64_SR_TXRXS (0x1 << 30)
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#define SPI_K64_SR_TCF (0x1 << 31)
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/* DMA/Interrupt Request Select and Enable Register (RSER) settings */
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#define SPI_K64_RSER_RFDF_DIRS (0x1 << 16)
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#define SPI_K64_RSER_RFDF_RE (0x1 << 17)
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#define SPI_K64_RSER_RFOF_RE (0x1 << 19)
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#define SPI_K64_RSER_TFFF_DIRS (0x1 << 24)
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#define SPI_K64_RSER_TFFF_RE (0x1 << 25)
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#define SPI_K64_RSER_TFUF_RE (0x1 << 27)
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#define SPI_K64_RSER_EOQF_RE (0x1 << 28)
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#define SPI_K64_RSER_TCF_RE (0x1 << 31)
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/* Push Tx FIFO Register (PUSHR) settings */
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#define SPI_K64_PUSHR_TXDATA_MSK (0xFF)
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#define SPI_K64_PUSHR_PCS_MSK (0x3F << 16)
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#define SPI_K64_PUSHR_PCS_SET(pcs) ((pcs) << 16)
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#define SPI_K64_PUSHR_CTCNT (0x1 << 26)
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#define SPI_K64_PUSHR_EOQ (0x1 << 27)
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#define SPI_K64_PUSHR_CTAS_MSK (0x7 << 28)
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#define SPI_K64_PUSHR_CONT (0x1 << 31)
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#define SPI_K64_PUSHR_CONT_SET(cont) ((cont) << 31)
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/* Tx FIFO Register (TXFR) settings */
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#define SPI_K64_TXFR_TXDATA_MSK (0xFFFF)
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#define SPI_K64_TXFR_TXCMD_MSK (0xFFFF << 16)
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#endif /* __SPI_K64_PRIV_H__ */
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@ -1,68 +0,0 @@
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/* spi_k64.h - Freescale K64 SPI controller driver utilities */
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/*
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* Copyright (c) 2015 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __SPI_K64_H__
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#define __SPI_K64_H__
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/*
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* Device configuration
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*
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* Device-independent configuration:
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* Bits [0 : 11] in the config parameter of the spi_configure() API are defined
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* with the following fields.
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*
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* SCK polarity [ 0 ] - SCK inactive state (0 = low, 1 = high)
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* SCK phase [ 1 ] - Data captured/changed on which SCK edge:
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* - 0 = leading/following edges, respectively
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* - 1 = following/leading edges, respectively
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* loop_mode [ 2 ] - Not used/Unsupported
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* transfer_mode [ 3 ] - First significant bit (0 = MSB, 1 = LSB)
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* word_size [ 4 : 7 ] - Size of a data train in bits
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* unused [ 8 : 11 ] - Unused word_size field bits
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*
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* Device-specific configuration:
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* Bits [12 : 31] in the config parameter of the spi_configure() API are
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* available, with the following fields defined for this device.
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*
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* PCS0-5 polarity [ 12 : 17 ] - Periph. Chip Select inactive state, MCR[PCSIS]
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* - (0 = low, 1 = high)
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* Continuous SCK [ 18 ] - Continuous serial clocking, MCR[CONT_SCKE]
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* - (0 = disabled, 1 = enabled)
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* Continuous PCS [ 19 ] - Continuous selection format, PUSHR[CONT]
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* - (0 = disabled, 1 = enabled)
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*
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* Note that the number of valid PCS signals differs for each
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* K64 SPI module:
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* - SPI0 uses PCS0-5;
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* - SPI1 uses PCS0-3;
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* - SPI2 uses PCS0-1;
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*/
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/* PCS polarity access macros */
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#define SPI_PCS_POL_MASK (0x3F << 12)
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#define SPI_PCS_POL_GET(_in_) (((_in_) & SPI_PCS_POL_MASK) >> 12)
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#define SPI_PCS_POL_SET(_in_) ((_in_) << 12)
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/* Continuous SCK access macros */
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#define SPI_CONT_SCK_MASK (0x1 << 18)
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#define SPI_CONT_SCK_GET(_in_) (((_in_) & SPI_CONT_SCK_MASK) >> 18)
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#define SPI_CONT_SCK_SET(_in_) ((_in_) << 18)
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/* Continuous PCS access macros */
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#define SPI_CONT_PCS_MASK (0x1 << 19)
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#define SPI_CONT_PCS_GET(_in_) (((_in_) & SPI_CONT_PCS_MASK) >> 19)
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#define SPI_CONT_PCS_SET(_in_) ((_in_) << 19)
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/* K64 SPI word/frame size is limited to 16 bits, represented as: (size - 1) */
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#define SPI_K64_WORD_SIZE_MAX (16)
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#endif /* __SPI_K64_H__ */
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