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spi: k64: Remove the k64 spi driver

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Now that we have a more generic mcux spi driver that can be used across
multiple Kinetis SoCs, remove the specific k64 spi driver.

Jira: ZEP-1374
Change-Id: Ifc324374f305837f5e3d2cfd7ad30d3608865b5b
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This commit is contained in:
Maureen Helm 2017-01-14 14:22:34 -06:00 • committed by Kumar Gala
commit 8769cd585e
6 changed files with 0 additions and 1406 deletions
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25
arch/arm/soc/nxp_kinetis/k6x/soc.h
View file

@ -146,31 +146,6 @@ extern "C" {
#define PWM_K64_FTM_2_REG_BASE 0x4003A000
#define PWM_K64_FTM_3_REG_BASE 0x400B9000
/*
* SPI configuration settings
*/
#if defined(CONFIG_SPI_K64)
#define SPI_K64_0_BASE_ADDR 0x4002C000
#define SPI_K64_0_IRQ IRQ_SPI0
#define SPI_K64_0_PCS_NUM 6
#define SPI_K64_0_CLK_GATE_REG_ADDR 0x4004803C
#define SPI_K64_0_CLK_GATE_REG_BIT 12
#define SPI_K64_1_BASE_ADDR 0x4002D000
#define SPI_K64_1_IRQ IRQ_SPI1
#define SPI_K64_1_PCS_NUM 4
#define SPI_K64_1_CLK_GATE_REG_ADDR 0x4004803C
#define SPI_K64_1_CLK_GATE_REG_BIT 13
#define SPI_K64_2_BASE_ADDR 0x400AC000
#define SPI_K64_2_IRQ IRQ_SPI2
#define SPI_K64_2_PCS_NUM 2
#define SPI_K64_2_CLK_GATE_REG_ADDR 0x40048030
#define SPI_K64_2_CLK_GATE_REG_BIT 12
#endif /* CONFIG_SPI_K64 */
#endif /* !_ASMLANGUAGE */
#ifdef __cplusplus

8
drivers/spi/Kconfig
View file

@ -33,14 +33,6 @@ config SPI_QMSI_SS
SPI driver implementation using QMSI library. This instance is
for the Sensor Subsystem.
config SPI_K64
bool
prompt "Freescale K64-based SPI controller driver"
depends on SPI && SOC_MK64F12
default n
help
Enable support for Freescale K64-based SPI controllers.
config SPI_INTEL
bool
prompt "Intel SPI controller driver"

1
drivers/spi/Makefile
View file

@ -3,4 +3,3 @@ obj-$(CONFIG_SPI_DW) += spi_dw.o
obj-$(CONFIG_SPI_MCUX) += spi_mcux.o
obj-$(CONFIG_SPI_QMSI) += spi_qmsi.o
obj-$(CONFIG_SPI_QMSI_SS) += spi_qmsi_ss.o
obj-$(CONFIG_SPI_K64) += spi_k64.o

1138
drivers/spi/spi_k64.c
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File diff suppressed because it is too large Load diff

166
drivers/spi/spi_k64_priv.h
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@ -1,166 +0,0 @@
/* spi_k64_priv.h - Freescale K64 SPI driver private definitions */
/*
* Copyright (c) 2015-2016 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __SPI_K64_PRIV_H__
#define __SPI_K64_PRIV_H__
typedef void (*spi_k64_config_t)(void);
struct spi_k64_config {
uint32_t regs; /* base address of SPI module registers */
uint32_t clk_gate_reg; /* SPI module's clock gate register addr. */
uint32_t clk_gate_bit; /* SPI module's clock gate bit position */
uint32_t irq; /* SPI module IRQ number */
spi_k64_config_t config_func; /* IRQ configuration function pointer */
};
struct spi_k64_data {
uint8_t frame_sz; /* frame/word size, in bits */
uint8_t cont_pcs_sel; /* continuous slave/PCS selection enable */
uint8_t pcs; /* slave/PCS selection */
const uint8_t *tx_buf;
uint32_t tx_buf_len;
uint8_t *rx_buf;
uint32_t rx_buf_len;
uint32_t xfer_len;
struct k_sem device_sync_sem; /* sync call information */
uint8_t error; /* error condition */
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
uint32_t device_power_state;
#endif
};
/* Data transfer signal timing delays */
enum spi_k64_delay_id {
DELAY_PCS_TO_SCK,
DELAY_AFTER_SCK,
DELAY_AFTER_XFER
};
/* Register offsets */
#define SPI_K64_REG_MCR (0x00)
#define SPI_K64_REG_TCR (0x08)
#define SPI_K64_REG_CTAR0 (0x0C)
#define SPI_K64_REG_CTAR1 (0x10)
#define SPI_K64_REG_SR (0x2C)
#define SPI_K64_REG_RSER (0x30)
#define SPI_K64_REG_PUSHR (0x34)
#define SPI_K64_REG_POPR (0x38)
#define SPI_K64_REG_TXFR0 (0x3C)
#define SPI_K64_REG_RXFR0 (0x7C)
/* Module Control Register (MCR) settings */
#define SPI_K64_MCR_HALT (0x1)
#define SPI_K64_MCR_HALT_BIT (0)
#define SPI_K64_MCR_SMPL_PT_MSK (0x3 << 8)
#define SPI_K64_MCR_CLR_RXF (0x1 << 10)
#define SPI_K64_MCR_CLR_TXF (0x1 << 11)
#define SPI_K64_MCR_DIS_RXF (0x1 << 12)
#define SPI_K64_MCR_DIS_TXF (0x1 << 13)
#define SPI_K64_MCR_MDIS (0x1 << 14)
#define SPI_K64_MCR_MDIS_BIT (14)
#define SPI_K64_MCR_DOZE (0x1 << 15)
#define SPI_K64_MCR_PCSIS_MSK (0x3F << 16)
#define SPI_K64_MCR_PCSIS_SET(pcsis) ((pcsis) << 16)
#define SPI_K64_MCR_ROOE (0x1 << 24)
#define SPI_K64_MCR_PCSSE (0x1 << 25)
#define SPI_K64_MCR_MTFE (0x1 << 26)
#define SPI_K64_MCR_FRZ (0x1 << 27)
#define SPI_K64_MCR_DCONF_MSK (0x3 << 28)
#define SPI_K64_MCR_CONT_SCKE (0x1 << 30)
#define SPI_K64_MCR_CONT_SCKE_SET(cont) ((cont) << 30)
#define SPI_K64_MCR_MSTR (0x1 << 31)
/* Clock and Transfer Attributes Register (CTAR) settings */
#define SPI_K64_CTAR_BR_MSK (0xF)
#define SPI_K64_CTAR_DT_MSK (0xF << 4)
#define SPI_K64_CTAR_DT_SET(dt) ((dt) << 4)
#define SPI_K64_CTAR_ASC_MSK (0xF << 8)
#define SPI_K64_CTAR_ASC_SET(asc) ((asc) << 8)
#define SPI_K64_CTAR_CSSCK_MSK (0xF << 12)
#define SPI_K64_CTAR_CSSCK_SET(cssck) ((cssck) << 12)
#define SPI_K64_CTAR_PBR_MSK (0x3 << 16)
#define SPI_K64_CTAR_PBR_SET(pbr) ((pbr) << 16)
#define SPI_K64_CTAR_PDT_MSK (0xF << 18)
#define SPI_K64_CTAR_PDT_SET(pdt) ((pdt) << 18)
#define SPI_K64_CTAR_PASC_MSK (0xF << 20)
#define SPI_K64_CTAR_PASC_SET(pasc) ((pasc) << 20)
#define SPI_K64_CTAR_PCSSCK_MSK (0xF << 22)
#define SPI_K64_CTAR_PCSSCK_SET(pcssck) ((pcssck) << 22)
#define SPI_K64_CTAR_LSBFE (0x1 << 24)
#define SPI_K64_CTAR_CPHA (0x1 << 25)
#define SPI_K64_CTAR_CPOL (0x1 << 26)
#define SPI_K64_CTAR_FRMSZ_MSK (0xF << 27)
#define SPI_K64_CTAR_FRMSZ_SET(sz) ((sz) << 27)
#define SPI_K64_CTAR_DBR (0x1 << 31)
#define SPI_K64_CTAR_DBR_SET(dbr) ((dbr) << 31)
/* Status Register (SR) settings */
#define SPI_K64_SR_POPNXTPTR_MSK (0xF)
#define SPI_K64_SR_RXCTR_MSK (0xF << 4)
#define SPI_K64_SR_TXNXTPTR_MSK (0xF << 8)
#define SPI_K64_SR_TXCTR_MSK (0xF << 12)
#define SPI_K64_SR_RFDF (0x1 << 17)
#define SPI_K64_SR_RFOF (0x1 << 19)
#define SPI_K64_SR_TFFF (0x1 << 25)
#define SPI_K64_SR_TFUF (0x1 << 27)
#define SPI_K64_SR_EOQF (0x1 << 28)
#define SPI_K64_SR_TXRXS (0x1 << 30)
#define SPI_K64_SR_TCF (0x1 << 31)
/* DMA/Interrupt Request Select and Enable Register (RSER) settings */
#define SPI_K64_RSER_RFDF_DIRS (0x1 << 16)
#define SPI_K64_RSER_RFDF_RE (0x1 << 17)
#define SPI_K64_RSER_RFOF_RE (0x1 << 19)
#define SPI_K64_RSER_TFFF_DIRS (0x1 << 24)
#define SPI_K64_RSER_TFFF_RE (0x1 << 25)
#define SPI_K64_RSER_TFUF_RE (0x1 << 27)
#define SPI_K64_RSER_EOQF_RE (0x1 << 28)
#define SPI_K64_RSER_TCF_RE (0x1 << 31)
/* Push Tx FIFO Register (PUSHR) settings */
#define SPI_K64_PUSHR_TXDATA_MSK (0xFF)
#define SPI_K64_PUSHR_PCS_MSK (0x3F << 16)
#define SPI_K64_PUSHR_PCS_SET(pcs) ((pcs) << 16)
#define SPI_K64_PUSHR_CTCNT (0x1 << 26)
#define SPI_K64_PUSHR_EOQ (0x1 << 27)
#define SPI_K64_PUSHR_CTAS_MSK (0x7 << 28)
#define SPI_K64_PUSHR_CONT (0x1 << 31)
#define SPI_K64_PUSHR_CONT_SET(cont) ((cont) << 31)
/* Tx FIFO Register (TXFR) settings */
#define SPI_K64_TXFR_TXDATA_MSK (0xFFFF)
#define SPI_K64_TXFR_TXCMD_MSK (0xFFFF << 16)
#endif /* __SPI_K64_PRIV_H__ */

68
include/drivers/spi/spi_k64.h
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@ -1,68 +0,0 @@
/* spi_k64.h - Freescale K64 SPI controller driver utilities */
/*
* Copyright (c) 2015 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __SPI_K64_H__
#define __SPI_K64_H__
/*
* Device configuration
*
* Device-independent configuration:
* Bits [0 : 11] in the config parameter of the spi_configure() API are defined
* with the following fields.
*
* SCK polarity [ 0 ] - SCK inactive state (0 = low, 1 = high)
* SCK phase [ 1 ] - Data captured/changed on which SCK edge:
* - 0 = leading/following edges, respectively
* - 1 = following/leading edges, respectively
* loop_mode [ 2 ] - Not used/Unsupported
* transfer_mode [ 3 ] - First significant bit (0 = MSB, 1 = LSB)
* word_size [ 4 : 7 ] - Size of a data train in bits
* unused [ 8 : 11 ] - Unused word_size field bits
*
* Device-specific configuration:
* Bits [12 : 31] in the config parameter of the spi_configure() API are
* available, with the following fields defined for this device.
*
* PCS0-5 polarity [ 12 : 17 ] - Periph. Chip Select inactive state, MCR[PCSIS]
* - (0 = low, 1 = high)
* Continuous SCK [ 18 ] - Continuous serial clocking, MCR[CONT_SCKE]
* - (0 = disabled, 1 = enabled)
* Continuous PCS [ 19 ] - Continuous selection format, PUSHR[CONT]
* - (0 = disabled, 1 = enabled)
*
* Note that the number of valid PCS signals differs for each
* K64 SPI module:
* - SPI0 uses PCS0-5;
* - SPI1 uses PCS0-3;
* - SPI2 uses PCS0-1;
*/
/* PCS polarity access macros */
#define SPI_PCS_POL_MASK (0x3F << 12)
#define SPI_PCS_POL_GET(_in_) (((_in_) & SPI_PCS_POL_MASK) >> 12)
#define SPI_PCS_POL_SET(_in_) ((_in_) << 12)
/* Continuous SCK access macros */
#define SPI_CONT_SCK_MASK (0x1 << 18)
#define SPI_CONT_SCK_GET(_in_) (((_in_) & SPI_CONT_SCK_MASK) >> 18)
#define SPI_CONT_SCK_SET(_in_) ((_in_) << 18)
/* Continuous PCS access macros */
#define SPI_CONT_PCS_MASK (0x1 << 19)
#define SPI_CONT_PCS_GET(_in_) (((_in_) & SPI_CONT_PCS_MASK) >> 19)
#define SPI_CONT_PCS_SET(_in_) ((_in_) << 19)
/* K64 SPI word/frame size is limited to 16 bits, represented as: (size - 1) */
#define SPI_K64_WORD_SIZE_MAX (16)
#endif /* __SPI_K64_H__ */