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soc/intel_adsp: Increase init priority of trace windows

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These windows control host visibility of the trace output buffer.  The
buffer itself is writable memory always, but until we get to the
register init the host can't see them.  Since they contain
printk/logging output, they REALLY need to be initialized earlier than
anything else.

Also remove a rogue memset of the trace buffer.  That buffer is
already being initialized in a lazy-evaluated way by the trace output
code, and blowing it away here has the effect of forgetting anything
earlier code was trying to log!

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross 2021-06-21 19:01:06 -07:00 • committed by Anas Nashif
commit 87579a9daa
1 changed files with 6 additions and 4 deletions
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10
soc/xtensa/intel_adsp/common/adsp.c
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@ -33,12 +33,11 @@ static void prepare_host_windows(void)
HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END); HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);
/* window3, for trace /* window3, for trace
* zeroed by trace initialization * initialized in trace_out.c
*/ */
sys_write32((HP_SRAM_WIN3_SIZE | 0x7), DMWLO(3)); sys_write32((HP_SRAM_WIN3_SIZE | 0x7), DMWLO(3));
sys_write32((HP_SRAM_WIN3_BASE | DMWBA_READONLY | DMWBA_ENABLE), sys_write32((HP_SRAM_WIN3_BASE | DMWBA_READONLY | DMWBA_ENABLE),
DMWBA(3)); DMWBA(3));
memset((void *)HP_SRAM_WIN3_BASE, 0, HP_SRAM_WIN3_SIZE);
SOC_DCACHE_FLUSH((void *)HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE); SOC_DCACHE_FLUSH((void *)HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE);
} }
@ -49,5 +48,8 @@ static int adsp_init(const struct device *dev)
return 0; return 0;
} }
/* Init after IPM initialization and before logging (uses memory windows) */ /* Note priority zero: this is required for trace output to appear to
SYS_INIT(adsp_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); * the host (we can log to the buffer earlier, but the host needs our
* registers to see it), so we want it done FIRST.
*/
SYS_INIT(adsp_init, PRE_KERNEL_1, 0);