intel_adsp: Add board definitions for adsp simulator

Add board definition for Intel ADSP (ACE family) simulators.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>

boards/intel/adsp/Kconfig.intel_adsp

@@ -5,5 +5,8 @@ config BOARD_INTEL_ADSP
 	select SOC_INTEL_CAVS_V25 if BOARD_INTEL_ADSP_CAVS25
 	select SOC_INTEL_CAVS_V25 if BOARD_INTEL_ADSP_CAVS25_TGPH
 	select SOC_INTEL_ACE15_MTPM if BOARD_INTEL_ADSP_ACE15_MTPM
+	select SOC_INTEL_ACE15_MTPM if BOARD_INTEL_ADSP_ACE15_MTPM_SIM
 	select SOC_INTEL_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL
+	select SOC_INTEL_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL_SIM
 	select SOC_INTEL_ACE30_PTL if BOARD_INTEL_ADSP_ACE30_PTL
+	select SOC_INTEL_ACE30_PTL if BOARD_INTEL_ADSP_ACE30_PTL_SIM

boards/intel/adsp/board.cmake

@@ -23,7 +23,7 @@ if(CONFIG_BOARD_INTEL_ADSP_CAVS25 OR CONFIG_BOARD_INTEL_ADSP_CAVS25_TGPH)
 
   board_finalize_runner_args(intel_adsp)
 
-elseif(CONFIG_BOARD_INTEL_ADSP_ACE15_MTPM)
+elseif(CONFIG_BOARD_INTEL_ADSP_ACE15_MTPM  OR CONFIG_BOARD_INTEL_ADSP_ACE15_MTPM_SIM)
 
   board_set_rimage_target(mtl)
 
@@ -31,7 +31,7 @@ elseif(CONFIG_BOARD_INTEL_ADSP_ACE15_MTPM)
 
   board_finalize_runner_args(intel_adsp)
 
-elseif(CONFIG_BOARD_INTEL_ADSP_ACE20_LNL)
+elseif(CONFIG_BOARD_INTEL_ADSP_ACE20_LNL OR CONFIG_BOARD_INTEL_ADSP_ACE20_LNL_SIM)
 
   set(SUPPORTED_EMU_PLATFORMS acesim)
 
@@ -39,7 +39,7 @@ elseif(CONFIG_BOARD_INTEL_ADSP_ACE20_LNL)
 
   set(RIMAGE_SIGN_KEY "otc_private_key_3k.pem" CACHE STRING "default in ace20_lnl/board.cmake")
 
-elseif(CONFIG_BOARD_INTEL_ADSP_ACE30_PTL)
+elseif(CONFIG_BOARD_INTEL_ADSP_ACE30_PTL OR CONFIG_BOARD_INTEL_ADSP_ACE30_PTL_SIM)
 
   board_set_rimage_target(ptl)
 

boards/intel/adsp/board.yml

@@ -6,5 +6,11 @@ boards:
         variants:
           - name: 'tgph'
       - name: ace15_mtpm
+        variants:
+          - name: 'sim'
       - name: ace20_lnl
+        variants:
+          - name: 'sim'
       - name: ace30_ptl
+        variants:
+          - name: 'sim'

boards/intel/adsp/intel_adsp_ace15_mtpm_sim.dts

@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include "intel_adsp_ace15_mtpm.dts"

boards/intel/adsp/intel_adsp_ace15_mtpm_sim.yaml

@@ -0,0 +1,14 @@
+identifier: intel_adsp/ace15_mtpm/sim
+name: ACE 1.5 Meteor Lake M Audio DSP
+type: sim
+simulation: custom
+arch: xtensa
+toolchain:
+  - xcc
+  - zephyr
+  - xt-clang
+testing:
+  timeout_multiplier: 4
+  ignore_tags:
+    - net
+    - bluetooth

boards/intel/adsp/intel_adsp_ace15_mtpm_sim_defconfig

@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MAIN_STACK_SIZE=2048
+
+CONFIG_INTEL_ADSP_SIM=y
+CONFIG_INTEL_ADSP_SIM_NO_SECONDARY_CORE_FLOW=y
+
+CONFIG_GEN_ISR_TABLES=y
+CONFIG_GEN_IRQ_VECTOR_TABLE=n
+
+CONFIG_BUILD_OUTPUT_BIN=n
+CONFIG_MM_DRV=y
+CONFIG_CRYPTO=y
+
+CONFIG_DCACHE_LINE_SIZE=64

boards/intel/adsp/intel_adsp_ace20_lnl_sim.dts

@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include "intel_adsp_ace20_lnl.dts"

boards/intel/adsp/intel_adsp_ace20_lnl_sim.yaml

@@ -0,0 +1,13 @@
+identifier: intel_adsp/ace20_lnl/sim
+name: ACE 2.0 Lunar Lake Audio DSP
+type: sim
+simulation: custom
+arch: xtensa
+toolchain:
+  - xcc
+  - xt-clang
+testing:
+  timeout_multiplier: 6
+  ignore_tags:
+    - net
+    - bluetooth

boards/intel/adsp/intel_adsp_ace20_lnl_sim_defconfig

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MAIN_STACK_SIZE=2048
+CONFIG_INTEL_ADSP_SIM=y
+CONFIG_GEN_ISR_TABLES=y
+CONFIG_GEN_IRQ_VECTOR_TABLE=n
+
+CONFIG_BUILD_OUTPUT_BIN=n
+CONFIG_MM_DRV=y

boards/intel/adsp/intel_adsp_ace30_ptl_sim.dts

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2022 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <intel/intel_adsp_ace30_ptl.dtsi>
+
+/ {
+	model = "intel_adsp_ace30_ptl_sim";
+	compatible = "intel";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &mem_window3;
+	};
+};

boards/intel/adsp/intel_adsp_ace30_ptl_sim.yaml

@@ -0,0 +1,12 @@
+identifier: intel_adsp/ace30_ptl/sim
+name: ACE 3.0 Panther Lake Audio DSP
+type: sim
+simulation: custom
+arch: xtensa
+toolchain:
+  - xt-clang
+testing:
+  timeout_multiplier: 8
+  ignore_tags:
+    - net
+    - bluetooth

boards/intel/adsp/intel_adsp_ace30_ptl_sim_defconfig

@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MAIN_STACK_SIZE=2048
+
+CONFIG_INTEL_ADSP_SIM=y
+CONFIG_INTEL_ADSP_SIM_NO_SECONDARY_CORE_FLOW=y
+
+CONFIG_GEN_ISR_TABLES=y
+CONFIG_GEN_IRQ_VECTOR_TABLE=n
+
+CONFIG_BUILD_OUTPUT_BIN=n
+
+CONFIG_DAI_SSP_HAS_POWER_CONTROL=y
+
+CONFIG_DCACHE_LINE_SIZE=64

soc/intel/intel_adsp/Kconfig

@@ -15,6 +15,22 @@ if SOC_FAMILY_INTEL_ADSP
 
 rsource "*/Kconfig"
 
+config INTEL_ADSP_SIM
+	bool "Intel ADSP Simulator"
+	select SIMULATOR_XTENSA
+	help
+	  Running this SoC family in a simulator.
+
+if INTEL_ADSP_SIM
+
+config INTEL_ADSP_SIM_NO_SECONDARY_CORE_FLOW
+	bool "No secondary core flow."
+	help
+	  Select if simulator doesn't use the normal secondary core flow
+	  to initialise secondary clocks.
+
+endif # INTEL_ADSP_SIM
+
 DT_COMPAT_INTEL_ADSP_HOST_IPC := intel,adsp-host-ipc
 DT_COMPAT_INTEL_ADSP_IDC := intel,adsp-idc
 

soc/intel/intel_adsp/ace/Kconfig.defconfig.ace15_mtpm

@@ -8,6 +8,7 @@ config MP_MAX_NUM_CPUS
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 393216000 if XTENSA_TIMER
+	default 1000000 if INTEL_ADSP_SIM
 	default 38400000 if INTEL_ADSP_TIMER
 
 config XTENSA_CCOUNT_HZ

soc/intel/intel_adsp/ace/Kconfig.defconfig.ace20_lnl

@@ -8,6 +8,7 @@ config MP_MAX_NUM_CPUS
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 393216000 if XTENSA_TIMER
+	default 1000000 if INTEL_ADSP_SIM
 	default 38400000 if INTEL_ADSP_TIMER
 
 config XTENSA_CCOUNT_HZ

soc/intel/intel_adsp/ace/Kconfig.defconfig.ace30_ptl

@@ -9,6 +9,7 @@ config MP_MAX_NUM_CPUS
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 442368000 if XTENSA_TIMER
+	default 1000000 if INTEL_ADSP_SIM
 	default 38400000 if INTEL_ADSP_TIMER
 
 config XTENSA_CCOUNT_HZ

soc/intel/intel_adsp/ace/Kconfig.defconfig.series

@@ -41,6 +41,7 @@ config XTENSA_TIMER_ID
 	default 0
 
 config SYS_CLOCK_TICKS_PER_SEC
+	default 100 if INTEL_ADSP_SIM
 	default 12000
 
 config INTEL_ADSP_TIMER

soc/intel/intel_adsp/ace/multiprocessing.c

@@ -83,6 +83,13 @@ __imr void soc_num_cpus_init(void)
 
 void soc_mp_init(void)
 {
+#if defined(CONFIG_INTEL_ADSP_SIM_NO_SECONDARY_CORE_FLOW)
+	/* BADDR stores the Xtensa LX7 AltResetVec input */
+	for (int i = 0; i < soc_num_cpus; i++) {
+		DSPCS.bootctl[i].baddr = (uint32_t)z_soc_mp_asm_entry;
+	}
+#endif
+
 	IRQ_CONNECT(ACE_IRQ_TO_ZEPHYR(ACE_INTL_IDCA), 0, ipc_isr, 0, 0);
 
 	irq_enable(ACE_IRQ_TO_ZEPHYR(ACE_INTL_IDCA));
@@ -120,6 +127,7 @@ void soc_mp_on_d3_exit(void)
 
 void soc_start_core(int cpu_num)
 {
+#if !defined(CONFIG_INTEL_ADSP_SIM_NO_SECONDARY_CORE_FLOW)
 	int retry = CORE_POWER_CHECK_NUM;
 
 	if (cpu_num > 0) {
@@ -153,6 +161,7 @@ void soc_start_core(int cpu_num)
 		/* Tell the ACE ROM that it should use secondary core flow */
 		DSPCS.bootctl[cpu_num].battr |= DSPBR_BATTR_LPSCTL_BATTR_SLAVE_CORE;
 	}
+#endif /* !defined(CONFIG_INTEL_ADSP_SIM_NO_SECONDARY_CORE_FLOW) */
 
 	/* Setting the Power Active bit to the off state before powering up the core. This step is
 	 * required by the HW if we are starting core for a second time. Without this sequence, the
@@ -168,6 +177,7 @@ void soc_start_core(int cpu_num)
 
 	DSPCS.capctl[cpu_num].ctl |= DSPCS_CTL_SPA;
 
+#if !defined(CONFIG_INTEL_ADSP_SIM_NO_SECONDARY_CORE_FLOW)
 	/* Waiting for power up */
 	while (((DSPCS.capctl[cpu_num].ctl & DSPCS_CTL_CPA) != DSPCS_CTL_CPA) &&
 	       (retry > 0)) {
@@ -178,6 +188,7 @@ void soc_start_core(int cpu_num)
 	if (retry == 0) {
 		__ASSERT(false, "%s secondary core has not powered up", __func__);
 	}
+#endif /* !defined(CONFIG_INTEL_ADSP_SIM_NO_SECONDARY_CORE_FLOW) */
 }
 
 void soc_mp_startup(uint32_t cpu)

soc/intel/intel_adsp/common/boot.c

@@ -16,6 +16,10 @@
 #include <cpu_init.h>
 #include "manifest.h"
 
+#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
+#include <adsp_boot.h>
+#endif /* CONFIG_SOC_SERIES_INTEL_ADSP_ACE */
+
 /* Important note about linkage:
  *
  * The C code here, starting from boot_core0(), is running entirely in
@@ -138,6 +142,15 @@ extern void lp_sram_init(void);
 
 __imr void boot_core0(void)
 {
+#if defined(CONFIG_INTEL_ADSP_SIM_NO_SECONDARY_CORE_FLOW)
+	int prid;
+
+	prid = arch_proc_id();
+	if (prid != 0) {
+		((void (*)(void))DSPCS.bootctl[prid].baddr)();
+	}
+#endif
+
 	cpu_early_init();
 
 #ifdef CONFIG_ADSP_DISABLE_L2CACHE_AT_BOOT