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global: Replace BUILD_ASSERT_MSG() with BUILD_ASSERT()

Browse source 
Replace all occurences of BUILD_ASSERT_MSG() with BUILD_ASSERT()
as a result of merging BUILD_ASSERT() and BUILD_ASSERT_MSG().

Signed-off-by: Oleg Zhurakivskyy <oleg.zhurakivskyy@intel.com>
This commit is contained in:
Oleg Zhurakivskyy 2020-03-12 17:16:00 +02:00 • committed by Carles Cufí
commit 8739517107
52 changed files with 206 additions and 207 deletions
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28
boards/arm/nrf52840_pca10090/integrity.c
View file

@ -10,47 +10,47 @@
* used in board.c and the ones defined in Kconfig.
*/
BUILD_ASSERT_MSG(IS_ENABLED(CONFIG_BOARD_PCA10090_INTERFACE0_MCU) ||
BUILD_ASSERT(IS_ENABLED(CONFIG_BOARD_PCA10090_INTERFACE0_MCU) ||
IS_ENABLED(CONFIG_BOARD_PCA10090_INTERFACE0_ARDUINO),
"Invalid MCU interface 0 routing");
BUILD_ASSERT_MSG(IS_ENABLED(CONFIG_BOARD_PCA10090_INTERFACE1_MCU) ||
BUILD_ASSERT(IS_ENABLED(CONFIG_BOARD_PCA10090_INTERFACE1_MCU) ||
IS_ENABLED(CONFIG_BOARD_PCA10090_INTERFACE1_TRACE),
"Invalid MCU interface 1 routing");
BUILD_ASSERT_MSG(IS_ENABLED(CONFIG_BOARD_PCA10090_INTERFACE2_MCU) ||
BUILD_ASSERT(IS_ENABLED(CONFIG_BOARD_PCA10090_INTERFACE2_MCU) ||
IS_ENABLED(CONFIG_BOARD_PCA10090_INTERFACE2_COEX),
"Invalid MCU interface 2 routing");
BUILD_ASSERT_MSG(IS_ENABLED(CONFIG_BOARD_PCA10090_UART0_VCOM) ||
BUILD_ASSERT(IS_ENABLED(CONFIG_BOARD_PCA10090_UART0_VCOM) ||
IS_ENABLED(CONFIG_BOARD_PCA10090_UART0_ARDUINO),
"Invalid nRF9160 UART0 routing");
BUILD_ASSERT_MSG(IS_ENABLED(CONFIG_BOARD_PCA10090_UART1_VCOM) ||
BUILD_ASSERT(IS_ENABLED(CONFIG_BOARD_PCA10090_UART1_VCOM) ||
IS_ENABLED(CONFIG_BOARD_PCA10090_UART1_ARDUINO),
"Invalid nRF9160 UART1 routing");
BUILD_ASSERT_MSG(IS_ENABLED(CONFIG_BOARD_PCA10090_LED0_PHY) ||
BUILD_ASSERT(IS_ENABLED(CONFIG_BOARD_PCA10090_LED0_PHY) ||
IS_ENABLED(CONFIG_BOARD_PCA10090_LED0_ARDUINO),
"Invalid LED 1 routing");
BUILD_ASSERT_MSG(IS_ENABLED(CONFIG_BOARD_PCA10090_LED1_PHY) ||
BUILD_ASSERT(IS_ENABLED(CONFIG_BOARD_PCA10090_LED1_PHY) ||
IS_ENABLED(CONFIG_BOARD_PCA10090_LED1_ARDUINO),
"Invalid LED 2 routing");
BUILD_ASSERT_MSG(IS_ENABLED(CONFIG_BOARD_PCA10090_LED2_PHY) ||
BUILD_ASSERT(IS_ENABLED(CONFIG_BOARD_PCA10090_LED2_PHY) ||
IS_ENABLED(CONFIG_BOARD_PCA10090_LED2_ARDUINO),
"Invalid LED 3 routing");
BUILD_ASSERT_MSG(IS_ENABLED(CONFIG_BOARD_PCA10090_LED3_PHY) ||
BUILD_ASSERT(IS_ENABLED(CONFIG_BOARD_PCA10090_LED3_PHY) ||
IS_ENABLED(CONFIG_BOARD_PCA10090_LED3_ARDUINO),
"Invalid LED 4 routing");
BUILD_ASSERT_MSG(IS_ENABLED(CONFIG_BOARD_PCA10090_BUTTON0_PHY) ||
BUILD_ASSERT(IS_ENABLED(CONFIG_BOARD_PCA10090_BUTTON0_PHY) ||
IS_ENABLED(CONFIG_BOARD_PCA10090_BUTTON0_ARDUINO),
"Invalid button 1 routing");
BUILD_ASSERT_MSG(IS_ENABLED(CONFIG_BOARD_PCA10090_BUTTON1_PHY) ||
BUILD_ASSERT(IS_ENABLED(CONFIG_BOARD_PCA10090_BUTTON1_PHY) ||
IS_ENABLED(CONFIG_BOARD_PCA10090_BUTTON1_ARDUINO),
"Invalid button 2 routing");
BUILD_ASSERT_MSG(IS_ENABLED(CONFIG_BOARD_PCA10090_SWITCH0_PHY) ||
BUILD_ASSERT(IS_ENABLED(CONFIG_BOARD_PCA10090_SWITCH0_PHY) ||
IS_ENABLED(CONFIG_BOARD_PCA10090_SWITCH0_ARDUINO),
"Invalid switch 1 routing");
BUILD_ASSERT_MSG(IS_ENABLED(CONFIG_BOARD_PCA10090_SWITCH1_PHY) ||
BUILD_ASSERT(IS_ENABLED(CONFIG_BOARD_PCA10090_SWITCH1_PHY) ||
IS_ENABLED(CONFIG_BOARD_PCA10090_SWITCH1_ARDUINO),
"Invalid switch 2 routing");
BUILD_ASSERT_MSG(!IS_ENABLED(CONFIG_BOARD_PCA10090_NRF52840_RESET) ||
BUILD_ASSERT(!IS_ENABLED(CONFIG_BOARD_PCA10090_NRF52840_RESET) ||
IS_ENABLED(CONFIG_BOARD_PCA10090_NRF52840_RESET_P0_17) ||
IS_ENABLED(CONFIG_BOARD_PCA10090_NRF52840_RESET_P0_20) ||
IS_ENABLED(CONFIG_BOARD_PCA10090_NRF52840_RESET_P0_15) ||

2
boards/arm/nrf9160_pca10090/nrf52840_reset.c
View file

@ -13,7 +13,7 @@
/* Must be a pin from 17 to 23.
* Only those can be connected to the nRF52840.
*/
BUILD_ASSERT_MSG(RESET_PIN > 16 && RESET_PIN < 24,
BUILD_ASSERT(RESET_PIN > 16 && RESET_PIN < 24,
"Selected pin is not connected to nRF52840");
int bt_hci_transport_setup(struct device *h4)

2
drivers/adc/adc_lmp90xxx.c
View file

@ -1051,7 +1051,7 @@ static const struct adc_driver_api lmp90xxx_adc_api = {
};
#define ASSERT_LMP90XXX_CURRENT_VALID(v) \
BUILD_ASSERT_MSG(v == 0 || v == 100 || v == 200 || v == 300 || \
BUILD_ASSERT(v == 0 || v == 100 || v == 200 || v == 300 || \
v == 400 || v == 500 || v == 600 || v == 700 || \
v == 800 || v == 900 || v == 1000, \
"unsupported RTD current (" #v ")")

4
drivers/adc/adc_mcux_adc12.c
View file

@ -246,9 +246,9 @@ static const struct adc_driver_api mcux_adc12_driver_api = {
};
#define ASSERT_WITHIN_RANGE(val, min, max, str) \
BUILD_ASSERT_MSG(val >= min && val <= max, str)
BUILD_ASSERT(val >= min && val <= max, str)
#define ASSERT_ADC12_CLK_DIV_VALID(val, str) \
BUILD_ASSERT_MSG(val == 1 || val == 2 || val == 4 || val == 8, str)
BUILD_ASSERT(val == 1 || val == 2 || val == 4 || val == 8, str)
#define TO_ADC12_CLOCK_SRC(val) _DO_CONCAT(kADC12_ClockSourceAlt, val)
#define TO_ADC12_CLOCK_DIV(val) _DO_CONCAT(kADC12_ClockDivider, val)

2
drivers/counter/counter_nrfx_rtc.c
View file

@ -655,7 +655,7 @@ static const struct counter_driver_api counter_nrfx_driver_api = {
};
#define COUNTER_NRF_RTC_DEVICE(idx) \
BUILD_ASSERT_MSG((DT_NORDIC_NRF_RTC_RTC_##idx##_PRESCALER - 1) <= \
BUILD_ASSERT((DT_NORDIC_NRF_RTC_RTC_##idx##_PRESCALER - 1) <= \
RTC_PRESCALER_PRESCALER_Msk, \
"RTC prescaler out of range"); \
DEVICE_DECLARE(rtc_##idx); \

2
drivers/counter/counter_nrfx_timer.c
View file

@ -383,7 +383,7 @@ static const struct counter_driver_api counter_nrfx_driver_api = {
};
#define COUNTER_NRFX_TIMER_DEVICE(idx) \
BUILD_ASSERT_MSG(DT_NORDIC_NRF_TIMER_TIMER_##idx##_PRESCALER <= \
BUILD_ASSERT(DT_NORDIC_NRF_TIMER_TIMER_##idx##_PRESCALER <= \
TIMER_PRESCALER_PRESCALER_Msk, \
"TIMER prescaler out of range"); \
DEVICE_DECLARE(timer_##idx); \

8
drivers/eeprom/eeprom_at2x.c
View file

@ -535,19 +535,19 @@ static const struct eeprom_driver_api eeprom_at2x_api = {
};
#define ASSERT_AT24_ADDR_W_VALID(w) \
BUILD_ASSERT_MSG(w == 8U || w == 16U, \
BUILD_ASSERT(w == 8U || w == 16U, \
"Unsupported address width")
#define ASSERT_AT25_ADDR_W_VALID(w) \
BUILD_ASSERT_MSG(w == 8U || w == 16U || w == 24U, \
BUILD_ASSERT(w == 8U || w == 16U || w == 24U, \
"Unsupported address width")
#define ASSERT_PAGESIZE_IS_POWER_OF_2(page) \
BUILD_ASSERT_MSG((page != 0U) && ((page & (page - 1)) == 0U), \
BUILD_ASSERT((page != 0U) && ((page & (page - 1)) == 0U), \
"Page size is not a power of two")
#define ASSERT_SIZE_PAGESIZE_VALID(size, page) \
BUILD_ASSERT_MSG(size % page == 0U, \
BUILD_ASSERT(size % page == 0U, \
"Size is not an integer multiple of page size")
#define EEPROM_AT2X_DEVICE(t, n) \

4
drivers/entropy/entropy_nrf5.c
View file

@ -74,11 +74,11 @@ struct rng_pool {
#define RNG_POOL_DEFINE(name, len) u8_t name[sizeof(struct rng_pool) + (len)]
BUILD_ASSERT_MSG((CONFIG_ENTROPY_NRF5_ISR_POOL_SIZE &
BUILD_ASSERT((CONFIG_ENTROPY_NRF5_ISR_POOL_SIZE &
(CONFIG_ENTROPY_NRF5_ISR_POOL_SIZE - 1)) == 0,
"The CONFIG_ENTROPY_NRF5_ISR_POOL_SIZE must be a power of 2!");
BUILD_ASSERT_MSG((CONFIG_ENTROPY_NRF5_THR_POOL_SIZE &
BUILD_ASSERT((CONFIG_ENTROPY_NRF5_THR_POOL_SIZE &
(CONFIG_ENTROPY_NRF5_THR_POOL_SIZE - 1)) == 0,
"The CONFIG_ENTROPY_NRF5_THR_POOL_SIZE must be a power of 2!");

2
drivers/ethernet/eth_sam_gmac_priv.h
View file

@ -41,7 +41,7 @@
#endif
#define GMAC_PRIORITY_QUEUE_NUM (GMAC_QUEUE_NUM - 1)
#if (GMAC_PRIORITY_QUEUE_NUM >= 1)
BUILD_ASSERT_MSG(ARRAY_SIZE(GMAC->GMAC_TBQBAPQ) + 1 == GMAC_QUEUE_NUM,
BUILD_ASSERT(ARRAY_SIZE(GMAC->GMAC_TBQBAPQ) + 1 == GMAC_QUEUE_NUM,
"GMAC_QUEUE_NUM doesn't match soc header");
#endif
/** Number of priority queues used */

2
drivers/flash/nrf_qspi_nor.c
View file

@ -638,7 +638,7 @@ static int qspi_nor_init(struct device *dev)
#define LAYOUT_PAGES_COUNT (INST_0_BYTES / \
CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE)
BUILD_ASSERT_MSG((CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE *
BUILD_ASSERT((CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE *
LAYOUT_PAGES_COUNT)
== INST_0_BYTES,
"QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE incompatible with flash size");

4
drivers/flash/spi_nor.c
View file

@ -528,13 +528,13 @@ static int spi_nor_init(struct device *dev)
/* instance 0 size in bytes */
#define INST_0_BYTES (DT_INST_0_JEDEC_SPI_NOR_SIZE / 8)
BUILD_ASSERT_MSG(SPI_NOR_IS_SECTOR_ALIGNED(CONFIG_SPI_NOR_FLASH_LAYOUT_PAGE_SIZE),
BUILD_ASSERT(SPI_NOR_IS_SECTOR_ALIGNED(CONFIG_SPI_NOR_FLASH_LAYOUT_PAGE_SIZE),
"SPI_NOR_FLASH_LAYOUT_PAGE_SIZE must be multiple of 4096");
/* instance 0 page count */
#define LAYOUT_PAGES_COUNT (INST_0_BYTES / CONFIG_SPI_NOR_FLASH_LAYOUT_PAGE_SIZE)
BUILD_ASSERT_MSG((CONFIG_SPI_NOR_FLASH_LAYOUT_PAGE_SIZE * LAYOUT_PAGES_COUNT)
BUILD_ASSERT((CONFIG_SPI_NOR_FLASH_LAYOUT_PAGE_SIZE * LAYOUT_PAGES_COUNT)
== INST_0_BYTES,
"SPI_NOR_FLASH_LAYOUT_PAGE_SIZE incompatible with flash size");

2
drivers/gpio/gpio_litex.c
View file

@ -214,7 +214,7 @@ static const struct gpio_driver_api gpio_litex_driver_api = {
/* Device Instantiation */
#define GPIO_LITEX_INIT(n) \
BUILD_ASSERT_MSG(DT_INST_##n##_LITEX_GPIO_SIZE != 0 \
BUILD_ASSERT(DT_INST_##n##_LITEX_GPIO_SIZE != 0 \
&& DT_INST_##n##_LITEX_GPIO_SIZE % 4 == 0, \
"Register size must be a multiple of 4"); \
\

2
drivers/gpio/gpio_lmp90xxx.c
View file

@ -159,7 +159,7 @@ static const struct gpio_driver_api gpio_lmp90xxx_api = {
.port_get_raw = gpio_lmp90xxx_port_get_raw,
};
BUILD_ASSERT_MSG(CONFIG_GPIO_LMP90XXX_INIT_PRIORITY >
BUILD_ASSERT(CONFIG_GPIO_LMP90XXX_INIT_PRIORITY >
CONFIG_ADC_LMP90XXX_INIT_PRIORITY,
"LMP90xxx GPIO driver must be initialized after LMP90xxx ADC "
"driver");

2
drivers/i2c/i2c_dw.h
View file

@ -19,7 +19,7 @@
DT_INST_5_SNPS_DESIGNWARE_I2C_PCIE || \
DT_INST_6_SNPS_DESIGNWARE_I2C_PCIE || \
DT_INST_7_SNPS_DESIGNWARE_I2C_PCIE
BUILD_ASSERT_MSG(IS_ENABLED(CONFIG_PCIE), "DW I2C in DT needs CONFIG_PCIE");
BUILD_ASSERT(IS_ENABLED(CONFIG_PCIE), "DW I2C in DT needs CONFIG_PCIE");
#define I2C_DW_PCIE_ENABLED
#include <drivers/pcie/pcie.h>
#endif

2
drivers/i2c/i2c_dw_port_x.h
View file

@ -42,7 +42,7 @@ static void i2c_config_@NUM@(struct device *port)
/* PCI(e) with auto IRQ detection */
BUILD_ASSERT_MSG(IS_ENABLED(CONFIG_DYNAMIC_INTERRUPTS),
BUILD_ASSERT(IS_ENABLED(CONFIG_DYNAMIC_INTERRUPTS),
"DW I2C PCI auto-IRQ needs CONFIG_DYNAMIC_INTERRUPTS");
unsigned int irq;

2
drivers/i2c/i2c_nrfx_twi.c
View file

@ -242,7 +242,7 @@ static int twi_nrfx_pm_control(struct device *dev, u32_t ctrl_command,
: I2C_NRFX_TWI_INVALID_FREQUENCY)
#define I2C_NRFX_TWI_DEVICE(idx) \
BUILD_ASSERT_MSG( \
BUILD_ASSERT( \
I2C_NRFX_TWI_FREQUENCY( \
DT_NORDIC_NRF_TWI_I2C_##idx##_CLOCK_FREQUENCY) \
!= I2C_NRFX_TWI_INVALID_FREQUENCY, \

2
drivers/i2c/i2c_nrfx_twim.c
View file

@ -216,7 +216,7 @@ static int twim_nrfx_pm_control(struct device *dev, u32_t ctrl_command,
: I2C_NRFX_TWIM_INVALID_FREQUENCY)
#define I2C_NRFX_TWIM_DEVICE(idx) \
BUILD_ASSERT_MSG( \
BUILD_ASSERT( \
I2C_NRFX_TWIM_FREQUENCY( \
DT_NORDIC_NRF_TWIM_I2C_##idx##_CLOCK_FREQUENCY) \
!= I2C_NRFX_TWIM_INVALID_FREQUENCY, \

2
drivers/sensor/ms5607/ms5607.c
View file

@ -240,7 +240,7 @@ static int ms5607_init(struct device *dev)
#ifdef DT_MEAS_MS5607_BUS_SPI
ms5607_spi_init(dev);
#else
BUILD_ASSERT_MSG(1, "I2c interface not implemented yet");
BUILD_ASSERT(1, "I2c interface not implemented yet");
#endif
data->pressure = 0;

2
drivers/sensor/ms5607/ms5607.h
View file

@ -65,7 +65,7 @@
int ms5607_spi_init(struct device *dev);
#else
/* I2c Interface not implemented yet */
BUILD_ASSERT_MSG(1, "I2c interface not implemented yet");
BUILD_ASSERT(1, "I2c interface not implemented yet");
#endif
struct ms5607_config {

2
drivers/sensor/nxp_kinetis_temp/temp_kinetis.c
View file

@ -159,7 +159,7 @@ static int temp_kinetis_init(struct device *dev)
}
#ifdef DT_INST_0_NXP_KINETIS_TEMPERATURE
BUILD_ASSERT_MSG(DT_INST_0_NXP_KINETIS_TEMPERATURE_SENSOR_IO_CHANNELS_INPUT <
BUILD_ASSERT(DT_INST_0_NXP_KINETIS_TEMPERATURE_SENSOR_IO_CHANNELS_INPUT <
DT_INST_0_NXP_KINETIS_TEMPERATURE_BANDGAP_IO_CHANNELS_INPUT,
"This driver assumes sensor ADC channel to come before "
"bandgap ADC channel");

4
drivers/sensor/qdec_nrfx/qdec_nrfx.c
View file

@ -90,9 +90,9 @@ static int qdec_nrfx_channel_get(struct device *dev,
data->acc = 0;
irq_unlock(key);
BUILD_ASSERT_MSG(DT_NORDIC_NRF_QDEC_QDEC_0_STEPS > 0,
BUILD_ASSERT(DT_NORDIC_NRF_QDEC_QDEC_0_STEPS > 0,
"only positive number valid");
BUILD_ASSERT_MSG(DT_NORDIC_NRF_QDEC_QDEC_0_STEPS <= 2148,
BUILD_ASSERT(DT_NORDIC_NRF_QDEC_QDEC_0_STEPS <= 2148,
"overflow possible");
val->val1 = (acc * FULL_ANGLE) / DT_NORDIC_NRF_QDEC_QDEC_0_STEPS;

2
drivers/serial/uart_ns16550.c
View file

@ -58,7 +58,7 @@
DT_INST_1_NS16550_PCIE || \
DT_INST_2_NS16550_PCIE || \
DT_INST_3_NS16550_PCIE
BUILD_ASSERT_MSG(IS_ENABLED(CONFIG_PCIE), "NS16550(s) in DT need CONFIG_PCIE");
BUILD_ASSERT(IS_ENABLED(CONFIG_PCIE), "NS16550(s) in DT need CONFIG_PCIE");
#define UART_NS16550_PCIE_ENABLED
#include <drivers/pcie/pcie.h>
#endif

2
drivers/serial/uart_ns16550_port_x.h
View file

@ -69,7 +69,7 @@ static void irq_config_func_@NUM@(struct device *dev)
/* PCI(e) with auto IRQ detection */
BUILD_ASSERT_MSG(IS_ENABLED(CONFIG_DYNAMIC_INTERRUPTS),
BUILD_ASSERT(IS_ENABLED(CONFIG_DYNAMIC_INTERRUPTS),
"NS16550 PCI auto-IRQ needs CONFIG_DYNAMIC_INTERRUPTS");
unsigned int irq;

2
drivers/spi/spi_nrfx_spi.c
View file

@ -343,7 +343,7 @@ static int spi_nrfx_pm_control(struct device *dev, u32_t ctrl_command,
: NRF_GPIO_PIN_NOPULL)
#define SPI_NRFX_SPI_DEVICE(idx) \
BUILD_ASSERT_MSG( \
BUILD_ASSERT( \
!SPI_NRFX_MISO_PULL_UP(idx) || !SPI_NRFX_MISO_PULL_DOWN(idx), \
"SPI"#idx \
": cannot enable both pull-up and pull-down on MISO line"); \

2
drivers/spi/spi_nrfx_spim.c
View file

@ -389,7 +389,7 @@ static int spim_nrfx_pm_control(struct device *dev, u32_t ctrl_command,
))
#define SPI_NRFX_SPIM_DEVICE(idx) \
BUILD_ASSERT_MSG( \
BUILD_ASSERT( \
!SPIM_NRFX_MISO_PULL_UP(idx) || !SPIM_NRFX_MISO_PULL_DOWN(idx),\
"SPIM"#idx \
": cannot enable both pull-up and pull-down on MISO line"); \

4
drivers/timer/apic_timer.c
View file

@ -8,7 +8,7 @@
#include <spinlock.h>
#include <drivers/interrupt_controller/loapic.h>
BUILD_ASSERT_MSG(!IS_ENABLED(CONFIG_SMP), "APIC timer doesn't support SMP");
BUILD_ASSERT(!IS_ENABLED(CONFIG_SMP), "APIC timer doesn't support SMP");
/*
* Overview:
@ -55,7 +55,7 @@ BUILD_ASSERT_MSG(!IS_ENABLED(CONFIG_SMP), "APIC timer doesn't support SMP");
#define CYCLES_PER_TICK \
(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
BUILD_ASSERT_MSG(CYCLES_PER_TICK >= 2, "APIC timer: bad CYCLES_PER_TICK");
BUILD_ASSERT(CYCLES_PER_TICK >= 2, "APIC timer: bad CYCLES_PER_TICK");
/* max number of ticks we can load into the timer in one shot */

4
drivers/timer/mchp_xec_rtos_timer.c
View file

@ -9,8 +9,8 @@
#include <sys_clock.h>
#include <spinlock.h>
BUILD_ASSERT_MSG(!IS_ENABLED(CONFIG_SMP), "XEC RTOS timer doesn't support SMP");
BUILD_ASSERT_MSG(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 32768,
BUILD_ASSERT(!IS_ENABLED(CONFIG_SMP), "XEC RTOS timer doesn't support SMP");
BUILD_ASSERT(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 32768,
"XEC RTOS timer HW frequency is fixed at 32768");
#define DEBUG_RTOS_TIMER 0

4
drivers/timer/sam0_rtc_timer.c
View file

@ -44,7 +44,7 @@
*/
#define TICK_THRESHOLD 7
BUILD_ASSERT_MSG(CYCLES_PER_TICK > TICK_THRESHOLD,
BUILD_ASSERT(CYCLES_PER_TICK > TICK_THRESHOLD,
"CYCLES_PER_TICK must be greater than TICK_THRESHOLD for "
"tickless mode");
@ -55,7 +55,7 @@ BUILD_ASSERT_MSG(CYCLES_PER_TICK > TICK_THRESHOLD,
* MATCHCLR == 1 and PRESCALER == 0. So we need to check that CYCLES_PER_TICK
* is more than one.
*/
BUILD_ASSERT_MSG(CYCLES_PER_TICK > 1,
BUILD_ASSERT(CYCLES_PER_TICK > 1,
"CYCLES_PER_TICK must be greater than 1 for ticking mode");
#endif /* CONFIG_TICKLESS_KERNEL */

4
include/arch/arc/arch.h
View file

@ -207,14 +207,14 @@ extern "C" {
#if CONFIG_ARC_MPU_VER == 2
#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
BUILD_ASSERT_MSG(!(((size) & ((size) - 1))) && (size) >= STACK_ALIGN \
BUILD_ASSERT(!(((size) & ((size) - 1))) && (size) >= STACK_ALIGN \
&& !((u32_t)(start) & ((size) - 1)), \
"the size of the partition must be power of 2" \
" and greater than or equal to the mpu adddress alignment." \
"start address of the partition must align with size.")
#elif CONFIG_ARC_MPU_VER == 3
#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
BUILD_ASSERT_MSG((size) % STACK_ALIGN == 0 && (size) >= STACK_ALIGN \
BUILD_ASSERT((size) % STACK_ALIGN == 0 && (size) >= STACK_ALIGN \
&& (u32_t)(start) % STACK_ALIGN == 0, \
"the size of the partition must align with 32" \
" and greater than or equal to 32." \

2
include/arch/arc/v2/irq.h
View file

@ -81,7 +81,7 @@ extern void z_irq_spurious(void *unused);
#define ARCH_IRQ_DIRECT_CONNECT(irq_p, priority_p, isr_p, flags_p) \
({ \
Z_ISR_DECLARE(irq_p, ISR_FLAG_DIRECT, isr_p, NULL); \
BUILD_ASSERT_MSG(priority_p || !IS_ENABLED(CONFIG_ARC_FIRQ) || \
BUILD_ASSERT(priority_p || !IS_ENABLED(CONFIG_ARC_FIRQ) || \
(IS_ENABLED(CONFIG_ARC_FIRQ_STACK) && \
!IS_ENABLED(CONFIG_ARC_STACK_CHECKING)), \
"irq priority cannot be set to 0 when CONFIG_ARC_FIRQ_STACK" \

2
include/arch/arm/aarch32/cortex_m/mpu/arm_mpu_v7m.h
View file

@ -265,7 +265,7 @@ typedef struct {
#endif /* _ASMLANGUAGE */
#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
BUILD_ASSERT_MSG(!(((size) & ((size) - 1))) && \
BUILD_ASSERT(!(((size) & ((size) - 1))) && \
(size) >= CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE && \
!((u32_t)(start) & ((size) - 1)), \
"the size of the partition must be power of 2" \

2
include/arch/arm/aarch32/cortex_m/mpu/arm_mpu_v8m.h
View file

@ -252,7 +252,7 @@ typedef struct {
#endif /* _ASMLANGUAGE */
#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
BUILD_ASSERT_MSG((size > 0) && ((u32_t)start % \
BUILD_ASSERT((size > 0) && ((u32_t)start % \
CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0U) && \
((size) % CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0), \
" the start and size of the partition must align " \

2
include/arch/arm/aarch32/cortex_m/mpu/nxp_mpu.h
View file

@ -260,7 +260,7 @@ extern const struct nxp_mpu_config mpu_config;
#endif /* _ASMLANGUAGE */
#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
BUILD_ASSERT_MSG((size) % \
BUILD_ASSERT((size) % \
CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0 && \
(size) >= CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE && \
(u32_t)(start) % CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0, \

2
include/shell/shell.h
View file

@ -501,7 +501,7 @@ struct shell_flags {
u32_t last_nl :8; /*!< Last received new line character */
};
BUILD_ASSERT_MSG((sizeof(struct shell_flags) == sizeof(u32_t)),
BUILD_ASSERT((sizeof(struct shell_flags) == sizeof(u32_t)),
"Structure must fit in 4 bytes");

2
include/spinlock.h
View file

@ -19,7 +19,7 @@ struct k_spinlock;
bool z_spin_lock_valid(struct k_spinlock *l);
bool z_spin_unlock_valid(struct k_spinlock *l);
void z_spin_lock_set_owner(struct k_spinlock *l);
BUILD_ASSERT_MSG(CONFIG_MP_NUM_CPUS < 4, "Too many CPUs for mask");
BUILD_ASSERT(CONFIG_MP_NUM_CPUS < 4, "Too many CPUs for mask");
#endif /* CONFIG_SPIN_VALIDATE */
struct k_spinlock_key {

2
kernel/sched.c
View file

@ -1366,7 +1366,7 @@ static inline int z_vrfy_k_is_preempt_thread(void)
#ifdef CONFIG_SCHED_CPU_MASK
# ifdef CONFIG_SMP
/* Right now we use a single byte for this mask */
BUILD_ASSERT_MSG(CONFIG_MP_NUM_CPUS <= 8, "Too many CPUs for mask word");
BUILD_ASSERT(CONFIG_MP_NUM_CPUS <= 8, "Too many CPUs for mask word");
# endif

2
lib/cmsis_rtos_v1/cmsis_thread.c
View file

@ -51,7 +51,7 @@ osThreadId osThreadCreate(const osThreadDef_t *thread_def, void *arg)
return NULL;
}
BUILD_ASSERT_MSG(
BUILD_ASSERT(
CONFIG_NUM_PREEMPT_PRIORITIES >= TOTAL_CMSIS_THREAD_PRIORITIES,
"Configure NUM_PREEMPT_PRIORITIES to at least"
" TOTAL_CMSIS_THREAD_PRIORITIES");

2
lib/cmsis_rtos_v2/mempool.c
View file

@ -30,7 +30,7 @@ osMemoryPoolId_t osMemoryPoolNew(uint32_t block_count, uint32_t block_size,
{
struct cv2_mslab *mslab;
BUILD_ASSERT_MSG(CONFIG_HEAP_MEM_POOL_SIZE >=
BUILD_ASSERT(CONFIG_HEAP_MEM_POOL_SIZE >=
CONFIG_CMSIS_V2_MEM_SLAB_MAX_DYNAMIC_SIZE,
"heap must be configured to be at least the max dynamic size");

2
lib/cmsis_rtos_v2/msgq.c
View file

@ -28,7 +28,7 @@ osMessageQueueId_t osMessageQueueNew(uint32_t msg_count, uint32_t msg_size,
{
struct cv2_msgq *msgq;
BUILD_ASSERT_MSG(CONFIG_HEAP_MEM_POOL_SIZE >=
BUILD_ASSERT(CONFIG_HEAP_MEM_POOL_SIZE >=
CONFIG_CMSIS_V2_MSGQ_MAX_DYNAMIC_SIZE,
"heap must be configured to be at least the max dynamic size");

6
lib/cmsis_rtos_v2/thread.c
View file

@ -133,14 +133,14 @@ osThreadId_t osThreadNew(osThreadFunc_t threadfunc, void *arg,
return NULL;
}
BUILD_ASSERT_MSG(osPriorityISR <= CONFIG_NUM_PREEMPT_PRIORITIES,
BUILD_ASSERT(osPriorityISR <= CONFIG_NUM_PREEMPT_PRIORITIES,
"Configure NUM_PREEMPT_PRIORITIES to at least osPriorityISR");
BUILD_ASSERT_MSG(CONFIG_CMSIS_V2_THREAD_DYNAMIC_MAX_COUNT <=
BUILD_ASSERT(CONFIG_CMSIS_V2_THREAD_DYNAMIC_MAX_COUNT <=
CONFIG_CMSIS_V2_THREAD_MAX_COUNT,
"Number of dynamic threads cannot exceed max number of threads.");
BUILD_ASSERT_MSG(CONFIG_CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE <=
BUILD_ASSERT(CONFIG_CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE <=
CONFIG_CMSIS_V2_THREAD_MAX_STACK_SIZE,
"Default dynamic thread stack size cannot exceed max stack size");

3
lib/posix/fs.c
View file

@ -12,8 +12,7 @@
#include <string.h>
#include <sys/fdtable.h>
BUILD_ASSERT_MSG(PATH_MAX >= MAX_FILE_NAME,
"PATH_MAX is less than MAX_FILE_NAME");
BUILD_ASSERT(PATH_MAX >= MAX_FILE_NAME, "PATH_MAX is less than MAX_FILE_NAME");
struct posix_fs_desc {
union {

4
soc/arm/nxp_kinetis/ke1xf/soc.c
View file

@ -16,10 +16,10 @@
#include <arch/arm/aarch32/cortex_m/cmsis.h>
#define ASSERT_WITHIN_RANGE(val, min, max, str) \
BUILD_ASSERT_MSG(val >= min && val <= max, str)
BUILD_ASSERT(val >= min && val <= max, str)
#define ASSERT_ASYNC_CLK_DIV_VALID(val, str) \
BUILD_ASSERT_MSG(val == 0 || val == 1 || val == 2 || val == 4 || \
BUILD_ASSERT(val == 0 || val == 1 || val == 2 || val == 4 || \
val == 8 || val == 16 || val == 2 || val == 64, str)
#define TO_SYS_CLK_DIV(val) _DO_CONCAT(kSCG_SysClkDivBy, val)

2
subsys/bluetooth/common/dummy.c
View file

@ -35,6 +35,6 @@ BUILD_ASSERT(CONFIG_BT_CTLR_RX_PRIO < CONFIG_BT_HCI_TX_PRIO);
*/
#if !defined(CONFIG_TEST) && !defined(CONFIG_ARCH_POSIX) && \
(defined(CONFIG_BT_LL_SW_SPLIT) || defined(CONFIG_BT_LL_SW_LEGACY))
BUILD_ASSERT_MSG(!IS_ENABLED(CONFIG_LOG_IMMEDIATE), "Immediate logging not "
BUILD_ASSERT(!IS_ENABLED(CONFIG_LOG_IMMEDIATE), "Immediate logging not "
"supported with the software Link Layer");
#endif

18
subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_ppi.h
View file

@ -667,7 +667,7 @@ static inline void hal_radio_sw_switch_ppi_group_setup(void)
*/
#define NRFX_PPI_CHANNELS_USED_BY_PWM_SW 0
#endif
BUILD_ASSERT_MSG(
BUILD_ASSERT(
(HAL_USED_PPI_CHANNELS & NRFX_PPI_CHANNELS_USED_BY_PWM_SW) == 0,
"PPI channels used by the Bluetooth controller overlap with those "
"assigned to the pwm_nrf5_sw driver.");
@ -1217,22 +1217,22 @@ static inline void hal_radio_sw_switch_setup(
* - Group Enable
* tasks are all going to be subscribed on the same PPI.
*/
BUILD_ASSERT_MSG(
BUILD_ASSERT(
&HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_REGISTER_EVT ==
&HAL_SW_SWITCH_TIMER_CLEAR_PPI_REGISTER_EVT,
"SW SWitch Timer Clear and Group Disable"
" not on the same PPI channel.");
BUILD_ASSERT_MSG(
BUILD_ASSERT(
HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_EVT ==
HAL_SW_SWITCH_TIMER_CLEAR_PPI_EVT,
"SW SWitch Timer Clear and Group Disable"
" not on the same PPI channel.");
BUILD_ASSERT_MSG(
BUILD_ASSERT(
&HAL_RADIO_END_TIME_CAPTURE_PPI_REGISTER_EVT ==
&HAL_SW_SWITCH_TIMER_CLEAR_PPI_REGISTER_EVT,
"Radio End Timer Capture and Group Disable"
" not on the same PPI channel.");
BUILD_ASSERT_MSG(
BUILD_ASSERT(
HAL_RADIO_END_TIME_CAPTURE_PPI_EVT ==
HAL_SW_SWITCH_TIMER_CLEAR_PPI_EVT,
"Radio End Timer Capture and Group Disable"
@ -1364,19 +1364,19 @@ static inline void hal_radio_sw_switch_ppi_group_setup(void)
/* Sanity build-time check that RADIO Enable and Group Disable
* tasks are going to be subscribed on the same PPIs.
*/
BUILD_ASSERT_MSG(
BUILD_ASSERT(
HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_0_INCLUDE ==
BIT(HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(0)),
"Radio enable and Group disable not on the right PPI channel.");
BUILD_ASSERT_MSG(
BUILD_ASSERT(
HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_1_INCLUDE ==
BIT(HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(1)),
"Radio enable and Group disable not on the right PPI channel.");
BUILD_ASSERT_MSG(
BUILD_ASSERT(
HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_0_INCLUDE ==
HAL_SW_SWITCH_RADIO_ENABLE_PPI_0_INCLUDE,
"Radio enable and Group disable not on the same PPI channel.");
BUILD_ASSERT_MSG(
BUILD_ASSERT(
HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_1_INCLUDE ==
HAL_SW_SWITCH_RADIO_ENABLE_PPI_1_INCLUDE,
"Radio enable and Group disable not on the same PPI channel.");

2
subsys/dfu/img_util/flash_img.c
View file

@ -31,7 +31,7 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME);
#define FLASH_AREA_IMAGE_SECONDARY DT_FLASH_AREA_IMAGE_1_ID
#endif /* CONFIG_TRUSTED_EXECUTION_NONSECURE */
BUILD_ASSERT_MSG((CONFIG_IMG_BLOCK_BUF_SIZE % DT_FLASH_WRITE_BLOCK_SIZE == 0),
BUILD_ASSERT((CONFIG_IMG_BLOCK_BUF_SIZE % DT_FLASH_WRITE_BLOCK_SIZE == 0),
"CONFIG_IMG_BLOCK_BUF_SIZE is not a multiple of "
"DT_FLASH_WRITE_BLOCK_SIZE");

2
subsys/fs/nvs/nvs_priv.h
View file

@ -37,7 +37,7 @@ struct nvs_ate {
u8_t crc8; /* crc8 check of the entry */
} __packed;
BUILD_ASSERT_MSG(offsetof(struct nvs_ate, crc8) ==
BUILD_ASSERT(offsetof(struct nvs_ate, crc8) ==
sizeof(struct nvs_ate) - sizeof(u8_t),
"crc8 must be the last member");

10
subsys/logging/log_msg.c
View file

@ -11,19 +11,19 @@
#include <string.h>
#include <assert.h>
BUILD_ASSERT_MSG((sizeof(struct log_msg_ids) == sizeof(u16_t)),
BUILD_ASSERT((sizeof(struct log_msg_ids) == sizeof(u16_t)),
"Structure must fit in 2 bytes");
BUILD_ASSERT_MSG((sizeof(struct log_msg_generic_hdr) == sizeof(u16_t)),
BUILD_ASSERT((sizeof(struct log_msg_generic_hdr) == sizeof(u16_t)),
"Structure must fit in 2 bytes");
BUILD_ASSERT_MSG((sizeof(struct log_msg_std_hdr) == sizeof(u16_t)),
BUILD_ASSERT((sizeof(struct log_msg_std_hdr) == sizeof(u16_t)),
"Structure must fit in 2 bytes");
BUILD_ASSERT_MSG((sizeof(struct log_msg_hexdump_hdr) == sizeof(u16_t)),
BUILD_ASSERT((sizeof(struct log_msg_hexdump_hdr) == sizeof(u16_t)),
"Structure must fit in 2 bytes");
BUILD_ASSERT_MSG((sizeof(union log_msg_head_data) ==
BUILD_ASSERT((sizeof(union log_msg_head_data) ==
sizeof(struct log_msg_ext_head_data)),
"Structure must be same size");

4
subsys/net/ip/net_tc.c
View file

@ -104,7 +104,7 @@ static u8_t tx_tc2thread(u8_t tc)
#endif
};
BUILD_ASSERT_MSG(NET_TC_TX_COUNT <= CONFIG_NUM_COOP_PRIORITIES,
BUILD_ASSERT(NET_TC_TX_COUNT <= CONFIG_NUM_COOP_PRIORITIES,
"Too many traffic classes");
NET_ASSERT(tc < ARRAY_SIZE(thread_priorities));
@ -157,7 +157,7 @@ static u8_t rx_tc2thread(u8_t tc)
#endif
};
BUILD_ASSERT_MSG(NET_TC_RX_COUNT <= CONFIG_NUM_COOP_PRIORITIES,
BUILD_ASSERT(NET_TC_RX_COUNT <= CONFIG_NUM_COOP_PRIORITIES,
"Too many traffic classes");
NET_ASSERT(tc < ARRAY_SIZE(thread_priorities));

2
subsys/shell/shell_rtt.c
View file

@ -9,7 +9,7 @@
#include <SEGGER_RTT.h>
#include <logging/log.h>
BUILD_ASSERT_MSG(!(IS_ENABLED(CONFIG_LOG_BACKEND_RTT) &&
BUILD_ASSERT(!(IS_ENABLED(CONFIG_LOG_BACKEND_RTT) &&
COND_CODE_0(CONFIG_LOG_BACKEND_RTT_BUFFER, (1), (0))),
"Conflicting log RTT backend enabled on the same channel");

2
tests/application_development/cpp/src/main.cpp
View file

@ -47,7 +47,7 @@ BUILD_ASSERT(sizeof(foo) == sizeof(int));
static struct foo foos[5];
/* Check that ARRAY_SIZE compiles. */
BUILD_ASSERT_MSG(ARRAY_SIZE(foos) == 5, "expected 5 elements");
BUILD_ASSERT(ARRAY_SIZE(foos) == 5, "expected 5 elements");
/* Check that SYS_INIT() compiles. */
static int test_init(struct device *dev)

12
tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c
View file

@ -20,13 +20,13 @@
/* The customized solution for nRF51X-based and nRF52X-based
* platforms requires that the POWER_CLOCK_IRQn line equals 0.
*/
BUILD_ASSERT_MSG(POWER_CLOCK_IRQn == 0,
BUILD_ASSERT(POWER_CLOCK_IRQn == 0,
"POWER_CLOCK_IRQn != 0. Consider rework manual vector table.");
/* The customized solution for nRF51X-based and nRF52X-based
* platforms requires that the RTC1 IRQ line equals 17.
*/
BUILD_ASSERT_MSG(RTC1_IRQn == 17,
BUILD_ASSERT(RTC1_IRQn == 17,
"RTC1_IRQn != 17. Consider rework manual vector table.");
#undef _ISR_OFFSET
@ -37,7 +37,7 @@ BUILD_ASSERT_MSG(RTC1_IRQn == 17,
/* The customized solution for nRF51-based QEMU Cortex-M0 platform
* requires that the TIMER0 IRQ line equals 8.
*/
BUILD_ASSERT_MSG(TIMER0_IRQn == 8,
BUILD_ASSERT(TIMER0_IRQn == 8,
"TIMER0_IRQn != 8. Consider rework manual vector table.");
/* Interrupt lines 9-11 is the first set of consecutive interrupts implemented
* in QEMU Cortex M0.
@ -50,7 +50,7 @@ BUILD_ASSERT_MSG(TIMER0_IRQn == 8,
/* The customized solution for nRF91X-based and nRF53X-based
* platforms requires that the POWER_CLOCK_IRQn line equals 5.
*/
BUILD_ASSERT_MSG(CLOCK_POWER_IRQn == 5,
BUILD_ASSERT(CLOCK_POWER_IRQn == 5,
"POWER_CLOCK_IRQn != 5."
"Consider rework manual vector table.");
@ -58,14 +58,14 @@ BUILD_ASSERT_MSG(CLOCK_POWER_IRQn == 5,
/* The customized solution for nRF91X-based platforms
* requires that the RTC1 IRQ line equals 21.
*/
BUILD_ASSERT_MSG(RTC1_IRQn == 21,
BUILD_ASSERT(RTC1_IRQn == 21,
"RTC1_IRQn != 21. Consider rework manual vector table.");
#else /* CONFIG_SOC_NRF5340_CPUNET */
/* The customized solution for nRF5340_CPUNET
* requires that the RTC1 IRQ line equals 22.
*/
BUILD_ASSERT_MSG(RTC1_IRQn == 22,
BUILD_ASSERT(RTC1_IRQn == 22,
"RTC1_IRQn != 22. Consider rework manual vector table.");
#endif
#undef _ISR_OFFSET

4
tests/subsys/logging/log_core/src/log_core_test.c
View file

@ -333,7 +333,7 @@ static void test_log_strdup_gc(void)
log_setup(false);
BUILD_ASSERT_MSG(CONFIG_LOG_STRDUP_BUF_COUNT == 1,
BUILD_ASSERT(CONFIG_LOG_STRDUP_BUF_COUNT == 1,
"Test assumes certain configuration");
backend1_cb.check_strdup = true;
backend1_cb.exp_strdup[0] = true;
@ -419,7 +419,7 @@ static void test_strdup_trimming(void)
{
char test_str[] = "123456789";
BUILD_ASSERT_MSG(CONFIG_LOG_STRDUP_MAX_STRING == 8,
BUILD_ASSERT(CONFIG_LOG_STRDUP_MAX_STRING == 8,
"Test assumes certain configuration");
log_setup(false);