diff --git a/dts/arm/nxp/nxp_imx6sx_m4.dtsi b/dts/arm/nxp/nxp_imx6sx_m4.dtsi
index fc9a4131572..ea7d1cfa9b7 100644
--- a/dts/arm/nxp/nxp_imx6sx_m4.dtsi
+++ b/dts/arm/nxp/nxp_imx6sx_m4.dtsi
@@ -241,6 +241,18 @@
 			#gpio-cells = <2>;
 			status = "disabled";
 		};
+
+		mub:mu@4229c000 {
+			compatible = "nxp,imx-mu";
+			reg = <0x4229c000 0x4000>;
+			interrupts = <99 0>;
+			rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
+					       RDC_DOMAIN_PERM_RW)|\
+			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
+					       RDC_DOMAIN_PERM_RW))>;
+			label = "MU_B";
+			status = "disabled";
+		};
 	};
 };
 
diff --git a/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.defconfig.mcimx6x_m4 b/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.defconfig.mcimx6x_m4
index 11b50191bff..f4e184e5e88 100644
--- a/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.defconfig.mcimx6x_m4
+++ b/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.defconfig.mcimx6x_m4
@@ -32,4 +32,11 @@ config UART_IMX
 
 endif # SERIAL
 
+if IPM
+
+config IPM_IMX
+	def_bool y
+
+endif # IPM
+
 endif # SOC_MCIMX6X_M4
diff --git a/soc/arm/nxp_imx/mcimx6x_m4/dts_fixup.h b/soc/arm/nxp_imx/mcimx6x_m4/dts_fixup.h
index 11ac892aa92..9b033a7ded5 100644
--- a/soc/arm/nxp_imx/mcimx6x_m4/dts_fixup.h
+++ b/soc/arm/nxp_imx/mcimx6x_m4/dts_fixup.h
@@ -96,3 +96,8 @@
 #define DT_UART_IMX_UART_6_IRQ_PRI		DT_NXP_IMX_UART_422A0000_IRQ_0_PRIORITY
 #define DT_UART_IMX_UART_6_BAUD_RATE	DT_NXP_IMX_UART_422A0000_CURRENT_SPEED
 #define DT_UART_IMX_UART_6_MODEM_MODE	DT_NXP_IMX_UART_422A0000_MODEM_MODE
+
+#define DT_IPM_IMX_MU_B_BASE_ADDRESS	DT_NXP_IMX_MU_4229C000_BASE_ADDRESS
+#define DT_IPM_IMX_MU_B_IRQ			DT_NXP_IMX_MU_4229C000_IRQ_0
+#define DT_IPM_IMX_MU_B_IRQ_PRI		DT_NXP_IMX_MU_4229C000_IRQ_0_PRIORITY
+#define DT_IPM_IMX_MU_B_NAME			DT_NXP_IMX_MU_4229C000_LABEL
diff --git a/soc/arm/nxp_imx/mcimx6x_m4/soc.c b/soc/arm/nxp_imx/mcimx6x_m4/soc.c
index 989785ae34c..f744aaeed6b 100644
--- a/soc/arm/nxp_imx/mcimx6x_m4/soc.c
+++ b/soc/arm/nxp_imx/mcimx6x_m4/soc.c
@@ -73,6 +73,11 @@ static void SOC_RdcInit(void)
 	/* Set access to GPIO_7 for M4 core */
 	RDC_SetPdapAccess(RDC, rdcPdapGpio7, GPIO_7_RDC, false, false);
 #endif /* CONFIG_GPIO_IMX_PORT_7 */
+
+#ifdef CONFIG_IPM_IMX
+	/* Set access to MU B for M4 core */
+	RDC_SetPdapAccess(RDC, rdcPdapMuB, MU_B_RDC, false, false);
+#endif /* CONFIG_IPM_IMX */
 }
 
 /* Initialize cache. */