drivers: flash: stm32: ospi: read/erase single, dual and quad modes
Adds support to read and erase NOR-Flash over OSPI using the following modes: * 1-1-2 * 1-2-2 * 1-1-4 * 1-4-4 Supports 4-Byte opcodes conversion and gets address width from the SFDP:BFP. Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
This commit is contained in:
Georgij Cernysiov
Carles Cufí
parent
018375a42b
commit
871ded0e65
1 changed files with 243 additions and 83 deletions
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2022 STMicroelectronics
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* Copyright (c) 2022 Georgij Cernysiov
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -66,6 +67,12 @@ struct flash_stm32_ospi_data {
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struct jesd216_erase_type erase_types[JESD216_NUM_ERASE_TYPES];
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/* Number of bytes per page */
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uint16_t page_size;
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/* Address width in bytes */
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uint8_t address_width;
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/* Read operation dummy cycles */
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uint8_t read_dummy;
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uint32_t read_opcode;
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enum jesd216_mode_type read_mode;
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int cmd_status;
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};
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@ -175,30 +182,22 @@ static int ospi_write_access(const struct device *dev, OSPI_RegularCmdTypeDef *c
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*/
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static OSPI_RegularCmdTypeDef ospi_prepare_cmd(uint8_t transfer_mode, uint8_t transfer_rate)
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{
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OSPI_RegularCmdTypeDef cmd_tmp = {
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.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG,
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.FlashId = HAL_OSPI_FLASH_ID_1,
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.InstructionMode = ((transfer_mode == OSPI_SPI_MODE)
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? HAL_OSPI_INSTRUCTION_1_LINE
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: HAL_OSPI_INSTRUCTION_8_LINES),
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.InstructionSize = ((transfer_mode == OSPI_SPI_MODE)
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? HAL_OSPI_INSTRUCTION_8_BITS
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: HAL_OSPI_INSTRUCTION_16_BITS),
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.InstructionSize = ((transfer_mode == OSPI_OPI_MODE)
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? HAL_OSPI_INSTRUCTION_16_BITS
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: HAL_OSPI_INSTRUCTION_8_BITS),
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.InstructionDtrMode = ((transfer_rate == OSPI_DTR_TRANSFER)
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? HAL_OSPI_INSTRUCTION_DTR_ENABLE
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: HAL_OSPI_INSTRUCTION_DTR_DISABLE),
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.AddressMode = ((transfer_mode == OSPI_SPI_MODE)
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? HAL_OSPI_ADDRESS_1_LINE
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: HAL_OSPI_ADDRESS_8_LINES),
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.AddressDtrMode = ((transfer_rate == OSPI_DTR_TRANSFER)
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? HAL_OSPI_ADDRESS_DTR_ENABLE
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: HAL_OSPI_ADDRESS_DTR_DISABLE),
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.AddressSize = HAL_OSPI_ADDRESS_32_BITS,
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.AddressSize = ((transfer_mode == OSPI_OPI_MODE)
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? HAL_OSPI_ADDRESS_32_BITS
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: HAL_OSPI_ADDRESS_24_BITS),
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.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE,
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.DataMode = ((transfer_mode == OSPI_SPI_MODE)
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? HAL_OSPI_DATA_1_LINE
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: HAL_OSPI_DATA_8_LINES),
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.DataDtrMode = ((transfer_rate == OSPI_DTR_TRANSFER)
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? HAL_OSPI_DATA_DTR_ENABLE
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: HAL_OSPI_DATA_DTR_DISABLE),
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@ -208,6 +207,33 @@ static OSPI_RegularCmdTypeDef ospi_prepare_cmd(uint8_t transfer_mode, uint8_t tr
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.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD,
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};
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switch (transfer_mode) {
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case OSPI_OPI_MODE: {
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cmd_tmp.InstructionMode = HAL_OSPI_INSTRUCTION_8_LINES;
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cmd_tmp.AddressMode = HAL_OSPI_ADDRESS_8_LINES;
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cmd_tmp.DataMode = HAL_OSPI_DATA_8_LINES;
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break;
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}
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case OSPI_QUAD_MODE: {
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cmd_tmp.InstructionMode = HAL_OSPI_INSTRUCTION_4_LINES;
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cmd_tmp.AddressMode = HAL_OSPI_ADDRESS_4_LINES;
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cmd_tmp.DataMode = HAL_OSPI_DATA_4_LINES;
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break;
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}
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case OSPI_DUAL_MODE: {
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cmd_tmp.InstructionMode = HAL_OSPI_INSTRUCTION_2_LINES;
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cmd_tmp.AddressMode = HAL_OSPI_ADDRESS_2_LINES;
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cmd_tmp.DataMode = HAL_OSPI_DATA_2_LINES;
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break;
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}
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default: {
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cmd_tmp.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
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cmd_tmp.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
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cmd_tmp.DataMode = HAL_OSPI_DATA_1_LINE;
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break;
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}
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}
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return cmd_tmp;
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}
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@ -233,20 +259,22 @@ static int ospi_read_sfdp(const struct device *dev, off_t addr, uint8_t *data,
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OSPI_RegularCmdTypeDef cmd = ospi_prepare_cmd(dev_cfg->data_mode,
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dev_cfg->data_rate);
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cmd.Instruction = ((dev_cfg->data_mode == OSPI_SPI_MODE)
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? JESD216_CMD_READ_SFDP
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: JESD216_OCMD_READ_SFDP);
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if (dev_cfg->data_mode == OSPI_OPI_MODE) {
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cmd.Instruction = JESD216_OCMD_READ_SFDP;
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cmd.DummyCycles = 20U;
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} else {
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cmd.Instruction = JESD216_CMD_READ_SFDP;
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cmd.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
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cmd.DataMode = HAL_OSPI_DATA_1_LINE;
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cmd.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
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cmd.DummyCycles = 8U;
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}
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cmd.Address = addr;
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cmd.AddressSize = ((dev_cfg->data_mode == OSPI_SPI_MODE)
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? HAL_OSPI_ADDRESS_24_BITS
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: HAL_OSPI_ADDRESS_32_BITS);
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cmd.DummyCycles = ((dev_cfg->data_mode == OSPI_SPI_MODE) ? 8U : 20U);
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cmd.NbData = size;
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HAL_StatusTypeDef hal_ret;
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hal_ret = HAL_OSPI_Command(&dev_data->hospi, &cmd,
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HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
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hal_ret = HAL_OSPI_Command(&dev_data->hospi, &cmd, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
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if (hal_ret != HAL_OK) {
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LOG_ERR("%d: Failed to send OSPI instruction", hal_ret);
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return -EIO;
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@ -284,16 +312,22 @@ static int stm32_ospi_mem_ready(OSPI_HandleTypeDef *hospi, uint8_t nor_mode, uin
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OSPI_RegularCmdTypeDef s_command = ospi_prepare_cmd(nor_mode, nor_rate);
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/* Configure automatic polling mode command to wait for memory ready */
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s_command.Instruction = (nor_mode == OSPI_SPI_MODE)
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? SPI_NOR_CMD_RDSR
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: SPI_NOR_OCMD_RDSR;
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s_command.Address = 0;
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s_command.DummyCycles = (nor_mode == OSPI_SPI_MODE)
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? 0U
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: ((nor_rate == OSPI_DTR_TRANSFER)
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if (nor_mode == OSPI_OPI_MODE) {
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s_command.Instruction = SPI_NOR_OCMD_RDSR;
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} else {
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s_command.Instruction = SPI_NOR_CMD_RDSR;
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s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
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s_command.DataMode = HAL_OSPI_DATA_1_LINE;
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}
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s_command.NbData = ((nor_rate == OSPI_DTR_TRANSFER) ? 2U : 1U);
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s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
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s_command.Address = 0U;
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if (nor_mode == OSPI_OPI_MODE) {
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s_command.DummyCycles = (nor_rate == OSPI_DTR_TRANSFER)
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? SPI_NOR_DUMMY_REG_OCTAL_DTR
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: SPI_NOR_DUMMY_REG_OCTAL);
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s_command.NbData = (nor_rate == OSPI_DTR_TRANSFER) ? 2U : 1U;
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: SPI_NOR_DUMMY_REG_OCTAL;
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}
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/* Set the mask to 0x01 to mask all Status REG bits except WIP */
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/* Set the match to 0x00 to check if the WIP bit is Reset */
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@ -324,9 +358,12 @@ static int stm32_ospi_write_enable(OSPI_HandleTypeDef *hospi, uint8_t nor_mode,
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OSPI_RegularCmdTypeDef s_command = ospi_prepare_cmd(nor_mode, nor_rate);
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/* Initialize the write enable command */
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s_command.Instruction = (nor_mode == OSPI_SPI_MODE)
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? SPI_NOR_CMD_WREN
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: SPI_NOR_OCMD_WREN;
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if (nor_mode == OSPI_OPI_MODE) {
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s_command.Instruction = SPI_NOR_OCMD_WREN;
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} else {
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s_command.Instruction = SPI_NOR_CMD_WREN;
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s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
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}
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s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
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s_command.DataMode = HAL_OSPI_DATA_NONE;
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s_command.DummyCycles = 0U;
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@ -337,21 +374,16 @@ static int stm32_ospi_write_enable(OSPI_HandleTypeDef *hospi, uint8_t nor_mode,
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}
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/* Configure automatic polling mode to wait for write enabling */
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s_command.Instruction = (nor_mode == OSPI_SPI_MODE)
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? SPI_NOR_CMD_RDSR
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: SPI_NOR_OCMD_RDSR;
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s_command.AddressMode = (nor_mode == OSPI_SPI_MODE)
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? HAL_OSPI_ADDRESS_1_LINE
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: HAL_OSPI_ADDRESS_8_LINES;
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s_command.Address = 0U;
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s_command.DummyCycles = (nor_mode == OSPI_SPI_MODE)
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? 0U
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: ((nor_rate == OSPI_DTR_TRANSFER)
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if (nor_mode == OSPI_OPI_MODE) {
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s_command.Instruction = SPI_NOR_OCMD_RDSR;
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s_command.DummyCycles = (nor_rate == OSPI_DTR_TRANSFER)
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? SPI_NOR_DUMMY_REG_OCTAL_DTR
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: SPI_NOR_DUMMY_REG_OCTAL);
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s_command.DataMode = (nor_mode == OSPI_SPI_MODE)
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? HAL_OSPI_DATA_1_LINE
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: HAL_OSPI_DATA_8_LINES;
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: SPI_NOR_DUMMY_REG_OCTAL;
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} else {
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s_command.Instruction = SPI_NOR_CMD_RDSR;
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s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE,
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s_command.DataMode = HAL_OSPI_DATA_1_LINE;
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}
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s_command.NbData = (nor_rate == OSPI_DTR_TRANSFER) ? 2U : 1U;
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if (HAL_OSPI_Command(hospi, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
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@ -473,9 +505,9 @@ static int stm32_ospi_config_mem(const struct device *dev)
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uint8_t reg[2];
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/* Going to set the SPI mode and STR transfer rate : done */
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if ((dev_cfg->data_mode == OSPI_SPI_MODE)
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if ((dev_cfg->data_mode != OSPI_OPI_MODE)
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&& (dev_cfg->data_rate == OSPI_STR_TRANSFER)) {
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LOG_INF("OSPI flash config is SPI / STR");
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LOG_INF("OSPI flash config is SPI|DUAL|QUAD / STR");
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return 0;
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}
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@ -644,6 +676,17 @@ static int stm32_ospi_mem_reset(const struct device *dev)
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return 0;
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}
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static uint32_t stm32_ospi_hal_address_size(const struct device *dev)
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{
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struct flash_stm32_ospi_data *dev_data = dev->data;
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if (dev_data->address_width == 4U) {
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return HAL_OSPI_ADDRESS_32_BITS;
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}
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return HAL_OSPI_ADDRESS_24_BITS;
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}
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/*
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* Function to erase the flash : chip or sector with possible OSPI/SPI and STR/DTR
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* to erase the complete chip (using dedicated command) :
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@ -685,7 +728,7 @@ static int flash_stm32_ospi_erase(const struct device *dev, off_t addr,
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.FlashId = HAL_OSPI_FLASH_ID_1,
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.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE,
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.DataMode = HAL_OSPI_DATA_NONE,
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.DummyCycles = 0,
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.DummyCycles = 0U,
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.DQSMode = HAL_OSPI_DQS_DISABLE,
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.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD,
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};
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@ -704,23 +747,23 @@ static int flash_stm32_ospi_erase(const struct device *dev, off_t addr,
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return -EIO;
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}
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cmd_erase.InstructionMode = (dev_cfg->data_mode == OSPI_SPI_MODE)
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? HAL_OSPI_INSTRUCTION_1_LINE
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: HAL_OSPI_INSTRUCTION_8_LINES;
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cmd_erase.InstructionMode = (dev_cfg->data_mode == OSPI_OPI_MODE)
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? HAL_OSPI_INSTRUCTION_8_LINES
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: HAL_OSPI_INSTRUCTION_1_LINE;
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cmd_erase.InstructionDtrMode = (dev_cfg->data_rate == OSPI_DTR_TRANSFER)
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? HAL_OSPI_INSTRUCTION_DTR_ENABLE
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: HAL_OSPI_INSTRUCTION_DTR_DISABLE;
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cmd_erase.InstructionSize = (dev_cfg->data_mode == OSPI_SPI_MODE)
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? HAL_OSPI_INSTRUCTION_8_BITS
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: HAL_OSPI_INSTRUCTION_16_BITS;
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cmd_erase.InstructionSize = (dev_cfg->data_mode == OSPI_OPI_MODE)
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? HAL_OSPI_INSTRUCTION_16_BITS
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: HAL_OSPI_INSTRUCTION_8_BITS;
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while ((size > 0) && (ret == 0)) {
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if (size == dev_cfg->flash_size) {
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/* Chip erase */
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LOG_INF("Chip Erase");
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cmd_erase.Instruction = (dev_cfg->data_mode == OSPI_SPI_MODE)
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? SPI_NOR_CMD_BULKE
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: SPI_NOR_OCMD_BULKE;
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LOG_DBG("Chip Erase");
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cmd_erase.Instruction = (dev_cfg->data_mode == OSPI_OPI_MODE)
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? SPI_NOR_OCMD_BULKE
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: SPI_NOR_CMD_BULKE;
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cmd_erase.AddressMode = HAL_OSPI_ADDRESS_NONE;
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/* Full chip erase command */
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ospi_send_cmd(dev, &cmd_erase);
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@ -728,7 +771,7 @@ static int flash_stm32_ospi_erase(const struct device *dev, off_t addr,
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size -= dev_cfg->flash_size;
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} else {
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/* Sector erase */
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LOG_INF("Sector Erase");
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LOG_DBG("Sector Erase");
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cmd_erase.Address = addr;
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const struct jesd216_erase_type *erase_types =
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dev_data->erase_types;
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@ -749,18 +792,18 @@ static int flash_stm32_ospi_erase(const struct device *dev, off_t addr,
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} else {
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/* Use the default sector erase cmd */
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cmd_erase.Instruction =
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(dev_cfg->data_mode == OSPI_SPI_MODE)
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? SPI_NOR_CMD_SE /* Erase sector size 3 bytes */
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: SPI_NOR_OCMD_SE;
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(dev_cfg->data_mode == OSPI_OPI_MODE)
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? SPI_NOR_OCMD_SE
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: SPI_NOR_CMD_SE; /* Erase sector size 4K-Bytes */
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cmd_erase.AddressMode =
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(dev_cfg->data_mode == OSPI_SPI_MODE)
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? HAL_OSPI_ADDRESS_1_LINE
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: HAL_OSPI_ADDRESS_8_LINES;
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(dev_cfg->data_mode == OSPI_OPI_MODE)
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? HAL_OSPI_ADDRESS_8_LINES
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: HAL_OSPI_ADDRESS_1_LINE;
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cmd_erase.AddressDtrMode =
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(dev_cfg->data_rate == OSPI_DTR_TRANSFER)
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? HAL_OSPI_ADDRESS_DTR_ENABLE
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: HAL_OSPI_ADDRESS_DTR_DISABLE;
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cmd_erase.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
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cmd_erase.AddressSize = stm32_ospi_hal_address_size(dev);
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cmd_erase.Address = addr;
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}
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}
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@ -790,6 +833,7 @@ static int flash_stm32_ospi_read(const struct device *dev, off_t addr,
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void *data, size_t size)
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{
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const struct flash_stm32_ospi_config *dev_cfg = dev->config;
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struct flash_stm32_ospi_data *dev_data = dev->data;
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int ret;
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if (!ospi_address_is_valid(dev, addr, size)) {
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@ -804,13 +848,44 @@ static int flash_stm32_ospi_read(const struct device *dev, off_t addr,
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}
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OSPI_RegularCmdTypeDef cmd = ospi_prepare_cmd(dev_cfg->data_mode, dev_cfg->data_rate);
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if (dev_cfg->data_mode != OSPI_OPI_MODE) {
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switch (dev_data->read_mode) {
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case JESD216_MODE_112: {
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cmd.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
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cmd.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
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cmd.DataMode = HAL_OSPI_DATA_2_LINES;
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break;
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}
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case JESD216_MODE_122: {
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cmd.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
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cmd.AddressMode = HAL_OSPI_ADDRESS_2_LINES;
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cmd.DataMode = HAL_OSPI_DATA_2_LINES;
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break;
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}
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case JESD216_MODE_114: {
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cmd.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
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cmd.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
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cmd.DataMode = HAL_OSPI_DATA_4_LINES;
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break;
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}
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case JESD216_MODE_144: {
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cmd.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
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cmd.AddressMode = HAL_OSPI_ADDRESS_4_LINES;
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cmd.DataMode = HAL_OSPI_DATA_4_LINES;
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break;
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}
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default:
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/* use the mode from ospi_prepare_cmd */
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break;
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}
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}
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/* Instruction and DummyCycles are set below */
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cmd.Address = addr;
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cmd.AddressSize = stm32_ospi_hal_address_size(dev);
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/* DataSize is set by the read cmd */
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LOG_DBG("OSPI: read %u data", size);
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ospi_lock_thread(dev);
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/* Configure other parameters */
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if (dev_cfg->data_rate == OSPI_DTR_TRANSFER) {
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/* DTR transfer rate (==> Octal mode) */
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@ -818,17 +893,20 @@ static int flash_stm32_ospi_read(const struct device *dev, off_t addr,
|
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cmd.DummyCycles = SPI_NOR_DUMMY_RD_OCTAL_DTR;
|
||||
} else {
|
||||
/* STR transfer rate */
|
||||
if (dev_cfg->data_mode == OSPI_SPI_MODE) {
|
||||
/* SPI and STR : use fast read with addr on 4 bytes */
|
||||
cmd.Instruction = SPI_NOR_CMD_READ_FAST_4B;
|
||||
cmd.DummyCycles = SPI_NOR_DUMMY_RD;
|
||||
} else {
|
||||
if (dev_cfg->data_mode == OSPI_OPI_MODE) {
|
||||
/* OPI and STR */
|
||||
cmd.Instruction = SPI_NOR_OCMD_RD;
|
||||
cmd.DummyCycles = SPI_NOR_DUMMY_RD_OCTAL;
|
||||
} else {
|
||||
/* use SFDP:BFP read instruction */
|
||||
cmd.Instruction = dev_data->read_opcode;
|
||||
cmd.DummyCycles = dev_data->read_dummy;
|
||||
}
|
||||
}
|
||||
|
||||
LOG_DBG("OSPI: read %zu data", size);
|
||||
ospi_lock_thread(dev);
|
||||
|
||||
ret = ospi_read_access(dev, &cmd, data, size);
|
||||
|
||||
ospi_unlock_thread(dev);
|
||||
|
|
@ -1102,14 +1180,51 @@ static int setup_pages_layout(const struct device *dev)
|
|||
}
|
||||
#endif /* CONFIG_FLASH_PAGE_LAYOUT */
|
||||
|
||||
|
||||
static void spi_nor_process_bfp_addrbytes(const struct device *dev, const uint8_t jesd216_bfp_addrbytes) {
|
||||
struct flash_stm32_ospi_data *data = dev->data;
|
||||
|
||||
if (jesd216_bfp_addrbytes == JESD216_SFDP_BFP_DW1_ADDRBYTES_VAL_4B) {
|
||||
data->address_width = 4U;
|
||||
}
|
||||
|
||||
data->address_width = 3U;
|
||||
}
|
||||
|
||||
static inline uint8_t spi_nor_convert_read_to_4b(const uint8_t opcode)
|
||||
{
|
||||
switch (opcode) {
|
||||
case SPI_NOR_CMD_READ:
|
||||
return SPI_NOR_CMD_READ_4B;
|
||||
case SPI_NOR_CMD_DREAD:
|
||||
return SPI_NOR_CMD_DREAD_4B;
|
||||
case SPI_NOR_CMD_2READ:
|
||||
return SPI_NOR_CMD_2READ_4B;
|
||||
case SPI_NOR_CMD_QREAD:
|
||||
return SPI_NOR_CMD_QREAD_4B;
|
||||
case SPI_NOR_CMD_4READ:
|
||||
return SPI_NOR_CMD_4READ_4B;
|
||||
default:
|
||||
/* use provided */
|
||||
return opcode;
|
||||
}
|
||||
}
|
||||
|
||||
static int spi_nor_process_bfp(const struct device *dev,
|
||||
const struct jesd216_param_header *php,
|
||||
const struct jesd216_bfp *bfp)
|
||||
{
|
||||
const struct flash_stm32_ospi_config *dev_cfg = dev->config;
|
||||
struct flash_stm32_ospi_data *data = dev->data;
|
||||
/* must be kept in data mode order, ignore 1-1-1 (always supported) */
|
||||
const enum jesd216_mode_type supported_read_modes[] = { JESD216_MODE_112, JESD216_MODE_122,
|
||||
JESD216_MODE_114,
|
||||
JESD216_MODE_144 };
|
||||
size_t supported_read_modes_max_idx;
|
||||
struct jesd216_erase_type *etp = data->erase_types;
|
||||
size_t idx;
|
||||
const size_t flash_size = jesd216_bfp_density(bfp) / 8U;
|
||||
struct jesd216_instr read_instr = { 0 };
|
||||
|
||||
if (flash_size != dev_cfg->flash_size) {
|
||||
LOG_DBG("Unexpected flash size: %u", flash_size);
|
||||
|
|
@ -1121,18 +1236,63 @@ static int spi_nor_process_bfp(const struct device *dev,
|
|||
* Sector Map Parameter table references them by index.)
|
||||
*/
|
||||
memset(data->erase_types, 0, sizeof(data->erase_types));
|
||||
for (uint8_t ti = 1; ti <= ARRAY_SIZE(data->erase_types); ++ti) {
|
||||
if (jesd216_bfp_erase(bfp, ti, etp) == 0) {
|
||||
for (idx = 1U; idx <= ARRAY_SIZE(data->erase_types); ++idx) {
|
||||
if (jesd216_bfp_erase(bfp, idx, etp) == 0) {
|
||||
LOG_DBG("Erase %u with %02x",
|
||||
(uint32_t)BIT(etp->exp), etp->cmd);
|
||||
}
|
||||
++etp;
|
||||
}
|
||||
|
||||
spi_nor_process_bfp_addrbytes(dev, jesd216_bfp_addrbytes(bfp));
|
||||
LOG_DBG("Address width: %u Bytes", data->address_width);
|
||||
|
||||
if (dev_cfg->data_mode != OSPI_OPI_MODE) {
|
||||
/* determine supported read modes, begin from the slowest */
|
||||
data->read_mode = JESD216_MODE_111;
|
||||
data->read_opcode = SPI_NOR_CMD_READ;
|
||||
data->read_dummy = 0U;
|
||||
|
||||
if (dev_cfg->data_mode != OSPI_SPI_MODE) {
|
||||
if (dev_cfg->data_mode == OSPI_DUAL_MODE) {
|
||||
/* the index of JESD216_MODE_114 in supported_read_modes */
|
||||
supported_read_modes_max_idx = 2U;
|
||||
} else {
|
||||
supported_read_modes_max_idx = ARRAY_SIZE(supported_read_modes);
|
||||
}
|
||||
|
||||
for (idx = 0U; idx < supported_read_modes_max_idx; ++idx) {
|
||||
if (jesd216_bfp_read_support(php, bfp, supported_read_modes[idx],
|
||||
&read_instr) < 0) {
|
||||
/* not supported */
|
||||
continue;
|
||||
}
|
||||
|
||||
LOG_DBG("Supports read mode: %d, instr: 0x%X",
|
||||
supported_read_modes[idx], read_instr.instr);
|
||||
data->read_mode = supported_read_modes[idx];
|
||||
data->read_opcode = read_instr.instr;
|
||||
data->read_dummy =
|
||||
(read_instr.wait_states + read_instr.mode_clocks);
|
||||
}
|
||||
}
|
||||
|
||||
/* convert 3-Byte opcodes to 4-Byte (if required) */
|
||||
if (IS_ENABLED(DT_INST_PROP(0, four_byte_opcodes))) {
|
||||
if (data->address_width != 4U) {
|
||||
LOG_DBG("4-Byte opcodes require 4-Byte address width");
|
||||
return -ENOTSUP;
|
||||
}
|
||||
data->read_opcode = spi_nor_convert_read_to_4b(data->read_opcode);
|
||||
}
|
||||
}
|
||||
|
||||
data->page_size = jesd216_bfp_page_size(php, bfp);
|
||||
|
||||
LOG_DBG("Page size %u bytes", data->page_size);
|
||||
LOG_DBG("Flash size %u bytes", flash_size);
|
||||
LOG_DBG("Flash size %zu bytes", flash_size);
|
||||
LOG_DBG("Using read mode: %d, instr: 0x%X, dummy cycles: %u",
|
||||
data->read_mode, data->read_opcode, data->read_dummy);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1145,10 +1305,10 @@ static int flash_stm32_ospi_init(const struct device *dev)
|
|||
int ret;
|
||||
|
||||
/* The SPI/DTR is not a valid config of data_mode/data_rate according to the DTS */
|
||||
if ((dev_cfg->data_mode == OSPI_SPI_MODE)
|
||||
if ((dev_cfg->data_mode != OSPI_OPI_MODE)
|
||||
&& (dev_cfg->data_rate == OSPI_DTR_TRANSFER)) {
|
||||
/* already the right config, continue */
|
||||
LOG_ERR("OSPI mode SPI/DTR is not valid");
|
||||
LOG_ERR("OSPI mode SPI|DUAL|QUAD/DTR is not valid");
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue