drivers: spi: introduce new Telink B91 SPI driver
SPI driver basic support for Telink B91 SoC. Signed-off-by: Yuriy Vynnychek <yura.vynnychek@telink-semi.com>
This commit is contained in:
Yuriy Vynnychek
Christopher Friedt
parent
5d9d35dbb2
commit
87018c50cc
6 changed files with 499 additions and 0 deletions
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@ -327,6 +327,7 @@
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/drivers/net/ @rlubos @tbursztyka
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/drivers/ptp_clock/ @tbursztyka
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/drivers/spi/ @tbursztyka
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/drivers/spi/*b91* @yurvyn
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/drivers/spi/spi_rv32m1_lpspi* @karstenkoenig
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/drivers/timer/apic_timer.c @dcpleung @nashif
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/drivers/timer/apic_tsc.c @andyross
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@ -2,6 +2,7 @@
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zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_SPI_TELINK_B91 spi_b91.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_CC13XX_CC26XX spi_cc13xx_cc26xx.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_DW spi_dw.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_EMUL spi_emul.c)
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@ -41,6 +41,8 @@ module = SPI
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module-str = spi
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source "subsys/logging/Kconfig.template.log_config"
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source "drivers/spi/Kconfig.b91"
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source "drivers/spi/Kconfig.stm32"
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source "drivers/spi/Kconfig.dw"
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8
drivers/spi/Kconfig.b91
Normal file
8
drivers/spi/Kconfig.b91
Normal file
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@ -0,0 +1,8 @@
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# Copyright (c) 2021 Telink Semiconductor
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# SPDX-License-Identifier: Apache-2.0
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config SPI_TELINK_B91
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bool "Telink Semiconductor B91 SPI driver"
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depends on SOC_RISCV_TELINK_B91
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help
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Enables Telink B91 SPI driver.
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480
drivers/spi/spi_b91.c
Normal file
480
drivers/spi/spi_b91.c
Normal file
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@ -0,0 +1,480 @@
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/*
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* Copyright (c) 2021 Telink Semiconductor
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT telink_b91_spi
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/* Redefine 'spi_read' and 'spi_write' functions names from HAL */
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#define spi_read hal_spi_read
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#define spi_write hal_spi_write
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#include "spi.c"
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#undef spi_read
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#undef spi_write
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#include "clock.h"
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#include <logging/log.h>
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LOG_MODULE_REGISTER(spi_telink);
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#include <drivers/spi.h>
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#include "spi_context.h"
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#include <drivers/pinmux.h>
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#include <dt-bindings/pinctrl/b91-pinctrl.h>
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#define CHIP_SELECT_COUNT 3u
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#define SPI_WORD_SIZE 8u
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#define SPI_WR_RD_CHUNK_SIZE_MAX 16u
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/* SPI configuration structure */
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struct spi_b91_cfg {
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uint8_t peripheral_id;
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gpio_pin_e cs_pin[CHIP_SELECT_COUNT];
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const uint32_t *pinctrl_list;
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size_t pinctrl_list_size;
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};
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#define SPI_CFG(dev) ((struct spi_b91_cfg *) ((dev)->config))
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/* SPI data structure */
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struct spi_b91_data {
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struct spi_context ctx;
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};
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#define SPI_DATA(dev) ((struct spi_b91_data *) ((dev)->data))
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/* disable hardware cs flow control */
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static void spi_b91_hw_cs_disable(const struct spi_b91_cfg *config)
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{
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gpio_pin_e pin;
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/* loop through all cs pins (cs0..cs2) */
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for (int i = 0; i < CHIP_SELECT_COUNT; i++) {
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/* get CS pin defined in device tree */
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pin = config->cs_pin[i];
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/* if CS pin is defined in device tree */
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if (pin != 0) {
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if (config->peripheral_id == PSPI_MODULE) {
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/* disable CS pin for PSPI */
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pspi_cs_pin_dis(pin);
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} else {
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/* disable CS pin for MSPI */
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hspi_cs_pin_dis(pin);
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}
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}
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}
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}
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/* config cs flow control: hardware or software */
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static bool spi_b91_config_cs(const struct device *dev,
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const struct spi_config *config)
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{
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pspi_csn_pin_def_e cs_pin = 0;
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const struct spi_b91_cfg *b91_config = SPI_CFG(dev);
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/* software flow control */
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if (config->cs) {
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/* disable all hardware CS pins */
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spi_b91_hw_cs_disable(b91_config);
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return true;
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}
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/* hardware flow control */
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/* check for correct slave id */
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if (config->slave >= CHIP_SELECT_COUNT) {
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LOG_ERR("Slave %d not supported (max. %d)", config->slave, CHIP_SELECT_COUNT - 1);
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return false;
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}
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/* loop through all cs pins: cs0, cs1 and cs2 */
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for (int cs_id = 0; cs_id < CHIP_SELECT_COUNT; cs_id++) {
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/* get cs pin defined in device tree */
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cs_pin = b91_config->cs_pin[cs_id];
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/* if cs pin is not defined for the selected slave, return error */
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if ((cs_pin == 0) && (cs_id == config->slave)) {
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LOG_ERR("cs%d-pin is not defined in device tree", config->slave);
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return false;
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}
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/* disable cs pin if it is defined and is not requested */
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if ((cs_pin != 0) && (cs_id != config->slave)) {
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if (b91_config->peripheral_id == PSPI_MODULE) {
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pspi_cs_pin_dis(cs_pin);
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} else {
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hspi_cs_pin_dis(cs_pin);
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}
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}
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/* enable cs pin if it is defined and is requested */
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if ((cs_pin != 0) && (cs_id == config->slave)) {
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if (b91_config->peripheral_id == PSPI_MODULE) {
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pspi_set_pin_mux(cs_pin);
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pspi_cs_pin_en(cs_pin);
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} else {
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hspi_set_pin_mux(cs_pin);
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hspi_cs_pin_en(cs_pin);
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}
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}
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}
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return true;
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}
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/* get spi transaction length */
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static uint32_t spi_b91_get_txrx_len(const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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uint32_t len_tx = 0;
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uint32_t len_rx = 0;
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const struct spi_buf *tx_buf = tx_bufs->buffers;
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const struct spi_buf *rx_buf = rx_bufs->buffers;
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/* calculate tx len */
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for (int i = 0; i < tx_bufs->count; i++) {
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len_tx += tx_buf->len;
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tx_buf++;
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}
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/* calculate rx len */
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for (int i = 0; i < rx_bufs->count; i++) {
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len_rx += rx_buf->len;
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rx_buf++;
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}
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return MAX(len_tx, len_rx);
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}
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/* process tx data */
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_attribute_ram_code_sec_
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static void spi_b91_tx(uint8_t peripheral_id, struct spi_context *ctx, uint8_t len)
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{
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uint8_t tx;
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for (int i = 0; i < len; i++) {
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if (spi_context_tx_buf_on(ctx)) {
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tx = *(uint8_t *)(ctx->tx_buf);
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} else {
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tx = 0;
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}
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spi_context_update_tx(ctx, 1, 1);
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while (reg_spi_fifo_state(peripheral_id) & FLD_SPI_TXF_FULL) {
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};
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reg_spi_wr_rd_data(peripheral_id, i % 4) = tx;
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}
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}
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/* process rx data */
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_attribute_ram_code_sec_
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static void spi_b91_rx(uint8_t peripheral_id, struct spi_context *ctx, uint8_t len)
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{
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uint8_t rx = 0;
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for (int i = 0; i < len; i++) {
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while (reg_spi_fifo_state(peripheral_id) & FLD_SPI_RXF_EMPTY) {
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};
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rx = reg_spi_wr_rd_data(peripheral_id, i % 4);
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if (spi_context_rx_buf_on(ctx)) {
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*ctx->rx_buf = rx;
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}
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spi_context_update_rx(ctx, 1, 1);
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}
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}
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/* SPI transceive internal */
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_attribute_ram_code_sec_
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static void spi_b91_txrx(const struct device *dev, uint32_t len)
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{
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unsigned int chunk_size = SPI_WR_RD_CHUNK_SIZE_MAX;
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struct spi_b91_cfg *cfg = SPI_CFG(dev);
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struct spi_context *ctx = &SPI_DATA(dev)->ctx;
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/* prepare SPI module */
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spi_set_transmode(cfg->peripheral_id, SPI_MODE_WRITE_AND_READ);
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spi_set_cmd(cfg->peripheral_id, 0);
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spi_tx_cnt(cfg->peripheral_id, len);
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spi_rx_cnt(cfg->peripheral_id, len);
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/* write and read bytes in chunks */
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for (int i = 0; i < len; i = i + chunk_size) {
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/* check for tail */
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if (chunk_size > (len - i)) {
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chunk_size = len - i;
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}
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/* write bytes */
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spi_b91_tx(cfg->peripheral_id, ctx, chunk_size);
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/* read bytes */
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if (len <= SPI_WR_RD_CHUNK_SIZE_MAX) {
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/* read all bytes if len is less than chunk size */
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spi_b91_rx(cfg->peripheral_id, ctx, chunk_size);
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} else if (i == 0) {
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/* head, read 1 byte less than is sent */
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spi_b91_rx(cfg->peripheral_id, ctx, chunk_size - 1);
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} else if ((len - i) > SPI_WR_RD_CHUNK_SIZE_MAX) {
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/* body, read so many bytes as is sent*/
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spi_b91_rx(cfg->peripheral_id, ctx, chunk_size);
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} else {
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/* tail, read the rest bytes */
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spi_b91_rx(cfg->peripheral_id, ctx, chunk_size + 1);
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}
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/* clear TX and RX fifo */
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BM_SET(reg_spi_fifo_state(cfg->peripheral_id), FLD_SPI_TXF_CLR);
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BM_SET(reg_spi_fifo_state(cfg->peripheral_id), FLD_SPI_RXF_CLR);
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}
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/* wait fot SPI is ready */
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while (spi_is_busy(cfg->peripheral_id)) {
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};
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/* context complate */
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spi_context_complete(ctx, 0);
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}
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/* Check for supported configuration */
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static bool spi_b91_is_config_supported(const struct spi_config *config,
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struct spi_b91_cfg *b91_config)
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{
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/* check for loop back */
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if (config->operation & SPI_MODE_LOOP) {
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LOG_ERR("Loop back mode not supported");
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return false;
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}
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/* check for transfer LSB first */
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if (config->operation & SPI_TRANSFER_LSB) {
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LOG_ERR("LSB first not supported");
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return false;
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}
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/* check word size */
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if (SPI_WORD_SIZE_GET(config->operation) != SPI_WORD_SIZE) {
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LOG_ERR("Word size must be %d", SPI_WORD_SIZE);
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return false;
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}
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/* check for CS active hich */
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if (config->operation & SPI_CS_ACTIVE_HIGH) {
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LOG_ERR("CS active high not supported for HW flow control");
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return false;
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}
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/* check for lines configuration */
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if ((config->operation & SPI_LINES_MASK) == SPI_LINES_OCTAL) {
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LOG_ERR("SPI lines Octal configuration is not supported");
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return false;
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} else if (((config->operation & SPI_LINES_MASK) == SPI_LINES_QUAD) &&
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(b91_config->peripheral_id == PSPI_MODULE)) {
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LOG_ERR("SPI lines Quad configuration is not supported by PSPI");
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return false;
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}
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/* check for slave configuration */
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if (SPI_OP_MODE_GET(config->operation) == SPI_OP_MODE_SLAVE) {
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LOG_ERR("SPI Slave is not implemented");
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return -ENOTSUP;
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}
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return true;
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}
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/* SPI configuration */
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static int spi_b91_config(const struct device *dev,
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const struct spi_config *config)
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{
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const struct device *pinmux;
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spi_mode_type_e mode = SPI_MODE0;
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struct spi_b91_cfg *b91_config = SPI_CFG(dev);
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struct spi_b91_data *b91_data = SPI_DATA(dev);
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uint8_t clk_src = b91_config->peripheral_id == PSPI_MODULE ? sys_clk.pclk : sys_clk.hclk;
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/* check for unsupported configuration */
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if (!spi_b91_is_config_supported(config, b91_config)) {
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return -ENOTSUP;
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}
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/* config slave selection (CS): hw or sw */
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if (!spi_b91_config_cs(dev, config)) {
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return -ENOTSUP;
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}
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/* get SPI mode */
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if (((config->operation & SPI_MODE_CPHA) == 0) &&
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((config->operation & SPI_MODE_CPOL) == 0)) {
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mode = SPI_MODE0;
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} else if (((config->operation & SPI_MODE_CPHA) == 0) &&
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((config->operation & SPI_MODE_CPOL) == SPI_MODE_CPOL)) {
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mode = SPI_MODE1;
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} else if (((config->operation & SPI_MODE_CPHA) == SPI_MODE_CPHA) &&
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((config->operation & SPI_MODE_CPOL) == 0)) {
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mode = SPI_MODE2;
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} else if (((config->operation & SPI_MODE_CPHA) == SPI_MODE_CPHA) &&
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((config->operation & SPI_MODE_CPOL) == SPI_MODE_CPOL)) {
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mode = SPI_MODE3;
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}
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/* init SPI master */
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spi_master_init(b91_config->peripheral_id,
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clk_src * 1000000 / (2 * config->frequency) - 1, mode);
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spi_master_config(b91_config->peripheral_id, SPI_NOMAL);
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/* set lines configuration */
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if ((config->operation & SPI_LINES_MASK) == SPI_LINES_SINGLE) {
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spi_set_io_mode(b91_config->peripheral_id, SPI_SINGLE_MODE);
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} else if ((config->operation & SPI_LINES_MASK) == SPI_LINES_DUAL) {
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spi_set_io_mode(b91_config->peripheral_id, SPI_DUAL_MODE);
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} else if ((config->operation & SPI_LINES_MASK) == SPI_LINES_QUAD) {
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spi_set_io_mode(b91_config->peripheral_id, HSPI_QUAD_MODE);
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}
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/* get pinmux driver */
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pinmux = DEVICE_DT_GET(DT_NODELABEL(pinmux));
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if (!device_is_ready(pinmux)) {
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return -ENODEV;
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}
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/* config pins */
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for (int i = 0; i < b91_config->pinctrl_list_size; i++) {
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pinmux_pin_set(pinmux, B91_PINMUX_GET_PIN(b91_config->pinctrl_list[i]),
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B91_PINMUX_GET_FUNC(b91_config->pinctrl_list[i]));
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}
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/* save context config */
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b91_data->ctx.config = config;
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/* config software CS control if enabled */
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if (config->cs != NULL) {
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spi_context_cs_configure(&b91_data->ctx);
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}
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return 0;
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}
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/* API implementation: init */
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static int spi_b91_init(const struct device *dev)
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{
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struct spi_b91_data *data = SPI_DATA(dev);
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spi_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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/* API implementation: transceive */
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static int spi_b91_transceive(const struct device *dev,
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const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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int status = 0;
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struct spi_b91_data *data = SPI_DATA(dev);
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uint32_t txrx_len = spi_b91_get_txrx_len(tx_bufs, rx_bufs);
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/* set configuration */
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status = spi_b91_config(dev, config);
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if (status) {
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return status;
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}
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/* context setup */
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spi_context_lock(&data->ctx, false, NULL, config);
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spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
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/* if cs is defined: software cs control, set active true */
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if (config->cs) {
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spi_context_cs_control(&data->ctx, true);
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}
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/* transceive data */
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spi_b91_txrx(dev, txrx_len);
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/* if cs is defined: software cs control, set active false */
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if (config->cs) {
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spi_context_cs_control(&data->ctx, false);
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}
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/* release context */
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status = spi_context_wait_for_completion(&data->ctx);
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spi_context_release(&data->ctx, status);
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return status;
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}
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#ifdef CONFIG_SPI_ASYNC
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/* API implementation: transceive_async */
|
||||
static int spi_b91_transceive_async(const struct device *dev,
|
||||
const struct spi_config *config,
|
||||
const struct spi_buf_set *tx_bufs,
|
||||
const struct spi_buf_set *rx_bufs,
|
||||
struct k_poll_signal *async)
|
||||
{
|
||||
ARG_UNUSED(dev);
|
||||
ARG_UNUSED(config);
|
||||
ARG_UNUSED(tx_bufs);
|
||||
ARG_UNUSED(rx_bufs);
|
||||
ARG_UNUSED(async);
|
||||
|
||||
return -ENOTSUP;
|
||||
}
|
||||
#endif /* CONFIG_SPI_ASYNC */
|
||||
|
||||
/* API implementation: release */
|
||||
static int spi_b91_release(const struct device *dev,
|
||||
const struct spi_config *config)
|
||||
{
|
||||
struct spi_b91_data *data = SPI_DATA(dev);
|
||||
|
||||
if (!spi_context_configured(&data->ctx, config)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
spi_context_unlock_unconditionally(&data->ctx);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* SPI driver APIs structure */
|
||||
static struct spi_driver_api spi_b91_api = {
|
||||
.transceive = spi_b91_transceive,
|
||||
.release = spi_b91_release,
|
||||
#ifdef CONFIG_SPI_ASYNC
|
||||
.transceive_async = spi_b91_transceive_async,
|
||||
#endif /* CONFIG_SPI_ASYNC */
|
||||
};
|
||||
|
||||
/* SPI driver registration */
|
||||
#define SPI_B91_INIT(inst) \
|
||||
\
|
||||
static const uint32_t spi_pins_##inst[] = \
|
||||
B91_PINMUX_DT_INST_GET_ARRAY(inst, 0); \
|
||||
\
|
||||
static struct spi_b91_data spi_b91_data_##inst = { \
|
||||
SPI_CONTEXT_INIT_LOCK(spi_b91_data_##inst, ctx), \
|
||||
SPI_CONTEXT_INIT_SYNC(spi_b91_data_##inst, ctx), \
|
||||
}; \
|
||||
\
|
||||
static struct spi_b91_cfg spi_b91_cfg_##inst = { \
|
||||
.peripheral_id = DT_ENUM_IDX(DT_DRV_INST(inst), peripheral_id), \
|
||||
.cs_pin[0] = DT_STRING_TOKEN(DT_DRV_INST(inst), cs0_pin), \
|
||||
.cs_pin[1] = DT_STRING_TOKEN(DT_DRV_INST(inst), cs1_pin), \
|
||||
.cs_pin[2] = DT_STRING_TOKEN(DT_DRV_INST(inst), cs2_pin), \
|
||||
.pinctrl_list_size = ARRAY_SIZE(spi_pins_##inst), \
|
||||
.pinctrl_list = spi_pins_##inst \
|
||||
}; \
|
||||
\
|
||||
DEVICE_DT_INST_DEFINE(inst, spi_b91_init, \
|
||||
NULL, \
|
||||
&spi_b91_data_##inst, \
|
||||
&spi_b91_cfg_##inst, \
|
||||
POST_KERNEL, \
|
||||
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
|
||||
&spi_b91_api);
|
||||
|
||||
DT_INST_FOREACH_STATUS_OKAY(SPI_B91_INIT)
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
#
|
||||
# Copyright (c) 2021 Telink Semiconductor
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
CONFIG_SPI_LOOPBACK_DRV_NAME="PSPI"
|
||||
Loading…
Add table
Add a link
Reference in a new issue