From 86f1bdc0690d860b11eeae505307b693bfc3d541 Mon Sep 17 00:00:00 2001
From: Jingru Wang <jingru@synopsys.com>
Date: Thu, 26 Aug 2021 14:50:56 +0800
Subject: [PATCH] ARC: add config files for nsim_sem_mpu_stack_guard

Add nsim_sem_mpu_stack_guard.props and
nsim_sem_mpu_stack_guard.args, so we don't
do workarounds in cmake code.

Signed-off-by: Jingru Wang <jingru@synopsys.com>
---
 boards/arc/nsim/board.cmake                   |  2 +-
 .../support/nsim_sem_mpu_stack_guard.args     | 54 +++++++++++++++++
 .../support/nsim_sem_mpu_stack_guard.props    | 58 +++++++++++++++++++
 3 files changed, 113 insertions(+), 1 deletion(-)
 create mode 100644 boards/arc/nsim/support/nsim_sem_mpu_stack_guard.args
 create mode 100644 boards/arc/nsim/support/nsim_sem_mpu_stack_guard.props

diff --git a/boards/arc/nsim/board.cmake b/boards/arc/nsim/board.cmake
index a205b7460ce..a7e8d1ac4b3 100644
--- a/boards/arc/nsim/board.cmake
+++ b/boards/arc/nsim/board.cmake
@@ -5,8 +5,8 @@ if(NOT (CONFIG_SOC_NSIM_HS_SMP OR CONFIG_SOC_NSIM_HS6X_SMP))
   board_set_flasher_ifnset(arc-nsim)
   board_set_debugger_ifnset(arc-nsim)
 
-  board_runner_args(arc-nsim "--props=${BOARD}.props")
   set(NSIM_PROPS "${BOARD}.props")
+  board_runner_args(arc-nsim "--props=${NSIM_PROPS}")
 endif()
 
 string(REPLACE "nsim" "mdb" MDB_ARGS "${BOARD}.args")
diff --git a/boards/arc/nsim/support/nsim_sem_mpu_stack_guard.args b/boards/arc/nsim/support/nsim_sem_mpu_stack_guard.args
new file mode 100644
index 00000000000..eff65ee8170
--- /dev/null
+++ b/boards/arc/nsim/support/nsim_sem_mpu_stack_guard.args
@@ -0,0 +1,54 @@
+	-arcv2em
+	-core3
+	-rgf_num_banks=1
+	-rgf_num_wr_ports=1
+	-Xcode_density
+	-Xdiv_rem=radix2
+	-turbo_boost
+	-Xswap
+	-Xbitscan
+	-Xmpy_option=mpyd
+	-Xshift_assist
+	-Xbarrel_shifter
+	-Xdsp2
+	-Xdsp_complex
+	-Xdsp_divsqrt=radix2
+	-Xdsp_accshift=limited
+	-Xtimer0
+	-Xtimer0_level=1
+	-Xtimer1
+	-Xtimer1_level=0
+	-Xsec_timer0
+	-Xsec_timer0_level=1
+	-action_points=2
+	-Xstack_check
+	-smart_stack_entries=8
+	-mpuv4
+	-mpu_sid
+	-mpu_regions=16
+	-interrupts=22
+	-interrupt_priorities=4
+	-ext_interrupts=17
+	-interrupt_base=0x0
+	-sec_interrupt_base=0x0
+	-dcache=16384,32,2,a
+	-dcache_feature=2
+	-icache=16384,32,2,a
+	-icache_feature=2
+	-dccm_size=0x80000
+	-dccm_base=0x80000000
+	-dccm_interleave
+	-iccm0_size=0x80000
+	-iccm0_base=0x00000000
+	-esp_encrypt
+	-Xsec_modes
+	-iccm0_sec_lvl=NS
+	-dccm_sec_lvl=NS
+	-Xpct_counters=8
+	-dmac
+	-dmac_channels=2
+	-dmac_registers=0
+	-dmac_fifo_depth=2
+	-dmac_int_config=single_internal
+	-prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
+	-noprofile
diff --git a/boards/arc/nsim/support/nsim_sem_mpu_stack_guard.props b/boards/arc/nsim/support/nsim_sem_mpu_stack_guard.props
new file mode 100644
index 00000000000..857168a9ea8
--- /dev/null
+++ b/boards/arc/nsim/support/nsim_sem_mpu_stack_guard.props
@@ -0,0 +1,58 @@
+	nsim_isa_family=av2em
+	nsim_isa_core=3
+	arcver=0x43
+	nsim_isa_rgf_num_banks=1
+	nsim_isa_rgf_num_regs=32
+	nsim_isa_rgf_num_wr_ports=1
+	nsim_isa_big_endian=0
+	nsim_isa_lpc_size=32
+	nsim_isa_pc_size=32
+	nsim_isa_addr_size=32
+	nsim_isa_code_density_option=2
+	nsim_isa_div_rem_option=1
+	nsim_isa_turbo_boost=1
+	nsim_isa_swap_option=1
+	nsim_isa_bitscan_option=1
+	nsim_isa_mpy_option=8
+	nsim_isa_shift_option=3
+	nsim_isa_dsp_option=2
+	nsim_isa_dsp_complex_option=1
+	nsim_isa_dsp_divsqrt_option=1
+	nsim_isa_dsp_accshift_option=1
+	nsim_isa_enable_timer_0=1
+	nsim_isa_timer_0_int_level=1
+	nsim_isa_enable_timer_1=1
+	nsim_isa_timer_1_int_level=0
+	nsim_isa_enable_sec_timer_0=1
+	nsim_isa_stimer_0_int_level=1
+	nsim_isa_num_actionpoints=2
+	nsim_isa_stack_checking=1
+	nsim_isa_smart_stack_entries=8
+	mpu_sid_option=1
+	mpu_regions=16
+	mpu_version=4
+	nsim_isa_number_of_interrupts=22
+	nsim_isa_number_of_levels=4
+	nsim_isa_number_of_external_interrupts=17
+	nsim_isa_intvbase_preset=0x0
+	nsim_isa_intvbase_preset_s=0x0
+	dcache=16384,32,2,a
+	nsim_isa_dc_feature_level=2
+	icache=16384,32,2,a
+	nsim_isa_ic_feature_level=2
+	dccm_size=0x80000
+	dccm_base=0x80000000
+	nsim_isa_dccm_interleave=1
+	iccm0_size=0x80000
+	iccm0_base=0x00000000
+	nsim_isa_has_secure=1
+	nsim_isa_sec_modes_option=1
+	iccm0_sec_lvl=NS
+	dccm_sec_lvl=NS
+	nsim_isa_pct_counters=8
+	nsim_isa_dmac_option=1
+	nsim_isa_dmac_channels=2
+	nsim_isa_dmac_registers=0
+	nsim_isa_dmac_fifo_depth=2
+	nsim_isa_dmac_int_config=single_internal
+	nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24