diff --git a/dts/arm/st/f1/stm32f103Xe.dtsi b/dts/arm/st/f1/stm32f103Xe.dtsi
index 30974433e19..5fd6efdc218 100644
--- a/dts/arm/st/f1/stm32f103Xe.dtsi
+++ b/dts/arm/st/f1/stm32f103Xe.dtsi
@@ -98,6 +98,15 @@
 				clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000081>;
 				label = "GPIOF";
 			};
+
+			gpiog: gpio@40012000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40012000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000101>;
+				label = "GPIOG";
+			};
 		};
 
 		timers8: timers@40013400 {
diff --git a/soc/arm/st_stm32/stm32f1/dts_fixup.h b/soc/arm/st_stm32/stm32f1/dts_fixup.h
index f3e6e653175..53b65f8055f 100644
--- a/soc/arm/st_stm32/stm32f1/dts_fixup.h
+++ b/soc/arm/st_stm32/stm32f1/dts_fixup.h
@@ -56,6 +56,15 @@
 #define CONFIG_GPIO_STM32_GPIOF_CLOCK_BITS		ST_STM32_GPIO_40011C00_CLOCK_BITS
 #define CONFIG_GPIO_STM32_GPIOF_CLOCK_BUS		ST_STM32_GPIO_40011C00_CLOCK_BUS
 
+#define CONFIG_GPIO_STM32_GPIOG_BASE_ADDRESS		ST_STM32_GPIO_40012000_BASE_ADDRESS
+#define CONFIG_GPIO_STM32_GPIOG_CLOCK_BITS_0		ST_STM32_GPIO_40012000_CLOCK_BITS_0
+#define CONFIG_GPIO_STM32_GPIOG_CLOCK_BUS_0		ST_STM32_GPIO_40012000_CLOCK_BUS_0
+#define CONFIG_GPIO_STM32_GPIOG_CLOCK_CONTROLLER	ST_STM32_GPIO_40012000_CLOCK_CONTROLLER
+#define CONFIG_GPIO_STM32_GPIOG_LABEL			ST_STM32_GPIO_40012000_LABEL
+#define CONFIG_GPIO_STM32_GPIOG_SIZE			ST_STM32_GPIO_40012000_SIZE
+#define CONFIG_GPIO_STM32_GPIOG_CLOCK_BITS		ST_STM32_GPIO_40012000_CLOCK_BITS
+#define CONFIG_GPIO_STM32_GPIOG_CLOCK_BUS		ST_STM32_GPIO_40012000_CLOCK_BUS
+
 #define CONFIG_UART_STM32_USART_1_BASE_ADDRESS   ST_STM32_USART_40013800_BASE_ADDRESS
 #define CONFIG_UART_STM32_USART_1_BAUD_RATE      ST_STM32_USART_40013800_CURRENT_SPEED
 #define CONFIG_UART_STM32_USART_1_IRQ_PRI        ST_STM32_USART_40013800_IRQ_0_PRIORITY