diff --git a/arch/arm/soc/nxp_kinetis/Kconfig b/arch/arm/soc/nxp_kinetis/Kconfig index f925424b5c8..d08870f84d5 100644 --- a/arch/arm/soc/nxp_kinetis/Kconfig +++ b/arch/arm/soc/nxp_kinetis/Kconfig @@ -21,6 +21,7 @@ source "arch/arm/soc/nxp_kinetis/*/Kconfig.soc" config SOC_PART_NUMBER string default SOC_PART_NUMBER_KINETIS_K6X if SOC_SERIES_KINETIS_K6X + default SOC_PART_NUMBER_KINETIS_KWX if SOC_SERIES_KINETIS_KWX help This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines @@ -108,4 +109,13 @@ config MCG_FCRDIV Selects the amount to divide down the fast internal reference clock. The resulting frequency must be in the range 31.25 kHz to 4 MHz. +config MCG_FRDIV + int "FLL external reference divider" + range 0 7 + default 0 + help + Selects the amount to divide down the external reference clock for the + FLL. The resulting frequency must be in the range 31.25 kHz to 39.0625 + kHz. + endif # HAS_MCG diff --git a/arch/arm/soc/nxp_kinetis/kwx/Kconfig.defconfig.mkw41z4 b/arch/arm/soc/nxp_kinetis/kwx/Kconfig.defconfig.mkw41z4 new file mode 100644 index 00000000000..3a46d67cbaa --- /dev/null +++ b/arch/arm/soc/nxp_kinetis/kwx/Kconfig.defconfig.mkw41z4 @@ -0,0 +1,57 @@ +# Kconfig - Kinetis KWx SoC configuration options +# +# Copyright (c) 2017, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_MKW41Z4 + +config SOC + string + default mkw41z4 + +config NUM_IRQ_PRIO_BITS + int + default 2 + +config NUM_IRQS + int + default 32 + +if PINMUX + +config PINMUX_MCUX + def_bool y + +endif # PINMUX + +if GPIO + +config GPIO_MCUX + def_bool y + +endif # GPIO + +if SERIAL + +config UART_MCUX_LPUART + def_bool y + +endif # SERIAL + +if I2C + +config I2C_MCUX + def_bool y + +endif # I2C + +if FLASH + +config SOC_FLASH_MCUX + def_bool y + +endif # FLASH + +endif # SOC_MKW41Z4 diff --git a/arch/arm/soc/nxp_kinetis/kwx/Kconfig.defconfig.series b/arch/arm/soc/nxp_kinetis/kwx/Kconfig.defconfig.series new file mode 100644 index 00000000000..139ef437339 --- /dev/null +++ b/arch/arm/soc/nxp_kinetis/kwx/Kconfig.defconfig.series @@ -0,0 +1,21 @@ +# Kconfig - Kinetis KWx series configuration options +# +# Copyright (c) 2017, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_SERIES_KINETIS_KWX + +config SOC_SERIES + default kwx + +config SRAM_BASE_ADDRESS + default 0x20000000 + +config FLASH_BASE_ADDRESS + default 0x00000000 + +source "arch/arm/soc/nxp_kinetis/kwx/Kconfig.defconfig.mk*" + +endif # SOC_SERIES_KINETIS_KWX diff --git a/arch/arm/soc/nxp_kinetis/kwx/Kconfig.series b/arch/arm/soc/nxp_kinetis/kwx/Kconfig.series new file mode 100644 index 00000000000..df9fc11ca16 --- /dev/null +++ b/arch/arm/soc/nxp_kinetis/kwx/Kconfig.series @@ -0,0 +1,15 @@ +# Kconfig - Kinetis KWx MCU series +# +# Copyright (c) 2017, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_SERIES_KINETIS_KWX + bool "Kinetis KWx Series MCU" + select CPU_CORTEX_M + select SOC_FAMILY_KINETIS + select SYS_POWER_LOW_POWER_STATE_SUPPORTED + select CPU_HAS_SYSTICK + help + Enable support for Kinetis KWx MCU series diff --git a/arch/arm/soc/nxp_kinetis/kwx/Kconfig.soc b/arch/arm/soc/nxp_kinetis/kwx/Kconfig.soc new file mode 100644 index 00000000000..65dc76b5781 --- /dev/null +++ b/arch/arm/soc/nxp_kinetis/kwx/Kconfig.soc @@ -0,0 +1,39 @@ +# Kconfig - Kinetis KWx MCU series +# +# Copyright (c) 2017, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +choice +prompt "Kinetis KWx MCU Selection" +depends on SOC_SERIES_KINETIS_KWX + +config SOC_MKW41Z4 + bool "SOC_MKW41Z4" + select CPU_CORTEX_M0PLUS + select HAS_MCUX + select HAS_OSC + select HAS_MCG + select HAS_LPUART + +endchoice + +if SOC_SERIES_KINETIS_KWX + +config SOC_PART_NUMBER_MKW41Z256VHT4 + bool + +config SOC_PART_NUMBER_MKW41Z512VHT4 + bool + +config SOC_PART_NUMBER_KINETIS_KWX + string + default "MKW41Z256VHT4" if SOC_PART_NUMBER_MKW41Z256VHT4 + default "MKW41Z512VHT4" if SOC_PART_NUMBER_MKW41Z512VHT4 + help + This string holds the full part number of the SoC. It is a hidden option + that you should not set directly. The part number selection choice defines + the default value for this string. + +endif # SOC_SERIES_KINETIS_KWX diff --git a/arch/arm/soc/nxp_kinetis/kwx/Makefile b/arch/arm/soc/nxp_kinetis/kwx/Makefile new file mode 100644 index 00000000000..835c14e24ef --- /dev/null +++ b/arch/arm/soc/nxp_kinetis/kwx/Makefile @@ -0,0 +1,8 @@ +# Makefile - Kinetis KWx MCU series +# +# Copyright (c) 2017, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +obj-y += soc.o diff --git a/arch/arm/soc/nxp_kinetis/kwx/linker.ld b/arch/arm/soc/nxp_kinetis/kwx/linker.ld new file mode 100644 index 00000000000..383c0ab830d --- /dev/null +++ b/arch/arm/soc/nxp_kinetis/kwx/linker.ld @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2014 Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Linker command/script file + * + * This is the linker script for both standard images and XIP images. + */ + +#include + +/* + * KW41Z Flash configuration fields + * These are 16 bytes, which must be loaded to address 0x400, and include + * default protection and security settings. + * They are loaded at reset to various Flash Memory module (FTFE) registers. + */ + +/* + * No need to account for this when running a RAM-only image since that + * security feature resides in ROM. + */ +#if defined(CONFIG_XIP) + #define SKIP_TO_KINETIS_FLASH_CONFIG . = 0x400; +#endif + +#include diff --git a/arch/arm/soc/nxp_kinetis/kwx/soc.c b/arch/arm/soc/nxp_kinetis/kwx/soc.c new file mode 100644 index 00000000000..2467e4a3dbf --- /dev/null +++ b/arch/arm/soc/nxp_kinetis/kwx/soc.c @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2017, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ER32KSEL_OSC32KCLK (0) +#define ER32KSEL_RTC (2) +#define ER32KSEL_LPO1KHZ (3) + +#define LPUART0SRC_OSCERCLK (1) + +#define CLKDIV1_DIVBY2 (1) + +/* + * KW41Z Flash configuration fields + * These 16 bytes, which must be loaded to address 0x400, include default + * protection and security settings. + * They are loaded at reset to various Flash Memory module (FTFE) registers. + * + * The structure is: + * -Backdoor Comparison Key for unsecuring the MCU - 8 bytes + * -Program flash protection bytes, 4 bytes, written to FPROT0-3 + * -Flash security byte, 1 byte, written to FSEC + * -Flash nonvolatile option byte, 1 byte, written to FOPT + * -Reserved, 1 byte, (Data flash protection byte for FlexNVM) + * -Reserved, 1 byte, (EEPROM protection byte for FlexNVM) + * + */ +uint8_t __kinetis_flash_config_section __kinetis_flash_config[] = { + /* Backdoor Comparison Key (unused) */ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + /* Program flash protection; 1 bit/region - 0=protected, 1=unprotected + */ + 0xFF, 0xFF, 0xFF, 0xFF, + /* + * Flash security: Backdoor key disabled, Mass erase enabled, + * Factory access enabled, MCU is unsecure + */ + 0xFE, + /* Flash nonvolatile option: NMI enabled, EzPort enabled, Normal boot */ + 0xFF, + /* Reserved for FlexNVM feature (unsupported by this MCU) */ + 0xFF, 0xFF}; + +static const osc_config_t oscConfig = { + .freq = CONFIG_OSC_XTAL0_FREQ, + +#if defined(CONFIG_OSC_EXTERNAL) + .workMode = kOSC_ModeExt, +#elif defined(CONFIG_OSC_LOW_POWER) + .workMode = kOSC_ModeOscLowPower, +#elif defined(CONFIG_OSC_HIGH_GAIN) + .workMode = kOSC_ModeOscHighGain, +#else +#error "An oscillator mode must be defined" +#endif +}; + +static const sim_clock_config_t simConfig = { + .er32kSrc = ER32KSEL_OSC32KCLK, + .clkdiv1 = SIM_CLKDIV1_OUTDIV4(CLKDIV1_DIVBY2), +}; + +/* This function comes from the MCUX SDK: + * ext/hal/nxp/mcux/devices/MKW41Z4/clock_config.c + */ +static void CLOCK_SYS_FllStableDelay(void) +{ + uint32_t i = 30000U; + while (i--) { + __NOP(); + } +} + +static ALWAYS_INLINE void clkInit(void) +{ + CLOCK_SetSimSafeDivs(); + + CLOCK_InitOsc0(&oscConfig); + CLOCK_SetXtal0Freq(CONFIG_OSC_XTAL0_FREQ); + + CLOCK_BootToFeeMode(kMCG_OscselOsc, CONFIG_MCG_FRDIV, kMCG_Dmx32Default, + kMCG_DrsMid, CLOCK_SYS_FllStableDelay); + + CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, + CONFIG_MCG_FCRDIV); + + CLOCK_SetSimConfig(&simConfig); + +#if CONFIG_UART_MCUX_LPUART_0 + CLOCK_SetLpuartClock(LPUART0SRC_OSCERCLK); +#endif +} + +static int kwx_init(struct device *arg) +{ + ARG_UNUSED(arg); + + int oldLevel; /* old interrupt lock level */ + + /* disable interrupts */ + oldLevel = irq_lock(); + + /* Disable the watchdog */ + SIM->COPC = 0; + + /* Initialize system clock to 40 MHz */ + clkInit(); + + /* + * install default handler that simply resets the CPU + * if configured in the kernel, NOP otherwise + */ + NMI_INIT(); + + /* restore interrupt state */ + irq_unlock(oldLevel); + return 0; +} + +SYS_INIT(kwx_init, PRE_KERNEL_1, 0); diff --git a/arch/arm/soc/nxp_kinetis/kwx/soc.h b/arch/arm/soc/nxp_kinetis/kwx/soc.h new file mode 100644 index 00000000000..37b34122034 --- /dev/null +++ b/arch/arm/soc/nxp_kinetis/kwx/soc.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2017, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC__H_ +#define _SOC__H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define LPUART0_CLK_SRC kCLOCK_CoreSysClk + +/* IRQs */ + +#define IRQ_DMA_CHAN0 0 +#define IRQ_DMA_CHAN1 1 +#define IRQ_DMA_CHAN2 2 +#define IRQ_DMA_CHAN3 3 +#define IRQ_RESERVED0 4 +#define IRQ_FTFA 5 +#define IRQ_LOW_VOLTAGE 6 +#define IRQ_LOW_LEAKAGE 7 +#define IRQ_I2C0 8 +#define IRQ_I2C1 9 +#define IRQ_SPI0 10 +#define IRQ_TSI0 11 +#define IRQ_LPUART0 12 +#define IRQ_TRNG0 13 +#define IRQ_CMT 14 +#define IRQ_ADC0 15 +#define IRQ_CMP0 16 +#define IRQ_TPM0 17 +#define IRQ_TPM1 18 +#define IRQ_TPM2 19 +#define IRQ_RTC_ALARM 20 +#define IRQ_RTC_SEC 21 +#define IRQ_PIT 22 +#define IRQ_LTC0 23 +#define IRQ_RADIO0 24 +#define IRQ_DAC0 25 +#define IRQ_RADIO1 26 +#define IRQ_MCG 27 +#define IRQ_LPTMR0 28 +#define IRQ_SPI1 29 +#define IRQ_GPIO_PORTA 30 +#define IRQ_GPIO_PORTB 31 +#define IRQ_GPIO_PORTC 31 + +#ifndef _ASMLANGUAGE + +#include +#include +#include + +#endif /* !_ASMLANGUAGE */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC__H_ */