drivers: wdog: add Realtek RTS5912 wdog driver
Port Realtek RTS5912 wdog driver to Zephyr. Signed-off-by: Titan Chen <titan.chen@realtek.com>
This commit is contained in:
Titan Chen
Benjamin Cabé
parent
074215a30f
commit
865b8aa91d
7 changed files with 324 additions and 0 deletions
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@ -31,6 +31,7 @@ zephyr_library_sources_ifdef(CONFIG_WDT_NPM2100 wdt_npm2100.c)
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zephyr_library_sources_ifdef(CONFIG_WDT_NPM6001 wdt_npm6001.c)
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zephyr_library_sources_ifdef(CONFIG_WDT_NRFX wdt_nrfx.c)
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zephyr_library_sources_ifdef(CONFIG_WDT_RPI_PICO wdt_rpi_pico.c)
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zephyr_library_sources_ifdef(CONFIG_WDT_RTS5912 wdt_rts5912.c)
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zephyr_library_sources_ifdef(CONFIG_WDT_SAM wdt_sam.c)
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zephyr_library_sources_ifdef(CONFIG_WDT_SAM4L wdt_sam4l.c)
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zephyr_library_sources_ifdef(CONFIG_WDT_SAM0 wdt_sam0.c)
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@ -143,4 +143,6 @@ source "drivers/watchdog/Kconfig.ene"
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source "drivers/watchdog/Kconfig.litex"
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source "drivers/watchdog/Kconfig.rts5912"
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endif # WATCHDOG
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11
drivers/watchdog/Kconfig.rts5912
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11
drivers/watchdog/Kconfig.rts5912
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@ -0,0 +1,11 @@
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# Copyright (c) 2025, Realtek, SIBG-SD7
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# SPDX-License-Identifier: Apache-2.0
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config WDT_RTS5912
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bool "Realtek RTS5912 Embedded Controller Watchdog Driver"
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default y
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depends on DT_HAS_REALTEK_RTS5912_WATCHDOG_ENABLED
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select HAS_WDT_DISABLE_AT_BOOT
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help
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This option enables the WDT driver for Realtek RTS5912 family of
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processors.
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247
drivers/watchdog/wdt_rts5912.c
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247
drivers/watchdog/wdt_rts5912.c
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@ -0,0 +1,247 @@
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/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (c) 2025 Realtek Semiconductor Corporation, SIBG-SD7, Dylan Hsieh
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*/
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#define DT_DRV_COMPAT realtek_rts5912_watchdog
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#include <soc.h>
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#include <errno.h>
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/watchdog.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/clock_control_rts5912.h>
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#include <zephyr/irq.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(wdt_rts5912, CONFIG_WDT_LOG_LEVEL);
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#include "reg/reg_wdt.h"
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#define WDT_MAX_CNT 256
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#define WDT_CLK_CYCLE 32768UL
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BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, "multiple instances not supported");
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struct wdt_rts5912_config {
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uint32_t base;
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uint32_t div;
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const struct device *clk_dev;
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uint32_t clk_grp;
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uint32_t clk_idx;
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};
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struct wdt_rts5912_data {
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wdt_callback_t callback;
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bool timeout_installed;
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uint32_t timeout;
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};
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static void wdt_rts5912_isr(const struct device *dev)
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{
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const struct wdt_rts5912_config *const cfg = dev->config;
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struct wdt_rts5912_data *data = dev->data;
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WDT_Type *wdt_reg = (WDT_Type *)cfg->base;
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LOG_DBG("WDT ISR");
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wdt_reg->CTRL |= WDT_CTRL_CLRRSTFLAG;
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if (data->callback) {
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data->callback(dev, 0);
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}
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}
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static int wdt_rts5912_setup(const struct device *dev, uint8_t options)
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{
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const struct wdt_rts5912_config *const config = dev->config;
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struct wdt_rts5912_data *data = dev->data;
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WDT_Type *wdt_reg = (WDT_Type *)config->base;
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if (!data->timeout_installed) {
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LOG_ERR("No valid WDT timeout installed");
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return -EINVAL;
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}
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if (wdt_reg->CTRL & WDT_CTRL_EN) {
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LOG_ERR("WDT is already running");
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return -EBUSY;
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}
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if (options & WDT_OPT_PAUSE_IN_SLEEP) {
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LOG_ERR("WDT_OPT_PAUSE_IN_SLEEP is not supported");
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return -ENOTSUP;
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}
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if (options & WDT_OPT_PAUSE_HALTED_BY_DBG) {
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LOG_ERR("Pause when halted by debugger not supported");
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return -ENOTSUP;
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}
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irq_enable(DT_INST_IRQN(0));
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wdt_reg->INTEN = WDT_INTEN_WDTINTEN;
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wdt_reg->CTRL |= (WDT_CTRL_CLRRSTFLAG | WDT_CTRL_RELOAD);
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wdt_reg->CTRL |= WDT_CTRL_EN;
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LOG_DBG("WDT setup and enabled");
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return 0;
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}
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static int wdt_rts5912_disable(const struct device *dev)
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{
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const struct wdt_rts5912_config *const config = dev->config;
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struct wdt_rts5912_data *data = dev->data;
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WDT_Type *wdt_reg = (WDT_Type *)config->base;
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if (!(wdt_reg->CTRL & WDT_CTRL_EN)) {
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return -EALREADY;
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}
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wdt_reg->INTEN = 0ul;
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wdt_reg->CTRL |= WDT_CTRL_CLRRSTFLAG;
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wdt_reg->CTRL &= ~WDT_CTRL_EN;
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data->timeout_installed = false;
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LOG_DBG("WDT disabled");
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return 0;
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}
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static int wdt_rts5912_install_timeout(const struct device *dev,
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const struct wdt_timeout_cfg *config)
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{
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const struct wdt_rts5912_config *const cfg = dev->config;
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struct wdt_rts5912_data *data = dev->data;
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WDT_Type *wdt_reg = (WDT_Type *)cfg->base;
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uint32_t timeout;
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uint32_t max, min;
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LOG_DBG("WDT intstall timeout");
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if (wdt_reg->CTRL & WDT_CTRL_EN) {
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LOG_ERR("WDT is already running");
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return -EBUSY;
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}
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if (config->window.min > 0U) {
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LOG_ERR("Lower limit of watchdog is not supported, keep it zero");
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data->timeout_installed = false;
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return -EINVAL;
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}
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switch (config->flags) {
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case WDT_FLAG_RESET_SOC:
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wdt_reg->CTRL |= WDT_CTRL_RSTEN;
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break;
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case WDT_FLAG_RESET_NONE:
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wdt_reg->CTRL &= ~WDT_CTRL_RSTEN;
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break;
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case WDT_FLAG_RESET_CPU_CORE:
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LOG_ERR("WDT_FLAG_RESET_CPU_CORE is not supported\n");
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break;
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default:
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LOG_ERR("Unsupported watchdog config Flag\n");
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return -ENOTSUP;
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}
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timeout = config->window.max * 1000U;
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min = (cfg->div * USEC_PER_SEC) / WDT_CLK_CYCLE;
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max = min * WDT_MAX_CNT;
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if ((timeout < min) || (timeout > max)) {
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LOG_ERR("Invalid timeout value allowed range:"
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"%d ms to %d ms",
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min / MSEC_PER_SEC, max / MSEC_PER_SEC);
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return -EINVAL;
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}
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wdt_reg->CNT = timeout / min;
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data->callback = config->callback;
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data->timeout_installed = true;
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LOG_DBG("DIV: 0x%08x, CNT: 0x%08x", wdt_reg->DIV, wdt_reg->CNT);
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return 0;
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}
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static int wdt_rts5912_feed(const struct device *dev, int channel_id)
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{
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const struct wdt_rts5912_config *const cfg = dev->config;
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WDT_Type *wdt_reg = (WDT_Type *)cfg->base;
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ARG_UNUSED(dev);
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ARG_UNUSED(channel_id);
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if (!(wdt_reg->CTRL & WDT_CTRL_EN)) {
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return -EINVAL;
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}
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wdt_reg->CTRL |= WDT_CTRL_RELOAD;
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LOG_DBG("WDT feed");
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return 0;
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}
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static DEVICE_API(wdt, wdt_rts5912_api) = {
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.setup = wdt_rts5912_setup,
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.disable = wdt_rts5912_disable,
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.install_timeout = wdt_rts5912_install_timeout,
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.feed = wdt_rts5912_feed,
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};
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static int wdt_rts5912_init(const struct device *dev)
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{
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int rc;
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const struct wdt_rts5912_config *const cfg = dev->config;
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struct rts5912_sccon_subsys sccon;
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WDT_Type *wdt_reg = (WDT_Type *)cfg->base;
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LOG_DBG("WDT init");
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if (!device_is_ready(cfg->clk_dev)) {
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return -ENODEV;
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}
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sccon.clk_grp = cfg->clk_grp;
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sccon.clk_idx = cfg->clk_idx;
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rc = clock_control_on(cfg->clk_dev, (clock_control_subsys_t)&sccon);
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if (rc != 0) {
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return rc;
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}
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if (IS_ENABLED(CONFIG_WDT_DISABLE_AT_BOOT)) {
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wdt_rts5912_disable(dev);
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}
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wdt_reg->CTRL = 0ul;
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wdt_reg->DIV = cfg->div;
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wdt_reg->CTRL |= WDT_CTRL_CLRRSTFLAG;
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NVIC_ClearPendingIRQ(DT_INST_IRQN(0));
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IRQ_CONNECT(DT_INST_IRQN(0), 0, wdt_rts5912_isr, DEVICE_DT_INST_GET(0), 0);
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irq_enable(DT_INST_IRQN(0));
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return 0;
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}
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static const struct wdt_rts5912_config wdt_rts5912_cfg = {
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.base = DT_INST_REG_ADDR(0),
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.div = DT_INST_PROP(0, clk_divider),
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.clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
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.clk_grp = DT_CLOCKS_CELL_BY_NAME(DT_NODELABEL(wdog), watchdog, clk_grp),
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.clk_idx = DT_CLOCKS_CELL_BY_NAME(DT_NODELABEL(wdog), watchdog, clk_idx),
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};
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static struct wdt_rts5912_data wdt_rts5912_dev_data;
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DEVICE_DT_INST_DEFINE(0, wdt_rts5912_init, NULL, &wdt_rts5912_dev_data, &wdt_rts5912_cfg,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, &wdt_rts5912_api);
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@ -239,6 +239,17 @@
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140 0 141 0 142 0 143 0>;
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};
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};
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wdog: watchdog@4000c000 {
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compatible = "realtek,rts5912-watchdog";
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reg = <0x4000c000 0x14>;
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interrupt-parent = <&nvic>;
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interrupts = <209 0>;
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clocks = <&sccon RTS5912_SCCON_PERIPH_GRP2 PERIPH_GRP2_WDT_CLKPWR>;
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clock-names = "watchdog";
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clk-divider = <33>;
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status = "disabled";
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};
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};
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swj_port: swj-port {
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20
dts/bindings/watchdog/realtek,rts5912-watchdog.yaml
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20
dts/bindings/watchdog/realtek,rts5912-watchdog.yaml
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@ -0,0 +1,20 @@
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# Copyright (c) 2025 Realtek, SIBG-SD7
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# SPDX-License-Identifier: Apache-2.0
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description: Realtek RTS5912 watchdog timer
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include: base.yaml
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compatible: "realtek,rts5912-watchdog"
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properties:
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reg:
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required: true
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interrupts:
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required: true
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clk-divider:
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type: int
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description: Watchdog clock divider
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required: true
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32
soc/realtek/ec/rts5912/reg/reg_wdt.h
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32
soc/realtek/ec/rts5912/reg/reg_wdt.h
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@ -0,0 +1,32 @@
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/*
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* Copyright (c) 2025 Realtek, SIBG-SD7
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_REALTEK_RTS5912_REG_WDT_H
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#define ZEPHYR_SOC_REALTEK_RTS5912_REG_WDT_H
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/**
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* @brief WDT Controller (WDT)
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*/
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typedef struct {
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volatile uint32_t CTRL;
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const volatile uint32_t STS;
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volatile uint32_t CNT;
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volatile uint32_t DIV;
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volatile uint32_t INTEN;
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} WDT_Type;
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/* CTRL */
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#define WDT_CTRL_EN BIT(0)
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#define WDT_CTRL_RSTEN BIT(1)
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#define WDT_CTRL_RELOAD BIT(2)
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#define WDT_CTRL_CLRRSTFLAG BIT(3)
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/* STS */
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#define WDT_STS_RSTFLAG BIT(0)
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/* INTEN */
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#define WDT_INTEN_WDTINTEN BIT(0)
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#endif /* ZEPHYR_SOC_REALTEK_RTS5912_REG_WDT_H */
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