diff --git a/drivers/bluetooth/hci/ipm_stm32wb.c b/drivers/bluetooth/hci/ipm_stm32wb.c index 9c8c0a8dffa..91ce0faf47d 100644 --- a/drivers/bluetooth/hci/ipm_stm32wb.c +++ b/drivers/bluetooth/hci/ipm_stm32wb.c @@ -397,6 +397,8 @@ static void start_ble_rf(void) } #if STM32_LSE_ENABLED + /* Configure driving capability */ + LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos); /* Select LSE clock */ LL_RCC_LSE_Enable(); while (!LL_RCC_LSE_IsReady()) { diff --git a/drivers/clock_control/clock_stm32_ll_h7.c b/drivers/clock_control/clock_stm32_ll_h7.c index fff8c698894..4356a62a287 100644 --- a/drivers/clock_control/clock_stm32_ll_h7.c +++ b/drivers/clock_control/clock_stm32_ll_h7.c @@ -473,6 +473,9 @@ static void set_up_fixed_clock_sources(void) /* Enable backup domain */ LL_PWR_EnableBkUpAccess(); + /* Configure driving capability */ + LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos); + /* Enable LSE oscillator */ LL_RCC_LSE_Enable(); while (LL_RCC_LSE_IsReady() != 1) { diff --git a/drivers/clock_control/clock_stm32_ll_u5.c b/drivers/clock_control/clock_stm32_ll_u5.c index 1e999940462..6b86767d20d 100644 --- a/drivers/clock_control/clock_stm32_ll_u5.c +++ b/drivers/clock_control/clock_stm32_ll_u5.c @@ -336,6 +336,9 @@ static void set_up_fixed_clock_sources(void) } } + /* Configure driving capability */ + LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos); + /* Enable LSE Oscillator */ LL_RCC_LSE_Enable(); /* Wait for LSE ready */ diff --git a/drivers/clock_control/clock_stm32g4.c b/drivers/clock_control/clock_stm32g4.c index f7161fb2b7a..f465d51e4ae 100644 --- a/drivers/clock_control/clock_stm32g4.c +++ b/drivers/clock_control/clock_stm32g4.c @@ -75,6 +75,8 @@ void config_enable_default_clocks(void) /* Wait for Backup domain access */ } + /* Configure driving capability */ + LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos); /* Enable LSE Oscillator (32.768 kHz) */ LL_RCC_LSE_Enable(); while (!LL_RCC_LSE_IsReady()) { diff --git a/drivers/clock_control/clock_stm32l4_l5_wb_wl.c b/drivers/clock_control/clock_stm32l4_l5_wb_wl.c index b7e40add29d..a51e53b476d 100644 --- a/drivers/clock_control/clock_stm32l4_l5_wb_wl.c +++ b/drivers/clock_control/clock_stm32l4_l5_wb_wl.c @@ -88,6 +88,8 @@ void config_enable_default_clocks(void) /* Wait for Backup domain access */ } + /* Configure driving capability */ + LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos); /* Enable LSE Oscillator (32.768 kHz) */ LL_RCC_LSE_Enable(); while (!LL_RCC_LSE_IsReady()) { diff --git a/drivers/timer/stm32_lptim_timer.c b/drivers/timer/stm32_lptim_timer.c index bec9761e66c..9b9c56d4351 100644 --- a/drivers/timer/stm32_lptim_timer.c +++ b/drivers/timer/stm32_lptim_timer.c @@ -279,6 +279,7 @@ static int sys_clock_driver_init(const struct device *dev) /* enable LSE clock */ LL_RCC_LSE_DisableBypass(); + LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos); LL_RCC_LSE_Enable(); while (!LL_RCC_LSE_IsReady()) { /* Wait for LSE ready */ diff --git a/dts/arm/st/f0/stm32f0.dtsi b/dts/arm/st/f0/stm32f0.dtsi index c451144fc7f..9b9fa41a351 100644 --- a/dts/arm/st/f0/stm32f0.dtsi +++ b/dts/arm/st/f0/stm32f0.dtsi @@ -49,8 +49,9 @@ clk_lse: clk-lse { #clock-cells = <0>; - compatible = "fixed-clock"; + compatible = "st,stm32-lse-clock"; clock-frequency = <32768>; + driving-capability = <0>; status = "disabled"; }; diff --git a/dts/arm/st/f3/stm32f3.dtsi b/dts/arm/st/f3/stm32f3.dtsi index 6cf02b2e657..8e0ed3f0a0f 100644 --- a/dts/arm/st/f3/stm32f3.dtsi +++ b/dts/arm/st/f3/stm32f3.dtsi @@ -50,8 +50,9 @@ clk_lse: clk-lse { #clock-cells = <0>; - compatible = "fixed-clock"; + compatible = "st,stm32-lse-clock"; clock-frequency = <32768>; + driving-capability = <0>; status = "disabled"; }; diff --git a/dts/arm/st/f7/stm32f7.dtsi b/dts/arm/st/f7/stm32f7.dtsi index 06368a3667c..eecf384ed6b 100644 --- a/dts/arm/st/f7/stm32f7.dtsi +++ b/dts/arm/st/f7/stm32f7.dtsi @@ -55,8 +55,9 @@ clk_lse: clk-lse { #clock-cells = <0>; - compatible = "fixed-clock"; + compatible = "st,stm32-lse-clock"; clock-frequency = <32768>; + driving-capability = <0>; status = "disabled"; }; diff --git a/dts/arm/st/g0/stm32g0.dtsi b/dts/arm/st/g0/stm32g0.dtsi index 786a52a2a2e..640705e430f 100644 --- a/dts/arm/st/g0/stm32g0.dtsi +++ b/dts/arm/st/g0/stm32g0.dtsi @@ -52,8 +52,9 @@ clk_lse: clk-lse { #clock-cells = <0>; - compatible = "fixed-clock"; + compatible = "st,stm32-lse-clock"; clock-frequency = <32768>; + driving-capability = <0>; status = "disabled"; }; diff --git a/dts/arm/st/g4/stm32g4.dtsi b/dts/arm/st/g4/stm32g4.dtsi index 04a9342b7f3..4ac6a14467c 100644 --- a/dts/arm/st/g4/stm32g4.dtsi +++ b/dts/arm/st/g4/stm32g4.dtsi @@ -51,8 +51,9 @@ clk_lse: clk-lse { #clock-cells = <0>; - compatible = "fixed-clock"; + compatible = "st,stm32-lse-clock"; clock-frequency = <32768>; + driving-capability = <0>; status = "disabled"; }; diff --git a/dts/arm/st/h7/stm32h7.dtsi b/dts/arm/st/h7/stm32h7.dtsi index 81214a2b8af..6c2f5f0ab36 100644 --- a/dts/arm/st/h7/stm32h7.dtsi +++ b/dts/arm/st/h7/stm32h7.dtsi @@ -66,8 +66,9 @@ clk_lse: clk-lse { #clock-cells = <0>; - compatible = "fixed-clock"; + compatible = "st,stm32-lse-clock"; clock-frequency = <32768>; + driving-capability = <0>; status = "disabled"; }; diff --git a/dts/arm/st/l0/stm32l0.dtsi b/dts/arm/st/l0/stm32l0.dtsi index 31d3e396028..5b45d203fbc 100644 --- a/dts/arm/st/l0/stm32l0.dtsi +++ b/dts/arm/st/l0/stm32l0.dtsi @@ -56,8 +56,9 @@ clk_lse: clk-lse { #clock-cells = <0>; - compatible = "fixed-clock"; + compatible = "st,stm32-lse-clock"; clock-frequency = <32768>; + driving-capability = <0>; status = "disabled"; }; diff --git a/dts/arm/st/l4/stm32l4.dtsi b/dts/arm/st/l4/stm32l4.dtsi index 419779d50ce..34cae837b8d 100644 --- a/dts/arm/st/l4/stm32l4.dtsi +++ b/dts/arm/st/l4/stm32l4.dtsi @@ -58,8 +58,9 @@ clk_lse: clk-lse { #clock-cells = <0>; - compatible = "fixed-clock"; + compatible = "st,stm32-lse-clock"; clock-frequency = <32768>; + driving-capability = <0>; status = "disabled"; }; diff --git a/dts/arm/st/l5/stm32l5.dtsi b/dts/arm/st/l5/stm32l5.dtsi index 89e434cca6f..c9653906df0 100644 --- a/dts/arm/st/l5/stm32l5.dtsi +++ b/dts/arm/st/l5/stm32l5.dtsi @@ -66,8 +66,9 @@ clk_lse: clk-lse { #clock-cells = <0>; - compatible = "fixed-clock"; + compatible = "st,stm32-lse-clock"; clock-frequency = <32768>; + driving-capability = <0>; status = "disabled"; }; diff --git a/dts/arm/st/u5/stm32u5.dtsi b/dts/arm/st/u5/stm32u5.dtsi index 42289cbacf5..b299b9860cc 100644 --- a/dts/arm/st/u5/stm32u5.dtsi +++ b/dts/arm/st/u5/stm32u5.dtsi @@ -64,8 +64,9 @@ clk_lse: clk-lse { #clock-cells = <0>; - compatible = "fixed-clock"; + compatible = "st,stm32-lse-clock"; clock-frequency = <32768>; + driving-capability = <0>; status = "disabled"; }; diff --git a/dts/arm/st/wb/stm32wb.dtsi b/dts/arm/st/wb/stm32wb.dtsi index d42ccf24303..6383eaffacb 100644 --- a/dts/arm/st/wb/stm32wb.dtsi +++ b/dts/arm/st/wb/stm32wb.dtsi @@ -71,8 +71,9 @@ clk_lse: clk-lse { #clock-cells = <0>; - compatible = "fixed-clock"; + compatible = "st,stm32-lse-clock"; clock-frequency = <32768>; + driving-capability = <0>; status = "disabled"; }; diff --git a/dts/arm/st/wl/stm32wl.dtsi b/dts/arm/st/wl/stm32wl.dtsi index ff254d9d26d..76ff435f0a0 100644 --- a/dts/arm/st/wl/stm32wl.dtsi +++ b/dts/arm/st/wl/stm32wl.dtsi @@ -59,8 +59,9 @@ clk_lse: clk-lse { #clock-cells = <0>; - compatible = "fixed-clock"; + compatible = "st,stm32-lse-clock"; clock-frequency = <32768>; + driving-capability = <0>; status = "disabled"; }; diff --git a/dts/bindings/clock/st,stm32-lse-clock.yaml b/dts/bindings/clock/st,stm32-lse-clock.yaml new file mode 100644 index 00000000000..acc23db2b8b --- /dev/null +++ b/dts/bindings/clock/st,stm32-lse-clock.yaml @@ -0,0 +1,22 @@ +# Copyright (c) 2022, SILA Embedded Solutions GmbH +# SPDX-License-Identifier: Apache-2.0 + +description: STM32 LSE Clock + +compatible: "st,stm32-lse-clock" + +include: [fixed-clock.yaml] + +properties: + driving-capability: + type: int + required: true + description: | + LSE driving capability, within the range 0 to 3. + 0 represents the lowests driving capability, 3 + the highest. + enum: + - 0 + - 1 + - 2 + - 3 diff --git a/include/zephyr/drivers/clock_control/stm32_clock_control.h b/include/zephyr/drivers/clock_control/stm32_clock_control.h index 5ac43326fa9..ba36b5dc77a 100644 --- a/include/zephyr/drivers/clock_control/stm32_clock_control.h +++ b/include/zephyr/drivers/clock_control/stm32_clock_control.h @@ -180,9 +180,15 @@ #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), fixed_clock, okay) #define STM32_LSE_ENABLED 1 #define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency) +#define STM32_LSE_DRIVING 0 +#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), st_stm32_lse_clock, okay) +#define STM32_LSE_ENABLED 1 +#define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency) +#define STM32_LSE_DRIVING DT_PROP(DT_NODELABEL(clk_lse), driving_capability) #else #define STM32_LSE_ENABLED 0 #define STM32_LSE_FREQ 0 +#define STM32_LSE_DRIVING 0 #endif #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) || \