From 85feaa60e22237ef542d96bcf52991252712a7b5 Mon Sep 17 00:00:00 2001 From: Wilfried Chauveau Date: Sun, 8 Oct 2023 10:05:28 +0100 Subject: [PATCH] =?UTF-8?q?arch:=20arm:=C2=A0cortex=5Fm:=20Use=20r*=20regi?= =?UTF-8?q?ster=20names=20rather=20than=20v*?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit v* register aliases are uncommon and it can be surprising to find them. This change makes use of r* register names for a more consistent experience of reading assembly. Signed-off-by: Wilfried Chauveau --- arch/arm/core/cortex_m/swap_helper.S | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/core/cortex_m/swap_helper.S b/arch/arm/core/cortex_m/swap_helper.S index af1d0d791dd..477ee2ac86d 100644 --- a/arch/arm/core/cortex_m/swap_helper.S +++ b/arch/arm/core/cortex_m/swap_helper.S @@ -94,7 +94,7 @@ SECTION_FUNC(TEXT, z_arm_pendsv) /* store r8-12 */ stmea r0!, {r3-r7} #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) - stmia r0, {v1-v8, ip} + stmia r0, {r4-r11, ip} #ifdef CONFIG_FPU_SHARING /* Assess whether switched-out thread had been using the FP registers. */ tst lr, #_EXC_RETURN_FTYPE_Msk @@ -135,8 +135,8 @@ out_fp_endif: * to pend PendSV have been taken with the current kernel * state and this is what we're handling currently. */ - ldr v4, =_SCS_ICSR - ldr v3, =_SCS_ICSR_UNPENDSV + ldr r7, =_SCS_ICSR + ldr r6, =_SCS_ICSR_UNPENDSV /* _kernel is still in r1 */ @@ -154,8 +154,8 @@ out_fp_endif: * has been handled. */ - /* _SCS_ICSR is still in v4 and _SCS_ICSR_UNPENDSV in v3 */ - str v3, [v4, #0] + /* _SCS_ICSR is still in r7 and _SCS_ICSR_UNPENDSV in r6 */ + str r6, [r7, #0] #if defined(CONFIG_THREAD_LOCAL_STORAGE) /* Grab the TLS pointer */ @@ -311,7 +311,7 @@ in_fp_endif: /* load callee-saved + psp from thread */ add r0, r2, #_thread_offset_to_callee_saved - ldmia r0, {v1-v8, ip} + ldmia r0, {r4-r11, ip} #else #error Unknown ARM architecture #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */