diff --git a/drivers/clock_control/Kconfig.stm32 b/drivers/clock_control/Kconfig.stm32
index 2d53eff7d42..4932e79056d 100644
--- a/drivers/clock_control/Kconfig.stm32
+++ b/drivers/clock_control/Kconfig.stm32
@@ -366,6 +366,20 @@ config CLOCK_STM32_PLL_R_DIVISOR
 	help
 	  PLL R Output divisor, allowed values: 0, 2, 4, 6, 8.
 
+config CLOCK_STM32_LSE
+	bool "Low-speed external clock"
+	default n
+	help
+	  Enable the low-speed external (LSE) clock supplied with a 32.768 kHz
+	  crystal resonator oscillator.
+
+config CLOCK_STM32_MSI_PLL_MODE
+	bool "MSI PLL MODE"
+	depends on CLOCK_STM32_LSE
+	default n
+	help
+	  Enable hardware auto-calibration with LSE.
+
 endif # SOC_SERIES_STM32L4X
 
 config CLOCK_STM32_AHB_PRESCALER
diff --git a/drivers/clock_control/stm32_ll_clock.c b/drivers/clock_control/stm32_ll_clock.c
index 3f031114691..8c16455d0dc 100644
--- a/drivers/clock_control/stm32_ll_clock.c
+++ b/drivers/clock_control/stm32_ll_clock.c
@@ -363,6 +363,10 @@ static int stm32_clock_control_init(struct device *dev)
 		while (LL_RCC_MSI_IsReady() != 1) {
 		/* Wait for HSI ready */
 		}
+#ifdef CONFIG_CLOCK_STM32_MSI_PLL_MODE
+		/* Enable MSI hardware auto calibration */
+		LL_RCC_MSI_EnablePLLMode();
+#endif
 	}
 
 	/* Set MSI as SYSCLCK source */
diff --git a/drivers/clock_control/stm32l4x_ll_clock.c b/drivers/clock_control/stm32l4x_ll_clock.c
index 075f9f31779..a21654c67ea 100644
--- a/drivers/clock_control/stm32l4x_ll_clock.c
+++ b/drivers/clock_control/stm32l4x_ll_clock.c
@@ -39,5 +39,24 @@ void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
  */
 void config_enable_default_clocks(void)
 {
-	/* Nothing for now */
+#ifdef CONFIG_CLOCK_STM32_LSE
+	/* LSE belongs to the back-up domain, enable access.*/
+
+	/* Enable the power interface clock */
+	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
+
+	/* Set the DBP bit in the Power control register 1 (PWR_CR1) */
+	LL_PWR_EnableBkUpAccess();
+	while (!LL_PWR_IsEnabledBkUpAccess()) {
+		/* Wait for Backup domain access */
+	}
+
+	/* Enable LSE Oscillator (32.768 kHz) */
+	LL_RCC_LSE_Enable();
+	while (!LL_RCC_LSE_IsReady()) {
+		/* Wait for LSE ready */
+	}
+
+	LL_PWR_DisableBkUpAccess();
+#endif
 }
diff --git a/soc/arm/st_stm32/stm32l4/soc.h b/soc/arm/st_stm32/stm32l4/soc.h
index d744898bbe8..d81acf964fb 100644
--- a/soc/arm/st_stm32/stm32l4/soc.h
+++ b/soc/arm/st_stm32/stm32l4/soc.h
@@ -44,6 +44,7 @@
 #include <stm32l4xx_ll_bus.h>
 #include <stm32l4xx_ll_rcc.h>
 #include <stm32l4xx_ll_system.h>
+#include <stm32l4xx_ll_pwr.h>
 #endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
 
 #ifdef CONFIG_SPI_STM32