From 857a188c76063a271ce4f8ceba788da90c721243 Mon Sep 17 00:00:00 2001 From: Felipe Neves Date: Wed, 3 Nov 2021 20:51:35 -0300 Subject: [PATCH] drivers: watchdog: esp32: enabled esp32c3 support for the unified esp32 wdt driver. Signed-off-by: Felipe Neves --- .../riscv/esp32c3_devkitm/esp32c3_devkitm.dts | 4 +++ drivers/watchdog/Kconfig.esp32 | 2 +- drivers/watchdog/wdt_esp32.c | 27 +++++++++++++++++-- dts/riscv/espressif/esp32c3.dtsi | 19 +++++++++++++ 4 files changed, 49 insertions(+), 3 deletions(-) diff --git a/boards/riscv/esp32c3_devkitm/esp32c3_devkitm.dts b/boards/riscv/esp32c3_devkitm/esp32c3_devkitm.dts index ece4e0ba14e..c44ff88af05 100644 --- a/boards/riscv/esp32c3_devkitm/esp32c3_devkitm.dts +++ b/boards/riscv/esp32c3_devkitm/esp32c3_devkitm.dts @@ -69,6 +69,10 @@ status = "okay"; }; +&wdt0 { + status = "okay"; +}; + &flash0 { status = "okay"; partitions { diff --git a/drivers/watchdog/Kconfig.esp32 b/drivers/watchdog/Kconfig.esp32 index 13aca00f112..0a6456d1fc6 100644 --- a/drivers/watchdog/Kconfig.esp32 +++ b/drivers/watchdog/Kconfig.esp32 @@ -7,7 +7,7 @@ DT_COMPAT_ESP32_WDT := espressif,esp32-watchdog config WDT_ESP32 bool "ESP32 Watchdog (WDT) Driver" - depends on SOC_ESP32 || SOC_ESP32S2 + depends on SOC_ESP32 || SOC_ESP32S2 || SOC_ESP32C3 default $(dt_compat_enabled,$(DT_COMPAT_ESP32_WDT)) help Enable WDT driver for ESP32. diff --git a/drivers/watchdog/wdt_esp32.c b/drivers/watchdog/wdt_esp32.c index 0909f11a78b..a90dec24069 100644 --- a/drivers/watchdog/wdt_esp32.c +++ b/drivers/watchdog/wdt_esp32.c @@ -12,9 +12,19 @@ #include #include +#ifndef CONFIG_SOC_ESP32C3 #include +#else +#include +#endif #include +#ifdef CONFIG_SOC_ESP32C3 +#define ISR_HANDLER isr_handler_t +#else +#define ISR_HANDLER intr_handler_t +#endif + /* FIXME: This struct shall be removed from here, when esp32 timer driver got * implemented. * That's why the type name starts with `timer` not `wdt` @@ -150,15 +160,23 @@ static int wdt_esp32_set_config(const struct device *dev, uint8_t options) v |= TIMG_WDT_STG_SEL_OFF << TIMG_WDT_STG1_S; /* Disable interrupts for this mode. */ + #ifndef CONFIG_SOC_ESP32C3 v &= ~(TIMG_WDT_LEVEL_INT_EN | TIMG_WDT_EDGE_INT_EN); + #else + v &= ~(TIMG_WDT_INT_ENA); + #endif } else if (data->mode == WDT_MODE_INTERRUPT_RESET) { /* Interrupt first, and warm reset if not reloaded */ v |= TIMG_WDT_STG_SEL_INT << TIMG_WDT_STG0_S; v |= TIMG_WDT_STG_SEL_RESET_SYSTEM << TIMG_WDT_STG1_S; /* Use level-triggered interrupts. */ + #ifndef CONFIG_SOC_ESP32C3 v |= TIMG_WDT_LEVEL_INT_EN; v &= ~TIMG_WDT_EDGE_INT_EN; + #else + v |= TIMG_WDT_INT_ENA; + #endif } else { return -EINVAL; } @@ -206,10 +224,15 @@ static int wdt_esp32_init(const struct device *dev) wdt_esp32_disable(dev); #endif - /* This is a level 4 interrupt, which is handled by _Level4Vector, + /* For xtensa esp32 chips, this is a level 4 interrupt, + * which is handled by _Level4Vector, * located in xtensa_vectors.S. */ - data->irq_line = esp_intr_alloc(config->irq_source, 0, wdt_esp32_isr, (void *)dev, NULL); + data->irq_line = esp_intr_alloc(config->irq_source, + 0, + (ISR_HANDLER)wdt_esp32_isr, + (void *)dev, + NULL); wdt_esp32_enable(dev); diff --git a/dts/riscv/espressif/esp32c3.dtsi b/dts/riscv/espressif/esp32c3.dtsi index a5dbd7f3b3f..d4ae13f45ed 100644 --- a/dts/riscv/espressif/esp32c3.dtsi +++ b/dts/riscv/espressif/esp32c3.dtsi @@ -153,6 +153,25 @@ status = "disabled"; use-iomux; }; + + wdt0: watchdog@6001f048 { + compatible = "espressif,esp32-watchdog"; + reg = <0x6001f048 0x20>; + interrupts = ; + interrupt-parent = <&intc>; + label = "WDT_0"; + status = "disabled"; + }; + + wdt1: watchdog@60020048 { + compatible = "espressif,esp32-watchdog"; + reg = <0x60020048 0x20>; + interrupts = ; + interrupt-parent = <&intc>; + label = "WDT_1"; + status = "disabled"; + }; + }; };