boards: nxp/frdm_mcxn947: Support lpadc for NXP frdm_mcxn947

Support lpadc for NXP frdm_mcxn947

Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>

boards/nxp/frdm_mcxn947/board.c

@@ -210,6 +210,11 @@ static int frdm_mcxn947_init(void)
 	SPC_EnableActiveModeAnalogModules(SPC0, kSPC_controlVref);
 #endif
 
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpadc0), okay)
+	CLOCK_SetClkDiv(kCLOCK_DivAdc0Clk, 1U);
+	CLOCK_AttachClk(kFRO_HF_to_ADC0);
+#endif
+
 	/* Set SystemCoreClock variable. */
 	SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
 

boards/nxp/frdm_mcxn947/doc/index.rst

@@ -86,6 +86,8 @@ The FRDM-MCXN947 board configuration supports the following hardware features:
 +-----------+------------+-------------------------------------+
 | VREF      | on-chip    | REGULATOR                           |
 +-----------+------------+-------------------------------------+
+| ADC       | on-chip    | adc                                 |
++-----------+------------+-------------------------------------+
 
 Targets available
 ==================

boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi

@@ -148,4 +148,13 @@
 			input-enable;
 		};
 	};
+	pinmux_lpadc0: pinmux_lpadc0 {
+		group0 {
+			pinmux = <ADC0_A2_PIO4_23>,
+				<ADC0_A1_PIO4_15>,
+				<ADC0_B1_PIO4_19>;
+			slew-rate = "fast";
+			drive-strength = "low";
+		};
+	};
 };

boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi

@@ -183,3 +183,8 @@
 	pinctrl-names = "default", "slow", "med";
 	no-1-8-v;
 };
+
+&lpadc0 {
+	pinctrl-0 = <&pinmux_lpadc0>;
+	pinctrl-names = "default";
+};

boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts

@@ -157,3 +157,7 @@
 &vref {
 	status = "okay";
 };
+
+&lpadc0 {
+	status = "okay";
+};

boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml

@@ -25,4 +25,5 @@ supported:
   - counter
   - sdhc
   - regulator
+  - adc
 vendor: nxp