michaelh/zephyr
1
0
Fork 0
Code Releases Activity

drivers: eth: sam_gmac: Add data cache checks

Browse source 
Improve data cache conditional build. Now data cache code is build
only if device have support to it. This enables GMAC driver for use
with devices that don't have data cache instructions.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This commit is contained in:
Gerson Fernando Budke 2020-02-19 23:49:01 -03:00 • committed by Jukka Rissanen
commit 84ecfd9b57
1 changed files with 39 additions and 33 deletions
Download patch file Download diff file Expand all files Collapse all files

72
drivers/ethernet/eth_sam_gmac.c
View file

@ -46,6 +46,44 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME);
#include <net/gptp.h>
#endif
#ifdef __DCACHE_PRESENT
static bool dcache_enabled;
static inline void dcache_is_enabled(void)
{
dcache_enabled = (SCB->CCR & SCB_CCR_DC_Msk);
}
static inline void dcache_invalidate(u32_t addr, u32_t size)
{
if (!dcache_enabled) {
return;
}
/* Make sure it is aligned to 32B */
u32_t start_addr = addr & (u32_t)~(GMAC_DCACHE_ALIGNMENT - 1);
u32_t size_full = size + addr - start_addr;
SCB_InvalidateDCache_by_Addr((uint32_t *)start_addr, size_full);
}
static inline void dcache_clean(u32_t addr, u32_t size)
{
if (!dcache_enabled) {
return;
}
/* Make sure it is aligned to 32B */
u32_t start_addr = addr & (u32_t)~(GMAC_DCACHE_ALIGNMENT - 1);
u32_t size_full = size + addr - start_addr;
SCB_CleanDCache_by_Addr((uint32_t *)start_addr, size_full);
}
#else
#define dcache_is_enabled()
#define dcache_invalidate(addr, size)
#define dcache_clean(addr, size)
#endif
/*
* Verify Kconfig configuration
*/
@ -340,38 +378,6 @@ static inline void eth_sam_gmac_init_qav(Gmac *gmac)
#endif
/*
* Cache helpers
*/
static bool dcache_enabled;
static inline void dcache_invalidate(u32_t addr, u32_t size)
{
if (!dcache_enabled) {
return;
}
/* Make sure it is aligned to 32B */
u32_t start_addr = addr & (u32_t)~(GMAC_DCACHE_ALIGNMENT - 1);
u32_t size_full = size + addr - start_addr;
SCB_InvalidateDCache_by_Addr((uint32_t *)start_addr, size_full);
}
static inline void dcache_clean(u32_t addr, u32_t size)
{
if (!dcache_enabled) {
return;
}
/* Make sure it is aligned to 32B */
u32_t start_addr = addr & (u32_t)~(GMAC_DCACHE_ALIGNMENT - 1);
u32_t size_full = size + addr - start_addr;
SCB_CleanDCache_by_Addr((uint32_t *)start_addr, size_full);
}
#if GMAC_MULTIPLE_TX_PACKETS == 1
/*
* Reset ring buffer
@ -1871,7 +1877,7 @@ static void eth0_iface_init(struct net_if *iface)
}
/* Check the status of data caches */
dcache_enabled = (SCB->CCR & SCB_CCR_DC_Msk);
dcache_is_enabled();
/* Initialize GMAC driver, maximum frame length is 1518 bytes */
gmac_ncfgr_val =