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gpio: reduce Kconfigs and use consistent name for GPIOs

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Using AON for GPIO kconfigs is very specifc to quark se, there
is no need to make this special for this platform. Use the
existing scheme instead.

Change-Id: I946431490380dc0f537d6056277a94c9c9c80fed
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2016-10-02 10:23:26 -04:00 • committed by Anas Nashif
commit 84c9db39e7
8 changed files with 37 additions and 55 deletions
Download patch file Download diff file Expand all files Collapse all files

4
arch/x86/soc/intel_quark/quark_se/Kconfig.defconfig.series
View file

@ -68,9 +68,9 @@ config GPIO_QMSI_0
config GPIO_QMSI_0_IRQ_PRI
default 2
config GPIO_QMSI_AON
config GPIO_QMSI_1
def_bool y
config GPIO_QMSI_AON_IRQ_PRI
config GPIO_QMSI_1_IRQ_PRI
default 2
endif # GPIO

12
boards/quark_se_c1000_devboard/Kconfig.defconfig
View file

@ -72,10 +72,10 @@ config TI_CC2520_SPI_SLAVE
if GPIO_QMSI
config TI_CC2520_GPIO_NAME
config TI_CC2520_GPIO_0_NAME
default GPIO_QMSI_0_NAME
config TI_CC2520_GPIO_AON_NAME
default GPIO_QMSI_AON_NAME
config TI_CC2520_GPIO_1_NAME
default GPIO_QMSI_1_NAME
endif # GPIO_QMSI
@ -86,12 +86,12 @@ config SPI_1_CS_GPIO_PORT
default GPIO_QMSI_0_NAME
config SPI_1_CS_GPIO_PIN
default 11
config TI_CC2520_GPIO_NAME
config TI_CC2520_GPIO_0_NAME
string
default GPIO_QMSI_0_NAME
config TI_CC2520_GPIO_AON_NAME
config TI_CC2520_GPIO_1_NAME
string
default GPIO_QMSI_AON_NAME
default GPIO_QMSI_1_NAME
endif
endif # NETWORKING_WITH_15_4_TI_CC2520

4
boards/quark_se_c1000_devboard/board.c
View file

@ -35,14 +35,14 @@ struct device **cc2520_configure_gpios(void)
const int flags_int_in = (GPIO_DIR_IN | GPIO_INT | GPIO_INT_EDGE |
GPIO_INT_ACTIVE_HIGH | GPIO_INT_DEBOUNCE);
gpio = device_get_binding(CONFIG_TI_CC2520_GPIO_AON_NAME);
gpio = device_get_binding(CONFIG_TI_CC2520_GPIO_1_NAME);
gpio_pin_configure(gpio, CONFIG_CC2520_GPIO_VREG_EN, flags_noint_out);
gpio_pin_configure(gpio, CONFIG_CC2520_GPIO_RESET, flags_noint_out);
cc2520_gpio_config[CC2520_GPIO_IDX_VREG_EN] = gpio;
cc2520_gpio_config[CC2520_GPIO_IDX_RESET] = gpio;
gpio = device_get_binding(CONFIG_TI_CC2520_GPIO_NAME);
gpio = device_get_binding(CONFIG_TI_CC2520_GPIO_0_NAME);
gpio_pin_configure(gpio, CONFIG_CC2520_GPIO_SFD, flags_int_in);
gpio_pin_configure(gpio, CONFIG_CC2520_GPIO_FIFOP, flags_int_in);
gpio_pin_configure(gpio, CONFIG_CC2520_GPIO_FIFO, flags_noint_in);

2
boards/quark_se_c1000_devboard/board.h
View file

@ -21,7 +21,7 @@
/* Push button switch 0 */
#define SW0_GPIO_PIN 4
#define SW0_GPIO_NAME CONFIG_GPIO_QMSI_AON_NAME
#define SW0_GPIO_NAME CONFIG_GPIO_QMSI_1_NAME
/* Push button switch 1 */
#define SW1_GPIO_PIN 5

18
drivers/gpio/Kconfig.qmsi
View file

@ -76,24 +76,6 @@ config GPIO_QMSI_1_IRQ_PRI
help
IRQ priority
config GPIO_QMSI_AON
bool "QMSI GPIO block AON"
depends on GPIO_QMSI
default n
help
Include support for the GPIO AON (always on) port using QMSI.
config GPIO_QMSI_AON_NAME
string "Driver name"
depends on GPIO_QMSI_AON
default "GPIO_AON_0"
config GPIO_QMSI_AON_IRQ_PRI
int "Controller interrupt priority"
depends on GPIO_QMSI_AON
help
IRQ priority
config GPIO_QMSI_API_REENTRANCY
bool
prompt "GPIO driver API reentrancy"

20
drivers/gpio/gpio_qmsi.c
View file

@ -179,7 +179,7 @@ DEVICE_DEFINE(gpio_0, CONFIG_GPIO_QMSI_0_NAME, &gpio_qmsi_init,
#endif /* CONFIG_GPIO_QMSI_0 */
#ifdef CONFIG_GPIO_QMSI_AON
#ifdef CONFIG_GPIO_QMSI_1
static struct gpio_qmsi_config gpio_aon_config = {
.gpio = QM_AON_GPIO_0,
.num_pins = QM_NUM_AON_GPIO_PINS,
@ -226,11 +226,11 @@ static int gpio_aon_device_ctrl(struct device *port, uint32_t ctrl_command,
}
#endif
DEVICE_DEFINE(gpio_aon, CONFIG_GPIO_QMSI_AON_NAME, &gpio_qmsi_init,
DEVICE_DEFINE(gpio_aon, CONFIG_GPIO_QMSI_1_NAME, &gpio_qmsi_init,
gpio_aon_device_ctrl, &gpio_aon_runtime, &gpio_aon_config,
SECONDARY, CONFIG_GPIO_QMSI_INIT_PRIORITY, NULL);
#endif /* CONFIG_GPIO_QMSI_AON */
#endif /* CONFIG_GPIO_QMSI_1 */
/*
* TODO: Zephyr's API is not clear about the behavior of the this
@ -259,14 +259,14 @@ static void gpio_qmsi_0_int_callback(void *data, uint32_t status)
#endif
}
#ifdef CONFIG_GPIO_QMSI_AON
#ifdef CONFIG_GPIO_QMSI_1
static void gpio_qmsi_aon_int_callback(void *data, uint32_t status)
{
struct device *port = DEVICE_GET(gpio_aon);
gpio_qmsi_callback(port, status);
}
#endif /* CONFIG_GPIO_QMSI_AON */
#endif /* CONFIG_GPIO_QMSI_1 */
static void qmsi_write_bit(uint32_t *target, uint8_t bit, uint8_t value)
{
@ -313,11 +313,11 @@ static inline void qmsi_pin_config(struct device *port, uint32_t pin, int flags)
cfg.callback = gpio_qmsi_0_int_callback;
break;
#ifdef CONFIG_GPIO_QMSI_AON
#ifdef CONFIG_GPIO_QMSI_1
case QM_AON_GPIO_0:
cfg.callback = gpio_qmsi_aon_int_callback;
break;
#endif /* CONFIG_GPIO_QMSI_AON */
#endif /* CONFIG_GPIO_QMSI_1 */
default:
return;
@ -465,15 +465,15 @@ int gpio_qmsi_init(struct device *port)
irq_enable(QM_IRQ_GPIO_0);
QM_SCSS_INT->int_gpio_mask &= ~BIT(0);
break;
#ifdef CONFIG_GPIO_QMSI_AON
#ifdef CONFIG_GPIO_QMSI_1
case QM_AON_GPIO_0:
IRQ_CONNECT(QM_IRQ_AONGPIO_0,
CONFIG_GPIO_QMSI_AON_IRQ_PRI, qm_aon_gpio_isr_0,
CONFIG_GPIO_QMSI_1_IRQ_PRI, qm_aon_gpio_isr_0,
0, IOAPIC_LEVEL | IOAPIC_HIGH);
irq_enable(QM_IRQ_AONGPIO_0);
QM_SCSS_INT->int_aon_gpio_mask &= ~BIT(0);
break;
#endif /* CONFIG_GPIO_QMSI_AON */
#endif /* CONFIG_GPIO_QMSI_1 */
default:
return -EIO;
}

6
samples/sensor/bmi160/x86/prj.conf
View file

@ -12,6 +12,6 @@ CONFIG_RING_BUFFER=y
CONFIG_GPIO=y
CONFIG_GPIO_QMSI=y
CONFIG_GPIO_QMSI_0_PRI=2
CONFIG_GPIO_QMSI_AON=y
CONFIG_GPIO_QMSI_AON_NAME="GPIO_AON_0"
CONFIG_GPIO_QMSI_AON_PRI=2
CONFIG_GPIO_QMSI_1=y
CONFIG_GPIO_QMSI_1_NAME="GPIO_1"
CONFIG_GPIO_QMSI_1_PRI=2

26
samples/sensor/bmi160/x86/src/x86_bmi160.c
View file

@ -26,30 +26,30 @@
QUARK_SE_IPM_DEFINE(bmi160_ipm, 0, QUARK_SE_IPM_OUTBOUND);
#define SLEEPTIME MSEC(1000)
#define SLEEPTIME MSEC(1000)
#define BMI160_INTERRUPT_PIN 4
#define BMI160_INTERRUPT_PIN 4
struct device *ipm;
struct gpio_callback cb;
static void aon_gpio_callback(struct device *port,
struct gpio_callback *cb, uint32_t pins)
static void gpio_callback(struct device *port,
struct gpio_callback *cb, uint32_t pins)
{
ipm_send(ipm, 0, 0, NULL, 0);
}
void main(void)
{
uint32_t timer_data[2] = {0, 0};
struct device *aon_gpio;
uint32_t timer_data[2] = { 0, 0 };
struct device *gpio;
struct nano_timer timer;
nano_timer_init(&timer, timer_data);
aon_gpio = device_get_binding("GPIO_AON_0");
if (!aon_gpio) {
printf("aon_gpio device not found.\n");
gpio = device_get_binding("GPIO_1");
if (!gpio) {
printf("gpio device not found.\n");
return;
}
@ -59,14 +59,14 @@ void main(void)
return;
}
gpio_init_callback(&cb, aon_gpio_callback, BIT(BMI160_INTERRUPT_PIN));
gpio_add_callback(aon_gpio, &cb);
gpio_init_callback(&cb, gpio_callback, BIT(BMI160_INTERRUPT_PIN));
gpio_add_callback(gpio, &cb);
gpio_pin_configure(aon_gpio, BMI160_INTERRUPT_PIN,
gpio_pin_configure(gpio, BMI160_INTERRUPT_PIN,
GPIO_DIR_IN | GPIO_INT | GPIO_INT_EDGE |
GPIO_INT_ACTIVE_LOW | GPIO_INT_DEBOUNCE);
gpio_pin_enable_callback(aon_gpio, BMI160_INTERRUPT_PIN);
gpio_pin_enable_callback(gpio, BMI160_INTERRUPT_PIN);
while (1) {
nano_task_timer_start(&timer, SLEEPTIME);