diff --git a/boards/arm64/nxp_ls1046ardb/doc/index.rst b/boards/arm64/nxp_ls1046ardb/doc/index.rst
index bed0c29abdc..b843392c676 100644
--- a/boards/arm64/nxp_ls1046ardb/doc/index.rst
+++ b/boards/arm64/nxp_ls1046ardb/doc/index.rst
@@ -65,10 +65,14 @@ hardware features:
 
 Other hardware features are not supported by the Zephyr kernel.
 
-The default configuration can be found in the defconfig file:
+The default configuration can be found in the defconfig file for NON-SMP:
 
         ``boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_defconfig``
 
+Or for SMP:
+
+	``boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_defconfig``
+
 There are two serial port on the board: uart1 and uart2, Zephyr is using
 uart2 as serial console.
 
diff --git a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp.dts b/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp.dts
new file mode 100644
index 00000000000..c91db189591
--- /dev/null
+++ b/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp.dts
@@ -0,0 +1,102 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <arm64/armv8-a.dtsi>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <mem.h>
+
+/ {
+	model = "NXP ls1046a RDB";
+	compatible = "fsl,ls1046ardb";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen {
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,sram = &sram0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <1>;
+		};
+
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <2>;
+		};
+
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <3>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+		label = "PSCI";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>;
+		label = "arch_timer";
+	};
+
+	gic: interrupt-controller@1410000 {
+		compatible = "arm,gic";
+		reg = <0x01410000 0x10000>, /* GICD */
+		      <0x0142f000 0x1000>; /* GICC */
+		interrupt-controller;
+		#interrupt-cells = <4>;
+			label = "GIC";
+		status = "okay";
+	};
+
+	uart1: serial@21c0600 {
+			compatible = "fsl,ns16550", "ns16550";
+			reg = <0x21c0600 0x100>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clock-frequency = <350000000>;
+			label = "UART_1";
+		};
+
+	sram0: memory@c0000000 {
+		       reg = <0xc0000000 DT_SIZE_M(1)>;
+	       };
+
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+};
diff --git a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp.yaml b/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp.yaml
new file mode 100644
index 00000000000..221aaf872e3
--- /dev/null
+++ b/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp.yaml
@@ -0,0 +1,8 @@
+identifier: nxp_ls1046ardb_smp
+name: NXP LS1046ARDB SMP
+type: mcu
+arch: arm64
+toolchain:
+  - zephyr
+  - cross-compile
+ram: 1024
diff --git a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_defconfig b/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_defconfig
new file mode 100644
index 00000000000..a631363c286
--- /dev/null
+++ b/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_defconfig
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Platform Configuration
+CONFIG_SOC_SERIES_LS1046A=y
+CONFIG_SOC_LS1046A=y
+CONFIG_BOARD_NXP_LS1046ARDB=y
+CONFIG_ARM64_VA_BITS_40=y
+CONFIG_ARM64_PA_BITS_40=y
+# 1.8GHz system clock
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1800000000
+
+# Zephyr Kernel Configuration
+CONFIG_XIP=n
+CONFIG_AARCH64_IMAGE_HEADER=y
+CONFIG_MAX_THREAD_BYTES=5
+CONFIG_MAX_XLAT_TABLES=10
+
+# SMP support
+CONFIG_SMP=y
+CONFIG_MP_NUM_CPUS=4
+CONFIG_CACHE_MANAGEMENT=y
+CONFIG_ARMV8_A_NS=y
+
+# PSCI is supported
+CONFIG_PM_CPU_OPS=y
+CONFIG_PM_CPU_OPS_PSCI=y
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_UART_NS16550=y
+
+# Enable Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y