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soc: imx: imx95: enable cache management for M7

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Enable cache management for the M7-based i.MX95 soc.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This commit is contained in:
Laurentiu Mihalcea 2024-09-18 11:24:44 +03:00 • committed by Alberto Escolar
commit 848907c0f8
4 changed files with 22 additions and 0 deletions
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1
soc/nxp/imx/imx9/imx95/Kconfig
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@ -10,6 +10,7 @@ config SOC_MIMX9596_M7
select CPU_HAS_DCACHE select CPU_HAS_DCACHE
select CPU_HAS_ARM_MPU select CPU_HAS_ARM_MPU
select ARM_MPU select ARM_MPU
select SOC_LATE_INIT_HOOK
select HAS_MCUX select HAS_MCUX
config SOC_MIMX9596_A55 config SOC_MIMX9596_A55

3
soc/nxp/imx/imx9/imx95/Kconfig.defconfig.mimx95.m7
View file

@ -19,4 +19,7 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
int int
default 800000000 default 800000000
config CACHE_MANAGEMENT
default y
endif # SOC_MIMX9596_M7 endif # SOC_MIMX9596_M7

3
soc/nxp/imx/imx9/imx95/m7/CMakeLists.txt
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@ -2,4 +2,7 @@
zephyr_include_directories(.) zephyr_include_directories(.)
zephyr_library()
zephyr_library_sources(soc.c)
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

15
soc/nxp/imx/imx9/imx95/m7/soc.c Normal file
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@ -0,0 +1,15 @@
/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/cache.h>
void soc_late_init_hook(void)
{
#ifdef CONFIG_CACHE_MANAGEMENT
sys_cache_data_enable();
sys_cache_instr_enable();
#endif /* CONFIG_CACHE_MANAGEMENT */
}