diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index a7832472821..8f426d09d3f 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -1,4 +1,5 @@ # Copyright (c) 2016 Jean-Paul Etienne +# Copyright (c) 2024 Antmicro # SPDX-License-Identifier: Apache-2.0 menu "RISCV Options" @@ -375,6 +376,15 @@ config NULL_POINTER_EXCEPTION_REGION_SIZE endif # NULL_POINTER_EXCEPTION_DETECTION_PMP +config RISCV_IMPRECISE_FPU_STATE_TRACKING + bool "Imprecise implementation of FPU state tracking" + depends on FPU + help + According to the RISC-V Instruction Set Manual: Volume II, Version 20240411 + (Section 3.1.6.6), some implementations may choose to track the dirtiness of + the floating-point register state imprecisely by reporting the state to be + dirty even when it has not been modified. This option reflects that. + endmenu config MAIN_STACK_SIZE diff --git a/tests/arch/riscv/fpu_sharing/testcase.yaml b/tests/arch/riscv/fpu_sharing/testcase.yaml index 2ec10f2aa26..797f750f893 100644 --- a/tests/arch/riscv/fpu_sharing/testcase.yaml +++ b/tests/arch/riscv/fpu_sharing/testcase.yaml @@ -1,4 +1,4 @@ tests: arch.riscv.fpu_sharing: arch_allow: riscv - filter: CONFIG_CPU_HAS_FPU + filter: CONFIG_CPU_HAS_FPU and not CONFIG_RISCV_IMPRECISE_FPU_STATE_TRACKING