michaelh/zephyr
1
0
Fork 0
Code Releases Activity

drivers/clock_control: fix: stm32wb series has only a single msi range

Browse source 
stm32wb only has a single msi clock range, in contrast to wl, l4, l5
which have a second range that is active after exit from standby mode.
This difference must be taken account of in the driver.

This commit abstracts __LL_RCC_CALC_MSI_FREQ macro such that all series
can be supported, additionally the switch to the msirange
(LL_RCC_MSI_EnableRangeSelection) is now only executed on series
that support it.

As a result stm32wb socs can use msi as sysclock.
The same should be done for stm32l0, but this commit series limits
the scope of socs to avoid getting too bloated.

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit is contained in:
Thomas Stranger 2021-05-03 14:33:06 +02:00 • committed by Kumar Gala
commit 844277f4aa
1 changed files with 16 additions and 8 deletions
Download patch file Download diff file Expand all files Collapse all files

24
drivers/clock_control/clock_stm32_ll_common.c
View file

@ -36,6 +36,15 @@
#define z_mco2_prescaler(v) LL_RCC_MCO2_DIV_ ## v
#define mco2_prescaler(v) z_mco2_prescaler(v)
/* Calculate MSI freq for the given range(at RUN range, not after standby) */
#if defined(CONFIG_SOC_SERIES_STM32WBX)
#define RCC_CALC_MSI_RUN_FREQ(range) __LL_RCC_CALC_MSI_FREQ( \
range << RCC_CR_MSIRANGE_Pos)
#else
#define RCC_CALC_MSI_RUN_FREQ(range) __LL_RCC_CALC_MSI_FREQ( \
LL_RCC_MSIRANGESEL_RUN, range << RCC_CR_MSIRANGE_Pos)
#endif
#if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(CONFIG_SOC_SERIES_STM32WLX)
#define __LL_RCC_CALC_HCLK_FREQ __LL_RCC_CALC_HCLK1_FREQ
#endif /* CONFIG_SOC_SERIES_STM32F0X */
@ -401,7 +410,9 @@ int stm32_clock_control_init(const struct device *dev)
#if STM32_PLL_SRC_MSI
/* Set MSI Range */
#if !defined(CONFIG_SOC_SERIES_STM32WBX)
LL_RCC_MSI_EnableRangeSelection();
#endif
LL_RCC_MSI_SetRange(STM32_MSI_RANGE << RCC_CR_MSIRANGE_Pos);
LL_RCC_MSI_SetCalibTrimming(0);
@ -523,14 +534,9 @@ int stm32_clock_control_init(const struct device *dev)
#elif STM32_SYSCLK_SRC_MSI
old_hclk_freq = HAL_RCC_GetHCLKFreq();
/* Calculate new SystemCoreClock variable with MSI freq */
/* MSI freq is defined from RUN range selection */
new_hclk_freq =
__LL_RCC_CALC_HCLK_FREQ(
__LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGESEL_RUN,
STM32_MSI_RANGE << RCC_CR_MSIRANGE_Pos),
hclk_prescaler);
new_hclk_freq = __LL_RCC_CALC_HCLK_FREQ(
RCC_CALC_MSI_RUN_FREQ(STM32_MSI_RANGE),
hclk_prescaler);
#if defined(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC)
__ASSERT(new_hclk_freq == CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
@ -544,7 +550,9 @@ int stm32_clock_control_init(const struct device *dev)
}
/* Set MSI Range */
#if !defined(CONFIG_SOC_SERIES_STM32WBX)
LL_RCC_MSI_EnableRangeSelection();
#endif
LL_RCC_MSI_SetRange(STM32_MSI_RANGE << RCC_CR_MSIRANGE_Pos);
#if STM32_MSI_PLL_MODE