From 83fe349ad5661e93824eb35a90dae20bb09cf24e Mon Sep 17 00:00:00 2001 From: Khanh Nguyen Date: Fri, 28 Mar 2025 13:40:15 +0700 Subject: [PATCH] dts: arm: renesas: ra: add ELC node and enums for RA SoCs Add ELC nodes to RA SoC DTS files and provide device-specific ELC signal enums for Devicetree bindings Signed-off-by: Khanh Nguyen --- dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi | 2 + dts/arm/renesas/ra/ra2/ra2l1.dtsi | 11 +- dts/arm/renesas/ra/ra2/ra2xx.dtsi | 9 + dts/arm/renesas/ra/ra4/r7fa4e10x.dtsi | 1 + dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi | 1 + dts/arm/renesas/ra/ra4/r7fa4l1bx.dtsi | 9 + dts/arm/renesas/ra/ra4/r7fa4m1ax.dtsi | 1 + dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi | 3 +- dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi | 3 +- dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi | 3 +- dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi | 8 + dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi | 10 +- dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi | 1 + dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi | 3 +- dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi | 1 + dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi | 3 +- dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi | 3 +- dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi | 3 +- dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi | 3 +- dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi | 8 + dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi | 8 + dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi | 3 +- dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi | 3 +- dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi | 3 +- dts/arm/renesas/ra/ra8/ra8x1.dtsi | 8 + .../misc/renesas/ra-elc/ra2a1-elc.h | 169 ++++++++ .../misc/renesas/ra-elc/ra2l1-elc.h | 188 +++++++++ .../misc/renesas/ra-elc/ra4e1-elc.h | 175 ++++++++ .../misc/renesas/ra-elc/ra4e2-elc.h | 200 +++++++++ .../misc/renesas/ra-elc/ra4l1-elc.h | 242 +++++++++++ .../misc/renesas/ra-elc/ra4m1-elc.h | 211 ++++++++++ .../misc/renesas/ra-elc/ra4m2-elc.h | 258 ++++++++++++ .../misc/renesas/ra-elc/ra4m3-elc.h | 271 +++++++++++++ .../misc/renesas/ra-elc/ra4w1-elc.h | 196 +++++++++ .../misc/renesas/ra-elc/ra6e1-elc.h | 233 +++++++++++ .../misc/renesas/ra-elc/ra6e2-elc.h | 222 ++++++++++ .../misc/renesas/ra-elc/ra6m1-elc.h | 319 +++++++++++++++ .../misc/renesas/ra-elc/ra6m2-elc.h | 352 ++++++++++++++++ .../misc/renesas/ra-elc/ra6m3-elc.h | 380 ++++++++++++++++++ .../misc/renesas/ra-elc/ra6m4-elc.h | 314 +++++++++++++++ .../misc/renesas/ra-elc/ra6m5-elc.h | 335 +++++++++++++++ .../misc/renesas/ra-elc/ra8d1-elc.h | 364 +++++++++++++++++ .../misc/renesas/ra-elc/ra8m1-elc.h | 354 ++++++++++++++++ .../misc/renesas/ra-elc/ra8t1-elc.h | 337 ++++++++++++++++ 44 files changed, 5218 insertions(+), 13 deletions(-) create mode 100644 include/zephyr/dt-bindings/misc/renesas/ra-elc/ra2a1-elc.h create mode 100644 include/zephyr/dt-bindings/misc/renesas/ra-elc/ra2l1-elc.h create mode 100644 include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4e1-elc.h create mode 100644 include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4e2-elc.h create mode 100644 include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4l1-elc.h create mode 100644 include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4m1-elc.h create mode 100644 include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4m2-elc.h create mode 100644 include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4m3-elc.h create mode 100644 include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4w1-elc.h create mode 100644 include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6e1-elc.h create mode 100644 include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6e2-elc.h create mode 100644 include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6m1-elc.h create mode 100644 include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6m2-elc.h create mode 100644 include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6m3-elc.h create mode 100644 include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6m4-elc.h create mode 100644 include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6m5-elc.h create mode 100644 include/zephyr/dt-bindings/misc/renesas/ra-elc/ra8d1-elc.h create mode 100644 include/zephyr/dt-bindings/misc/renesas/ra-elc/ra8m1-elc.h create mode 100644 include/zephyr/dt-bindings/misc/renesas/ra-elc/ra8t1-elc.h diff --git a/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi b/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi index d6e38b79bc3..053bc9ac165 100644 --- a/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi +++ b/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2024 TOKITA Hiroshi + * Copyright (c) 2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +8,7 @@ #include #include #include +#include /delete-node/ &sci2; /delete-node/ &sci3; diff --git a/dts/arm/renesas/ra/ra2/ra2l1.dtsi b/dts/arm/renesas/ra/ra2/ra2l1.dtsi index c8a41ea46fd..7e02b13ad0f 100644 --- a/dts/arm/renesas/ra/ra2/ra2l1.dtsi +++ b/dts/arm/renesas/ra/ra2/ra2l1.dtsi @@ -1,6 +1,6 @@ /** * Copyright (c) 2021-2024 MUNIC SA - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * Renesas RA2L1 MCU series device tree * @@ -12,6 +12,7 @@ #include #include #include +#include / { cpus { @@ -46,6 +47,14 @@ status = "okay"; }; + elc: elc@40041000 { + compatible = "renesas,ra-elc"; + reg = <0x40041000 0x6c>; + #renesas-elc-cells = <2>; + clocks = <&pclkb MSTPC 14>; + status = "disabled"; + }; + flcn: flash-controller@407ec000 { reg = <0x407ec000 0x10000>; diff --git a/dts/arm/renesas/ra/ra2/ra2xx.dtsi b/dts/arm/renesas/ra/ra2/ra2xx.dtsi index 2d9807c2787..2924b028e19 100644 --- a/dts/arm/renesas/ra/ra2/ra2xx.dtsi +++ b/dts/arm/renesas/ra/ra2/ra2xx.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2024 TOKITA Hiroshi + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ @@ -30,6 +31,14 @@ status = "okay"; }; + elc: elc@40041000 { + compatible = "renesas,ra-elc"; + reg = <0x40041000 0x6c>; + #renesas-elc-cells = <2>; + clocks = <&pclkb MSTPC 14>; + status = "disabled"; + }; + ioport0: gpio@40040000 { compatible = "renesas,ra-gpio-ioport"; reg = <0x40040000 0x20>; diff --git a/dts/arm/renesas/ra/ra4/r7fa4e10x.dtsi b/dts/arm/renesas/ra/ra4/r7fa4e10x.dtsi index 33baec96894..017005f0e56 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4e10x.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4e10x.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include /delete-node/ &spi1; /delete-node/ &agt4; diff --git a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi index f611aee538f..3bd77819bd3 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi @@ -6,6 +6,7 @@ #include #include +#include /delete-node/ &agt0; /delete-node/ &agt1; diff --git a/dts/arm/renesas/ra/ra4/r7fa4l1bx.dtsi b/dts/arm/renesas/ra/ra4/r7fa4l1bx.dtsi index 06c8139ab5b..f04a0c795fc 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4l1bx.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4l1bx.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include / { @@ -39,6 +40,14 @@ status = "okay"; }; + elc: elc@40082000 { + compatible = "renesas,ra-elc"; + reg = <0x40082000 0x70>; + #renesas-elc-cells = <2>; + clocks = <&pclkb MSTPC 14>; + status = "disabled"; + }; + sram0: memory@20000000 { compatible = "mmio-sram"; reg = <0x20000000 DT_SIZE_K(64)>; diff --git a/dts/arm/renesas/ra/ra4/r7fa4m1ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m1ax.dtsi index 1a0570dc064..88f1ccd1aa3 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4m1ax.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4m1ax.dtsi @@ -6,6 +6,7 @@ #include #include +#include / { soc { diff --git a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi index fcbf52a9b12..51deca4f154 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +7,7 @@ #include #include #include +#include /delete-node/ &spi1; diff --git a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi index 019a3947d21..5e0c9be2bf7 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +7,7 @@ #include #include #include +#include /delete-node/ &spi1; diff --git a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi index 44af76cf559..14a8bd51faf 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +7,7 @@ #include #include #include +#include / { soc { diff --git a/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi b/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi index aa88f96a304..4423fa9c8e9 100644 --- a/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi +++ b/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi @@ -38,6 +38,14 @@ status = "okay"; }; + elc: elc@40082000 { + compatible = "renesas,ra-elc"; + reg = <0x40082000 0x70>; + #renesas-elc-cells = <2>; + clocks = <&pclkb MSTPC 14>; + status = "disabled"; + }; + flash: flash-controller@407e0000 { compatible = "renesas,ra-flash-hp-controller"; reg = <0x407e0000 0x10000>; diff --git a/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi b/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi index 5234212dd28..7319a75f79f 100644 --- a/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi +++ b/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ @@ -37,6 +37,14 @@ status = "okay"; }; + elc: elc@40041000 { + compatible = "renesas,ra-elc"; + reg = <0x40041000 0x70>; + #renesas-elc-cells = <2>; + clocks = <&pclkb MSTPC 14>; + status = "disabled"; + }; + flash-controller@407e0000 { reg = <0x407e0000 0x10000>; #address-cells = <1>; diff --git a/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi index 7eb89905448..8ebba8a22ba 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include /delete-node/ &adc1; /delete-node/ &dac1; diff --git a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi index 1efe5c8ab31..68336cafa89 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +7,7 @@ #include #include #include +#include /delete-node/ &agt0; /delete-node/ &agt1; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi index 784689fcf73..6fd22614366 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi @@ -6,6 +6,7 @@ #include #include +#include /delete-node/ ð /delete-node/ &mdio; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi index 5a07efd2800..0908d4e6545 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +7,7 @@ #include #include #include +#include /delete-node/ ð /delete-node/ &mdio; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi index 78e71409cc9..d0d96a1ec1d 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +7,7 @@ #include #include #include +#include / { soc { diff --git a/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi index e629ed5b3fa..83a19e70135 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +7,7 @@ #include #include #include +#include / { soc { diff --git a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi index 4675d23d6b2..e130b075513 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +7,7 @@ #include #include #include +#include / { soc { diff --git a/dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi b/dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi index daeabd1e3f8..9625343ec27 100644 --- a/dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi +++ b/dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi @@ -39,6 +39,14 @@ status = "okay"; }; + elc: elc@40082000 { + compatible = "renesas,ra-elc"; + reg = <0x40082000 0x70>; + #renesas-elc-cells = <2>; + clocks = <&pclkb MSTPC 14>; + status = "disabled"; + }; + ioport0: gpio@40080000 { compatible = "renesas,ra-gpio-ioport"; reg = <0x40080000 0x20>; diff --git a/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi b/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi index 191e14252fa..dd2c9cacddf 100644 --- a/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi +++ b/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi @@ -38,6 +38,14 @@ status = "okay"; }; + elc: elc@40041000 { + compatible = "renesas,ra-elc"; + reg = <0x40041000 0x70>; + #renesas-elc-cells = <2>; + clocks = <&pclkb MSTPC 14>; + status = "disabled"; + }; + ioport0: gpio@40040000 { compatible = "renesas,ra-gpio-ioport"; reg = <0x40040000 0x20>; diff --git a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi index 629908e00e4..e1abfa50248 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi @@ -1,11 +1,12 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ #include #include +#include / { soc { diff --git a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi index 88661e3abfe..60fbd8c287e 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi @@ -1,11 +1,12 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ #include #include +#include / { clocks: clocks { diff --git a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi index 9c45b770951..489d74ce78f 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi @@ -1,11 +1,12 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ #include #include +#include / { clocks: clocks { diff --git a/dts/arm/renesas/ra/ra8/ra8x1.dtsi b/dts/arm/renesas/ra/ra8/ra8x1.dtsi index 95920b98671..58e4c07b7ad 100644 --- a/dts/arm/renesas/ra/ra8/ra8x1.dtsi +++ b/dts/arm/renesas/ra/ra8/ra8x1.dtsi @@ -60,6 +60,14 @@ status = "okay"; }; + elc: elc@40201000 { + compatible = "renesas,ra-elc"; + reg = <0x40201000 0xf8>; + #renesas-elc-cells = <2>; + clocks = <&pclkb MSTPC 14>; + status = "disabled"; + }; + pinctrl: pin-controller@40400800 { compatible = "renesas,ra-pinctrl-pfs"; reg = <0x40400800 0x3c0>; diff --git a/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra2a1-elc.h b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra2a1-elc.h new file mode 100644 index 00000000000..b6c1e7efd4f --- /dev/null +++ b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra2a1-elc.h @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA2A1_ELC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA2A1_ELC_H_ + +/* Sources of event signals to be linked to other peripherals or the CPU */ +#define RA_ELC_EVENT_NONE 0x0 +#define RA_ELC_EVENT_ICU_IRQ0 0x001 +#define RA_ELC_EVENT_ICU_IRQ1 0x002 +#define RA_ELC_EVENT_ICU_IRQ2 0x003 +#define RA_ELC_EVENT_ICU_IRQ3 0x004 +#define RA_ELC_EVENT_ICU_IRQ4 0x005 +#define RA_ELC_EVENT_ICU_IRQ5 0x006 +#define RA_ELC_EVENT_ICU_IRQ6 0x007 +#define RA_ELC_EVENT_ICU_IRQ7 0x008 +#define RA_ELC_EVENT_DTC_COMPLETE 0x009 +#define RA_ELC_EVENT_DTC_END 0x00A +#define RA_ELC_EVENT_ICU_SNOOZE_CANCEL 0x00B +#define RA_ELC_EVENT_FCU_FRDYI 0x00C +#define RA_ELC_EVENT_LVD_LVD1 0x00D +#define RA_ELC_EVENT_LVD_LVD2 0x00E +#define RA_ELC_EVENT_CGC_MOSC_STOP 0x00F +#define RA_ELC_EVENT_LPM_SNOOZE_REQUEST 0x010 +#define RA_ELC_EVENT_AGT0_INT 0x011 +#define RA_ELC_EVENT_AGT0_COMPARE_A 0x012 +#define RA_ELC_EVENT_AGT0_COMPARE_B 0x013 +#define RA_ELC_EVENT_AGT1_INT 0x014 +#define RA_ELC_EVENT_AGT1_COMPARE_A 0x015 +#define RA_ELC_EVENT_AGT1_COMPARE_B 0x016 +#define RA_ELC_EVENT_IWDT_UNDERFLOW 0x017 +#define RA_ELC_EVENT_WDT_UNDERFLOW 0x018 +#define RA_ELC_EVENT_RTC_ALARM 0x019 +#define RA_ELC_EVENT_RTC_PERIOD 0x01A +#define RA_ELC_EVENT_RTC_CARRY 0x01B +#define RA_ELC_EVENT_ADC0_SCAN_END 0x01C +#define RA_ELC_EVENT_ADC0_SCAN_END_B 0x01D +#define RA_ELC_EVENT_ADC0_WINDOW_A 0x01E +#define RA_ELC_EVENT_ADC0_WINDOW_B 0x01F +#define RA_ELC_EVENT_ADC0_COMPARE_MATCH 0x020 +#define RA_ELC_EVENT_ADC0_COMPARE_MISMATCH 0x021 +#define RA_ELC_EVENT_ACMPHS0_INT 0x022 +#define RA_ELC_EVENT_ACMPLP0_INT 0x023 +#define RA_ELC_EVENT_ACMPLP1_INT 0x024 +#define RA_ELC_EVENT_USBFS_INT 0x025 +#define RA_ELC_EVENT_USBFS_RESUME 0x026 +#define RA_ELC_EVENT_IIC0_RXI 0x027 +#define RA_ELC_EVENT_IIC0_TXI 0x028 +#define RA_ELC_EVENT_IIC0_TEI 0x029 +#define RA_ELC_EVENT_IIC0_ERI 0x02A +#define RA_ELC_EVENT_IIC0_WUI 0x02B +#define RA_ELC_EVENT_IIC1_RXI 0x02C +#define RA_ELC_EVENT_IIC1_TXI 0x02D +#define RA_ELC_EVENT_IIC1_TEI 0x02E +#define RA_ELC_EVENT_IIC1_ERI 0x02F +#define RA_ELC_EVENT_CTSU_WRITE 0x030 +#define RA_ELC_EVENT_CTSU_READ 0x031 +#define RA_ELC_EVENT_CTSU_END 0x032 +#define RA_ELC_EVENT_KEY_INT 0x033 +#define RA_ELC_EVENT_DOC_INT 0x034 +#define RA_ELC_EVENT_CAC_FREQUENCY_ERROR 0x035 +#define RA_ELC_EVENT_CAC_MEASUREMENT_END 0x036 +#define RA_ELC_EVENT_CAC_OVERFLOW 0x037 +#define RA_ELC_EVENT_CAN0_ERROR 0x038 +#define RA_ELC_EVENT_CAN0_FIFO_RX 0x039 +#define RA_ELC_EVENT_CAN0_FIFO_TX 0x03A +#define RA_ELC_EVENT_CAN0_MAILBOX_RX 0x03B +#define RA_ELC_EVENT_CAN0_MAILBOX_TX 0x03C +#define RA_ELC_EVENT_IOPORT_EVENT_1 0x03D +#define RA_ELC_EVENT_IOPORT_EVENT_2 0x03E +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0 0x03F +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1 0x040 +#define RA_ELC_EVENT_POEG0_EVENT 0x041 +#define RA_ELC_EVENT_POEG1_EVENT 0x042 +#define RA_ELC_EVENT_SDADC0_ADI 0x043 +#define RA_ELC_EVENT_SDADC0_SCANEND 0x044 +#define RA_ELC_EVENT_SDADC0_CALIEND 0x045 +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_A 0x046 +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_B 0x047 +#define RA_ELC_EVENT_GPT0_COMPARE_C 0x048 +#define RA_ELC_EVENT_GPT0_COMPARE_D 0x049 +#define RA_ELC_EVENT_GPT0_COUNTER_OVERFLOW 0x04A +#define RA_ELC_EVENT_GPT0_COUNTER_UNDERFLOW 0x04B +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_A 0x04C +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_B 0x04D +#define RA_ELC_EVENT_GPT1_COMPARE_C 0x04E +#define RA_ELC_EVENT_GPT1_COMPARE_D 0x04F +#define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x050 +#define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x051 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_A 0x052 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_B 0x053 +#define RA_ELC_EVENT_GPT2_COMPARE_C 0x054 +#define RA_ELC_EVENT_GPT2_COMPARE_D 0x055 +#define RA_ELC_EVENT_GPT2_COUNTER_OVERFLOW 0x056 +#define RA_ELC_EVENT_GPT2_COUNTER_UNDERFLOW 0x057 +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_A 0x058 +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_B 0x059 +#define RA_ELC_EVENT_GPT3_COMPARE_C 0x05A +#define RA_ELC_EVENT_GPT3_COMPARE_D 0x05B +#define RA_ELC_EVENT_GPT3_COUNTER_OVERFLOW 0x05C +#define RA_ELC_EVENT_GPT3_COUNTER_UNDERFLOW 0x05D +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_A 0x05E +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_B 0x05F +#define RA_ELC_EVENT_GPT4_COMPARE_C 0x060 +#define RA_ELC_EVENT_GPT4_COMPARE_D 0x061 +#define RA_ELC_EVENT_GPT4_COUNTER_OVERFLOW 0x062 +#define RA_ELC_EVENT_GPT4_COUNTER_UNDERFLOW 0x063 +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_A 0x064 +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_B 0x065 +#define RA_ELC_EVENT_GPT5_COMPARE_C 0x066 +#define RA_ELC_EVENT_GPT5_COMPARE_D 0x067 +#define RA_ELC_EVENT_GPT5_COUNTER_OVERFLOW 0x068 +#define RA_ELC_EVENT_GPT5_COUNTER_UNDERFLOW 0x069 +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_A 0x06A +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_B 0x06B +#define RA_ELC_EVENT_GPT6_COMPARE_C 0x06C +#define RA_ELC_EVENT_GPT6_COMPARE_D 0x06D +#define RA_ELC_EVENT_GPT6_COUNTER_OVERFLOW 0x06E +#define RA_ELC_EVENT_GPT6_COUNTER_UNDERFLOW 0x06F +#define RA_ELC_EVENT_OPS_UVW_EDGE 0x070 +#define RA_ELC_EVENT_SCI0_RXI 0x071 +#define RA_ELC_EVENT_SCI0_TXI 0x072 +#define RA_ELC_EVENT_SCI0_TEI 0x073 +#define RA_ELC_EVENT_SCI0_ERI 0x074 +#define RA_ELC_EVENT_SCI0_AM 0x075 +#define RA_ELC_EVENT_SCI0_RXI_OR_ERI 0x076 +#define RA_ELC_EVENT_SCI1_RXI 0x077 +#define RA_ELC_EVENT_SCI1_TXI 0x078 +#define RA_ELC_EVENT_SCI1_TEI 0x079 +#define RA_ELC_EVENT_SCI1_ERI 0x07A +#define RA_ELC_EVENT_SCI1_AM 0x07B +#define RA_ELC_EVENT_SCI9_RXI 0x07C +#define RA_ELC_EVENT_SCI9_TXI 0x07D +#define RA_ELC_EVENT_SCI9_TEI 0x07E +#define RA_ELC_EVENT_SCI9_ERI 0x07F +#define RA_ELC_EVENT_SCI9_AM 0x080 +#define RA_ELC_EVENT_SPI0_RXI 0x081 +#define RA_ELC_EVENT_SPI0_TXI 0x082 +#define RA_ELC_EVENT_SPI0_IDLE 0x083 +#define RA_ELC_EVENT_SPI0_ERI 0x084 +#define RA_ELC_EVENT_SPI0_TEI 0x085 +#define RA_ELC_EVENT_SPI1_RXI 0x086 +#define RA_ELC_EVENT_SPI1_TXI 0x087 +#define RA_ELC_EVENT_SPI1_IDLE 0x088 +#define RA_ELC_EVENT_SPI1_ERI 0x089 +#define RA_ELC_EVENT_SPI1_TEI 0x08A +#define RA_ELC_EVENT_AES_WRREQ 0x08B +#define RA_ELC_EVENT_AES_RDREQ 0x08C +#define RA_ELC_EVENT_TRNG_RDREQ 0x08D + +/* Possible peripherals to be linked to event signals */ +#define RA_ELC_PERIPHERAL_GPT_A 0 +#define RA_ELC_PERIPHERAL_GPT_B 1 +#define RA_ELC_PERIPHERAL_GPT_C 2 +#define RA_ELC_PERIPHERAL_GPT_D 3 +#define RA_ELC_PERIPHERAL_ADC0 8 +#define RA_ELC_PERIPHERAL_ADC0_B 9 +#define RA_ELC_PERIPHERAL_DAC0 12 +#define RA_ELC_PERIPHERAL_IOPORT1 14 +#define RA_ELC_PERIPHERAL_IOPORT2 15 +#define RA_ELC_PERIPHERAL_CTSU 18 +#define RA_ELC_PERIPHERAL_DA8_0 19 +#define RA_ELC_PERIPHERAL_DA8_1 20 +#define RA_ELC_PERIPHERAL_SDADC0 22 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA2A1_ELC_H_ */ diff --git a/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra2l1-elc.h b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra2l1-elc.h new file mode 100644 index 00000000000..cb73ffcf9fa --- /dev/null +++ b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra2l1-elc.h @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA2L1_ELC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA2L1_ELC_H_ + +/* Sources of event signals to be linked to other peripherals or the CPU */ +#define RA_ELC_EVENT_NONE 0x0 +#define RA_ELC_EVENT_ICU_IRQ0 0x001 +#define RA_ELC_EVENT_ICU_IRQ1 0x002 +#define RA_ELC_EVENT_ICU_IRQ2 0x003 +#define RA_ELC_EVENT_ICU_IRQ3 0x004 +#define RA_ELC_EVENT_ICU_IRQ4 0x005 +#define RA_ELC_EVENT_ICU_IRQ5 0x006 +#define RA_ELC_EVENT_ICU_IRQ6 0x007 +#define RA_ELC_EVENT_ICU_IRQ7 0x008 +#define RA_ELC_EVENT_DTC_COMPLETE 0x009 +#define RA_ELC_EVENT_DTC_END 0x00A +#define RA_ELC_EVENT_ICU_SNOOZE_CANCEL 0x00B +#define RA_ELC_EVENT_FCU_FRDYI 0x00C +#define RA_ELC_EVENT_LVD_LVD1 0x00D +#define RA_ELC_EVENT_LVD_LVD2 0x00E +#define RA_ELC_EVENT_CGC_MOSC_STOP 0x00F +#define RA_ELC_EVENT_LPM_SNOOZE_REQUEST 0x010 +#define RA_ELC_EVENT_AGT0_INT 0x011 +#define RA_ELC_EVENT_AGT0_COMPARE_A 0x012 +#define RA_ELC_EVENT_AGT0_COMPARE_B 0x013 +#define RA_ELC_EVENT_AGT1_INT 0x014 +#define RA_ELC_EVENT_AGT1_COMPARE_A 0x015 +#define RA_ELC_EVENT_AGT1_COMPARE_B 0x016 +#define RA_ELC_EVENT_IWDT_UNDERFLOW 0x017 +#define RA_ELC_EVENT_WDT_UNDERFLOW 0x018 +#define RA_ELC_EVENT_RTC_ALARM 0x019 +#define RA_ELC_EVENT_RTC_PERIOD 0x01A +#define RA_ELC_EVENT_RTC_CARRY 0x01B +#define RA_ELC_EVENT_ADC0_SCAN_END 0x01C +#define RA_ELC_EVENT_ADC0_SCAN_END_B 0x01D +#define RA_ELC_EVENT_ADC0_WINDOW_A 0x01E +#define RA_ELC_EVENT_ADC0_WINDOW_B 0x01F +#define RA_ELC_EVENT_ADC0_COMPARE_MATCH 0x020 +#define RA_ELC_EVENT_ADC0_COMPARE_MISMATCH 0x021 +#define RA_ELC_EVENT_ACMPLP0_INT 0x023 +#define RA_ELC_EVENT_ACMPLP1_INT 0x024 +#define RA_ELC_EVENT_IIC0_RXI 0x027 +#define RA_ELC_EVENT_IIC0_TXI 0x028 +#define RA_ELC_EVENT_IIC0_TEI 0x029 +#define RA_ELC_EVENT_IIC0_ERI 0x02A +#define RA_ELC_EVENT_IIC0_WUI 0x02B +#define RA_ELC_EVENT_IIC1_RXI 0x02C +#define RA_ELC_EVENT_IIC1_TXI 0x02D +#define RA_ELC_EVENT_IIC1_TEI 0x02E +#define RA_ELC_EVENT_IIC1_ERI 0x02F +#define RA_ELC_EVENT_CTSU_WRITE 0x030 +#define RA_ELC_EVENT_CTSU_READ 0x031 +#define RA_ELC_EVENT_CTSU_END 0x032 +#define RA_ELC_EVENT_KEY_INT 0x033 +#define RA_ELC_EVENT_DOC_INT 0x034 +#define RA_ELC_EVENT_CAC_FREQUENCY_ERROR 0x035 +#define RA_ELC_EVENT_CAC_MEASUREMENT_END 0x036 +#define RA_ELC_EVENT_CAC_OVERFLOW 0x037 +#define RA_ELC_EVENT_CAN0_ERROR 0x038 +#define RA_ELC_EVENT_CAN0_FIFO_RX 0x039 +#define RA_ELC_EVENT_CAN0_FIFO_TX 0x03A +#define RA_ELC_EVENT_CAN0_MAILBOX_RX 0x03B +#define RA_ELC_EVENT_CAN0_MAILBOX_TX 0x03C +#define RA_ELC_EVENT_IOPORT_EVENT_1 0x03D +#define RA_ELC_EVENT_IOPORT_EVENT_2 0x03E +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0 0x03F +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1 0x040 +#define RA_ELC_EVENT_POEG0_EVENT 0x041 +#define RA_ELC_EVENT_POEG1_EVENT 0x042 +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_A 0x046 +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_B 0x047 +#define RA_ELC_EVENT_GPT0_COMPARE_C 0x048 +#define RA_ELC_EVENT_GPT0_COMPARE_D 0x049 +#define RA_ELC_EVENT_GPT0_COUNTER_OVERFLOW 0x04A +#define RA_ELC_EVENT_GPT0_COUNTER_UNDERFLOW 0x04B +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_A 0x04C +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_B 0x04D +#define RA_ELC_EVENT_GPT1_COMPARE_C 0x04E +#define RA_ELC_EVENT_GPT1_COMPARE_D 0x04F +#define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x050 +#define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x051 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_A 0x052 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_B 0x053 +#define RA_ELC_EVENT_GPT2_COMPARE_C 0x054 +#define RA_ELC_EVENT_GPT2_COMPARE_D 0x055 +#define RA_ELC_EVENT_GPT2_COUNTER_OVERFLOW 0x056 +#define RA_ELC_EVENT_GPT2_COUNTER_UNDERFLOW 0x057 +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_A 0x058 +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_B 0x059 +#define RA_ELC_EVENT_GPT3_COMPARE_C 0x05A +#define RA_ELC_EVENT_GPT3_COMPARE_D 0x05B +#define RA_ELC_EVENT_GPT3_COUNTER_OVERFLOW 0x05C +#define RA_ELC_EVENT_GPT3_COUNTER_UNDERFLOW 0x05D +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_A 0x05E +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_B 0x05F +#define RA_ELC_EVENT_GPT4_COMPARE_C 0x060 +#define RA_ELC_EVENT_GPT4_COMPARE_D 0x061 +#define RA_ELC_EVENT_GPT4_COUNTER_OVERFLOW 0x062 +#define RA_ELC_EVENT_GPT4_COUNTER_UNDERFLOW 0x063 +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_A 0x064 +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_B 0x065 +#define RA_ELC_EVENT_GPT5_COMPARE_C 0x066 +#define RA_ELC_EVENT_GPT5_COMPARE_D 0x067 +#define RA_ELC_EVENT_GPT5_COUNTER_OVERFLOW 0x068 +#define RA_ELC_EVENT_GPT5_COUNTER_UNDERFLOW 0x069 +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_A 0x06A +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_B 0x06B +#define RA_ELC_EVENT_GPT6_COMPARE_C 0x06C +#define RA_ELC_EVENT_GPT6_COMPARE_D 0x06D +#define RA_ELC_EVENT_GPT6_COUNTER_OVERFLOW 0x06E +#define RA_ELC_EVENT_GPT6_COUNTER_UNDERFLOW 0x06F +#define RA_ELC_EVENT_GPT_UVWEDGE 0x070 +#define RA_ELC_EVENT_SCI0_RXI 0x071 +#define RA_ELC_EVENT_SCI0_TXI 0x072 +#define RA_ELC_EVENT_SCI0_TEI 0x073 +#define RA_ELC_EVENT_SCI0_ERI 0x074 +#define RA_ELC_EVENT_SCI0_AM 0x075 +#define RA_ELC_EVENT_SCI0_RXI_OR_ERI 0x076 +#define RA_ELC_EVENT_SCI1_RXI 0x077 +#define RA_ELC_EVENT_SCI1_TXI 0x078 +#define RA_ELC_EVENT_SCI1_TEI 0x079 +#define RA_ELC_EVENT_SCI1_ERI 0x07A +#define RA_ELC_EVENT_SCI1_AM 0x07B +#define RA_ELC_EVENT_SCI9_RXI 0x07C +#define RA_ELC_EVENT_SCI9_TXI 0x07D +#define RA_ELC_EVENT_SCI9_TEI 0x07E +#define RA_ELC_EVENT_SCI9_ERI 0x07F +#define RA_ELC_EVENT_SCI9_AM 0x080 +#define RA_ELC_EVENT_SPI0_RXI 0x081 +#define RA_ELC_EVENT_SPI0_TXI 0x082 +#define RA_ELC_EVENT_SPI0_IDLE 0x083 +#define RA_ELC_EVENT_SPI0_ERI 0x084 +#define RA_ELC_EVENT_SPI0_TEI 0x085 +#define RA_ELC_EVENT_SPI1_RXI 0x086 +#define RA_ELC_EVENT_SPI1_TXI 0x087 +#define RA_ELC_EVENT_SPI1_IDLE 0x088 +#define RA_ELC_EVENT_SPI1_ERI 0x089 +#define RA_ELC_EVENT_SPI1_TEI 0x08A +#define RA_ELC_EVENT_AES_WRREQ 0x08B +#define RA_ELC_EVENT_AES_RDREQ 0x08C +#define RA_ELC_EVENT_TRNG_RDREQ 0x08D +#define RA_ELC_EVENT_SCI2_RXI 0x08E +#define RA_ELC_EVENT_SCI2_TXI 0x08F +#define RA_ELC_EVENT_SCI2_TEI 0x090 +#define RA_ELC_EVENT_SCI2_ERI 0x091 +#define RA_ELC_EVENT_SCI2_AM 0x092 +#define RA_ELC_EVENT_SCI3_RXI 0x093 +#define RA_ELC_EVENT_SCI3_TXI 0x094 +#define RA_ELC_EVENT_SCI3_TEI 0x095 +#define RA_ELC_EVENT_SCI3_ERI 0x096 +#define RA_ELC_EVENT_SCI3_AM 0x097 +#define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_A 0x098 +#define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_B 0x099 +#define RA_ELC_EVENT_GPT7_COMPARE_C 0x09A +#define RA_ELC_EVENT_GPT7_COMPARE_D 0x09B +#define RA_ELC_EVENT_GPT7_COUNTER_OVERFLOW 0x09C +#define RA_ELC_EVENT_GPT7_COUNTER_UNDERFLOW 0x09D +#define RA_ELC_EVENT_GPT8_CAPTURE_COMPARE_A 0x09E +#define RA_ELC_EVENT_GPT8_CAPTURE_COMPARE_B 0x09F +#define RA_ELC_EVENT_GPT8_COMPARE_C 0x0A0 +#define RA_ELC_EVENT_GPT8_COMPARE_D 0x0A1 +#define RA_ELC_EVENT_GPT8_COUNTER_OVERFLOW 0x0A2 +#define RA_ELC_EVENT_GPT8_COUNTER_UNDERFLOW 0x0A3 +#define RA_ELC_EVENT_GPT9_CAPTURE_COMPARE_A 0x0A4 +#define RA_ELC_EVENT_GPT9_CAPTURE_COMPARE_B 0x0A5 +#define RA_ELC_EVENT_GPT9_COMPARE_C 0x0A6 +#define RA_ELC_EVENT_GPT9_COMPARE_D 0x0A7 +#define RA_ELC_EVENT_GPT9_COUNTER_OVERFLOW 0x0A8 +#define RA_ELC_EVENT_GPT9_COUNTER_UNDERFLOW 0x0A9 + +/* Possible peripherals to be linked to event signals */ +#define RA_ELC_PERIPHERAL_GPT_A 0 +#define RA_ELC_PERIPHERAL_GPT_B 1 +#define RA_ELC_PERIPHERAL_GPT_C 2 +#define RA_ELC_PERIPHERAL_GPT_D 3 +#define RA_ELC_PERIPHERAL_ADC0 8 +#define RA_ELC_PERIPHERAL_ADC0_B 9 +#define RA_ELC_PERIPHERAL_DAC0 12 +#define RA_ELC_PERIPHERAL_IOPORT1 14 +#define RA_ELC_PERIPHERAL_IOPORT2 15 +#define RA_ELC_PERIPHERAL_CTSU 18 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA2L1_ELC_H_ */ diff --git a/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4e1-elc.h b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4e1-elc.h new file mode 100644 index 00000000000..5e04a41f525 --- /dev/null +++ b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4e1-elc.h @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4E1_ELC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4E1_ELC_H_ + +/* Sources of event signals to be linked to other peripherals or the CPU */ +#define RA_ELC_EVENT_NONE 0x0 +#define RA_ELC_EVENT_ICU_IRQ0 0x001 +#define RA_ELC_EVENT_ICU_IRQ1 0x002 +#define RA_ELC_EVENT_ICU_IRQ2 0x003 +#define RA_ELC_EVENT_ICU_IRQ3 0x004 +#define RA_ELC_EVENT_ICU_IRQ4 0x005 +#define RA_ELC_EVENT_ICU_IRQ5 0x006 +#define RA_ELC_EVENT_ICU_IRQ6 0x007 +#define RA_ELC_EVENT_ICU_IRQ7 0x008 +#define RA_ELC_EVENT_ICU_IRQ8 0x009 +#define RA_ELC_EVENT_ICU_IRQ9 0x00A +#define RA_ELC_EVENT_ICU_IRQ13 0x00E +#define RA_ELC_EVENT_DMAC0_INT 0x020 +#define RA_ELC_EVENT_DMAC1_INT 0x021 +#define RA_ELC_EVENT_DMAC2_INT 0x022 +#define RA_ELC_EVENT_DMAC3_INT 0x023 +#define RA_ELC_EVENT_DMAC4_INT 0x024 +#define RA_ELC_EVENT_DMAC5_INT 0x025 +#define RA_ELC_EVENT_DMAC6_INT 0x026 +#define RA_ELC_EVENT_DMAC7_INT 0x027 +#define RA_ELC_EVENT_DTC_COMPLETE 0x029 +#define RA_ELC_EVENT_DTC_END 0x02A +#define RA_ELC_EVENT_DMA_TRANSERR 0x02B +#define RA_ELC_EVENT_ICU_SNOOZE_CANCEL 0x02D +#define RA_ELC_EVENT_FCU_FIFERR 0x030 +#define RA_ELC_EVENT_FCU_FRDYI 0x031 +#define RA_ELC_EVENT_LVD_LVD1 0x038 +#define RA_ELC_EVENT_LVD_LVD2 0x039 +#define RA_ELC_EVENT_CGC_MOSC_STOP 0x03B +#define RA_ELC_EVENT_LPM_SNOOZE_REQUEST 0x03C +#define RA_ELC_EVENT_AGT0_INT 0x040 +#define RA_ELC_EVENT_AGT0_COMPARE_A 0x041 +#define RA_ELC_EVENT_AGT0_COMPARE_B 0x042 +#define RA_ELC_EVENT_AGT1_INT 0x043 +#define RA_ELC_EVENT_AGT1_COMPARE_A 0x044 +#define RA_ELC_EVENT_AGT1_COMPARE_B 0x045 +#define RA_ELC_EVENT_AGT2_INT 0x046 +#define RA_ELC_EVENT_AGT2_COMPARE_A 0x047 +#define RA_ELC_EVENT_AGT2_COMPARE_B 0x048 +#define RA_ELC_EVENT_AGT3_INT 0x049 +#define RA_ELC_EVENT_AGT3_COMPARE_A 0x04A +#define RA_ELC_EVENT_AGT3_COMPARE_B 0x04B +#define RA_ELC_EVENT_AGT5_INT 0x04F +#define RA_ELC_EVENT_AGT5_COMPARE_A 0x050 +#define RA_ELC_EVENT_AGT5_COMPARE_B 0x051 +#define RA_ELC_EVENT_IWDT_UNDERFLOW 0x052 +#define RA_ELC_EVENT_WDT_UNDERFLOW 0x053 +#define RA_ELC_EVENT_RTC_ALARM 0x054 +#define RA_ELC_EVENT_RTC_PERIOD 0x055 +#define RA_ELC_EVENT_RTC_CARRY 0x056 +#define RA_ELC_EVENT_USBFS_FIFO_0 0x06B +#define RA_ELC_EVENT_USBFS_FIFO_1 0x06C +#define RA_ELC_EVENT_USBFS_INT 0x06D +#define RA_ELC_EVENT_USBFS_RESUME 0x06E +#define RA_ELC_EVENT_IIC0_RXI 0x073 +#define RA_ELC_EVENT_IIC0_TXI 0x074 +#define RA_ELC_EVENT_IIC0_TEI 0x075 +#define RA_ELC_EVENT_IIC0_ERI 0x076 +#define RA_ELC_EVENT_IIC0_WUI 0x077 +#define RA_ELC_EVENT_CAC_FREQUENCY_ERROR 0x09E +#define RA_ELC_EVENT_CAC_MEASUREMENT_END 0x09F +#define RA_ELC_EVENT_CAC_OVERFLOW 0x0A0 +#define RA_ELC_EVENT_CAN0_ERROR 0x0A1 +#define RA_ELC_EVENT_CAN0_FIFO_RX 0x0A2 +#define RA_ELC_EVENT_CAN0_FIFO_TX 0x0A3 +#define RA_ELC_EVENT_CAN0_MAILBOX_RX 0x0A4 +#define RA_ELC_EVENT_CAN0_MAILBOX_TX 0x0A5 +#define RA_ELC_EVENT_IOPORT_EVENT_1 0x0B1 +#define RA_ELC_EVENT_IOPORT_EVENT_2 0x0B2 +#define RA_ELC_EVENT_IOPORT_EVENT_3 0x0B3 +#define RA_ELC_EVENT_IOPORT_EVENT_4 0x0B4 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0 0x0B5 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1 0x0B6 +#define RA_ELC_EVENT_POEG0_EVENT 0x0B7 +#define RA_ELC_EVENT_POEG1_EVENT 0x0B8 +#define RA_ELC_EVENT_POEG2_EVENT 0x0B9 +#define RA_ELC_EVENT_POEG3_EVENT 0x0BA +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_A 0x0C9 +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_B 0x0CA +#define RA_ELC_EVENT_GPT1_COMPARE_C 0x0CB +#define RA_ELC_EVENT_GPT1_COMPARE_D 0x0CC +#define RA_ELC_EVENT_GPT1_COMPARE_E 0x0CD +#define RA_ELC_EVENT_GPT1_COMPARE_F 0x0CE +#define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x0CF +#define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x0D0 +#define RA_ELC_EVENT_GPT1_PC 0x0D1 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_A 0x0D2 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_B 0x0D3 +#define RA_ELC_EVENT_GPT2_COMPARE_C 0x0D4 +#define RA_ELC_EVENT_GPT2_COMPARE_D 0x0D5 +#define RA_ELC_EVENT_GPT2_COMPARE_E 0x0D6 +#define RA_ELC_EVENT_GPT2_COMPARE_F 0x0D7 +#define RA_ELC_EVENT_GPT2_COUNTER_OVERFLOW 0x0D8 +#define RA_ELC_EVENT_GPT2_COUNTER_UNDERFLOW 0x0D9 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_A 0x0E4 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_B 0x0E5 +#define RA_ELC_EVENT_GPT4_COMPARE_C 0x0E6 +#define RA_ELC_EVENT_GPT4_COMPARE_D 0x0E7 +#define RA_ELC_EVENT_GPT4_COMPARE_E 0x0E8 +#define RA_ELC_EVENT_GPT4_COMPARE_F 0x0E9 +#define RA_ELC_EVENT_GPT4_COUNTER_OVERFLOW 0x0EA +#define RA_ELC_EVENT_GPT4_COUNTER_UNDERFLOW 0x0EB +#define RA_ELC_EVENT_GPT4_PC 0x0EC +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_A 0x0ED +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_B 0x0EE +#define RA_ELC_EVENT_GPT5_COMPARE_C 0x0EF +#define RA_ELC_EVENT_GPT5_COMPARE_D 0x0F0 +#define RA_ELC_EVENT_GPT5_COMPARE_E 0x0F1 +#define RA_ELC_EVENT_GPT5_COMPARE_F 0x0F2 +#define RA_ELC_EVENT_GPT5_COUNTER_OVERFLOW 0x0F3 +#define RA_ELC_EVENT_GPT5_COUNTER_UNDERFLOW 0x0F4 +#define RA_ELC_EVENT_GPT5_PC 0x0F5 +#define RA_ELC_EVENT_ADC0_SCAN_END 0x160 +#define RA_ELC_EVENT_ADC0_SCAN_END_B 0x161 +#define RA_ELC_EVENT_ADC0_WINDOW_A 0x162 +#define RA_ELC_EVENT_ADC0_WINDOW_B 0x163 +#define RA_ELC_EVENT_ADC0_COMPARE_MATCH 0x164 +#define RA_ELC_EVENT_ADC0_COMPARE_MISMATCH 0x165 +#define RA_ELC_EVENT_SCI0_RXI 0x180 +#define RA_ELC_EVENT_SCI0_TXI 0x181 +#define RA_ELC_EVENT_SCI0_TEI 0x182 +#define RA_ELC_EVENT_SCI0_ERI 0x183 +#define RA_ELC_EVENT_SCI0_AM 0x184 +#define RA_ELC_EVENT_SCI0_RXI_OR_ERI 0x185 +#define RA_ELC_EVENT_SCI3_RXI 0x192 +#define RA_ELC_EVENT_SCI3_TXI 0x193 +#define RA_ELC_EVENT_SCI3_TEI 0x194 +#define RA_ELC_EVENT_SCI3_ERI 0x195 +#define RA_ELC_EVENT_SCI3_AM 0x196 +#define RA_ELC_EVENT_SCI4_RXI 0x198 +#define RA_ELC_EVENT_SCI4_TXI 0x199 +#define RA_ELC_EVENT_SCI4_TEI 0x19A +#define RA_ELC_EVENT_SCI4_ERI 0x19B +#define RA_ELC_EVENT_SCI4_AM 0x19C +#define RA_ELC_EVENT_SCI9_RXI 0x1B6 +#define RA_ELC_EVENT_SCI9_TXI 0x1B7 +#define RA_ELC_EVENT_SCI9_TEI 0x1B8 +#define RA_ELC_EVENT_SCI9_ERI 0x1B9 +#define RA_ELC_EVENT_SCI9_AM 0x1BA +#define RA_ELC_EVENT_SPI0_RXI 0x1C4 +#define RA_ELC_EVENT_SPI0_TXI 0x1C5 +#define RA_ELC_EVENT_SPI0_IDLE 0x1C6 +#define RA_ELC_EVENT_SPI0_ERI 0x1C7 +#define RA_ELC_EVENT_SPI0_TEI 0x1C8 +#define RA_ELC_EVENT_QSPI_INT 0x1DA +#define RA_ELC_EVENT_DOC_INT 0x1DB + +/* Possible peripherals to be linked to event signals */ +#define RA_ELC_PERIPHERAL_GPT_A 0 +#define RA_ELC_PERIPHERAL_GPT_B 1 +#define RA_ELC_PERIPHERAL_GPT_C 2 +#define RA_ELC_PERIPHERAL_GPT_D 3 +#define RA_ELC_PERIPHERAL_GPT_E 4 +#define RA_ELC_PERIPHERAL_GPT_F 5 +#define RA_ELC_PERIPHERAL_GPT_G 6 +#define RA_ELC_PERIPHERAL_GPT_H 7 +#define RA_ELC_PERIPHERAL_ADC0 8 +#define RA_ELC_PERIPHERAL_ADC0_B 9 +#define RA_ELC_PERIPHERAL_DAC0 12 +#define RA_ELC_PERIPHERAL_IOPORT1 14 +#define RA_ELC_PERIPHERAL_IOPORT2 15 +#define RA_ELC_PERIPHERAL_IOPORT3 16 +#define RA_ELC_PERIPHERAL_IOPORT4 17 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4E1_ELC_H_ */ diff --git a/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4e2-elc.h b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4e2-elc.h new file mode 100644 index 00000000000..50d72fd42f5 --- /dev/null +++ b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4e2-elc.h @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4E2_ELC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4E2_ELC_H_ + +/* Sources of event signals to be linked to other peripherals or the CPU */ +#define RA_ELC_EVENT_NONE 0x0 +#define RA_ELC_EVENT_ICU_IRQ0 0x001 +#define RA_ELC_EVENT_ICU_IRQ1 0x002 +#define RA_ELC_EVENT_ICU_IRQ2 0x003 +#define RA_ELC_EVENT_ICU_IRQ3 0x004 +#define RA_ELC_EVENT_ICU_IRQ4 0x005 +#define RA_ELC_EVENT_ICU_IRQ5 0x006 +#define RA_ELC_EVENT_ICU_IRQ6 0x007 +#define RA_ELC_EVENT_ICU_IRQ7 0x008 +#define RA_ELC_EVENT_ICU_IRQ8 0x009 +#define RA_ELC_EVENT_ICU_IRQ9 0x00A +#define RA_ELC_EVENT_ICU_IRQ10 0x00B +#define RA_ELC_EVENT_ICU_IRQ11 0x00C +#define RA_ELC_EVENT_ICU_IRQ12 0x00D +#define RA_ELC_EVENT_ICU_IRQ13 0x00E +#define RA_ELC_EVENT_ICU_IRQ14 0x00F +#define RA_ELC_EVENT_DMAC0_INT 0x020 +#define RA_ELC_EVENT_DMAC1_INT 0x021 +#define RA_ELC_EVENT_DMAC2_INT 0x022 +#define RA_ELC_EVENT_DMAC3_INT 0x023 +#define RA_ELC_EVENT_DMAC4_INT 0x024 +#define RA_ELC_EVENT_DMAC5_INT 0x025 +#define RA_ELC_EVENT_DMAC6_INT 0x026 +#define RA_ELC_EVENT_DMAC7_INT 0x027 +#define RA_ELC_EVENT_DTC_COMPLETE 0x029 +#define RA_ELC_EVENT_DMA_TRANSERR 0x02B +#define RA_ELC_EVENT_ICU_SNOOZE_CANCEL 0x02D +#define RA_ELC_EVENT_FCU_FIFERR 0x030 +#define RA_ELC_EVENT_FCU_FRDYI 0x031 +#define RA_ELC_EVENT_LVD_LVD1 0x038 +#define RA_ELC_EVENT_LVD_LVD2 0x039 +#define RA_ELC_EVENT_CGC_MOSC_STOP 0x03B +#define RA_ELC_EVENT_LPM_SNOOZE_REQUEST 0x03C +#define RA_ELC_EVENT_AGT0_INT 0x040 +#define RA_ELC_EVENT_AGT0_COMPARE_A 0x041 +#define RA_ELC_EVENT_AGT0_COMPARE_B 0x042 +#define RA_ELC_EVENT_AGT1_INT 0x043 +#define RA_ELC_EVENT_AGT1_COMPARE_A 0x044 +#define RA_ELC_EVENT_AGT1_COMPARE_B 0x045 +#define RA_ELC_EVENT_IWDT_UNDERFLOW 0x052 +#define RA_ELC_EVENT_WDT_UNDERFLOW 0x053 +#define RA_ELC_EVENT_RTC_ALARM 0x054 +#define RA_ELC_EVENT_RTC_PERIOD 0x055 +#define RA_ELC_EVENT_RTC_CARRY 0x056 +#define RA_ELC_EVENT_CAN_RXF 0x059 +#define RA_ELC_EVENT_CAN_GLERR 0x05A +#define RA_ELC_EVENT_CAN_DMAREQ0 0x05B +#define RA_ELC_EVENT_CAN_DMAREQ1 0x05C +#define RA_ELC_EVENT_CAN0_TX 0x063 +#define RA_ELC_EVENT_CAN0_CHERR 0x064 +#define RA_ELC_EVENT_CAN0_COMFRX 0x065 +#define RA_ELC_EVENT_CAN0_CF_DMAREQ 0x066 +#define RA_ELC_EVENT_CAN0_RXMB 0x067 +#define RA_ELC_EVENT_USBFS_INT 0x06D +#define RA_ELC_EVENT_USBFS_RESUME 0x06E +#define RA_ELC_EVENT_SSI0_TXI 0x08A +#define RA_ELC_EVENT_SSI0_RXI 0x08B +#define RA_ELC_EVENT_SSI0_INT 0x08D +#define RA_ELC_EVENT_CAC_FREQUENCY_ERROR 0x09E +#define RA_ELC_EVENT_CAC_MEASUREMENT_END 0x09F +#define RA_ELC_EVENT_CAC_OVERFLOW 0x0A0 +#define RA_ELC_EVENT_CEC_INTDA 0x0AB +#define RA_ELC_EVENT_CEC_INTCE 0x0AC +#define RA_ELC_EVENT_CEC_INTERR 0x0AD +#define RA_ELC_EVENT_IOPORT_EVENT_1 0x0B1 +#define RA_ELC_EVENT_IOPORT_EVENT_2 0x0B2 +#define RA_ELC_EVENT_IOPORT_EVENT_3 0x0B3 +#define RA_ELC_EVENT_IOPORT_EVENT_4 0x0B4 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0 0x0B5 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1 0x0B6 +#define RA_ELC_EVENT_POEG0_EVENT 0x0B7 +#define RA_ELC_EVENT_POEG1_EVENT 0x0B8 +#define RA_ELC_EVENT_POEG2_EVENT 0x0B9 +#define RA_ELC_EVENT_POEG3_EVENT 0x0BA +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_A 0x0C0 +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_B 0x0C1 +#define RA_ELC_EVENT_GPT0_COMPARE_C 0x0C2 +#define RA_ELC_EVENT_GPT0_COMPARE_D 0x0C3 +#define RA_ELC_EVENT_GPT0_COMPARE_E 0x0C4 +#define RA_ELC_EVENT_GPT0_COMPARE_F 0x0C5 +#define RA_ELC_EVENT_GPT0_COUNTER_OVERFLOW 0x0C6 +#define RA_ELC_EVENT_GPT0_COUNTER_UNDERFLOW 0x0C7 +#define RA_ELC_EVENT_GPT0_PC 0x0C8 +#define RA_ELC_EVENT_GPT0_AD_TRIG_A 0x0C9 +#define RA_ELC_EVENT_GPT0_AD_TRIG_B 0x0CA +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_A 0x0CB +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_B 0x0CC +#define RA_ELC_EVENT_GPT1_COMPARE_C 0x0CD +#define RA_ELC_EVENT_GPT1_COMPARE_D 0x0CE +#define RA_ELC_EVENT_GPT1_COMPARE_E 0x0CF +#define RA_ELC_EVENT_GPT1_COMPARE_F 0x0D0 +#define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x0D1 +#define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x0D2 +#define RA_ELC_EVENT_GPT1_PC 0x0D3 +#define RA_ELC_EVENT_GPT1_AD_TRIG_A 0x0D4 +#define RA_ELC_EVENT_GPT1_AD_TRIG_B 0x0D5 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_A 0x0EC +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_B 0x0ED +#define RA_ELC_EVENT_GPT4_COMPARE_C 0x0EE +#define RA_ELC_EVENT_GPT4_COMPARE_D 0x0EF +#define RA_ELC_EVENT_GPT4_COMPARE_E 0x0F0 +#define RA_ELC_EVENT_GPT4_COMPARE_F 0x0F1 +#define RA_ELC_EVENT_GPT4_COUNTER_OVERFLOW 0x0F2 +#define RA_ELC_EVENT_GPT4_COUNTER_UNDERFLOW 0x0F3 +#define RA_ELC_EVENT_GPT4_PC 0x0F4 +#define RA_ELC_EVENT_GPT4_AD_TRIG_A 0x0F5 +#define RA_ELC_EVENT_GPT4_AD_TRIG_B 0x0F6 +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_A 0x0F7 +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_B 0x0F8 +#define RA_ELC_EVENT_GPT5_COMPARE_C 0x0F9 +#define RA_ELC_EVENT_GPT5_COMPARE_D 0x0FA +#define RA_ELC_EVENT_GPT5_COMPARE_E 0x0FB +#define RA_ELC_EVENT_GPT5_COMPARE_F 0x0FC +#define RA_ELC_EVENT_GPT5_COUNTER_OVERFLOW 0x0FD +#define RA_ELC_EVENT_GPT5_COUNTER_UNDERFLOW 0x0FE +#define RA_ELC_EVENT_GPT5_PC 0x0FF +#define RA_ELC_EVENT_GPT5_AD_TRIG_A 0x100 +#define RA_ELC_EVENT_GPT5_AD_TRIG_B 0x101 +#define RA_ELC_EVENT_OPS_UVW_EDGE 0x15C +#define RA_ELC_EVENT_ADC0_SCAN_END 0x160 +#define RA_ELC_EVENT_ADC0_SCAN_END_B 0x161 +#define RA_ELC_EVENT_ADC0_WINDOW_A 0x162 +#define RA_ELC_EVENT_ADC0_WINDOW_B 0x163 +#define RA_ELC_EVENT_ADC0_COMPARE_MATCH 0x164 +#define RA_ELC_EVENT_ADC0_COMPARE_MISMATCH 0x165 +#define RA_ELC_EVENT_SCI0_RXI 0x180 +#define RA_ELC_EVENT_SCI0_TXI 0x181 +#define RA_ELC_EVENT_SCI0_TEI 0x182 +#define RA_ELC_EVENT_SCI0_ERI 0x183 +#define RA_ELC_EVENT_SCI0_AM 0x184 +#define RA_ELC_EVENT_SCI0_RXI_OR_ERI 0x185 +#define RA_ELC_EVENT_SCI9_RXI 0x1B6 +#define RA_ELC_EVENT_SCI9_TXI 0x1B7 +#define RA_ELC_EVENT_SCI9_TEI 0x1B8 +#define RA_ELC_EVENT_SCI9_ERI 0x1B9 +#define RA_ELC_EVENT_SCI9_AM 0x1BA +#define RA_ELC_EVENT_SPI0_RXI 0x1C4 +#define RA_ELC_EVENT_SPI0_TXI 0x1C5 +#define RA_ELC_EVENT_SPI0_IDLE 0x1C6 +#define RA_ELC_EVENT_SPI0_ERI 0x1C7 +#define RA_ELC_EVENT_SPI0_TEI 0x1C8 +#define RA_ELC_EVENT_SPI1_RXI 0x1C9 +#define RA_ELC_EVENT_SPI1_TXI 0x1CA +#define RA_ELC_EVENT_SPI1_IDLE 0x1CB +#define RA_ELC_EVENT_SPI1_ERI 0x1CC +#define RA_ELC_EVENT_SPI1_TEI 0x1CD +#define RA_ELC_EVENT_CAN0_MRAM_ERI 0x1D0 +#define RA_ELC_EVENT_DOC_INT 0x1DB +#define RA_ELC_EVENT_I3C0_RESPONSE 0x1DC +#define RA_ELC_EVENT_I3C0_COMMAND 0x1DD +#define RA_ELC_EVENT_I3C0_IBI 0x1DE +#define RA_ELC_EVENT_I3C0_RX 0x1DF +#define RA_ELC_EVENT_IICB0_RXI 0x1DF +#define RA_ELC_EVENT_I3C0_TX 0x1E0 +#define RA_ELC_EVENT_IICB0_TXI 0x1E0 +#define RA_ELC_EVENT_I3C0_RCV_STATUS 0x1E1 +#define RA_ELC_EVENT_I3C0_HRESP 0x1E2 +#define RA_ELC_EVENT_I3C0_HCMD 0x1E3 +#define RA_ELC_EVENT_I3C0_HRX 0x1E4 +#define RA_ELC_EVENT_I3C0_HTX 0x1E5 +#define RA_ELC_EVENT_I3C0_TEND 0x1E6 +#define RA_ELC_EVENT_IICB0_TEI 0x1E6 +#define RA_ELC_EVENT_I3C0_EEI 0x1E7 +#define RA_ELC_EVENT_IICB0_ERI 0x1E7 +#define RA_ELC_EVENT_I3C0_STEV 0x1E8 +#define RA_ELC_EVENT_I3C0_MREFOVF 0x1E9 +#define RA_ELC_EVENT_I3C0_MREFCPT 0x1EA +#define RA_ELC_EVENT_I3C0_AMEV 0x1EB +#define RA_ELC_EVENT_I3C0_WU 0x1EC +#define RA_ELC_EVENT_TRNG_RDREQ 0x1F3 + +/* Possible peripherals to be linked to event signals */ +#define RA_ELC_PERIPHERAL_GPT_A 0 +#define RA_ELC_PERIPHERAL_GPT_B 1 +#define RA_ELC_PERIPHERAL_GPT_C 2 +#define RA_ELC_PERIPHERAL_GPT_D 3 +#define RA_ELC_PERIPHERAL_GPT_E 4 +#define RA_ELC_PERIPHERAL_GPT_F 5 +#define RA_ELC_PERIPHERAL_GPT_G 6 +#define RA_ELC_PERIPHERAL_GPT_H 7 +#define RA_ELC_PERIPHERAL_ADC0 8 +#define RA_ELC_PERIPHERAL_ADC0_B 9 +#define RA_ELC_PERIPHERAL_DAC0 12 +#define RA_ELC_PERIPHERAL_IOPORT1 14 +#define RA_ELC_PERIPHERAL_IOPORT2 15 +#define RA_ELC_PERIPHERAL_IOPORT3 16 +#define RA_ELC_PERIPHERAL_IOPORT4 17 +#define RA_ELC_PERIPHERAL_I3C 23 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4E2_ELC_H_ */ diff --git a/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4l1-elc.h b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4l1-elc.h new file mode 100644 index 00000000000..119bdfb7292 --- /dev/null +++ b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4l1-elc.h @@ -0,0 +1,242 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4L1_ELC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4L1_ELC_H_ + +/* Sources of event signals to be linked to other peripherals or the CPU */ +#define RA_ELC_EVENT_NONE 0x0 +#define RA_ELC_EVENT_ICU_IRQ0 0x001 +#define RA_ELC_EVENT_ICU_IRQ1 0x002 +#define RA_ELC_EVENT_ICU_IRQ2 0x003 +#define RA_ELC_EVENT_ICU_IRQ3 0x004 +#define RA_ELC_EVENT_ICU_IRQ4 0x005 +#define RA_ELC_EVENT_ICU_IRQ5 0x006 +#define RA_ELC_EVENT_ICU_IRQ6 0x007 +#define RA_ELC_EVENT_ICU_IRQ7 0x008 +#define RA_ELC_EVENT_ICU_IRQ8 0x009 +#define RA_ELC_EVENT_ICU_IRQ9 0x00A +#define RA_ELC_EVENT_ICU_IRQ10 0x00B +#define RA_ELC_EVENT_ICU_IRQ11 0x00C +#define RA_ELC_EVENT_ICU_IRQ12 0x00D +#define RA_ELC_EVENT_ICU_IRQ13 0x00E +#define RA_ELC_EVENT_ICU_IRQ14 0x00F +#define RA_ELC_EVENT_ICU_IRQ15 0x010 +#define RA_ELC_EVENT_DMAC0_INT 0x020 +#define RA_ELC_EVENT_DMAC1_INT 0x021 +#define RA_ELC_EVENT_DMAC2_INT 0x022 +#define RA_ELC_EVENT_DMAC3_INT 0x023 +#define RA_ELC_EVENT_DMAC4_INT 0x024 +#define RA_ELC_EVENT_DMAC5_INT 0x025 +#define RA_ELC_EVENT_DMAC6_INT 0x026 +#define RA_ELC_EVENT_DMAC7_INT 0x027 +#define RA_ELC_EVENT_DTC_COMPLETE 0x029 +#define RA_ELC_EVENT_DTC_END 0x02A +#define RA_ELC_EVENT_DMA_TRANSERR 0x02B +#define RA_ELC_EVENT_ICU_SNOOZE_CANCEL 0x02D +#define RA_ELC_EVENT_FCU_FIFERR 0x030 +#define RA_ELC_EVENT_FCU_FRDYI 0x031 +#define RA_ELC_EVENT_LVD_LVD1 0x038 +#define RA_ELC_EVENT_LVD_LVD2 0x039 +#define RA_ELC_EVENT_CGC_MOSC_STOP 0x03B +#define RA_ELC_EVENT_LPM_SNOOZE_REQUEST 0x03C +#define RA_ELC_EVENT_CGC_SOSC_STOP 0x03D +#define RA_ELC_EVENT_AGT0_INT 0x040 +#define RA_ELC_EVENT_AGT0_COMPARE_A 0x041 +#define RA_ELC_EVENT_AGT0_COMPARE_B 0x042 +#define RA_ELC_EVENT_AGT1_INT 0x043 +#define RA_ELC_EVENT_AGT1_COMPARE_A 0x044 +#define RA_ELC_EVENT_AGT1_COMPARE_B 0x045 +#define RA_ELC_EVENT_IWDT_UNDERFLOW 0x052 +#define RA_ELC_EVENT_WDT_UNDERFLOW 0x053 +#define RA_ELC_EVENT_RTC_ALARM 0x054 +#define RA_ELC_EVENT_RTC_PERIOD 0x055 +#define RA_ELC_EVENT_RTC_CARRY 0x056 +#define RA_ELC_EVENT_CAN_RXF 0x059 +#define RA_ELC_EVENT_CAN_GLERR 0x05A +#define RA_ELC_EVENT_CAN_DMAREQ0 0x05B +#define RA_ELC_EVENT_CAN_DMAREQ1 0x05C +#define RA_ELC_EVENT_CAN0_TX 0x063 +#define RA_ELC_EVENT_CAN0_CHERR 0x064 +#define RA_ELC_EVENT_CAN0_COMFRX 0x065 +#define RA_ELC_EVENT_CAN0_CF_DMAREQ 0x066 +#define RA_ELC_EVENT_CAN0_RXMB 0x067 +#define RA_ELC_EVENT_USBFS_FIFO_0 0x06B +#define RA_ELC_EVENT_USBFS_FIFO_1 0x06C +#define RA_ELC_EVENT_USBFS_INT 0x06D +#define RA_ELC_EVENT_USBFS_RESUME 0x06E +#define RA_ELC_EVENT_IIC0_RXI 0x073 +#define RA_ELC_EVENT_IIC0_TXI 0x074 +#define RA_ELC_EVENT_IIC0_TEI 0x075 +#define RA_ELC_EVENT_IIC0_ERI 0x076 +#define RA_ELC_EVENT_IIC0_WUI 0x077 +#define RA_ELC_EVENT_SSI0_TXI 0x08A +#define RA_ELC_EVENT_SSI0_RXI 0x08B +#define RA_ELC_EVENT_SSI0_INT 0x08D +#define RA_ELC_EVENT_UARTA0_TXI 0x08E +#define RA_ELC_EVENT_UARTA0_RXI 0x08F +#define RA_ELC_EVENT_UARTA0_ERRI 0x090 +#define RA_ELC_EVENT_UARTA1_TXI 0x091 +#define RA_ELC_EVENT_UARTA1_RXI 0x092 +#define RA_ELC_EVENT_UARTA1_ERRI 0x093 +#define RA_ELC_EVENT_ACMPLP0_INT 0x094 +#define RA_ELC_EVENT_ACMPLP1_INT 0x095 +#define RA_ELC_EVENT_CTSU_WRITE 0x09A +#define RA_ELC_EVENT_CTSU_READ 0x09B +#define RA_ELC_EVENT_CTSU_END 0x09C +#define RA_ELC_EVENT_CAC_FREQUENCY_ERROR 0x09E +#define RA_ELC_EVENT_CAC_MEASUREMENT_END 0x09F +#define RA_ELC_EVENT_CAC_OVERFLOW 0x0A0 +#define RA_ELC_EVENT_IOPORT_EVENT_1 0x0B1 +#define RA_ELC_EVENT_IOPORT_EVENT_2 0x0B2 +#define RA_ELC_EVENT_IOPORT_EVENT_3 0x0B3 +#define RA_ELC_EVENT_IOPORT_EVENT_4 0x0B4 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0 0x0B5 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1 0x0B6 +#define RA_ELC_EVENT_POEG0_EVENT 0x0B7 +#define RA_ELC_EVENT_POEG1_EVENT 0x0B8 +#define RA_ELC_EVENT_POEG2_EVENT 0x0B9 +#define RA_ELC_EVENT_POEG3_EVENT 0x0BA +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_A 0x0C0 +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_B 0x0C1 +#define RA_ELC_EVENT_GPT0_COMPARE_C 0x0C2 +#define RA_ELC_EVENT_GPT0_COMPARE_D 0x0C3 +#define RA_ELC_EVENT_GPT0_COMPARE_E 0x0C4 +#define RA_ELC_EVENT_GPT0_COMPARE_F 0x0C5 +#define RA_ELC_EVENT_GPT0_COUNTER_OVERFLOW 0x0C6 +#define RA_ELC_EVENT_GPT0_COUNTER_UNDERFLOW 0x0C7 +#define RA_ELC_EVENT_GPT0_PC 0x0C8 +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_A 0x0C9 +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_B 0x0CA +#define RA_ELC_EVENT_GPT1_COMPARE_C 0x0CB +#define RA_ELC_EVENT_GPT1_COMPARE_D 0x0CC +#define RA_ELC_EVENT_GPT1_COMPARE_E 0x0CD +#define RA_ELC_EVENT_GPT1_COMPARE_F 0x0CE +#define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x0CF +#define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x0D0 +#define RA_ELC_EVENT_GPT1_PC 0x0D1 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_A 0x0D2 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_B 0x0D3 +#define RA_ELC_EVENT_GPT2_COMPARE_C 0x0D4 +#define RA_ELC_EVENT_GPT2_COMPARE_D 0x0D5 +#define RA_ELC_EVENT_GPT2_COMPARE_E 0x0D6 +#define RA_ELC_EVENT_GPT2_COMPARE_F 0x0D7 +#define RA_ELC_EVENT_GPT2_COUNTER_OVERFLOW 0x0D8 +#define RA_ELC_EVENT_GPT2_COUNTER_UNDERFLOW 0x0D9 +#define RA_ELC_EVENT_GPT2_PC 0x0DA +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_A 0x0DB +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_B 0x0DC +#define RA_ELC_EVENT_GPT3_COMPARE_C 0x0DD +#define RA_ELC_EVENT_GPT3_COMPARE_D 0x0DE +#define RA_ELC_EVENT_GPT3_COMPARE_E 0x0DF +#define RA_ELC_EVENT_GPT3_COMPARE_F 0x0E0 +#define RA_ELC_EVENT_GPT3_COUNTER_OVERFLOW 0x0E1 +#define RA_ELC_EVENT_GPT3_COUNTER_UNDERFLOW 0x0E2 +#define RA_ELC_EVENT_GPT3_PC 0x0E3 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_A 0x0E4 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_B 0x0E5 +#define RA_ELC_EVENT_GPT4_COMPARE_C 0x0E6 +#define RA_ELC_EVENT_GPT4_COMPARE_D 0x0E7 +#define RA_ELC_EVENT_GPT4_COMPARE_E 0x0E8 +#define RA_ELC_EVENT_GPT4_COMPARE_F 0x0E9 +#define RA_ELC_EVENT_GPT4_COUNTER_OVERFLOW 0x0EA +#define RA_ELC_EVENT_GPT4_COUNTER_UNDERFLOW 0x0EB +#define RA_ELC_EVENT_GPT4_PC 0x0EC +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_A 0x0ED +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_B 0x0EE +#define RA_ELC_EVENT_GPT5_COMPARE_C 0x0EF +#define RA_ELC_EVENT_GPT5_COMPARE_D 0x0F0 +#define RA_ELC_EVENT_GPT5_COMPARE_E 0x0F1 +#define RA_ELC_EVENT_GPT5_COMPARE_F 0x0F2 +#define RA_ELC_EVENT_GPT5_COUNTER_OVERFLOW 0x0F3 +#define RA_ELC_EVENT_GPT5_COUNTER_UNDERFLOW 0x0F4 +#define RA_ELC_EVENT_OPS_UVW_EDGE 0x150 +#define RA_ELC_EVENT_ADC0_SCAN_END 0x160 +#define RA_ELC_EVENT_ADC0_SCAN_END_B 0x161 +#define RA_ELC_EVENT_ADC0_WINDOW_A 0x162 +#define RA_ELC_EVENT_ADC0_WINDOW_B 0x163 +#define RA_ELC_EVENT_ADC0_COMPARE_MATCH 0x164 +#define RA_ELC_EVENT_ADC0_COMPARE_MISMATCH 0x165 +#define RA_ELC_EVENT_SCI0_RXI 0x180 +#define RA_ELC_EVENT_SCI0_TXI 0x181 +#define RA_ELC_EVENT_SCI0_TEI 0x182 +#define RA_ELC_EVENT_SCI0_ERI 0x183 +#define RA_ELC_EVENT_SCI0_AM 0x184 +#define RA_ELC_EVENT_SCI0_RXI_OR_ERI 0x185 +#define RA_ELC_EVENT_SCI1_RXI 0x186 +#define RA_ELC_EVENT_SCI1_TXI 0x187 +#define RA_ELC_EVENT_SCI1_TEI 0x188 +#define RA_ELC_EVENT_SCI1_ERI 0x189 +#define RA_ELC_EVENT_SCI3_RXI 0x192 +#define RA_ELC_EVENT_SCI3_TXI 0x193 +#define RA_ELC_EVENT_SCI3_TEI 0x194 +#define RA_ELC_EVENT_SCI3_ERI 0x195 +#define RA_ELC_EVENT_SCI3_AM 0x196 +#define RA_ELC_EVENT_SCI4_RXI 0x198 +#define RA_ELC_EVENT_SCI4_TXI 0x199 +#define RA_ELC_EVENT_SCI4_TEI 0x19A +#define RA_ELC_EVENT_SCI4_ERI 0x19B +#define RA_ELC_EVENT_SCI4_AM 0x19C +#define RA_ELC_EVENT_SCI5_RXI 0x19E +#define RA_ELC_EVENT_SCI5_TXI 0x19F +#define RA_ELC_EVENT_SCI5_TEI 0x1A0 +#define RA_ELC_EVENT_SCI5_ERI 0x1A1 +#define RA_ELC_EVENT_SCI5_AM 0x1A2 +#define RA_ELC_EVENT_SCI9_RXI 0x1B6 +#define RA_ELC_EVENT_SCI9_TXI 0x1B7 +#define RA_ELC_EVENT_SCI9_TEI 0x1B8 +#define RA_ELC_EVENT_SCI9_ERI 0x1B9 +#define RA_ELC_EVENT_SCI9_AM 0x1BA +#define RA_ELC_EVENT_SCIX0_SCIX0 0x1BC +#define RA_ELC_EVENT_SCI1_SCIX0 0x1BC +#define RA_ELC_EVENT_SCIX0_SCIX1 0x1BD +#define RA_ELC_EVENT_SCI1_SCIX1 0x1BD +#define RA_ELC_EVENT_SCIX0_SCIX2 0x1BE +#define RA_ELC_EVENT_SCI1_SCIX2 0x1BE +#define RA_ELC_EVENT_SCIX0_SCIX3 0x1BF +#define RA_ELC_EVENT_SCI1_SCIX3 0x1BF +#define RA_ELC_EVENT_SPI0_RXI 0x1C4 +#define RA_ELC_EVENT_SPI0_TXI 0x1C5 +#define RA_ELC_EVENT_SPI0_IDLE 0x1C6 +#define RA_ELC_EVENT_SPI0_ERI 0x1C7 +#define RA_ELC_EVENT_SPI0_TEI 0x1C8 +#define RA_ELC_EVENT_CAN0_MRAM_ERI 0x1D0 +#define RA_ELC_EVENT_QSPI_INT 0x1DA +#define RA_ELC_EVENT_DOC_INT 0x1DB +#define RA_ELC_EVENT_I3C0_RESPONSE 0x1DC +#define RA_ELC_EVENT_I3C0_COMMAND 0x1DD +#define RA_ELC_EVENT_I3C0_IBI 0x1DE +#define RA_ELC_EVENT_I3C0_RX 0x1DF +#define RA_ELC_EVENT_IICB0_RXI 0x1DF +#define RA_ELC_EVENT_I3C0_TX 0x1E0 +#define RA_ELC_EVENT_IICB0_TXI 0x1E0 +#define RA_ELC_EVENT_I3C0_RCV_STATUS 0x1E1 +#define RA_ELC_EVENT_I3C0_TEND 0x1E6 +#define RA_ELC_EVENT_IICB0_TEI 0x1E6 +#define RA_ELC_EVENT_I3C0_EEI 0x1E7 +#define RA_ELC_EVENT_IICB0_ERI 0x1E7 +#define RA_ELC_EVENT_I3C0_WU 0x1EC +#define RA_ELC_EVENT_RSIP_TADI 0x1EE + +/* Possible peripherals to be linked to event signals */ +#define RA_ELC_PERIPHERAL_GPT_A 0 +#define RA_ELC_PERIPHERAL_GPT_B 1 +#define RA_ELC_PERIPHERAL_GPT_C 2 +#define RA_ELC_PERIPHERAL_GPT_D 3 +#define RA_ELC_PERIPHERAL_GPT_E 4 +#define RA_ELC_PERIPHERAL_GPT_F 5 +#define RA_ELC_PERIPHERAL_GPT_G 6 +#define RA_ELC_PERIPHERAL_GPT_H 7 +#define RA_ELC_PERIPHERAL_ADC0 8 +#define RA_ELC_PERIPHERAL_ADC0_B 9 +#define RA_ELC_PERIPHERAL_DAC0 12 +#define RA_ELC_PERIPHERAL_IOPORT1 14 +#define RA_ELC_PERIPHERAL_IOPORT2 15 +#define RA_ELC_PERIPHERAL_IOPORT3 16 +#define RA_ELC_PERIPHERAL_IOPORT4 17 +#define RA_ELC_PERIPHERAL_CTSU 18 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4L1_ELC_H_ */ diff --git a/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4m1-elc.h b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4m1-elc.h new file mode 100644 index 00000000000..c88d1d6c40b --- /dev/null +++ b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4m1-elc.h @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4M1_ELC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4M1_ELC_H_ + +/* Sources of event signals to be linked to other peripherals or the CPU */ +#define RA_ELC_EVENT_NONE 0x0 +#define RA_ELC_EVENT_ICU_IRQ0 0x001 +#define RA_ELC_EVENT_ICU_IRQ1 0x002 +#define RA_ELC_EVENT_ICU_IRQ2 0x003 +#define RA_ELC_EVENT_ICU_IRQ3 0x004 +#define RA_ELC_EVENT_ICU_IRQ4 0x005 +#define RA_ELC_EVENT_ICU_IRQ5 0x006 +#define RA_ELC_EVENT_ICU_IRQ6 0x007 +#define RA_ELC_EVENT_ICU_IRQ7 0x008 +#define RA_ELC_EVENT_ICU_IRQ8 0x009 +#define RA_ELC_EVENT_ICU_IRQ9 0x00A +#define RA_ELC_EVENT_ICU_IRQ10 0x00B +#define RA_ELC_EVENT_ICU_IRQ11 0x00C +#define RA_ELC_EVENT_ICU_IRQ12 0x00D +#define RA_ELC_EVENT_ICU_IRQ14 0x00F +#define RA_ELC_EVENT_ICU_IRQ15 0x010 +#define RA_ELC_EVENT_DMAC0_INT 0x011 +#define RA_ELC_EVENT_DMAC1_INT 0x012 +#define RA_ELC_EVENT_DMAC2_INT 0x013 +#define RA_ELC_EVENT_DMAC3_INT 0x014 +#define RA_ELC_EVENT_DTC_COMPLETE 0x015 +#define RA_ELC_EVENT_DTC_END 0x016 +#define RA_ELC_EVENT_ICU_SNOOZE_CANCEL 0x017 +#define RA_ELC_EVENT_FCU_FRDYI 0x018 +#define RA_ELC_EVENT_LVD_LVD1 0x019 +#define RA_ELC_EVENT_LVD_LVD2 0x01A +#define RA_ELC_EVENT_LVD_VBATT 0x01B +#define RA_ELC_EVENT_CGC_MOSC_STOP 0x01C +#define RA_ELC_EVENT_LPM_SNOOZE_REQUEST 0x01D +#define RA_ELC_EVENT_AGT0_INT 0x01E +#define RA_ELC_EVENT_AGT0_COMPARE_A 0x01F +#define RA_ELC_EVENT_AGT0_COMPARE_B 0x020 +#define RA_ELC_EVENT_AGT1_INT 0x021 +#define RA_ELC_EVENT_AGT1_COMPARE_A 0x022 +#define RA_ELC_EVENT_AGT1_COMPARE_B 0x023 +#define RA_ELC_EVENT_IWDT_UNDERFLOW 0x024 +#define RA_ELC_EVENT_WDT_UNDERFLOW 0x025 +#define RA_ELC_EVENT_RTC_ALARM 0x026 +#define RA_ELC_EVENT_RTC_PERIOD 0x027 +#define RA_ELC_EVENT_RTC_CARRY 0x028 +#define RA_ELC_EVENT_ADC0_SCAN_END 0x029 +#define RA_ELC_EVENT_ADC0_SCAN_END_B 0x02A +#define RA_ELC_EVENT_ADC0_WINDOW_A 0x02B +#define RA_ELC_EVENT_ADC0_WINDOW_B 0x02C +#define RA_ELC_EVENT_ADC0_COMPARE_MATCH 0x02D +#define RA_ELC_EVENT_ADC0_COMPARE_MISMATCH 0x02E +#define RA_ELC_EVENT_ACMPLP0_INT 0x02F +#define RA_ELC_EVENT_ACMPLP1_INT 0x030 +#define RA_ELC_EVENT_USBFS_FIFO_0 0x031 +#define RA_ELC_EVENT_USBFS_FIFO_1 0x032 +#define RA_ELC_EVENT_USBFS_INT 0x033 +#define RA_ELC_EVENT_USBFS_RESUME 0x034 +#define RA_ELC_EVENT_IIC0_RXI 0x035 +#define RA_ELC_EVENT_IIC0_TXI 0x036 +#define RA_ELC_EVENT_IIC0_TEI 0x037 +#define RA_ELC_EVENT_IIC0_ERI 0x038 +#define RA_ELC_EVENT_IIC0_WUI 0x039 +#define RA_ELC_EVENT_IIC1_RXI 0x03A +#define RA_ELC_EVENT_IIC1_TXI 0x03B +#define RA_ELC_EVENT_IIC1_TEI 0x03C +#define RA_ELC_EVENT_IIC1_ERI 0x03D +#define RA_ELC_EVENT_SSI0_TXI 0x03E +#define RA_ELC_EVENT_SSI0_RXI 0x03F +#define RA_ELC_EVENT_SSI0_INT 0x041 +#define RA_ELC_EVENT_CTSU_WRITE 0x042 +#define RA_ELC_EVENT_CTSU_READ 0x043 +#define RA_ELC_EVENT_CTSU_END 0x044 +#define RA_ELC_EVENT_KEY_INT 0x045 +#define RA_ELC_EVENT_DOC_INT 0x046 +#define RA_ELC_EVENT_CAC_FREQUENCY_ERROR 0x047 +#define RA_ELC_EVENT_CAC_MEASUREMENT_END 0x048 +#define RA_ELC_EVENT_CAC_OVERFLOW 0x049 +#define RA_ELC_EVENT_CAN0_ERROR 0x04A +#define RA_ELC_EVENT_CAN0_FIFO_RX 0x04B +#define RA_ELC_EVENT_CAN0_FIFO_TX 0x04C +#define RA_ELC_EVENT_CAN0_MAILBOX_RX 0x04D +#define RA_ELC_EVENT_CAN0_MAILBOX_TX 0x04E +#define RA_ELC_EVENT_IOPORT_EVENT_1 0x04F +#define RA_ELC_EVENT_IOPORT_EVENT_2 0x050 +#define RA_ELC_EVENT_IOPORT_EVENT_3 0x051 +#define RA_ELC_EVENT_IOPORT_EVENT_4 0x052 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0 0x053 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1 0x054 +#define RA_ELC_EVENT_POEG0_EVENT 0x055 +#define RA_ELC_EVENT_POEG1_EVENT 0x056 +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_A 0x057 +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_B 0x058 +#define RA_ELC_EVENT_GPT0_COMPARE_C 0x059 +#define RA_ELC_EVENT_GPT0_COMPARE_D 0x05A +#define RA_ELC_EVENT_GPT0_COMPARE_E 0x05B +#define RA_ELC_EVENT_GPT0_COMPARE_F 0x05C +#define RA_ELC_EVENT_GPT0_COUNTER_OVERFLOW 0x05D +#define RA_ELC_EVENT_GPT0_COUNTER_UNDERFLOW 0x05E +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_A 0x05F +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_B 0x060 +#define RA_ELC_EVENT_GPT1_COMPARE_C 0x061 +#define RA_ELC_EVENT_GPT1_COMPARE_D 0x062 +#define RA_ELC_EVENT_GPT1_COMPARE_E 0x063 +#define RA_ELC_EVENT_GPT1_COMPARE_F 0x064 +#define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x065 +#define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x066 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_A 0x067 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_B 0x068 +#define RA_ELC_EVENT_GPT2_COMPARE_C 0x069 +#define RA_ELC_EVENT_GPT2_COMPARE_D 0x06A +#define RA_ELC_EVENT_GPT2_COMPARE_E 0x06B +#define RA_ELC_EVENT_GPT2_COMPARE_F 0x06C +#define RA_ELC_EVENT_GPT2_COUNTER_OVERFLOW 0x06D +#define RA_ELC_EVENT_GPT2_COUNTER_UNDERFLOW 0x06E +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_A 0x06F +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_B 0x070 +#define RA_ELC_EVENT_GPT3_COMPARE_C 0x071 +#define RA_ELC_EVENT_GPT3_COMPARE_D 0x072 +#define RA_ELC_EVENT_GPT3_COMPARE_E 0x073 +#define RA_ELC_EVENT_GPT3_COMPARE_F 0x074 +#define RA_ELC_EVENT_GPT3_COUNTER_OVERFLOW 0x075 +#define RA_ELC_EVENT_GPT3_COUNTER_UNDERFLOW 0x076 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_A 0x077 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_B 0x078 +#define RA_ELC_EVENT_GPT4_COMPARE_C 0x079 +#define RA_ELC_EVENT_GPT4_COMPARE_D 0x07A +#define RA_ELC_EVENT_GPT4_COMPARE_E 0x07B +#define RA_ELC_EVENT_GPT4_COMPARE_F 0x07C +#define RA_ELC_EVENT_GPT4_COUNTER_OVERFLOW 0x07D +#define RA_ELC_EVENT_GPT4_COUNTER_UNDERFLOW 0x07E +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_A 0x07F +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_B 0x080 +#define RA_ELC_EVENT_GPT5_COMPARE_C 0x081 +#define RA_ELC_EVENT_GPT5_COMPARE_D 0x082 +#define RA_ELC_EVENT_GPT5_COMPARE_E 0x083 +#define RA_ELC_EVENT_GPT5_COMPARE_F 0x084 +#define RA_ELC_EVENT_GPT5_COUNTER_OVERFLOW 0x085 +#define RA_ELC_EVENT_GPT5_COUNTER_UNDERFLOW 0x086 +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_A 0x087 +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_B 0x088 +#define RA_ELC_EVENT_GPT6_COMPARE_C 0x089 +#define RA_ELC_EVENT_GPT6_COMPARE_D 0x08A +#define RA_ELC_EVENT_GPT6_COMPARE_E 0x08B +#define RA_ELC_EVENT_GPT6_COMPARE_F 0x08C +#define RA_ELC_EVENT_GPT6_COUNTER_OVERFLOW 0x08D +#define RA_ELC_EVENT_GPT6_COUNTER_UNDERFLOW 0x08E +#define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_A 0x08F +#define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_B 0x090 +#define RA_ELC_EVENT_GPT7_COMPARE_C 0x091 +#define RA_ELC_EVENT_GPT7_COMPARE_D 0x092 +#define RA_ELC_EVENT_GPT7_COMPARE_E 0x093 +#define RA_ELC_EVENT_GPT7_COMPARE_F 0x094 +#define RA_ELC_EVENT_GPT7_COUNTER_OVERFLOW 0x095 +#define RA_ELC_EVENT_GPT7_COUNTER_UNDERFLOW 0x096 +#define RA_ELC_EVENT_OPS_UVW_EDGE 0x097 +#define RA_ELC_EVENT_SCI0_RXI 0x098 +#define RA_ELC_EVENT_SCI0_TXI 0x099 +#define RA_ELC_EVENT_SCI0_TEI 0x09A +#define RA_ELC_EVENT_SCI0_ERI 0x09B +#define RA_ELC_EVENT_SCI0_AM 0x09C +#define RA_ELC_EVENT_SCI0_RXI_OR_ERI 0x09D +#define RA_ELC_EVENT_SCI1_RXI 0x09E +#define RA_ELC_EVENT_SCI1_TXI 0x09F +#define RA_ELC_EVENT_SCI1_TEI 0x0A0 +#define RA_ELC_EVENT_SCI1_ERI 0x0A1 +#define RA_ELC_EVENT_SCI1_AM 0x0A2 +#define RA_ELC_EVENT_SCI2_RXI 0x0A3 +#define RA_ELC_EVENT_SCI2_TXI 0x0A4 +#define RA_ELC_EVENT_SCI2_TEI 0x0A5 +#define RA_ELC_EVENT_SCI2_ERI 0x0A6 +#define RA_ELC_EVENT_SCI2_AM 0x0A7 +#define RA_ELC_EVENT_SCI9_RXI 0x0A8 +#define RA_ELC_EVENT_SCI9_TXI 0x0A9 +#define RA_ELC_EVENT_SCI9_TEI 0x0AA +#define RA_ELC_EVENT_SCI9_ERI 0x0AB +#define RA_ELC_EVENT_SCI9_AM 0x0AC +#define RA_ELC_EVENT_SPI0_RXI 0x0AD +#define RA_ELC_EVENT_SPI0_TXI 0x0AE +#define RA_ELC_EVENT_SPI0_IDLE 0x0AF +#define RA_ELC_EVENT_SPI0_ERI 0x0B0 +#define RA_ELC_EVENT_SPI0_TEI 0x0B1 +#define RA_ELC_EVENT_SPI1_RXI 0x0B2 +#define RA_ELC_EVENT_SPI1_TXI 0x0B3 +#define RA_ELC_EVENT_SPI1_IDLE 0x0B4 +#define RA_ELC_EVENT_SPI1_ERI 0x0B5 +#define RA_ELC_EVENT_SPI1_TEI 0x0B6 + +/* Possible peripherals to be linked to event signals */ +#define RA_ELC_PERIPHERAL_GPT_A 0 +#define RA_ELC_PERIPHERAL_GPT_B 1 +#define RA_ELC_PERIPHERAL_GPT_C 2 +#define RA_ELC_PERIPHERAL_GPT_D 3 +#define RA_ELC_PERIPHERAL_GPT_E 4 +#define RA_ELC_PERIPHERAL_GPT_F 5 +#define RA_ELC_PERIPHERAL_GPT_G 6 +#define RA_ELC_PERIPHERAL_GPT_H 7 +#define RA_ELC_PERIPHERAL_ADC0 8 +#define RA_ELC_PERIPHERAL_ADC0_B 9 +#define RA_ELC_PERIPHERAL_DAC0 12 +#define RA_ELC_PERIPHERAL_IOPORT1 14 +#define RA_ELC_PERIPHERAL_IOPORT2 15 +#define RA_ELC_PERIPHERAL_IOPORT3 16 +#define RA_ELC_PERIPHERAL_IOPORT4 17 +#define RA_ELC_PERIPHERAL_CTSU 18 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4M1_ELC_H_ */ diff --git a/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4m2-elc.h b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4m2-elc.h new file mode 100644 index 00000000000..f1ac2d36b23 --- /dev/null +++ b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4m2-elc.h @@ -0,0 +1,258 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4M2_ELC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4M2_ELC_H_ + +/* Sources of event signals to be linked to other peripherals or the CPU */ +#define RA_ELC_EVENT_NONE 0x0 +#define RA_ELC_EVENT_ICU_IRQ0 0x001 +#define RA_ELC_EVENT_ICU_IRQ1 0x002 +#define RA_ELC_EVENT_ICU_IRQ2 0x003 +#define RA_ELC_EVENT_ICU_IRQ3 0x004 +#define RA_ELC_EVENT_ICU_IRQ4 0x005 +#define RA_ELC_EVENT_ICU_IRQ5 0x006 +#define RA_ELC_EVENT_ICU_IRQ6 0x007 +#define RA_ELC_EVENT_ICU_IRQ7 0x008 +#define RA_ELC_EVENT_ICU_IRQ8 0x009 +#define RA_ELC_EVENT_ICU_IRQ9 0x00A +#define RA_ELC_EVENT_ICU_IRQ10 0x00B +#define RA_ELC_EVENT_ICU_IRQ11 0x00C +#define RA_ELC_EVENT_ICU_IRQ12 0x00D +#define RA_ELC_EVENT_ICU_IRQ13 0x00E +#define RA_ELC_EVENT_ICU_IRQ14 0x00F +#define RA_ELC_EVENT_ICU_IRQ15 0x010 +#define RA_ELC_EVENT_DMAC0_INT 0x020 +#define RA_ELC_EVENT_DMAC1_INT 0x021 +#define RA_ELC_EVENT_DMAC2_INT 0x022 +#define RA_ELC_EVENT_DMAC3_INT 0x023 +#define RA_ELC_EVENT_DMAC4_INT 0x024 +#define RA_ELC_EVENT_DMAC5_INT 0x025 +#define RA_ELC_EVENT_DMAC6_INT 0x026 +#define RA_ELC_EVENT_DMAC7_INT 0x027 +#define RA_ELC_EVENT_DTC_COMPLETE 0x029 +#define RA_ELC_EVENT_DTC_END 0x02A +#define RA_ELC_EVENT_DMA_TRANSERR 0x02B +#define RA_ELC_EVENT_ICU_SNOOZE_CANCEL 0x02D +#define RA_ELC_EVENT_FCU_FIFERR 0x030 +#define RA_ELC_EVENT_FCU_FRDYI 0x031 +#define RA_ELC_EVENT_LVD_LVD1 0x038 +#define RA_ELC_EVENT_LVD_LVD2 0x039 +#define RA_ELC_EVENT_CGC_MOSC_STOP 0x03B +#define RA_ELC_EVENT_LPM_SNOOZE_REQUEST 0x03C +#define RA_ELC_EVENT_AGT0_INT 0x040 +#define RA_ELC_EVENT_AGT0_COMPARE_A 0x041 +#define RA_ELC_EVENT_AGT0_COMPARE_B 0x042 +#define RA_ELC_EVENT_AGT1_INT 0x043 +#define RA_ELC_EVENT_AGT1_COMPARE_A 0x044 +#define RA_ELC_EVENT_AGT1_COMPARE_B 0x045 +#define RA_ELC_EVENT_AGT2_INT 0x046 +#define RA_ELC_EVENT_AGT2_COMPARE_A 0x047 +#define RA_ELC_EVENT_AGT2_COMPARE_B 0x048 +#define RA_ELC_EVENT_AGT3_INT 0x049 +#define RA_ELC_EVENT_AGT3_COMPARE_A 0x04A +#define RA_ELC_EVENT_AGT3_COMPARE_B 0x04B +#define RA_ELC_EVENT_AGT4_INT 0x04C +#define RA_ELC_EVENT_AGT4_COMPARE_A 0x04D +#define RA_ELC_EVENT_AGT4_COMPARE_B 0x04E +#define RA_ELC_EVENT_AGT5_INT 0x04F +#define RA_ELC_EVENT_AGT5_COMPARE_A 0x050 +#define RA_ELC_EVENT_AGT5_COMPARE_B 0x051 +#define RA_ELC_EVENT_IWDT_UNDERFLOW 0x052 +#define RA_ELC_EVENT_WDT_UNDERFLOW 0x053 +#define RA_ELC_EVENT_RTC_ALARM 0x054 +#define RA_ELC_EVENT_RTC_PERIOD 0x055 +#define RA_ELC_EVENT_RTC_CARRY 0x056 +#define RA_ELC_EVENT_USBFS_FIFO_0 0x06B +#define RA_ELC_EVENT_USBFS_FIFO_1 0x06C +#define RA_ELC_EVENT_USBFS_INT 0x06D +#define RA_ELC_EVENT_USBFS_RESUME 0x06E +#define RA_ELC_EVENT_IIC0_RXI 0x073 +#define RA_ELC_EVENT_IIC0_TXI 0x074 +#define RA_ELC_EVENT_IIC0_TEI 0x075 +#define RA_ELC_EVENT_IIC0_ERI 0x076 +#define RA_ELC_EVENT_IIC0_WUI 0x077 +#define RA_ELC_EVENT_IIC1_RXI 0x078 +#define RA_ELC_EVENT_IIC1_TXI 0x079 +#define RA_ELC_EVENT_IIC1_TEI 0x07A +#define RA_ELC_EVENT_IIC1_ERI 0x07B +#define RA_ELC_EVENT_SDHIMMC0_ACCS 0x082 +#define RA_ELC_EVENT_SDHIMMC0_SDIO 0x083 +#define RA_ELC_EVENT_SDHIMMC0_CARD 0x084 +#define RA_ELC_EVENT_SDHIMMC0_DMA_REQ 0x085 +#define RA_ELC_EVENT_SSI0_TXI 0x08A +#define RA_ELC_EVENT_SSI0_RXI 0x08B +#define RA_ELC_EVENT_SSI0_INT 0x08D +#define RA_ELC_EVENT_CTSU_WRITE 0x09A +#define RA_ELC_EVENT_CTSU_READ 0x09B +#define RA_ELC_EVENT_CTSU_END 0x09C +#define RA_ELC_EVENT_CAC_FREQUENCY_ERROR 0x09E +#define RA_ELC_EVENT_CAC_MEASUREMENT_END 0x09F +#define RA_ELC_EVENT_CAC_OVERFLOW 0x0A0 +#define RA_ELC_EVENT_CAN0_ERROR 0x0A1 +#define RA_ELC_EVENT_CAN0_FIFO_RX 0x0A2 +#define RA_ELC_EVENT_CAN0_FIFO_TX 0x0A3 +#define RA_ELC_EVENT_CAN0_MAILBOX_RX 0x0A4 +#define RA_ELC_EVENT_CAN0_MAILBOX_TX 0x0A5 +#define RA_ELC_EVENT_IOPORT_EVENT_1 0x0B1 +#define RA_ELC_EVENT_IOPORT_EVENT_2 0x0B2 +#define RA_ELC_EVENT_IOPORT_EVENT_3 0x0B3 +#define RA_ELC_EVENT_IOPORT_EVENT_4 0x0B4 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0 0x0B5 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1 0x0B6 +#define RA_ELC_EVENT_POEG0_EVENT 0x0B7 +#define RA_ELC_EVENT_POEG1_EVENT 0x0B8 +#define RA_ELC_EVENT_POEG2_EVENT 0x0B9 +#define RA_ELC_EVENT_POEG3_EVENT 0x0BA +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_A 0x0C0 +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_B 0x0C1 +#define RA_ELC_EVENT_GPT0_COMPARE_C 0x0C2 +#define RA_ELC_EVENT_GPT0_COMPARE_D 0x0C3 +#define RA_ELC_EVENT_GPT0_COMPARE_E 0x0C4 +#define RA_ELC_EVENT_GPT0_COMPARE_F 0x0C5 +#define RA_ELC_EVENT_GPT0_COUNTER_OVERFLOW 0x0C6 +#define RA_ELC_EVENT_GPT0_COUNTER_UNDERFLOW 0x0C7 +#define RA_ELC_EVENT_GPT0_PC 0x0C8 +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_A 0x0C9 +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_B 0x0CA +#define RA_ELC_EVENT_GPT1_COMPARE_C 0x0CB +#define RA_ELC_EVENT_GPT1_COMPARE_D 0x0CC +#define RA_ELC_EVENT_GPT1_COMPARE_E 0x0CD +#define RA_ELC_EVENT_GPT1_COMPARE_F 0x0CE +#define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x0CF +#define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x0D0 +#define RA_ELC_EVENT_GPT1_PC 0x0D1 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_A 0x0D2 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_B 0x0D3 +#define RA_ELC_EVENT_GPT2_COMPARE_C 0x0D4 +#define RA_ELC_EVENT_GPT2_COMPARE_D 0x0D5 +#define RA_ELC_EVENT_GPT2_COMPARE_E 0x0D6 +#define RA_ELC_EVENT_GPT2_COMPARE_F 0x0D7 +#define RA_ELC_EVENT_GPT2_COUNTER_OVERFLOW 0x0D8 +#define RA_ELC_EVENT_GPT2_COUNTER_UNDERFLOW 0x0D9 +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_A 0x0DB +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_B 0x0DC +#define RA_ELC_EVENT_GPT3_COMPARE_C 0x0DD +#define RA_ELC_EVENT_GPT3_COMPARE_D 0x0DE +#define RA_ELC_EVENT_GPT3_COMPARE_E 0x0DF +#define RA_ELC_EVENT_GPT3_COMPARE_F 0x0E0 +#define RA_ELC_EVENT_GPT3_COUNTER_OVERFLOW 0x0E1 +#define RA_ELC_EVENT_GPT3_COUNTER_UNDERFLOW 0x0E2 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_A 0x0E4 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_B 0x0E5 +#define RA_ELC_EVENT_GPT4_COMPARE_C 0x0E6 +#define RA_ELC_EVENT_GPT4_COMPARE_D 0x0E7 +#define RA_ELC_EVENT_GPT4_COMPARE_E 0x0E8 +#define RA_ELC_EVENT_GPT4_COMPARE_F 0x0E9 +#define RA_ELC_EVENT_GPT4_COUNTER_OVERFLOW 0x0EA +#define RA_ELC_EVENT_GPT4_COUNTER_UNDERFLOW 0x0EB +#define RA_ELC_EVENT_GPT4_PC 0x0EC +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_A 0x0ED +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_B 0x0EE +#define RA_ELC_EVENT_GPT5_COMPARE_C 0x0EF +#define RA_ELC_EVENT_GPT5_COMPARE_D 0x0F0 +#define RA_ELC_EVENT_GPT5_COMPARE_E 0x0F1 +#define RA_ELC_EVENT_GPT5_COMPARE_F 0x0F2 +#define RA_ELC_EVENT_GPT5_COUNTER_OVERFLOW 0x0F3 +#define RA_ELC_EVENT_GPT5_COUNTER_UNDERFLOW 0x0F4 +#define RA_ELC_EVENT_GPT5_PC 0x0F5 +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_A 0x0F6 +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_B 0x0F7 +#define RA_ELC_EVENT_GPT6_COMPARE_C 0x0F8 +#define RA_ELC_EVENT_GPT6_COMPARE_D 0x0F9 +#define RA_ELC_EVENT_GPT6_COMPARE_E 0x0FA +#define RA_ELC_EVENT_GPT6_COMPARE_F 0x0FB +#define RA_ELC_EVENT_GPT6_COUNTER_OVERFLOW 0x0FC +#define RA_ELC_EVENT_GPT6_COUNTER_UNDERFLOW 0x0FD +#define RA_ELC_EVENT_GPT6_PC 0x0FE +#define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_A 0x0FF +#define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_B 0x100 +#define RA_ELC_EVENT_GPT7_COMPARE_C 0x101 +#define RA_ELC_EVENT_GPT7_COMPARE_D 0x102 +#define RA_ELC_EVENT_GPT7_COMPARE_E 0x103 +#define RA_ELC_EVENT_GPT7_COMPARE_F 0x104 +#define RA_ELC_EVENT_GPT7_COUNTER_OVERFLOW 0x105 +#define RA_ELC_EVENT_GPT7_COUNTER_UNDERFLOW 0x106 +#define RA_ELC_EVENT_OPS_UVW_EDGE 0x150 +#define RA_ELC_EVENT_ADC0_SCAN_END 0x160 +#define RA_ELC_EVENT_ADC0_SCAN_END_B 0x161 +#define RA_ELC_EVENT_ADC0_WINDOW_A 0x162 +#define RA_ELC_EVENT_ADC0_WINDOW_B 0x163 +#define RA_ELC_EVENT_ADC0_COMPARE_MATCH 0x164 +#define RA_ELC_EVENT_ADC0_COMPARE_MISMATCH 0x165 +#define RA_ELC_EVENT_SCI0_RXI 0x180 +#define RA_ELC_EVENT_SCI0_TXI 0x181 +#define RA_ELC_EVENT_SCI0_TEI 0x182 +#define RA_ELC_EVENT_SCI0_ERI 0x183 +#define RA_ELC_EVENT_SCI0_AM 0x184 +#define RA_ELC_EVENT_SCI0_RXI_OR_ERI 0x185 +#define RA_ELC_EVENT_SCI1_RXI 0x186 +#define RA_ELC_EVENT_SCI1_TXI 0x187 +#define RA_ELC_EVENT_SCI1_TEI 0x188 +#define RA_ELC_EVENT_SCI1_ERI 0x189 +#define RA_ELC_EVENT_SCI2_RXI 0x18C +#define RA_ELC_EVENT_SCI2_TXI 0x18D +#define RA_ELC_EVENT_SCI2_TEI 0x18E +#define RA_ELC_EVENT_SCI2_ERI 0x18F +#define RA_ELC_EVENT_SCI3_RXI 0x192 +#define RA_ELC_EVENT_SCI3_TXI 0x193 +#define RA_ELC_EVENT_SCI3_TEI 0x194 +#define RA_ELC_EVENT_SCI3_ERI 0x195 +#define RA_ELC_EVENT_SCI3_AM 0x196 +#define RA_ELC_EVENT_SCI4_RXI 0x198 +#define RA_ELC_EVENT_SCI4_TXI 0x199 +#define RA_ELC_EVENT_SCI4_TEI 0x19A +#define RA_ELC_EVENT_SCI4_ERI 0x19B +#define RA_ELC_EVENT_SCI4_AM 0x19C +#define RA_ELC_EVENT_SCI9_RXI 0x1B6 +#define RA_ELC_EVENT_SCI9_TXI 0x1B7 +#define RA_ELC_EVENT_SCI9_TEI 0x1B8 +#define RA_ELC_EVENT_SCI9_ERI 0x1B9 +#define RA_ELC_EVENT_SCI9_AM 0x1BA +#define RA_ELC_EVENT_SCIX0_SCIX0 0x1BC +#define RA_ELC_EVENT_SCI1_SCIX0 0x1BC +#define RA_ELC_EVENT_SCIX0_SCIX1 0x1BD +#define RA_ELC_EVENT_SCI1_SCIX1 0x1BD +#define RA_ELC_EVENT_SCIX0_SCIX2 0x1BE +#define RA_ELC_EVENT_SCI1_SCIX2 0x1BE +#define RA_ELC_EVENT_SCIX0_SCIX3 0x1BF +#define RA_ELC_EVENT_SCI1_SCIX3 0x1BF +#define RA_ELC_EVENT_SCIX1_SCIX0 0x1C0 +#define RA_ELC_EVENT_SCI2_SCIX0 0x1C0 +#define RA_ELC_EVENT_SCIX1_SCIX1 0x1C1 +#define RA_ELC_EVENT_SCI2_SCIX1 0x1C1 +#define RA_ELC_EVENT_SCIX1_SCIX2 0x1C2 +#define RA_ELC_EVENT_SCI2_SCIX2 0x1C2 +#define RA_ELC_EVENT_SCIX1_SCIX3 0x1C3 +#define RA_ELC_EVENT_SCI2_SCIX3 0x1C3 +#define RA_ELC_EVENT_SPI0_RXI 0x1C4 +#define RA_ELC_EVENT_SPI0_TXI 0x1C5 +#define RA_ELC_EVENT_SPI0_IDLE 0x1C6 +#define RA_ELC_EVENT_SPI0_ERI 0x1C7 +#define RA_ELC_EVENT_SPI0_TEI 0x1C8 +#define RA_ELC_EVENT_QSPI_INT 0x1DA +#define RA_ELC_EVENT_DOC_INT 0x1DB + +/* Possible peripherals to be linked to event signals */ +#define RA_ELC_PERIPHERAL_GPT_A 0 +#define RA_ELC_PERIPHERAL_GPT_B 1 +#define RA_ELC_PERIPHERAL_GPT_C 2 +#define RA_ELC_PERIPHERAL_GPT_D 3 +#define RA_ELC_PERIPHERAL_GPT_E 4 +#define RA_ELC_PERIPHERAL_GPT_F 5 +#define RA_ELC_PERIPHERAL_GPT_G 6 +#define RA_ELC_PERIPHERAL_GPT_H 7 +#define RA_ELC_PERIPHERAL_ADC0 8 +#define RA_ELC_PERIPHERAL_ADC0_B 9 +#define RA_ELC_PERIPHERAL_DAC0 12 +#define RA_ELC_PERIPHERAL_DAC1 13 +#define RA_ELC_PERIPHERAL_IOPORT1 14 +#define RA_ELC_PERIPHERAL_IOPORT2 15 +#define RA_ELC_PERIPHERAL_IOPORT3 16 +#define RA_ELC_PERIPHERAL_IOPORT4 17 +#define RA_ELC_PERIPHERAL_CTSU 18 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4M2_ELC_H_ */ diff --git a/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4m3-elc.h b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4m3-elc.h new file mode 100644 index 00000000000..6cdf4101d40 --- /dev/null +++ b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4m3-elc.h @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4M3_ELC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4M3_ELC_H_ + +/* Sources of event signals to be linked to other peripherals or the CPU */ +#define RA_ELC_EVENT_NONE 0x0 +#define RA_ELC_EVENT_ICU_IRQ0 0x001 +#define RA_ELC_EVENT_ICU_IRQ1 0x002 +#define RA_ELC_EVENT_ICU_IRQ2 0x003 +#define RA_ELC_EVENT_ICU_IRQ3 0x004 +#define RA_ELC_EVENT_ICU_IRQ4 0x005 +#define RA_ELC_EVENT_ICU_IRQ5 0x006 +#define RA_ELC_EVENT_ICU_IRQ6 0x007 +#define RA_ELC_EVENT_ICU_IRQ7 0x008 +#define RA_ELC_EVENT_ICU_IRQ8 0x009 +#define RA_ELC_EVENT_ICU_IRQ9 0x00A +#define RA_ELC_EVENT_ICU_IRQ10 0x00B +#define RA_ELC_EVENT_ICU_IRQ11 0x00C +#define RA_ELC_EVENT_ICU_IRQ12 0x00D +#define RA_ELC_EVENT_ICU_IRQ13 0x00E +#define RA_ELC_EVENT_ICU_IRQ14 0x00F +#define RA_ELC_EVENT_ICU_IRQ15 0x010 +#define RA_ELC_EVENT_DMAC0_INT 0x020 +#define RA_ELC_EVENT_DMAC1_INT 0x021 +#define RA_ELC_EVENT_DMAC2_INT 0x022 +#define RA_ELC_EVENT_DMAC3_INT 0x023 +#define RA_ELC_EVENT_DMAC4_INT 0x024 +#define RA_ELC_EVENT_DMAC5_INT 0x025 +#define RA_ELC_EVENT_DMAC6_INT 0x026 +#define RA_ELC_EVENT_DMAC7_INT 0x027 +#define RA_ELC_EVENT_DTC_COMPLETE 0x029 +#define RA_ELC_EVENT_DTC_END 0x02A +#define RA_ELC_EVENT_DMA_TRANSERR 0x02B +#define RA_ELC_EVENT_ICU_SNOOZE_CANCEL 0x02D +#define RA_ELC_EVENT_FCU_FIFERR 0x030 +#define RA_ELC_EVENT_FCU_FRDYI 0x031 +#define RA_ELC_EVENT_LVD_LVD1 0x038 +#define RA_ELC_EVENT_LVD_LVD2 0x039 +#define RA_ELC_EVENT_CGC_MOSC_STOP 0x03B +#define RA_ELC_EVENT_LPM_SNOOZE_REQUEST 0x03C +#define RA_ELC_EVENT_AGT0_INT 0x040 +#define RA_ELC_EVENT_AGT0_COMPARE_A 0x041 +#define RA_ELC_EVENT_AGT0_COMPARE_B 0x042 +#define RA_ELC_EVENT_AGT1_INT 0x043 +#define RA_ELC_EVENT_AGT1_COMPARE_A 0x044 +#define RA_ELC_EVENT_AGT1_COMPARE_B 0x045 +#define RA_ELC_EVENT_AGT2_INT 0x046 +#define RA_ELC_EVENT_AGT2_COMPARE_A 0x047 +#define RA_ELC_EVENT_AGT2_COMPARE_B 0x048 +#define RA_ELC_EVENT_AGT3_INT 0x049 +#define RA_ELC_EVENT_AGT3_COMPARE_A 0x04A +#define RA_ELC_EVENT_AGT3_COMPARE_B 0x04B +#define RA_ELC_EVENT_AGT4_INT 0x04C +#define RA_ELC_EVENT_AGT4_COMPARE_A 0x04D +#define RA_ELC_EVENT_AGT4_COMPARE_B 0x04E +#define RA_ELC_EVENT_AGT5_INT 0x04F +#define RA_ELC_EVENT_AGT5_COMPARE_A 0x050 +#define RA_ELC_EVENT_AGT5_COMPARE_B 0x051 +#define RA_ELC_EVENT_IWDT_UNDERFLOW 0x052 +#define RA_ELC_EVENT_WDT_UNDERFLOW 0x053 +#define RA_ELC_EVENT_RTC_ALARM 0x054 +#define RA_ELC_EVENT_RTC_PERIOD 0x055 +#define RA_ELC_EVENT_RTC_CARRY 0x056 +#define RA_ELC_EVENT_USBFS_FIFO_0 0x06B +#define RA_ELC_EVENT_USBFS_FIFO_1 0x06C +#define RA_ELC_EVENT_USBFS_INT 0x06D +#define RA_ELC_EVENT_USBFS_RESUME 0x06E +#define RA_ELC_EVENT_IIC0_RXI 0x073 +#define RA_ELC_EVENT_IIC0_TXI 0x074 +#define RA_ELC_EVENT_IIC0_TEI 0x075 +#define RA_ELC_EVENT_IIC0_ERI 0x076 +#define RA_ELC_EVENT_IIC0_WUI 0x077 +#define RA_ELC_EVENT_IIC1_RXI 0x078 +#define RA_ELC_EVENT_IIC1_TXI 0x079 +#define RA_ELC_EVENT_IIC1_TEI 0x07A +#define RA_ELC_EVENT_IIC1_ERI 0x07B +#define RA_ELC_EVENT_SDHIMMC0_ACCS 0x082 +#define RA_ELC_EVENT_SDHIMMC0_SDIO 0x083 +#define RA_ELC_EVENT_SDHIMMC0_CARD 0x084 +#define RA_ELC_EVENT_SDHIMMC0_DMA_REQ 0x085 +#define RA_ELC_EVENT_SSI0_TXI 0x08A +#define RA_ELC_EVENT_SSI0_RXI 0x08B +#define RA_ELC_EVENT_SSI0_INT 0x08D +#define RA_ELC_EVENT_CTSU_WRITE 0x09A +#define RA_ELC_EVENT_CTSU_READ 0x09B +#define RA_ELC_EVENT_CTSU_END 0x09C +#define RA_ELC_EVENT_CAC_FREQUENCY_ERROR 0x09E +#define RA_ELC_EVENT_CAC_MEASUREMENT_END 0x09F +#define RA_ELC_EVENT_CAC_OVERFLOW 0x0A0 +#define RA_ELC_EVENT_CAN0_ERROR 0x0A1 +#define RA_ELC_EVENT_CAN0_FIFO_RX 0x0A2 +#define RA_ELC_EVENT_CAN0_FIFO_TX 0x0A3 +#define RA_ELC_EVENT_CAN0_MAILBOX_RX 0x0A4 +#define RA_ELC_EVENT_CAN0_MAILBOX_TX 0x0A5 +#define RA_ELC_EVENT_CAN1_ERROR 0x0A6 +#define RA_ELC_EVENT_CAN1_FIFO_RX 0x0A7 +#define RA_ELC_EVENT_CAN1_FIFO_TX 0x0A8 +#define RA_ELC_EVENT_CAN1_MAILBOX_RX 0x0A9 +#define RA_ELC_EVENT_CAN1_MAILBOX_TX 0x0AA +#define RA_ELC_EVENT_IOPORT_EVENT_1 0x0B1 +#define RA_ELC_EVENT_IOPORT_EVENT_2 0x0B2 +#define RA_ELC_EVENT_IOPORT_EVENT_3 0x0B3 +#define RA_ELC_EVENT_IOPORT_EVENT_4 0x0B4 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0 0x0B5 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1 0x0B6 +#define RA_ELC_EVENT_POEG0_EVENT 0x0B7 +#define RA_ELC_EVENT_POEG1_EVENT 0x0B8 +#define RA_ELC_EVENT_POEG2_EVENT 0x0B9 +#define RA_ELC_EVENT_POEG3_EVENT 0x0BA +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_A 0x0C0 +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_B 0x0C1 +#define RA_ELC_EVENT_GPT0_COMPARE_C 0x0C2 +#define RA_ELC_EVENT_GPT0_COMPARE_D 0x0C3 +#define RA_ELC_EVENT_GPT0_COMPARE_E 0x0C4 +#define RA_ELC_EVENT_GPT0_COMPARE_F 0x0C5 +#define RA_ELC_EVENT_GPT0_COUNTER_OVERFLOW 0x0C6 +#define RA_ELC_EVENT_GPT0_COUNTER_UNDERFLOW 0x0C7 +#define RA_ELC_EVENT_GPT0_PC 0x0C8 +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_A 0x0C9 +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_B 0x0CA +#define RA_ELC_EVENT_GPT1_COMPARE_C 0x0CB +#define RA_ELC_EVENT_GPT1_COMPARE_D 0x0CC +#define RA_ELC_EVENT_GPT1_COMPARE_E 0x0CD +#define RA_ELC_EVENT_GPT1_COMPARE_F 0x0CE +#define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x0CF +#define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x0D0 +#define RA_ELC_EVENT_GPT1_PC 0x0D1 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_A 0x0D2 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_B 0x0D3 +#define RA_ELC_EVENT_GPT2_COMPARE_C 0x0D4 +#define RA_ELC_EVENT_GPT2_COMPARE_D 0x0D5 +#define RA_ELC_EVENT_GPT2_COMPARE_E 0x0D6 +#define RA_ELC_EVENT_GPT2_COMPARE_F 0x0D7 +#define RA_ELC_EVENT_GPT2_COUNTER_OVERFLOW 0x0D8 +#define RA_ELC_EVENT_GPT2_COUNTER_UNDERFLOW 0x0D9 +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_A 0x0DB +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_B 0x0DC +#define RA_ELC_EVENT_GPT3_COMPARE_C 0x0DD +#define RA_ELC_EVENT_GPT3_COMPARE_D 0x0DE +#define RA_ELC_EVENT_GPT3_COMPARE_E 0x0DF +#define RA_ELC_EVENT_GPT3_COMPARE_F 0x0E0 +#define RA_ELC_EVENT_GPT3_COUNTER_OVERFLOW 0x0E1 +#define RA_ELC_EVENT_GPT3_COUNTER_UNDERFLOW 0x0E2 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_A 0x0E4 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_B 0x0E5 +#define RA_ELC_EVENT_GPT4_COMPARE_C 0x0E6 +#define RA_ELC_EVENT_GPT4_COMPARE_D 0x0E7 +#define RA_ELC_EVENT_GPT4_COMPARE_E 0x0E8 +#define RA_ELC_EVENT_GPT4_COMPARE_F 0x0E9 +#define RA_ELC_EVENT_GPT4_COUNTER_OVERFLOW 0x0EA +#define RA_ELC_EVENT_GPT4_COUNTER_UNDERFLOW 0x0EB +#define RA_ELC_EVENT_GPT4_PC 0x0EC +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_A 0x0ED +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_B 0x0EE +#define RA_ELC_EVENT_GPT5_COMPARE_C 0x0EF +#define RA_ELC_EVENT_GPT5_COMPARE_D 0x0F0 +#define RA_ELC_EVENT_GPT5_COMPARE_E 0x0F1 +#define RA_ELC_EVENT_GPT5_COMPARE_F 0x0F2 +#define RA_ELC_EVENT_GPT5_COUNTER_OVERFLOW 0x0F3 +#define RA_ELC_EVENT_GPT5_COUNTER_UNDERFLOW 0x0F4 +#define RA_ELC_EVENT_GPT5_PC 0x0F5 +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_A 0x0F6 +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_B 0x0F7 +#define RA_ELC_EVENT_GPT6_COMPARE_C 0x0F8 +#define RA_ELC_EVENT_GPT6_COMPARE_D 0x0F9 +#define RA_ELC_EVENT_GPT6_COMPARE_E 0x0FA +#define RA_ELC_EVENT_GPT6_COMPARE_F 0x0FB +#define RA_ELC_EVENT_GPT6_COUNTER_OVERFLOW 0x0FC +#define RA_ELC_EVENT_GPT6_COUNTER_UNDERFLOW 0x0FD +#define RA_ELC_EVENT_GPT6_PC 0x0FE +#define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_A 0x0FF +#define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_B 0x100 +#define RA_ELC_EVENT_GPT7_COMPARE_C 0x101 +#define RA_ELC_EVENT_GPT7_COMPARE_D 0x102 +#define RA_ELC_EVENT_GPT7_COMPARE_E 0x103 +#define RA_ELC_EVENT_GPT7_COMPARE_F 0x104 +#define RA_ELC_EVENT_GPT7_COUNTER_OVERFLOW 0x105 +#define RA_ELC_EVENT_GPT7_COUNTER_UNDERFLOW 0x106 +#define RA_ELC_EVENT_OPS_UVW_EDGE 0x150 +#define RA_ELC_EVENT_ADC0_SCAN_END 0x160 +#define RA_ELC_EVENT_ADC0_SCAN_END_B 0x161 +#define RA_ELC_EVENT_ADC0_WINDOW_A 0x162 +#define RA_ELC_EVENT_ADC0_WINDOW_B 0x163 +#define RA_ELC_EVENT_ADC0_COMPARE_MATCH 0x164 +#define RA_ELC_EVENT_ADC0_COMPARE_MISMATCH 0x165 +#define RA_ELC_EVENT_ADC1_SCAN_END 0x166 +#define RA_ELC_EVENT_ADC1_SCAN_END_B 0x167 +#define RA_ELC_EVENT_ADC1_WINDOW_A 0x168 +#define RA_ELC_EVENT_ADC1_WINDOW_B 0x169 +#define RA_ELC_EVENT_ADC1_COMPARE_MATCH 0x16A +#define RA_ELC_EVENT_ADC1_COMPARE_MISMATCH 0x16B +#define RA_ELC_EVENT_SCI0_RXI 0x180 +#define RA_ELC_EVENT_SCI0_TXI 0x181 +#define RA_ELC_EVENT_SCI0_TEI 0x182 +#define RA_ELC_EVENT_SCI0_ERI 0x183 +#define RA_ELC_EVENT_SCI0_AM 0x184 +#define RA_ELC_EVENT_SCI0_RXI_OR_ERI 0x185 +#define RA_ELC_EVENT_SCI1_RXI 0x186 +#define RA_ELC_EVENT_SCI1_TXI 0x187 +#define RA_ELC_EVENT_SCI1_TEI 0x188 +#define RA_ELC_EVENT_SCI1_ERI 0x189 +#define RA_ELC_EVENT_SCI2_RXI 0x18C +#define RA_ELC_EVENT_SCI2_TXI 0x18D +#define RA_ELC_EVENT_SCI2_TEI 0x18E +#define RA_ELC_EVENT_SCI2_ERI 0x18F +#define RA_ELC_EVENT_SCI3_RXI 0x192 +#define RA_ELC_EVENT_SCI3_TXI 0x193 +#define RA_ELC_EVENT_SCI3_TEI 0x194 +#define RA_ELC_EVENT_SCI3_ERI 0x195 +#define RA_ELC_EVENT_SCI3_AM 0x196 +#define RA_ELC_EVENT_SCI4_RXI 0x198 +#define RA_ELC_EVENT_SCI4_TXI 0x199 +#define RA_ELC_EVENT_SCI4_TEI 0x19A +#define RA_ELC_EVENT_SCI4_ERI 0x19B +#define RA_ELC_EVENT_SCI4_AM 0x19C +#define RA_ELC_EVENT_SCI9_RXI 0x1B6 +#define RA_ELC_EVENT_SCI9_TXI 0x1B7 +#define RA_ELC_EVENT_SCI9_TEI 0x1B8 +#define RA_ELC_EVENT_SCI9_ERI 0x1B9 +#define RA_ELC_EVENT_SCI9_AM 0x1BA +#define RA_ELC_EVENT_SCIX0_SCIX0 0x1BC +#define RA_ELC_EVENT_SCI1_SCIX0 0x1BC +#define RA_ELC_EVENT_SCIX0_SCIX1 0x1BD +#define RA_ELC_EVENT_SCI1_SCIX1 0x1BD +#define RA_ELC_EVENT_SCIX0_SCIX2 0x1BE +#define RA_ELC_EVENT_SCI1_SCIX2 0x1BE +#define RA_ELC_EVENT_SCIX0_SCIX3 0x1BF +#define RA_ELC_EVENT_SCI1_SCIX3 0x1BF +#define RA_ELC_EVENT_SCIX1_SCIX0 0x1C0 +#define RA_ELC_EVENT_SCI2_SCIX0 0x1C0 +#define RA_ELC_EVENT_SCIX1_SCIX1 0x1C1 +#define RA_ELC_EVENT_SCI2_SCIX1 0x1C1 +#define RA_ELC_EVENT_SCIX1_SCIX2 0x1C2 +#define RA_ELC_EVENT_SCI2_SCIX2 0x1C2 +#define RA_ELC_EVENT_SCIX1_SCIX3 0x1C3 +#define RA_ELC_EVENT_SCI2_SCIX3 0x1C3 +#define RA_ELC_EVENT_SPI0_RXI 0x1C4 +#define RA_ELC_EVENT_SPI0_TXI 0x1C5 +#define RA_ELC_EVENT_SPI0_IDLE 0x1C6 +#define RA_ELC_EVENT_SPI0_ERI 0x1C7 +#define RA_ELC_EVENT_SPI0_TEI 0x1C8 +#define RA_ELC_EVENT_QSPI_INT 0x1DA +#define RA_ELC_EVENT_DOC_INT 0x1DB + +/* Possible peripherals to be linked to event signals */ +#define RA_ELC_PERIPHERAL_GPT_A 0 +#define RA_ELC_PERIPHERAL_GPT_B 1 +#define RA_ELC_PERIPHERAL_GPT_C 2 +#define RA_ELC_PERIPHERAL_GPT_D 3 +#define RA_ELC_PERIPHERAL_GPT_E 4 +#define RA_ELC_PERIPHERAL_GPT_F 5 +#define RA_ELC_PERIPHERAL_GPT_G 6 +#define RA_ELC_PERIPHERAL_GPT_H 7 +#define RA_ELC_PERIPHERAL_ADC0 8 +#define RA_ELC_PERIPHERAL_ADC0_B 9 +#define RA_ELC_PERIPHERAL_ADC1 10 +#define RA_ELC_PERIPHERAL_ADC1_B 11 +#define RA_ELC_PERIPHERAL_DAC0 12 +#define RA_ELC_PERIPHERAL_DAC1 13 +#define RA_ELC_PERIPHERAL_IOPORT1 14 +#define RA_ELC_PERIPHERAL_IOPORT2 15 +#define RA_ELC_PERIPHERAL_IOPORT3 16 +#define RA_ELC_PERIPHERAL_IOPORT4 17 +#define RA_ELC_PERIPHERAL_CTSU 18 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4M3_ELC_H_ */ diff --git a/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4w1-elc.h b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4w1-elc.h new file mode 100644 index 00000000000..b518c48d08a --- /dev/null +++ b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra4w1-elc.h @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4W1_ELC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4W1_ELC_H_ + +/* Sources of event signals to be linked to other peripherals or the CPU */ +#define RA_ELC_EVENT_NONE 0x0 +#define RA_ELC_EVENT_ICU_IRQ0 0x001 +#define RA_ELC_EVENT_ICU_IRQ1 0x002 +#define RA_ELC_EVENT_ICU_IRQ2 0x003 +#define RA_ELC_EVENT_ICU_IRQ3 0x004 +#define RA_ELC_EVENT_ICU_IRQ4 0x005 +#define RA_ELC_EVENT_ICU_IRQ6 0x007 +#define RA_ELC_EVENT_ICU_IRQ7 0x008 +#define RA_ELC_EVENT_ICU_IRQ8 0x009 +#define RA_ELC_EVENT_ICU_IRQ9 0x00A +#define RA_ELC_EVENT_ICU_IRQ11 0x00C +#define RA_ELC_EVENT_ICU_IRQ14 0x00F +#define RA_ELC_EVENT_ICU_IRQ15 0x010 +#define RA_ELC_EVENT_DMAC0_INT 0x011 +#define RA_ELC_EVENT_DMAC1_INT 0x012 +#define RA_ELC_EVENT_DMAC2_INT 0x013 +#define RA_ELC_EVENT_DMAC3_INT 0x014 +#define RA_ELC_EVENT_DTC_COMPLETE 0x015 +#define RA_ELC_EVENT_DTC_END 0x016 +#define RA_ELC_EVENT_ICU_SNOOZE_CANCEL 0x017 +#define RA_ELC_EVENT_FCU_FRDYI 0x018 +#define RA_ELC_EVENT_LVD_LVD1 0x019 +#define RA_ELC_EVENT_LVD_VBATT 0x01B +#define RA_ELC_EVENT_CGC_MOSC_STOP 0x01C +#define RA_ELC_EVENT_LPM_SNOOZE_REQUEST 0x01D +#define RA_ELC_EVENT_AGT0_INT 0x01E +#define RA_ELC_EVENT_AGT0_COMPARE_A 0x01F +#define RA_ELC_EVENT_AGT0_COMPARE_B 0x020 +#define RA_ELC_EVENT_AGT1_INT 0x021 +#define RA_ELC_EVENT_AGT1_COMPARE_A 0x022 +#define RA_ELC_EVENT_AGT1_COMPARE_B 0x023 +#define RA_ELC_EVENT_IWDT_UNDERFLOW 0x024 +#define RA_ELC_EVENT_WDT_UNDERFLOW 0x025 +#define RA_ELC_EVENT_RTC_ALARM 0x026 +#define RA_ELC_EVENT_RTC_PERIOD 0x027 +#define RA_ELC_EVENT_RTC_CARRY 0x028 +#define RA_ELC_EVENT_ADC0_SCAN_END 0x029 +#define RA_ELC_EVENT_ADC0_SCAN_END_B 0x02A +#define RA_ELC_EVENT_ADC0_WINDOW_A 0x02B +#define RA_ELC_EVENT_ADC0_WINDOW_B 0x02C +#define RA_ELC_EVENT_ADC0_COMPARE_MATCH 0x02D +#define RA_ELC_EVENT_ADC0_COMPARE_MISMATCH 0x02E +#define RA_ELC_EVENT_ACMPLP0_INT 0x02F +#define RA_ELC_EVENT_ACMPLP1_INT 0x030 +#define RA_ELC_EVENT_USBFS_FIFO_0 0x031 +#define RA_ELC_EVENT_USBFS_FIFO_1 0x032 +#define RA_ELC_EVENT_USBFS_INT 0x033 +#define RA_ELC_EVENT_USBFS_RESUME 0x034 +#define RA_ELC_EVENT_IIC0_RXI 0x035 +#define RA_ELC_EVENT_IIC0_TXI 0x036 +#define RA_ELC_EVENT_IIC0_TEI 0x037 +#define RA_ELC_EVENT_IIC0_ERI 0x038 +#define RA_ELC_EVENT_IIC0_WUI 0x039 +#define RA_ELC_EVENT_IIC1_RXI 0x03A +#define RA_ELC_EVENT_IIC1_TXI 0x03B +#define RA_ELC_EVENT_IIC1_TEI 0x03C +#define RA_ELC_EVENT_IIC1_ERI 0x03D +#define RA_ELC_EVENT_CTSU_WRITE 0x046 +#define RA_ELC_EVENT_CTSU_READ 0x047 +#define RA_ELC_EVENT_CTSU_END 0x048 +#define RA_ELC_EVENT_KEY_INT 0x049 +#define RA_ELC_EVENT_DOC_INT 0x04A +#define RA_ELC_EVENT_CAC_FREQUENCY_ERROR 0x04B +#define RA_ELC_EVENT_CAC_MEASUREMENT_END 0x04C +#define RA_ELC_EVENT_CAC_OVERFLOW 0x04D +#define RA_ELC_EVENT_CAN0_ERROR 0x04E +#define RA_ELC_EVENT_CAN0_FIFO_RX 0x04F +#define RA_ELC_EVENT_CAN0_FIFO_TX 0x050 +#define RA_ELC_EVENT_CAN0_MAILBOX_RX 0x051 +#define RA_ELC_EVENT_CAN0_MAILBOX_TX 0x052 +#define RA_ELC_EVENT_IOPORT_EVENT_1 0x053 +#define RA_ELC_EVENT_IOPORT_EVENT_2 0x054 +#define RA_ELC_EVENT_IOPORT_EVENT_3 0x055 +#define RA_ELC_EVENT_IOPORT_EVENT_4 0x056 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0 0x057 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1 0x058 +#define RA_ELC_EVENT_POEG0_EVENT 0x059 +#define RA_ELC_EVENT_POEG1_EVENT 0x05A +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_A 0x05B +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_B 0x05C +#define RA_ELC_EVENT_GPT0_COMPARE_C 0x05D +#define RA_ELC_EVENT_GPT0_COMPARE_D 0x05E +#define RA_ELC_EVENT_GPT0_COMPARE_E 0x05F +#define RA_ELC_EVENT_GPT0_COMPARE_F 0x060 +#define RA_ELC_EVENT_GPT0_COUNTER_OVERFLOW 0x061 +#define RA_ELC_EVENT_GPT0_COUNTER_UNDERFLOW 0x062 +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_A 0x063 +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_B 0x064 +#define RA_ELC_EVENT_GPT1_COMPARE_C 0x065 +#define RA_ELC_EVENT_GPT1_COMPARE_D 0x066 +#define RA_ELC_EVENT_GPT1_COMPARE_E 0x067 +#define RA_ELC_EVENT_GPT1_COMPARE_F 0x068 +#define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x069 +#define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x06A +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_A 0x06B +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_B 0x06C +#define RA_ELC_EVENT_GPT2_COMPARE_C 0x06D +#define RA_ELC_EVENT_GPT2_COMPARE_D 0x06E +#define RA_ELC_EVENT_GPT2_COMPARE_E 0x06F +#define RA_ELC_EVENT_GPT2_COMPARE_F 0x070 +#define RA_ELC_EVENT_GPT2_COUNTER_OVERFLOW 0x071 +#define RA_ELC_EVENT_GPT2_COUNTER_UNDERFLOW 0x072 +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_A 0x073 +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_B 0x074 +#define RA_ELC_EVENT_GPT3_COMPARE_C 0x075 +#define RA_ELC_EVENT_GPT3_COMPARE_D 0x076 +#define RA_ELC_EVENT_GPT3_COMPARE_E 0x077 +#define RA_ELC_EVENT_GPT3_COMPARE_F 0x078 +#define RA_ELC_EVENT_GPT3_COUNTER_OVERFLOW 0x079 +#define RA_ELC_EVENT_GPT3_COUNTER_UNDERFLOW 0x07A +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_A 0x07B +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_B 0x07C +#define RA_ELC_EVENT_GPT4_COMPARE_C 0x07D +#define RA_ELC_EVENT_GPT4_COMPARE_D 0x07E +#define RA_ELC_EVENT_GPT4_COMPARE_E 0x07F +#define RA_ELC_EVENT_GPT4_COMPARE_F 0x080 +#define RA_ELC_EVENT_GPT4_COUNTER_OVERFLOW 0x081 +#define RA_ELC_EVENT_GPT4_COUNTER_UNDERFLOW 0x082 +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_A 0x083 +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_B 0x084 +#define RA_ELC_EVENT_GPT5_COMPARE_C 0x085 +#define RA_ELC_EVENT_GPT5_COMPARE_D 0x086 +#define RA_ELC_EVENT_GPT5_COMPARE_E 0x087 +#define RA_ELC_EVENT_GPT5_COMPARE_F 0x088 +#define RA_ELC_EVENT_GPT5_COUNTER_OVERFLOW 0x089 +#define RA_ELC_EVENT_GPT5_COUNTER_UNDERFLOW 0x08A +#define RA_ELC_EVENT_GPT8_CAPTURE_COMPARE_A 0x09B +#define RA_ELC_EVENT_GPT8_CAPTURE_COMPARE_B 0x09C +#define RA_ELC_EVENT_GPT8_COMPARE_C 0x09D +#define RA_ELC_EVENT_GPT8_COMPARE_D 0x09E +#define RA_ELC_EVENT_GPT8_COMPARE_E 0x09F +#define RA_ELC_EVENT_GPT8_COMPARE_F 0x0A0 +#define RA_ELC_EVENT_GPT8_COUNTER_OVERFLOW 0x0A1 +#define RA_ELC_EVENT_GPT8_COUNTER_UNDERFLOW 0x0A2 +#define RA_ELC_EVENT_OPS_UVW_EDGE 0x0AB +#define RA_ELC_EVENT_SCI0_RXI 0x0AC +#define RA_ELC_EVENT_SCI0_TXI 0x0AD +#define RA_ELC_EVENT_SCI0_TEI 0x0AE +#define RA_ELC_EVENT_SCI0_ERI 0x0AF +#define RA_ELC_EVENT_SCI0_AM 0x0B0 +#define RA_ELC_EVENT_SCI0_RXI_OR_ERI 0x0B1 +#define RA_ELC_EVENT_SCI1_RXI 0x0B2 +#define RA_ELC_EVENT_SCI1_TXI 0x0B3 +#define RA_ELC_EVENT_SCI1_TEI 0x0B4 +#define RA_ELC_EVENT_SCI1_ERI 0x0B5 +#define RA_ELC_EVENT_SCI1_AM 0x0B6 +#define RA_ELC_EVENT_SCI4_RXI 0x0C1 +#define RA_ELC_EVENT_SCI4_TXI 0x0C2 +#define RA_ELC_EVENT_SCI4_TEI 0x0C3 +#define RA_ELC_EVENT_SCI4_ERI 0x0C4 +#define RA_ELC_EVENT_SCI4_AM 0x0C5 +#define RA_ELC_EVENT_SCI9_RXI 0x0C6 +#define RA_ELC_EVENT_SCI9_TXI 0x0C7 +#define RA_ELC_EVENT_SCI9_TEI 0x0C8 +#define RA_ELC_EVENT_SCI9_ERI 0x0C9 +#define RA_ELC_EVENT_SCI9_AM 0x0CA +#define RA_ELC_EVENT_SPI0_RXI 0x0CB +#define RA_ELC_EVENT_SPI0_TXI 0x0CC +#define RA_ELC_EVENT_SPI0_IDLE 0x0CD +#define RA_ELC_EVENT_SPI0_ERI 0x0CE +#define RA_ELC_EVENT_SPI0_TEI 0x0CF +#define RA_ELC_EVENT_SPI1_RXI 0x0D0 +#define RA_ELC_EVENT_SPI1_TXI 0x0D1 +#define RA_ELC_EVENT_SPI1_IDLE 0x0D2 +#define RA_ELC_EVENT_SPI1_ERI 0x0D3 +#define RA_ELC_EVENT_SPI1_TEI 0x0D4 + +/* Possible peripherals to be linked to event signals */ +#define RA_ELC_PERIPHERAL_GPT_A 0 +#define RA_ELC_PERIPHERAL_GPT_B 1 +#define RA_ELC_PERIPHERAL_GPT_C 2 +#define RA_ELC_PERIPHERAL_GPT_D 3 +#define RA_ELC_PERIPHERAL_GPT_E 4 +#define RA_ELC_PERIPHERAL_GPT_F 5 +#define RA_ELC_PERIPHERAL_GPT_G 6 +#define RA_ELC_PERIPHERAL_GPT_H 7 +#define RA_ELC_PERIPHERAL_ADC0 8 +#define RA_ELC_PERIPHERAL_ADC0_B 9 +#define RA_ELC_PERIPHERAL_DAC0 12 +#define RA_ELC_PERIPHERAL_IOPORT1 14 +#define RA_ELC_PERIPHERAL_IOPORT2 15 +#define RA_ELC_PERIPHERAL_IOPORT3 16 +#define RA_ELC_PERIPHERAL_IOPORT4 17 +#define RA_ELC_PERIPHERAL_CTSU 18 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4W1_ELC_H_ */ diff --git a/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6e1-elc.h b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6e1-elc.h new file mode 100644 index 00000000000..74f0d4b7580 --- /dev/null +++ b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6e1-elc.h @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6E1_ELC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6E1_ELC_H_ + +/* Sources of event signals to be linked to other peripherals or the CPU */ +#define RA_ELC_EVENT_NONE 0x0 +#define RA_ELC_EVENT_ICU_IRQ0 0x001 +#define RA_ELC_EVENT_ICU_IRQ1 0x002 +#define RA_ELC_EVENT_ICU_IRQ2 0x003 +#define RA_ELC_EVENT_ICU_IRQ3 0x004 +#define RA_ELC_EVENT_ICU_IRQ4 0x005 +#define RA_ELC_EVENT_ICU_IRQ5 0x006 +#define RA_ELC_EVENT_ICU_IRQ6 0x007 +#define RA_ELC_EVENT_ICU_IRQ7 0x008 +#define RA_ELC_EVENT_ICU_IRQ8 0x009 +#define RA_ELC_EVENT_ICU_IRQ9 0x00A +#define RA_ELC_EVENT_ICU_IRQ10 0x00B +#define RA_ELC_EVENT_ICU_IRQ11 0x00C +#define RA_ELC_EVENT_ICU_IRQ12 0x00D +#define RA_ELC_EVENT_ICU_IRQ13 0x00E +#define RA_ELC_EVENT_ICU_IRQ14 0x00F +#define RA_ELC_EVENT_ICU_IRQ15 0x010 +#define RA_ELC_EVENT_DMAC0_INT 0x020 +#define RA_ELC_EVENT_DMAC1_INT 0x021 +#define RA_ELC_EVENT_DMAC2_INT 0x022 +#define RA_ELC_EVENT_DMAC3_INT 0x023 +#define RA_ELC_EVENT_DMAC4_INT 0x024 +#define RA_ELC_EVENT_DMAC5_INT 0x025 +#define RA_ELC_EVENT_DMAC6_INT 0x026 +#define RA_ELC_EVENT_DMAC7_INT 0x027 +#define RA_ELC_EVENT_DTC_COMPLETE 0x029 +#define RA_ELC_EVENT_DTC_END 0x02A +#define RA_ELC_EVENT_DMA_TRANSERR 0x02B +#define RA_ELC_EVENT_ICU_SNOOZE_CANCEL 0x02D +#define RA_ELC_EVENT_FCU_FIFERR 0x030 +#define RA_ELC_EVENT_FCU_FRDYI 0x031 +#define RA_ELC_EVENT_LVD_LVD1 0x038 +#define RA_ELC_EVENT_LVD_LVD2 0x039 +#define RA_ELC_EVENT_CGC_MOSC_STOP 0x03B +#define RA_ELC_EVENT_LPM_SNOOZE_REQUEST 0x03C +#define RA_ELC_EVENT_AGT0_INT 0x040 +#define RA_ELC_EVENT_AGT0_COMPARE_A 0x041 +#define RA_ELC_EVENT_AGT0_COMPARE_B 0x042 +#define RA_ELC_EVENT_AGT1_INT 0x043 +#define RA_ELC_EVENT_AGT1_COMPARE_A 0x044 +#define RA_ELC_EVENT_AGT1_COMPARE_B 0x045 +#define RA_ELC_EVENT_AGT2_INT 0x046 +#define RA_ELC_EVENT_AGT2_COMPARE_A 0x047 +#define RA_ELC_EVENT_AGT2_COMPARE_B 0x048 +#define RA_ELC_EVENT_AGT3_INT 0x049 +#define RA_ELC_EVENT_AGT3_COMPARE_A 0x04A +#define RA_ELC_EVENT_AGT3_COMPARE_B 0x04B +#define RA_ELC_EVENT_AGT4_INT 0x04C +#define RA_ELC_EVENT_AGT4_COMPARE_A 0x04D +#define RA_ELC_EVENT_AGT4_COMPARE_B 0x04E +#define RA_ELC_EVENT_AGT5_INT 0x04F +#define RA_ELC_EVENT_AGT5_COMPARE_A 0x050 +#define RA_ELC_EVENT_AGT5_COMPARE_B 0x051 +#define RA_ELC_EVENT_IWDT_UNDERFLOW 0x052 +#define RA_ELC_EVENT_WDT_UNDERFLOW 0x053 +#define RA_ELC_EVENT_RTC_ALARM 0x054 +#define RA_ELC_EVENT_RTC_PERIOD 0x055 +#define RA_ELC_EVENT_RTC_CARRY 0x056 +#define RA_ELC_EVENT_USBFS_FIFO_0 0x06B +#define RA_ELC_EVENT_USBFS_FIFO_1 0x06C +#define RA_ELC_EVENT_USBFS_INT 0x06D +#define RA_ELC_EVENT_USBFS_RESUME 0x06E +#define RA_ELC_EVENT_IIC0_RXI 0x073 +#define RA_ELC_EVENT_IIC0_TXI 0x074 +#define RA_ELC_EVENT_IIC0_TEI 0x075 +#define RA_ELC_EVENT_IIC0_ERI 0x076 +#define RA_ELC_EVENT_IIC0_WUI 0x077 +#define RA_ELC_EVENT_IIC1_RXI 0x078 +#define RA_ELC_EVENT_IIC1_TXI 0x079 +#define RA_ELC_EVENT_IIC1_TEI 0x07A +#define RA_ELC_EVENT_IIC1_ERI 0x07B +#define RA_ELC_EVENT_SDHIMMC0_ACCS 0x082 +#define RA_ELC_EVENT_SDHIMMC0_SDIO 0x083 +#define RA_ELC_EVENT_SDHIMMC0_CARD 0x084 +#define RA_ELC_EVENT_SDHIMMC0_DMA_REQ 0x085 +#define RA_ELC_EVENT_SSI0_TXI 0x08A +#define RA_ELC_EVENT_SSI0_RXI 0x08B +#define RA_ELC_EVENT_SSI0_INT 0x08D +#define RA_ELC_EVENT_CAC_FREQUENCY_ERROR 0x09E +#define RA_ELC_EVENT_CAC_MEASUREMENT_END 0x09F +#define RA_ELC_EVENT_CAC_OVERFLOW 0x0A0 +#define RA_ELC_EVENT_CAN0_ERROR 0x0A1 +#define RA_ELC_EVENT_CAN0_FIFO_RX 0x0A2 +#define RA_ELC_EVENT_CAN0_FIFO_TX 0x0A3 +#define RA_ELC_EVENT_CAN0_MAILBOX_RX 0x0A4 +#define RA_ELC_EVENT_CAN0_MAILBOX_TX 0x0A5 +#define RA_ELC_EVENT_IOPORT_EVENT_1 0x0B1 +#define RA_ELC_EVENT_IOPORT_EVENT_2 0x0B2 +#define RA_ELC_EVENT_IOPORT_EVENT_3 0x0B3 +#define RA_ELC_EVENT_IOPORT_EVENT_4 0x0B4 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0 0x0B5 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1 0x0B6 +#define RA_ELC_EVENT_POEG0_EVENT 0x0B7 +#define RA_ELC_EVENT_POEG1_EVENT 0x0B8 +#define RA_ELC_EVENT_POEG2_EVENT 0x0B9 +#define RA_ELC_EVENT_POEG3_EVENT 0x0BA +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_A 0x0C9 +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_B 0x0CA +#define RA_ELC_EVENT_GPT1_COMPARE_C 0x0CB +#define RA_ELC_EVENT_GPT1_COMPARE_D 0x0CC +#define RA_ELC_EVENT_GPT1_COMPARE_E 0x0CD +#define RA_ELC_EVENT_GPT1_COMPARE_F 0x0CE +#define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x0CF +#define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x0D0 +#define RA_ELC_EVENT_GPT1_PC 0x0D1 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_A 0x0D2 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_B 0x0D3 +#define RA_ELC_EVENT_GPT2_COMPARE_C 0x0D4 +#define RA_ELC_EVENT_GPT2_COMPARE_D 0x0D5 +#define RA_ELC_EVENT_GPT2_COMPARE_E 0x0D6 +#define RA_ELC_EVENT_GPT2_COMPARE_F 0x0D7 +#define RA_ELC_EVENT_GPT2_COUNTER_OVERFLOW 0x0D8 +#define RA_ELC_EVENT_GPT2_COUNTER_UNDERFLOW 0x0D9 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_A 0x0E4 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_B 0x0E5 +#define RA_ELC_EVENT_GPT4_COMPARE_C 0x0E6 +#define RA_ELC_EVENT_GPT4_COMPARE_D 0x0E7 +#define RA_ELC_EVENT_GPT4_COMPARE_E 0x0E8 +#define RA_ELC_EVENT_GPT4_COMPARE_F 0x0E9 +#define RA_ELC_EVENT_GPT4_COUNTER_OVERFLOW 0x0EA +#define RA_ELC_EVENT_GPT4_COUNTER_UNDERFLOW 0x0EB +#define RA_ELC_EVENT_GPT4_PC 0x0EC +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_A 0x0ED +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_B 0x0EE +#define RA_ELC_EVENT_GPT5_COMPARE_C 0x0EF +#define RA_ELC_EVENT_GPT5_COMPARE_D 0x0F0 +#define RA_ELC_EVENT_GPT5_COMPARE_E 0x0F1 +#define RA_ELC_EVENT_GPT5_COMPARE_F 0x0F2 +#define RA_ELC_EVENT_GPT5_COUNTER_OVERFLOW 0x0F3 +#define RA_ELC_EVENT_GPT5_COUNTER_UNDERFLOW 0x0F4 +#define RA_ELC_EVENT_GPT5_PC 0x0F5 +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_A 0x0F6 +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_B 0x0F7 +#define RA_ELC_EVENT_GPT6_COMPARE_C 0x0F8 +#define RA_ELC_EVENT_GPT6_COMPARE_D 0x0F9 +#define RA_ELC_EVENT_GPT6_COMPARE_E 0x0FA +#define RA_ELC_EVENT_GPT6_COMPARE_F 0x0FB +#define RA_ELC_EVENT_GPT6_COUNTER_OVERFLOW 0x0FC +#define RA_ELC_EVENT_GPT6_COUNTER_UNDERFLOW 0x0FD +#define RA_ELC_EVENT_GPT6_PC 0x0FE +#define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_A 0x0FF +#define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_B 0x100 +#define RA_ELC_EVENT_GPT7_COMPARE_C 0x101 +#define RA_ELC_EVENT_GPT7_COMPARE_D 0x102 +#define RA_ELC_EVENT_GPT7_COMPARE_E 0x103 +#define RA_ELC_EVENT_GPT7_COMPARE_F 0x104 +#define RA_ELC_EVENT_GPT7_COUNTER_OVERFLOW 0x105 +#define RA_ELC_EVENT_GPT7_COUNTER_UNDERFLOW 0x106 +#define RA_ELC_EVENT_ADC0_SCAN_END 0x160 +#define RA_ELC_EVENT_ADC0_SCAN_END_B 0x161 +#define RA_ELC_EVENT_ADC0_WINDOW_A 0x162 +#define RA_ELC_EVENT_ADC0_WINDOW_B 0x163 +#define RA_ELC_EVENT_ADC0_COMPARE_MATCH 0x164 +#define RA_ELC_EVENT_ADC0_COMPARE_MISMATCH 0x165 +#define RA_ELC_EVENT_EDMAC0_EINT 0x16F +#define RA_ELC_EVENT_SCI0_RXI 0x180 +#define RA_ELC_EVENT_SCI0_TXI 0x181 +#define RA_ELC_EVENT_SCI0_TEI 0x182 +#define RA_ELC_EVENT_SCI0_ERI 0x183 +#define RA_ELC_EVENT_SCI0_AM 0x184 +#define RA_ELC_EVENT_SCI0_RXI_OR_ERI 0x185 +#define RA_ELC_EVENT_SCI1_RXI 0x186 +#define RA_ELC_EVENT_SCI1_TXI 0x187 +#define RA_ELC_EVENT_SCI1_TEI 0x188 +#define RA_ELC_EVENT_SCI1_ERI 0x189 +#define RA_ELC_EVENT_SCI2_RXI 0x18C +#define RA_ELC_EVENT_SCI2_TXI 0x18D +#define RA_ELC_EVENT_SCI2_TEI 0x18E +#define RA_ELC_EVENT_SCI2_ERI 0x18F +#define RA_ELC_EVENT_SCI3_RXI 0x192 +#define RA_ELC_EVENT_SCI3_TXI 0x193 +#define RA_ELC_EVENT_SCI3_TEI 0x194 +#define RA_ELC_EVENT_SCI3_ERI 0x195 +#define RA_ELC_EVENT_SCI3_AM 0x196 +#define RA_ELC_EVENT_SCI4_RXI 0x198 +#define RA_ELC_EVENT_SCI4_TXI 0x199 +#define RA_ELC_EVENT_SCI4_TEI 0x19A +#define RA_ELC_EVENT_SCI4_ERI 0x19B +#define RA_ELC_EVENT_SCI4_AM 0x19C +#define RA_ELC_EVENT_SCI9_RXI 0x1B6 +#define RA_ELC_EVENT_SCI9_TXI 0x1B7 +#define RA_ELC_EVENT_SCI9_TEI 0x1B8 +#define RA_ELC_EVENT_SCI9_ERI 0x1B9 +#define RA_ELC_EVENT_SCI9_AM 0x1BA +#define RA_ELC_EVENT_SCIX1_SCIX0 0x1C0 +#define RA_ELC_EVENT_SCI2_SCIX0 0x1C0 +#define RA_ELC_EVENT_SCIX1_SCIX1 0x1C1 +#define RA_ELC_EVENT_SCI2_SCIX1 0x1C1 +#define RA_ELC_EVENT_SCIX1_SCIX2 0x1C2 +#define RA_ELC_EVENT_SCI2_SCIX2 0x1C2 +#define RA_ELC_EVENT_SCIX1_SCIX3 0x1C3 +#define RA_ELC_EVENT_SCI2_SCIX3 0x1C3 +#define RA_ELC_EVENT_SPI0_RXI 0x1C4 +#define RA_ELC_EVENT_SPI0_TXI 0x1C5 +#define RA_ELC_EVENT_SPI0_IDLE 0x1C6 +#define RA_ELC_EVENT_SPI0_ERI 0x1C7 +#define RA_ELC_EVENT_SPI0_TEI 0x1C8 +#define RA_ELC_EVENT_SPI1_RXI 0x1C9 +#define RA_ELC_EVENT_SPI1_TXI 0x1CA +#define RA_ELC_EVENT_SPI1_IDLE 0x1CB +#define RA_ELC_EVENT_SPI1_ERI 0x1CC +#define RA_ELC_EVENT_SPI1_TEI 0x1CD +#define RA_ELC_EVENT_QSPI_INT 0x1DA +#define RA_ELC_EVENT_DOC_INT 0x1DB + +/* Possible peripherals to be linked to event signals */ +#define RA_ELC_PERIPHERAL_GPT_A 0 +#define RA_ELC_PERIPHERAL_GPT_B 1 +#define RA_ELC_PERIPHERAL_GPT_C 2 +#define RA_ELC_PERIPHERAL_GPT_D 3 +#define RA_ELC_PERIPHERAL_GPT_E 4 +#define RA_ELC_PERIPHERAL_GPT_F 5 +#define RA_ELC_PERIPHERAL_GPT_G 6 +#define RA_ELC_PERIPHERAL_GPT_H 7 +#define RA_ELC_PERIPHERAL_ADC0 8 +#define RA_ELC_PERIPHERAL_ADC0_B 9 +#define RA_ELC_PERIPHERAL_DAC0 12 +#define RA_ELC_PERIPHERAL_IOPORT1 14 +#define RA_ELC_PERIPHERAL_IOPORT2 15 +#define RA_ELC_PERIPHERAL_IOPORT3 16 +#define RA_ELC_PERIPHERAL_IOPORT4 17 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6E1_ELC_H_ */ diff --git a/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6e2-elc.h b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6e2-elc.h new file mode 100644 index 00000000000..6f9a2c526f0 --- /dev/null +++ b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6e2-elc.h @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6E2_ELC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6E2_ELC_H_ + +/* Sources of event signals to be linked to other peripherals or the CPU */ +#define RA_ELC_EVENT_NONE 0x0 +#define RA_ELC_EVENT_ICU_IRQ0 0x001 +#define RA_ELC_EVENT_ICU_IRQ1 0x002 +#define RA_ELC_EVENT_ICU_IRQ2 0x003 +#define RA_ELC_EVENT_ICU_IRQ3 0x004 +#define RA_ELC_EVENT_ICU_IRQ4 0x005 +#define RA_ELC_EVENT_ICU_IRQ5 0x006 +#define RA_ELC_EVENT_ICU_IRQ6 0x007 +#define RA_ELC_EVENT_ICU_IRQ7 0x008 +#define RA_ELC_EVENT_ICU_IRQ8 0x009 +#define RA_ELC_EVENT_ICU_IRQ9 0x00A +#define RA_ELC_EVENT_ICU_IRQ10 0x00B +#define RA_ELC_EVENT_ICU_IRQ11 0x00C +#define RA_ELC_EVENT_ICU_IRQ12 0x00D +#define RA_ELC_EVENT_ICU_IRQ13 0x00E +#define RA_ELC_EVENT_ICU_IRQ14 0x00F +#define RA_ELC_EVENT_DMAC0_INT 0x020 +#define RA_ELC_EVENT_DMAC1_INT 0x021 +#define RA_ELC_EVENT_DMAC2_INT 0x022 +#define RA_ELC_EVENT_DMAC3_INT 0x023 +#define RA_ELC_EVENT_DMAC4_INT 0x024 +#define RA_ELC_EVENT_DMAC5_INT 0x025 +#define RA_ELC_EVENT_DMAC6_INT 0x026 +#define RA_ELC_EVENT_DMAC7_INT 0x027 +#define RA_ELC_EVENT_DTC_COMPLETE 0x029 +#define RA_ELC_EVENT_DMA_TRANSERR 0x02B +#define RA_ELC_EVENT_ICU_SNOOZE_CANCEL 0x02D +#define RA_ELC_EVENT_FCU_FIFERR 0x030 +#define RA_ELC_EVENT_FCU_FRDYI 0x031 +#define RA_ELC_EVENT_LVD_LVD1 0x038 +#define RA_ELC_EVENT_LVD_LVD2 0x039 +#define RA_ELC_EVENT_CGC_MOSC_STOP 0x03B +#define RA_ELC_EVENT_LPM_SNOOZE_REQUEST 0x03C +#define RA_ELC_EVENT_AGT0_INT 0x040 +#define RA_ELC_EVENT_AGT0_COMPARE_A 0x041 +#define RA_ELC_EVENT_AGT0_COMPARE_B 0x042 +#define RA_ELC_EVENT_AGT1_INT 0x043 +#define RA_ELC_EVENT_AGT1_COMPARE_A 0x044 +#define RA_ELC_EVENT_AGT1_COMPARE_B 0x045 +#define RA_ELC_EVENT_IWDT_UNDERFLOW 0x052 +#define RA_ELC_EVENT_WDT_UNDERFLOW 0x053 +#define RA_ELC_EVENT_RTC_ALARM 0x054 +#define RA_ELC_EVENT_RTC_PERIOD 0x055 +#define RA_ELC_EVENT_RTC_CARRY 0x056 +#define RA_ELC_EVENT_CAN_RXF 0x059 +#define RA_ELC_EVENT_CAN_GLERR 0x05A +#define RA_ELC_EVENT_CAN_DMAREQ0 0x05B +#define RA_ELC_EVENT_CAN_DMAREQ1 0x05C +#define RA_ELC_EVENT_CAN0_TX 0x063 +#define RA_ELC_EVENT_CAN0_CHERR 0x064 +#define RA_ELC_EVENT_CAN0_COMFRX 0x065 +#define RA_ELC_EVENT_CAN0_CF_DMAREQ 0x066 +#define RA_ELC_EVENT_CAN0_RXMB 0x067 +#define RA_ELC_EVENT_USBFS_INT 0x06D +#define RA_ELC_EVENT_USBFS_RESUME 0x06E +#define RA_ELC_EVENT_SSI0_TXI 0x08A +#define RA_ELC_EVENT_SSI0_RXI 0x08B +#define RA_ELC_EVENT_SSI0_INT 0x08D +#define RA_ELC_EVENT_CAC_FREQUENCY_ERROR 0x09E +#define RA_ELC_EVENT_CAC_MEASUREMENT_END 0x09F +#define RA_ELC_EVENT_CAC_OVERFLOW 0x0A0 +#define RA_ELC_EVENT_CEC_INTDA 0x0AB +#define RA_ELC_EVENT_CEC_INTCE 0x0AC +#define RA_ELC_EVENT_CEC_INTERR 0x0AD +#define RA_ELC_EVENT_IOPORT_EVENT_1 0x0B1 +#define RA_ELC_EVENT_IOPORT_EVENT_2 0x0B2 +#define RA_ELC_EVENT_IOPORT_EVENT_3 0x0B3 +#define RA_ELC_EVENT_IOPORT_EVENT_4 0x0B4 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0 0x0B5 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1 0x0B6 +#define RA_ELC_EVENT_POEG0_EVENT 0x0B7 +#define RA_ELC_EVENT_POEG1_EVENT 0x0B8 +#define RA_ELC_EVENT_POEG2_EVENT 0x0B9 +#define RA_ELC_EVENT_POEG3_EVENT 0x0BA +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_A 0x0C0 +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_B 0x0C1 +#define RA_ELC_EVENT_GPT0_COMPARE_C 0x0C2 +#define RA_ELC_EVENT_GPT0_COMPARE_D 0x0C3 +#define RA_ELC_EVENT_GPT0_COMPARE_E 0x0C4 +#define RA_ELC_EVENT_GPT0_COMPARE_F 0x0C5 +#define RA_ELC_EVENT_GPT0_COUNTER_OVERFLOW 0x0C6 +#define RA_ELC_EVENT_GPT0_COUNTER_UNDERFLOW 0x0C7 +#define RA_ELC_EVENT_GPT0_PC 0x0C8 +#define RA_ELC_EVENT_GPT0_AD_TRIG_A 0x0C9 +#define RA_ELC_EVENT_GPT0_AD_TRIG_B 0x0CA +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_A 0x0CB +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_B 0x0CC +#define RA_ELC_EVENT_GPT1_COMPARE_C 0x0CD +#define RA_ELC_EVENT_GPT1_COMPARE_D 0x0CE +#define RA_ELC_EVENT_GPT1_COMPARE_E 0x0CF +#define RA_ELC_EVENT_GPT1_COMPARE_F 0x0D0 +#define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x0D1 +#define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x0D2 +#define RA_ELC_EVENT_GPT1_PC 0x0D3 +#define RA_ELC_EVENT_GPT1_AD_TRIG_A 0x0D4 +#define RA_ELC_EVENT_GPT1_AD_TRIG_B 0x0D5 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_A 0x0D6 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_B 0x0D7 +#define RA_ELC_EVENT_GPT2_COMPARE_C 0x0D8 +#define RA_ELC_EVENT_GPT2_COMPARE_D 0x0D9 +#define RA_ELC_EVENT_GPT2_COMPARE_E 0x0DA +#define RA_ELC_EVENT_GPT2_COMPARE_F 0x0DB +#define RA_ELC_EVENT_GPT2_COUNTER_OVERFLOW 0x0DC +#define RA_ELC_EVENT_GPT2_COUNTER_UNDERFLOW 0x0DD +#define RA_ELC_EVENT_GPT2_AD_TRIG_A 0x0DF +#define RA_ELC_EVENT_GPT2_AD_TRIG_B 0x0E0 +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_A 0x0E1 +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_B 0x0E2 +#define RA_ELC_EVENT_GPT3_COMPARE_C 0x0E3 +#define RA_ELC_EVENT_GPT3_COMPARE_D 0x0E4 +#define RA_ELC_EVENT_GPT3_COMPARE_E 0x0E5 +#define RA_ELC_EVENT_GPT3_COMPARE_F 0x0E6 +#define RA_ELC_EVENT_GPT3_COUNTER_OVERFLOW 0x0E7 +#define RA_ELC_EVENT_GPT3_COUNTER_UNDERFLOW 0x0E8 +#define RA_ELC_EVENT_GPT3_AD_TRIG_A 0x0EA +#define RA_ELC_EVENT_GPT3_AD_TRIG_B 0x0EB +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_A 0x0EC +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_B 0x0ED +#define RA_ELC_EVENT_GPT4_COMPARE_C 0x0EE +#define RA_ELC_EVENT_GPT4_COMPARE_D 0x0EF +#define RA_ELC_EVENT_GPT4_COMPARE_E 0x0F0 +#define RA_ELC_EVENT_GPT4_COMPARE_F 0x0F1 +#define RA_ELC_EVENT_GPT4_COUNTER_OVERFLOW 0x0F2 +#define RA_ELC_EVENT_GPT4_COUNTER_UNDERFLOW 0x0F3 +#define RA_ELC_EVENT_GPT4_PC 0x0F4 +#define RA_ELC_EVENT_GPT4_AD_TRIG_A 0x0F5 +#define RA_ELC_EVENT_GPT4_AD_TRIG_B 0x0F6 +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_A 0x0F7 +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_B 0x0F8 +#define RA_ELC_EVENT_GPT5_COMPARE_C 0x0F9 +#define RA_ELC_EVENT_GPT5_COMPARE_D 0x0FA +#define RA_ELC_EVENT_GPT5_COMPARE_E 0x0FB +#define RA_ELC_EVENT_GPT5_COMPARE_F 0x0FC +#define RA_ELC_EVENT_GPT5_COUNTER_OVERFLOW 0x0FD +#define RA_ELC_EVENT_GPT5_COUNTER_UNDERFLOW 0x0FE +#define RA_ELC_EVENT_GPT5_PC 0x0FF +#define RA_ELC_EVENT_GPT5_AD_TRIG_A 0x100 +#define RA_ELC_EVENT_GPT5_AD_TRIG_B 0x101 +#define RA_ELC_EVENT_OPS_UVW_EDGE 0x15C +#define RA_ELC_EVENT_ADC0_SCAN_END 0x160 +#define RA_ELC_EVENT_ADC0_SCAN_END_B 0x161 +#define RA_ELC_EVENT_ADC0_WINDOW_A 0x162 +#define RA_ELC_EVENT_ADC0_WINDOW_B 0x163 +#define RA_ELC_EVENT_ADC0_COMPARE_MATCH 0x164 +#define RA_ELC_EVENT_ADC0_COMPARE_MISMATCH 0x165 +#define RA_ELC_EVENT_SCI0_RXI 0x180 +#define RA_ELC_EVENT_SCI0_TXI 0x181 +#define RA_ELC_EVENT_SCI0_TEI 0x182 +#define RA_ELC_EVENT_SCI0_ERI 0x183 +#define RA_ELC_EVENT_SCI0_AM 0x184 +#define RA_ELC_EVENT_SCI0_RXI_OR_ERI 0x185 +#define RA_ELC_EVENT_SCI9_RXI 0x1B6 +#define RA_ELC_EVENT_SCI9_TXI 0x1B7 +#define RA_ELC_EVENT_SCI9_TEI 0x1B8 +#define RA_ELC_EVENT_SCI9_ERI 0x1B9 +#define RA_ELC_EVENT_SCI9_AM 0x1BA +#define RA_ELC_EVENT_SPI0_RXI 0x1C4 +#define RA_ELC_EVENT_SPI0_TXI 0x1C5 +#define RA_ELC_EVENT_SPI0_IDLE 0x1C6 +#define RA_ELC_EVENT_SPI0_ERI 0x1C7 +#define RA_ELC_EVENT_SPI0_TEI 0x1C8 +#define RA_ELC_EVENT_SPI1_RXI 0x1C9 +#define RA_ELC_EVENT_SPI1_TXI 0x1CA +#define RA_ELC_EVENT_SPI1_IDLE 0x1CB +#define RA_ELC_EVENT_SPI1_ERI 0x1CC +#define RA_ELC_EVENT_SPI1_TEI 0x1CD +#define RA_ELC_EVENT_CAN0_MRAM_ERI 0x1D0 +#define RA_ELC_EVENT_QSPI_INT 0x1DA +#define RA_ELC_EVENT_DOC_INT 0x1DB +#define RA_ELC_EVENT_I3C0_RESPONSE 0x1DC +#define RA_ELC_EVENT_I3C0_COMMAND 0x1DD +#define RA_ELC_EVENT_I3C0_IBI 0x1DE +#define RA_ELC_EVENT_I3C0_RX 0x1DF +#define RA_ELC_EVENT_IICB0_RXI 0x1DF +#define RA_ELC_EVENT_I3C0_TX 0x1E0 +#define RA_ELC_EVENT_IICB0_TXI 0x1E0 +#define RA_ELC_EVENT_I3C0_RCV_STATUS 0x1E1 +#define RA_ELC_EVENT_I3C0_HRESP 0x1E2 +#define RA_ELC_EVENT_I3C0_HCMD 0x1E3 +#define RA_ELC_EVENT_I3C0_HRX 0x1E4 +#define RA_ELC_EVENT_I3C0_HTX 0x1E5 +#define RA_ELC_EVENT_I3C0_TEND 0x1E6 +#define RA_ELC_EVENT_IICB0_TEI 0x1E6 +#define RA_ELC_EVENT_I3C0_EEI 0x1E7 +#define RA_ELC_EVENT_IICB0_ERI 0x1E7 +#define RA_ELC_EVENT_I3C0_STEV 0x1E8 +#define RA_ELC_EVENT_I3C0_MREFOVF 0x1E9 +#define RA_ELC_EVENT_I3C0_MREFCPT 0x1EA +#define RA_ELC_EVENT_I3C0_AMEV 0x1EB +#define RA_ELC_EVENT_I3C0_WU 0x1EC +#define RA_ELC_EVENT_TRNG_RDREQ 0x1F3 + +/* Possible peripherals to be linked to event signals */ +#define RA_ELC_PERIPHERAL_GPT_A 0 +#define RA_ELC_PERIPHERAL_GPT_B 1 +#define RA_ELC_PERIPHERAL_GPT_C 2 +#define RA_ELC_PERIPHERAL_GPT_D 3 +#define RA_ELC_PERIPHERAL_GPT_E 4 +#define RA_ELC_PERIPHERAL_GPT_F 5 +#define RA_ELC_PERIPHERAL_GPT_G 6 +#define RA_ELC_PERIPHERAL_GPT_H 7 +#define RA_ELC_PERIPHERAL_ADC0 8 +#define RA_ELC_PERIPHERAL_ADC0_B 9 +#define RA_ELC_PERIPHERAL_DAC0 12 +#define RA_ELC_PERIPHERAL_DAC1 13 +#define RA_ELC_PERIPHERAL_IOPORT1 14 +#define RA_ELC_PERIPHERAL_IOPORT2 15 +#define RA_ELC_PERIPHERAL_IOPORT3 16 +#define RA_ELC_PERIPHERAL_IOPORT4 17 +#define RA_ELC_PERIPHERAL_I3C 23 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6E2_ELC_H_ */ diff --git a/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6m1-elc.h b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6m1-elc.h new file mode 100644 index 00000000000..7c18f63fad3 --- /dev/null +++ b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6m1-elc.h @@ -0,0 +1,319 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6M1_ELC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6M1_ELC_H_ + +/* Sources of event signals to be linked to other peripherals or the CPU */ +#define RA_ELC_EVENT_NONE 0x0 +#define RA_ELC_EVENT_ICU_IRQ0 0x001 +#define RA_ELC_EVENT_ICU_IRQ1 0x002 +#define RA_ELC_EVENT_ICU_IRQ2 0x003 +#define RA_ELC_EVENT_ICU_IRQ3 0x004 +#define RA_ELC_EVENT_ICU_IRQ4 0x005 +#define RA_ELC_EVENT_ICU_IRQ5 0x006 +#define RA_ELC_EVENT_ICU_IRQ6 0x007 +#define RA_ELC_EVENT_ICU_IRQ7 0x008 +#define RA_ELC_EVENT_ICU_IRQ8 0x009 +#define RA_ELC_EVENT_ICU_IRQ9 0x00A +#define RA_ELC_EVENT_ICU_IRQ10 0x00B +#define RA_ELC_EVENT_ICU_IRQ11 0x00C +#define RA_ELC_EVENT_ICU_IRQ12 0x00D +#define RA_ELC_EVENT_ICU_IRQ13 0x00E +#define RA_ELC_EVENT_DMAC0_INT 0x020 +#define RA_ELC_EVENT_DMAC1_INT 0x021 +#define RA_ELC_EVENT_DMAC2_INT 0x022 +#define RA_ELC_EVENT_DMAC3_INT 0x023 +#define RA_ELC_EVENT_DMAC4_INT 0x024 +#define RA_ELC_EVENT_DMAC5_INT 0x025 +#define RA_ELC_EVENT_DMAC6_INT 0x026 +#define RA_ELC_EVENT_DMAC7_INT 0x027 +#define RA_ELC_EVENT_DTC_COMPLETE 0x029 +#define RA_ELC_EVENT_DTC_END 0x02A +#define RA_ELC_EVENT_ICU_SNOOZE_CANCEL 0x02D +#define RA_ELC_EVENT_FCU_FIFERR 0x030 +#define RA_ELC_EVENT_FCU_FRDYI 0x031 +#define RA_ELC_EVENT_LVD_LVD1 0x038 +#define RA_ELC_EVENT_LVD_LVD2 0x039 +#define RA_ELC_EVENT_CGC_MOSC_STOP 0x03B +#define RA_ELC_EVENT_LPM_SNOOZE_REQUEST 0x03C +#define RA_ELC_EVENT_AGT0_INT 0x040 +#define RA_ELC_EVENT_AGT0_COMPARE_A 0x041 +#define RA_ELC_EVENT_AGT0_COMPARE_B 0x042 +#define RA_ELC_EVENT_AGT1_INT 0x043 +#define RA_ELC_EVENT_AGT1_COMPARE_A 0x044 +#define RA_ELC_EVENT_AGT1_COMPARE_B 0x045 +#define RA_ELC_EVENT_IWDT_UNDERFLOW 0x046 +#define RA_ELC_EVENT_WDT_UNDERFLOW 0x047 +#define RA_ELC_EVENT_RTC_ALARM 0x048 +#define RA_ELC_EVENT_RTC_PERIOD 0x049 +#define RA_ELC_EVENT_RTC_CARRY 0x04A +#define RA_ELC_EVENT_ADC0_SCAN_END 0x04B +#define RA_ELC_EVENT_ADC0_SCAN_END_B 0x04C +#define RA_ELC_EVENT_ADC0_WINDOW_A 0x04D +#define RA_ELC_EVENT_ADC0_WINDOW_B 0x04E +#define RA_ELC_EVENT_ADC0_COMPARE_MATCH 0x04F +#define RA_ELC_EVENT_ADC0_COMPARE_MISMATCH 0x050 +#define RA_ELC_EVENT_ADC1_SCAN_END 0x051 +#define RA_ELC_EVENT_ADC1_SCAN_END_B 0x052 +#define RA_ELC_EVENT_ADC1_WINDOW_A 0x053 +#define RA_ELC_EVENT_ADC1_WINDOW_B 0x054 +#define RA_ELC_EVENT_ADC1_COMPARE_MATCH 0x055 +#define RA_ELC_EVENT_ADC1_COMPARE_MISMATCH 0x056 +#define RA_ELC_EVENT_ACMPHS0_INT 0x057 +#define RA_ELC_EVENT_ACMPHS1_INT 0x058 +#define RA_ELC_EVENT_ACMPHS2_INT 0x059 +#define RA_ELC_EVENT_ACMPHS3_INT 0x05A +#define RA_ELC_EVENT_ACMPHS4_INT 0x05B +#define RA_ELC_EVENT_ACMPHS5_INT 0x05C +#define RA_ELC_EVENT_USBFS_FIFO_0 0x05F +#define RA_ELC_EVENT_USBFS_FIFO_1 0x060 +#define RA_ELC_EVENT_USBFS_INT 0x061 +#define RA_ELC_EVENT_USBFS_RESUME 0x062 +#define RA_ELC_EVENT_IIC0_RXI 0x063 +#define RA_ELC_EVENT_IIC0_TXI 0x064 +#define RA_ELC_EVENT_IIC0_TEI 0x065 +#define RA_ELC_EVENT_IIC0_ERI 0x066 +#define RA_ELC_EVENT_IIC0_WUI 0x067 +#define RA_ELC_EVENT_IIC1_RXI 0x068 +#define RA_ELC_EVENT_IIC1_TXI 0x069 +#define RA_ELC_EVENT_IIC1_TEI 0x06A +#define RA_ELC_EVENT_IIC1_ERI 0x06B +#define RA_ELC_EVENT_SSI0_TXI 0x072 +#define RA_ELC_EVENT_SSI0_RXI 0x073 +#define RA_ELC_EVENT_SSI0_INT 0x075 +#define RA_ELC_EVENT_SRC_INPUT_FIFO_EMPTY 0x07A +#define RA_ELC_EVENT_SRC_OUTPUT_FIFO_FULL 0x07B +#define RA_ELC_EVENT_SRC_OUTPUT_FIFO_OVERFLOW 0x07C +#define RA_ELC_EVENT_SRC_OUTPUT_FIFO_UNDERFLOW 0x07D +#define RA_ELC_EVENT_SRC_CONVERSION_END 0x07E +#define RA_ELC_EVENT_CTSU_WRITE 0x082 +#define RA_ELC_EVENT_CTSU_READ 0x083 +#define RA_ELC_EVENT_CTSU_END 0x084 +#define RA_ELC_EVENT_KEY_INT 0x085 +#define RA_ELC_EVENT_DOC_INT 0x086 +#define RA_ELC_EVENT_CAC_FREQUENCY_ERROR 0x087 +#define RA_ELC_EVENT_CAC_MEASUREMENT_END 0x088 +#define RA_ELC_EVENT_CAC_OVERFLOW 0x089 +#define RA_ELC_EVENT_CAN0_ERROR 0x08A +#define RA_ELC_EVENT_CAN0_FIFO_RX 0x08B +#define RA_ELC_EVENT_CAN0_FIFO_TX 0x08C +#define RA_ELC_EVENT_CAN0_MAILBOX_RX 0x08D +#define RA_ELC_EVENT_CAN0_MAILBOX_TX 0x08E +#define RA_ELC_EVENT_CAN1_ERROR 0x08F +#define RA_ELC_EVENT_CAN1_FIFO_RX 0x090 +#define RA_ELC_EVENT_CAN1_FIFO_TX 0x091 +#define RA_ELC_EVENT_CAN1_MAILBOX_RX 0x092 +#define RA_ELC_EVENT_CAN1_MAILBOX_TX 0x093 +#define RA_ELC_EVENT_IOPORT_EVENT_1 0x094 +#define RA_ELC_EVENT_IOPORT_EVENT_2 0x095 +#define RA_ELC_EVENT_IOPORT_EVENT_3 0x096 +#define RA_ELC_EVENT_IOPORT_EVENT_4 0x097 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0 0x098 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1 0x099 +#define RA_ELC_EVENT_POEG0_EVENT 0x09A +#define RA_ELC_EVENT_POEG1_EVENT 0x09B +#define RA_ELC_EVENT_POEG2_EVENT 0x09C +#define RA_ELC_EVENT_POEG3_EVENT 0x09D +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_A 0x0B0 +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_B 0x0B1 +#define RA_ELC_EVENT_GPT0_COMPARE_C 0x0B2 +#define RA_ELC_EVENT_GPT0_COMPARE_D 0x0B3 +#define RA_ELC_EVENT_GPT0_COMPARE_E 0x0B4 +#define RA_ELC_EVENT_GPT0_COMPARE_F 0x0B5 +#define RA_ELC_EVENT_GPT0_COUNTER_OVERFLOW 0x0B6 +#define RA_ELC_EVENT_GPT0_COUNTER_UNDERFLOW 0x0B7 +#define RA_ELC_EVENT_GPT0_AD_TRIG_A 0x0B8 +#define RA_ELC_EVENT_GPT0_AD_TRIG_B 0x0B9 +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_A 0x0BA +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_B 0x0BB +#define RA_ELC_EVENT_GPT1_COMPARE_C 0x0BC +#define RA_ELC_EVENT_GPT1_COMPARE_D 0x0BD +#define RA_ELC_EVENT_GPT1_COMPARE_E 0x0BE +#define RA_ELC_EVENT_GPT1_COMPARE_F 0x0BF +#define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x0C0 +#define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x0C1 +#define RA_ELC_EVENT_GPT1_AD_TRIG_A 0x0C2 +#define RA_ELC_EVENT_GPT1_AD_TRIG_B 0x0C3 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_A 0x0C4 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_B 0x0C5 +#define RA_ELC_EVENT_GPT2_COMPARE_C 0x0C6 +#define RA_ELC_EVENT_GPT2_COMPARE_D 0x0C7 +#define RA_ELC_EVENT_GPT2_COMPARE_E 0x0C8 +#define RA_ELC_EVENT_GPT2_COMPARE_F 0x0C9 +#define RA_ELC_EVENT_GPT2_COUNTER_OVERFLOW 0x0CA +#define RA_ELC_EVENT_GPT2_COUNTER_UNDERFLOW 0x0CB +#define RA_ELC_EVENT_GPT2_AD_TRIG_A 0x0CC +#define RA_ELC_EVENT_GPT2_AD_TRIG_B 0x0CD +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_A 0x0CE +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_B 0x0CF +#define RA_ELC_EVENT_GPT3_COMPARE_C 0x0D0 +#define RA_ELC_EVENT_GPT3_COMPARE_D 0x0D1 +#define RA_ELC_EVENT_GPT3_COMPARE_E 0x0D2 +#define RA_ELC_EVENT_GPT3_COMPARE_F 0x0D3 +#define RA_ELC_EVENT_GPT3_COUNTER_OVERFLOW 0x0D4 +#define RA_ELC_EVENT_GPT3_COUNTER_UNDERFLOW 0x0D5 +#define RA_ELC_EVENT_GPT3_AD_TRIG_A 0x0D6 +#define RA_ELC_EVENT_GPT3_AD_TRIG_B 0x0D7 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_A 0x0D8 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_B 0x0D9 +#define RA_ELC_EVENT_GPT4_COMPARE_C 0x0DA +#define RA_ELC_EVENT_GPT4_COMPARE_D 0x0DB +#define RA_ELC_EVENT_GPT4_COMPARE_E 0x0DC +#define RA_ELC_EVENT_GPT4_COMPARE_F 0x0DD +#define RA_ELC_EVENT_GPT4_COUNTER_OVERFLOW 0x0DE +#define RA_ELC_EVENT_GPT4_COUNTER_UNDERFLOW 0x0DF +#define RA_ELC_EVENT_GPT4_AD_TRIG_A 0x0E0 +#define RA_ELC_EVENT_GPT4_AD_TRIG_B 0x0E1 +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_A 0x0E2 +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_B 0x0E3 +#define RA_ELC_EVENT_GPT5_COMPARE_C 0x0E4 +#define RA_ELC_EVENT_GPT5_COMPARE_D 0x0E5 +#define RA_ELC_EVENT_GPT5_COMPARE_E 0x0E6 +#define RA_ELC_EVENT_GPT5_COMPARE_F 0x0E7 +#define RA_ELC_EVENT_GPT5_COUNTER_OVERFLOW 0x0E8 +#define RA_ELC_EVENT_GPT5_COUNTER_UNDERFLOW 0x0E9 +#define RA_ELC_EVENT_GPT5_AD_TRIG_A 0x0EA +#define RA_ELC_EVENT_GPT5_AD_TRIG_B 0x0EB +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_A 0x0EC +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_B 0x0ED +#define RA_ELC_EVENT_GPT6_COMPARE_C 0x0EE +#define RA_ELC_EVENT_GPT6_COMPARE_D 0x0EF +#define RA_ELC_EVENT_GPT6_COMPARE_E 0x0F0 +#define RA_ELC_EVENT_GPT6_COMPARE_F 0x0F1 +#define RA_ELC_EVENT_GPT6_COUNTER_OVERFLOW 0x0F2 +#define RA_ELC_EVENT_GPT6_COUNTER_UNDERFLOW 0x0F3 +#define RA_ELC_EVENT_GPT6_AD_TRIG_A 0x0F4 +#define RA_ELC_EVENT_GPT6_AD_TRIG_B 0x0F5 +#define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_A 0x0F6 +#define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_B 0x0F7 +#define RA_ELC_EVENT_GPT7_COMPARE_C 0x0F8 +#define RA_ELC_EVENT_GPT7_COMPARE_D 0x0F9 +#define RA_ELC_EVENT_GPT7_COMPARE_E 0x0FA +#define RA_ELC_EVENT_GPT7_COMPARE_F 0x0FB +#define RA_ELC_EVENT_GPT7_COUNTER_OVERFLOW 0x0FC +#define RA_ELC_EVENT_GPT7_COUNTER_UNDERFLOW 0x0FD +#define RA_ELC_EVENT_GPT7_AD_TRIG_A 0x0FE +#define RA_ELC_EVENT_GPT7_AD_TRIG_B 0x0FF +#define RA_ELC_EVENT_GPT8_CAPTURE_COMPARE_A 0x100 +#define RA_ELC_EVENT_GPT8_CAPTURE_COMPARE_B 0x101 +#define RA_ELC_EVENT_GPT8_COMPARE_C 0x102 +#define RA_ELC_EVENT_GPT8_COMPARE_D 0x103 +#define RA_ELC_EVENT_GPT8_COMPARE_E 0x104 +#define RA_ELC_EVENT_GPT8_COMPARE_F 0x105 +#define RA_ELC_EVENT_GPT8_COUNTER_OVERFLOW 0x106 +#define RA_ELC_EVENT_GPT8_COUNTER_UNDERFLOW 0x107 +#define RA_ELC_EVENT_GPT9_CAPTURE_COMPARE_A 0x10A +#define RA_ELC_EVENT_GPT9_CAPTURE_COMPARE_B 0x10B +#define RA_ELC_EVENT_GPT9_COMPARE_C 0x10C +#define RA_ELC_EVENT_GPT9_COMPARE_D 0x10D +#define RA_ELC_EVENT_GPT9_COMPARE_E 0x10E +#define RA_ELC_EVENT_GPT9_COMPARE_F 0x10F +#define RA_ELC_EVENT_GPT9_COUNTER_OVERFLOW 0x110 +#define RA_ELC_EVENT_GPT9_COUNTER_UNDERFLOW 0x111 +#define RA_ELC_EVENT_GPT10_CAPTURE_COMPARE_A 0x114 +#define RA_ELC_EVENT_GPT10_CAPTURE_COMPARE_B 0x115 +#define RA_ELC_EVENT_GPT10_COMPARE_C 0x116 +#define RA_ELC_EVENT_GPT10_COMPARE_D 0x117 +#define RA_ELC_EVENT_GPT10_COMPARE_E 0x118 +#define RA_ELC_EVENT_GPT10_COMPARE_F 0x119 +#define RA_ELC_EVENT_GPT10_COUNTER_OVERFLOW 0x11A +#define RA_ELC_EVENT_GPT10_COUNTER_UNDERFLOW 0x11B +#define RA_ELC_EVENT_GPT11_CAPTURE_COMPARE_A 0x11E +#define RA_ELC_EVENT_GPT11_CAPTURE_COMPARE_B 0x11F +#define RA_ELC_EVENT_GPT11_COMPARE_C 0x120 +#define RA_ELC_EVENT_GPT11_COMPARE_D 0x121 +#define RA_ELC_EVENT_GPT11_COMPARE_E 0x122 +#define RA_ELC_EVENT_GPT11_COMPARE_F 0x123 +#define RA_ELC_EVENT_GPT11_COUNTER_OVERFLOW 0x124 +#define RA_ELC_EVENT_GPT11_COUNTER_UNDERFLOW 0x125 +#define RA_ELC_EVENT_GPT12_CAPTURE_COMPARE_A 0x128 +#define RA_ELC_EVENT_GPT12_CAPTURE_COMPARE_B 0x129 +#define RA_ELC_EVENT_GPT12_COMPARE_C 0x12A +#define RA_ELC_EVENT_GPT12_COMPARE_D 0x12B +#define RA_ELC_EVENT_GPT12_COMPARE_E 0x12C +#define RA_ELC_EVENT_GPT12_COMPARE_F 0x12D +#define RA_ELC_EVENT_GPT12_COUNTER_OVERFLOW 0x12E +#define RA_ELC_EVENT_GPT12_COUNTER_UNDERFLOW 0x12F +#define RA_ELC_EVENT_OPS_UVW_EDGE 0x150 +#define RA_ELC_EVENT_SCI0_RXI 0x174 +#define RA_ELC_EVENT_SCI0_TXI 0x175 +#define RA_ELC_EVENT_SCI0_TEI 0x176 +#define RA_ELC_EVENT_SCI0_ERI 0x177 +#define RA_ELC_EVENT_SCI0_AM 0x178 +#define RA_ELC_EVENT_SCI0_RXI_OR_ERI 0x179 +#define RA_ELC_EVENT_SCI1_RXI 0x17A +#define RA_ELC_EVENT_SCI1_TXI 0x17B +#define RA_ELC_EVENT_SCI1_TEI 0x17C +#define RA_ELC_EVENT_SCI1_ERI 0x17D +#define RA_ELC_EVENT_SCI1_AM 0x17E +#define RA_ELC_EVENT_SCI2_RXI 0x180 +#define RA_ELC_EVENT_SCI2_TXI 0x181 +#define RA_ELC_EVENT_SCI2_TEI 0x182 +#define RA_ELC_EVENT_SCI2_ERI 0x183 +#define RA_ELC_EVENT_SCI2_AM 0x184 +#define RA_ELC_EVENT_SCI3_RXI 0x186 +#define RA_ELC_EVENT_SCI3_TXI 0x187 +#define RA_ELC_EVENT_SCI3_TEI 0x188 +#define RA_ELC_EVENT_SCI3_ERI 0x189 +#define RA_ELC_EVENT_SCI3_AM 0x18A +#define RA_ELC_EVENT_SCI4_RXI 0x18C +#define RA_ELC_EVENT_SCI4_TXI 0x18D +#define RA_ELC_EVENT_SCI4_TEI 0x18E +#define RA_ELC_EVENT_SCI4_ERI 0x18F +#define RA_ELC_EVENT_SCI4_AM 0x190 +#define RA_ELC_EVENT_SCI8_RXI 0x1A4 +#define RA_ELC_EVENT_SCI8_TXI 0x1A5 +#define RA_ELC_EVENT_SCI8_TEI 0x1A6 +#define RA_ELC_EVENT_SCI8_ERI 0x1A7 +#define RA_ELC_EVENT_SCI8_AM 0x1A8 +#define RA_ELC_EVENT_SCI9_RXI 0x1AA +#define RA_ELC_EVENT_SCI9_TXI 0x1AB +#define RA_ELC_EVENT_SCI9_TEI 0x1AC +#define RA_ELC_EVENT_SCI9_ERI 0x1AD +#define RA_ELC_EVENT_SCI9_AM 0x1AE +#define RA_ELC_EVENT_SPI0_RXI 0x1BC +#define RA_ELC_EVENT_SPI0_TXI 0x1BD +#define RA_ELC_EVENT_SPI0_IDLE 0x1BE +#define RA_ELC_EVENT_SPI0_ERI 0x1BF +#define RA_ELC_EVENT_SPI0_TEI 0x1C0 +#define RA_ELC_EVENT_SPI1_RXI 0x1C1 +#define RA_ELC_EVENT_SPI1_TXI 0x1C2 +#define RA_ELC_EVENT_SPI1_IDLE 0x1C3 +#define RA_ELC_EVENT_SPI1_ERI 0x1C4 +#define RA_ELC_EVENT_SPI1_TEI 0x1C5 +#define RA_ELC_EVENT_QSPI_INT 0x1C6 +#define RA_ELC_EVENT_SDHIMMC0_ACCS 0x1C7 +#define RA_ELC_EVENT_SDHIMMC0_SDIO 0x1C8 +#define RA_ELC_EVENT_SDHIMMC0_CARD 0x1C9 +#define RA_ELC_EVENT_SDHIMMC0_DMA_REQ 0x1CA +#define RA_ELC_EVENT_SDHIMMC1_ACCS 0x1CB +#define RA_ELC_EVENT_SDHIMMC1_SDIO 0x1CC +#define RA_ELC_EVENT_SDHIMMC1_CARD 0x1CD +#define RA_ELC_EVENT_SDHIMMC1_DMA_REQ 0x1CE + +/* Possible peripherals to be linked to event signals */ +#define RA_ELC_PERIPHERAL_GPT_A 0 +#define RA_ELC_PERIPHERAL_GPT_B 1 +#define RA_ELC_PERIPHERAL_GPT_C 2 +#define RA_ELC_PERIPHERAL_GPT_D 3 +#define RA_ELC_PERIPHERAL_GPT_E 4 +#define RA_ELC_PERIPHERAL_GPT_F 5 +#define RA_ELC_PERIPHERAL_GPT_G 6 +#define RA_ELC_PERIPHERAL_GPT_H 7 +#define RA_ELC_PERIPHERAL_ADC0 8 +#define RA_ELC_PERIPHERAL_ADC0_B 9 +#define RA_ELC_PERIPHERAL_ADC1 10 +#define RA_ELC_PERIPHERAL_ADC1_B 11 +#define RA_ELC_PERIPHERAL_DAC0 12 +#define RA_ELC_PERIPHERAL_DAC1 13 +#define RA_ELC_PERIPHERAL_IOPORT1 14 +#define RA_ELC_PERIPHERAL_IOPORT2 15 +#define RA_ELC_PERIPHERAL_IOPORT3 16 +#define RA_ELC_PERIPHERAL_IOPORT4 17 +#define RA_ELC_PERIPHERAL_CTSU 18 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6M1_ELC_H_ */ diff --git a/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6m2-elc.h b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6m2-elc.h new file mode 100644 index 00000000000..8aee6a666a8 --- /dev/null +++ b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6m2-elc.h @@ -0,0 +1,352 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6M2_ELC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6M2_ELC_H_ + +/* Sources of event signals to be linked to other peripherals or the CPU */ +#define RA_ELC_EVENT_NONE 0x0 +#define RA_ELC_EVENT_ICU_IRQ0 0x001 +#define RA_ELC_EVENT_ICU_IRQ1 0x002 +#define RA_ELC_EVENT_ICU_IRQ2 0x003 +#define RA_ELC_EVENT_ICU_IRQ3 0x004 +#define RA_ELC_EVENT_ICU_IRQ4 0x005 +#define RA_ELC_EVENT_ICU_IRQ5 0x006 +#define RA_ELC_EVENT_ICU_IRQ6 0x007 +#define RA_ELC_EVENT_ICU_IRQ7 0x008 +#define RA_ELC_EVENT_ICU_IRQ8 0x009 +#define RA_ELC_EVENT_ICU_IRQ9 0x00A +#define RA_ELC_EVENT_ICU_IRQ10 0x00B +#define RA_ELC_EVENT_ICU_IRQ11 0x00C +#define RA_ELC_EVENT_ICU_IRQ12 0x00D +#define RA_ELC_EVENT_ICU_IRQ13 0x00E +#define RA_ELC_EVENT_ICU_IRQ14 0x00F +#define RA_ELC_EVENT_ICU_IRQ15 0x010 +#define RA_ELC_EVENT_DMAC0_INT 0x020 +#define RA_ELC_EVENT_DMAC1_INT 0x021 +#define RA_ELC_EVENT_DMAC2_INT 0x022 +#define RA_ELC_EVENT_DMAC3_INT 0x023 +#define RA_ELC_EVENT_DMAC4_INT 0x024 +#define RA_ELC_EVENT_DMAC5_INT 0x025 +#define RA_ELC_EVENT_DMAC6_INT 0x026 +#define RA_ELC_EVENT_DMAC7_INT 0x027 +#define RA_ELC_EVENT_DTC_COMPLETE 0x029 +#define RA_ELC_EVENT_DTC_END 0x02A +#define RA_ELC_EVENT_ICU_SNOOZE_CANCEL 0x02D +#define RA_ELC_EVENT_FCU_FIFERR 0x030 +#define RA_ELC_EVENT_FCU_FRDYI 0x031 +#define RA_ELC_EVENT_LVD_LVD1 0x038 +#define RA_ELC_EVENT_LVD_LVD2 0x039 +#define RA_ELC_EVENT_CGC_MOSC_STOP 0x03B +#define RA_ELC_EVENT_LPM_SNOOZE_REQUEST 0x03C +#define RA_ELC_EVENT_AGT0_INT 0x040 +#define RA_ELC_EVENT_AGT0_COMPARE_A 0x041 +#define RA_ELC_EVENT_AGT0_COMPARE_B 0x042 +#define RA_ELC_EVENT_AGT1_INT 0x043 +#define RA_ELC_EVENT_AGT1_COMPARE_A 0x044 +#define RA_ELC_EVENT_AGT1_COMPARE_B 0x045 +#define RA_ELC_EVENT_IWDT_UNDERFLOW 0x046 +#define RA_ELC_EVENT_WDT_UNDERFLOW 0x047 +#define RA_ELC_EVENT_RTC_ALARM 0x048 +#define RA_ELC_EVENT_RTC_PERIOD 0x049 +#define RA_ELC_EVENT_RTC_CARRY 0x04A +#define RA_ELC_EVENT_ADC0_SCAN_END 0x04B +#define RA_ELC_EVENT_ADC0_SCAN_END_B 0x04C +#define RA_ELC_EVENT_ADC0_WINDOW_A 0x04D +#define RA_ELC_EVENT_ADC0_WINDOW_B 0x04E +#define RA_ELC_EVENT_ADC0_COMPARE_MATCH 0x04F +#define RA_ELC_EVENT_ADC0_COMPARE_MISMATCH 0x050 +#define RA_ELC_EVENT_ADC1_SCAN_END 0x051 +#define RA_ELC_EVENT_ADC1_SCAN_END_B 0x052 +#define RA_ELC_EVENT_ADC1_WINDOW_A 0x053 +#define RA_ELC_EVENT_ADC1_WINDOW_B 0x054 +#define RA_ELC_EVENT_ADC1_COMPARE_MATCH 0x055 +#define RA_ELC_EVENT_ADC1_COMPARE_MISMATCH 0x056 +#define RA_ELC_EVENT_ACMPHS0_INT 0x057 +#define RA_ELC_EVENT_ACMPHS1_INT 0x058 +#define RA_ELC_EVENT_ACMPHS2_INT 0x059 +#define RA_ELC_EVENT_ACMPHS3_INT 0x05A +#define RA_ELC_EVENT_ACMPHS4_INT 0x05B +#define RA_ELC_EVENT_ACMPHS5_INT 0x05C +#define RA_ELC_EVENT_USBFS_FIFO_0 0x05F +#define RA_ELC_EVENT_USBFS_FIFO_1 0x060 +#define RA_ELC_EVENT_USBFS_INT 0x061 +#define RA_ELC_EVENT_USBFS_RESUME 0x062 +#define RA_ELC_EVENT_IIC0_RXI 0x063 +#define RA_ELC_EVENT_IIC0_TXI 0x064 +#define RA_ELC_EVENT_IIC0_TEI 0x065 +#define RA_ELC_EVENT_IIC0_ERI 0x066 +#define RA_ELC_EVENT_IIC0_WUI 0x067 +#define RA_ELC_EVENT_IIC1_RXI 0x068 +#define RA_ELC_EVENT_IIC1_TXI 0x069 +#define RA_ELC_EVENT_IIC1_TEI 0x06A +#define RA_ELC_EVENT_IIC1_ERI 0x06B +#define RA_ELC_EVENT_IIC2_RXI 0x06D +#define RA_ELC_EVENT_IIC2_TXI 0x06E +#define RA_ELC_EVENT_IIC2_TEI 0x06F +#define RA_ELC_EVENT_IIC2_ERI 0x070 +#define RA_ELC_EVENT_SSI0_TXI 0x072 +#define RA_ELC_EVENT_SSI0_RXI 0x073 +#define RA_ELC_EVENT_SSI0_INT 0x075 +#define RA_ELC_EVENT_SRC_INPUT_FIFO_EMPTY 0x07A +#define RA_ELC_EVENT_SRC_OUTPUT_FIFO_FULL 0x07B +#define RA_ELC_EVENT_SRC_OUTPUT_FIFO_OVERFLOW 0x07C +#define RA_ELC_EVENT_SRC_OUTPUT_FIFO_UNDERFLOW 0x07D +#define RA_ELC_EVENT_SRC_CONVERSION_END 0x07E +#define RA_ELC_EVENT_PDC_RECEIVE_DATA_READY 0x07F +#define RA_ELC_EVENT_PDC_FRAME_END 0x080 +#define RA_ELC_EVENT_PDC_INT 0x081 +#define RA_ELC_EVENT_CTSU_WRITE 0x082 +#define RA_ELC_EVENT_CTSU_READ 0x083 +#define RA_ELC_EVENT_CTSU_END 0x084 +#define RA_ELC_EVENT_KEY_INT 0x085 +#define RA_ELC_EVENT_DOC_INT 0x086 +#define RA_ELC_EVENT_CAC_FREQUENCY_ERROR 0x087 +#define RA_ELC_EVENT_CAC_MEASUREMENT_END 0x088 +#define RA_ELC_EVENT_CAC_OVERFLOW 0x089 +#define RA_ELC_EVENT_CAN0_ERROR 0x08A +#define RA_ELC_EVENT_CAN0_FIFO_RX 0x08B +#define RA_ELC_EVENT_CAN0_FIFO_TX 0x08C +#define RA_ELC_EVENT_CAN0_MAILBOX_RX 0x08D +#define RA_ELC_EVENT_CAN0_MAILBOX_TX 0x08E +#define RA_ELC_EVENT_CAN1_ERROR 0x08F +#define RA_ELC_EVENT_CAN1_FIFO_RX 0x090 +#define RA_ELC_EVENT_CAN1_FIFO_TX 0x091 +#define RA_ELC_EVENT_CAN1_MAILBOX_RX 0x092 +#define RA_ELC_EVENT_CAN1_MAILBOX_TX 0x093 +#define RA_ELC_EVENT_IOPORT_EVENT_1 0x094 +#define RA_ELC_EVENT_IOPORT_EVENT_2 0x095 +#define RA_ELC_EVENT_IOPORT_EVENT_3 0x096 +#define RA_ELC_EVENT_IOPORT_EVENT_4 0x097 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0 0x098 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1 0x099 +#define RA_ELC_EVENT_POEG0_EVENT 0x09A +#define RA_ELC_EVENT_POEG1_EVENT 0x09B +#define RA_ELC_EVENT_POEG2_EVENT 0x09C +#define RA_ELC_EVENT_POEG3_EVENT 0x09D +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_A 0x0B0 +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_B 0x0B1 +#define RA_ELC_EVENT_GPT0_COMPARE_C 0x0B2 +#define RA_ELC_EVENT_GPT0_COMPARE_D 0x0B3 +#define RA_ELC_EVENT_GPT0_COMPARE_E 0x0B4 +#define RA_ELC_EVENT_GPT0_COMPARE_F 0x0B5 +#define RA_ELC_EVENT_GPT0_COUNTER_OVERFLOW 0x0B6 +#define RA_ELC_EVENT_GPT0_COUNTER_UNDERFLOW 0x0B7 +#define RA_ELC_EVENT_GPT0_AD_TRIG_A 0x0B8 +#define RA_ELC_EVENT_GPT0_AD_TRIG_B 0x0B9 +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_A 0x0BA +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_B 0x0BB +#define RA_ELC_EVENT_GPT1_COMPARE_C 0x0BC +#define RA_ELC_EVENT_GPT1_COMPARE_D 0x0BD +#define RA_ELC_EVENT_GPT1_COMPARE_E 0x0BE +#define RA_ELC_EVENT_GPT1_COMPARE_F 0x0BF +#define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x0C0 +#define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x0C1 +#define RA_ELC_EVENT_GPT1_AD_TRIG_A 0x0C2 +#define RA_ELC_EVENT_GPT1_AD_TRIG_B 0x0C3 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_A 0x0C4 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_B 0x0C5 +#define RA_ELC_EVENT_GPT2_COMPARE_C 0x0C6 +#define RA_ELC_EVENT_GPT2_COMPARE_D 0x0C7 +#define RA_ELC_EVENT_GPT2_COMPARE_E 0x0C8 +#define RA_ELC_EVENT_GPT2_COMPARE_F 0x0C9 +#define RA_ELC_EVENT_GPT2_COUNTER_OVERFLOW 0x0CA +#define RA_ELC_EVENT_GPT2_COUNTER_UNDERFLOW 0x0CB +#define RA_ELC_EVENT_GPT2_AD_TRIG_A 0x0CC +#define RA_ELC_EVENT_GPT2_AD_TRIG_B 0x0CD +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_A 0x0CE +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_B 0x0CF +#define RA_ELC_EVENT_GPT3_COMPARE_C 0x0D0 +#define RA_ELC_EVENT_GPT3_COMPARE_D 0x0D1 +#define RA_ELC_EVENT_GPT3_COMPARE_E 0x0D2 +#define RA_ELC_EVENT_GPT3_COMPARE_F 0x0D3 +#define RA_ELC_EVENT_GPT3_COUNTER_OVERFLOW 0x0D4 +#define RA_ELC_EVENT_GPT3_COUNTER_UNDERFLOW 0x0D5 +#define RA_ELC_EVENT_GPT3_AD_TRIG_A 0x0D6 +#define RA_ELC_EVENT_GPT3_AD_TRIG_B 0x0D7 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_A 0x0D8 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_B 0x0D9 +#define RA_ELC_EVENT_GPT4_COMPARE_C 0x0DA +#define RA_ELC_EVENT_GPT4_COMPARE_D 0x0DB +#define RA_ELC_EVENT_GPT4_COMPARE_E 0x0DC +#define RA_ELC_EVENT_GPT4_COMPARE_F 0x0DD +#define RA_ELC_EVENT_GPT4_COUNTER_OVERFLOW 0x0DE +#define RA_ELC_EVENT_GPT4_COUNTER_UNDERFLOW 0x0DF +#define RA_ELC_EVENT_GPT4_AD_TRIG_A 0x0E0 +#define RA_ELC_EVENT_GPT4_AD_TRIG_B 0x0E1 +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_A 0x0E2 +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_B 0x0E3 +#define RA_ELC_EVENT_GPT5_COMPARE_C 0x0E4 +#define RA_ELC_EVENT_GPT5_COMPARE_D 0x0E5 +#define RA_ELC_EVENT_GPT5_COMPARE_E 0x0E6 +#define RA_ELC_EVENT_GPT5_COMPARE_F 0x0E7 +#define RA_ELC_EVENT_GPT5_COUNTER_OVERFLOW 0x0E8 +#define RA_ELC_EVENT_GPT5_COUNTER_UNDERFLOW 0x0E9 +#define RA_ELC_EVENT_GPT5_AD_TRIG_A 0x0EA +#define RA_ELC_EVENT_GPT5_AD_TRIG_B 0x0EB +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_A 0x0EC +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_B 0x0ED +#define RA_ELC_EVENT_GPT6_COMPARE_C 0x0EE +#define RA_ELC_EVENT_GPT6_COMPARE_D 0x0EF +#define RA_ELC_EVENT_GPT6_COMPARE_E 0x0F0 +#define RA_ELC_EVENT_GPT6_COMPARE_F 0x0F1 +#define RA_ELC_EVENT_GPT6_COUNTER_OVERFLOW 0x0F2 +#define RA_ELC_EVENT_GPT6_COUNTER_UNDERFLOW 0x0F3 +#define RA_ELC_EVENT_GPT6_AD_TRIG_A 0x0F4 +#define RA_ELC_EVENT_GPT6_AD_TRIG_B 0x0F5 +#define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_A 0x0F6 +#define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_B 0x0F7 +#define RA_ELC_EVENT_GPT7_COMPARE_C 0x0F8 +#define RA_ELC_EVENT_GPT7_COMPARE_D 0x0F9 +#define RA_ELC_EVENT_GPT7_COMPARE_E 0x0FA +#define RA_ELC_EVENT_GPT7_COMPARE_F 0x0FB +#define RA_ELC_EVENT_GPT7_COUNTER_OVERFLOW 0x0FC +#define RA_ELC_EVENT_GPT7_COUNTER_UNDERFLOW 0x0FD +#define RA_ELC_EVENT_GPT7_AD_TRIG_A 0x0FE +#define RA_ELC_EVENT_GPT7_AD_TRIG_B 0x0FF +#define RA_ELC_EVENT_GPT8_CAPTURE_COMPARE_A 0x100 +#define RA_ELC_EVENT_GPT8_CAPTURE_COMPARE_B 0x101 +#define RA_ELC_EVENT_GPT8_COMPARE_C 0x102 +#define RA_ELC_EVENT_GPT8_COMPARE_D 0x103 +#define RA_ELC_EVENT_GPT8_COMPARE_E 0x104 +#define RA_ELC_EVENT_GPT8_COMPARE_F 0x105 +#define RA_ELC_EVENT_GPT8_COUNTER_OVERFLOW 0x106 +#define RA_ELC_EVENT_GPT8_COUNTER_UNDERFLOW 0x107 +#define RA_ELC_EVENT_GPT9_CAPTURE_COMPARE_A 0x10A +#define RA_ELC_EVENT_GPT9_CAPTURE_COMPARE_B 0x10B +#define RA_ELC_EVENT_GPT9_COMPARE_C 0x10C +#define RA_ELC_EVENT_GPT9_COMPARE_D 0x10D +#define RA_ELC_EVENT_GPT9_COMPARE_E 0x10E +#define RA_ELC_EVENT_GPT9_COMPARE_F 0x10F +#define RA_ELC_EVENT_GPT9_COUNTER_OVERFLOW 0x110 +#define RA_ELC_EVENT_GPT9_COUNTER_UNDERFLOW 0x111 +#define RA_ELC_EVENT_GPT10_CAPTURE_COMPARE_A 0x114 +#define RA_ELC_EVENT_GPT10_CAPTURE_COMPARE_B 0x115 +#define RA_ELC_EVENT_GPT10_COMPARE_C 0x116 +#define RA_ELC_EVENT_GPT10_COMPARE_D 0x117 +#define RA_ELC_EVENT_GPT10_COMPARE_E 0x118 +#define RA_ELC_EVENT_GPT10_COMPARE_F 0x119 +#define RA_ELC_EVENT_GPT10_COUNTER_OVERFLOW 0x11A +#define RA_ELC_EVENT_GPT10_COUNTER_UNDERFLOW 0x11B +#define RA_ELC_EVENT_GPT11_CAPTURE_COMPARE_A 0x11E +#define RA_ELC_EVENT_GPT11_CAPTURE_COMPARE_B 0x11F +#define RA_ELC_EVENT_GPT11_COMPARE_C 0x120 +#define RA_ELC_EVENT_GPT11_COMPARE_D 0x121 +#define RA_ELC_EVENT_GPT11_COMPARE_E 0x122 +#define RA_ELC_EVENT_GPT11_COMPARE_F 0x123 +#define RA_ELC_EVENT_GPT11_COUNTER_OVERFLOW 0x124 +#define RA_ELC_EVENT_GPT11_COUNTER_UNDERFLOW 0x125 +#define RA_ELC_EVENT_GPT12_CAPTURE_COMPARE_A 0x128 +#define RA_ELC_EVENT_GPT12_CAPTURE_COMPARE_B 0x129 +#define RA_ELC_EVENT_GPT12_COMPARE_C 0x12A +#define RA_ELC_EVENT_GPT12_COMPARE_D 0x12B +#define RA_ELC_EVENT_GPT12_COMPARE_E 0x12C +#define RA_ELC_EVENT_GPT12_COMPARE_F 0x12D +#define RA_ELC_EVENT_GPT12_COUNTER_OVERFLOW 0x12E +#define RA_ELC_EVENT_GPT12_COUNTER_UNDERFLOW 0x12F +#define RA_ELC_EVENT_GPT13_CAPTURE_COMPARE_A 0x132 +#define RA_ELC_EVENT_GPT13_CAPTURE_COMPARE_B 0x133 +#define RA_ELC_EVENT_GPT13_COMPARE_C 0x134 +#define RA_ELC_EVENT_GPT13_COMPARE_D 0x135 +#define RA_ELC_EVENT_GPT13_COMPARE_E 0x136 +#define RA_ELC_EVENT_GPT13_COMPARE_F 0x137 +#define RA_ELC_EVENT_GPT13_COUNTER_OVERFLOW 0x138 +#define RA_ELC_EVENT_GPT13_COUNTER_UNDERFLOW 0x139 +#define RA_ELC_EVENT_OPS_UVW_EDGE 0x150 +#define RA_ELC_EVENT_EDMAC0_EINT 0x163 +#define RA_ELC_EVENT_SCI0_RXI 0x174 +#define RA_ELC_EVENT_SCI0_TXI 0x175 +#define RA_ELC_EVENT_SCI0_TEI 0x176 +#define RA_ELC_EVENT_SCI0_ERI 0x177 +#define RA_ELC_EVENT_SCI0_AM 0x178 +#define RA_ELC_EVENT_SCI0_RXI_OR_ERI 0x179 +#define RA_ELC_EVENT_SCI1_RXI 0x17A +#define RA_ELC_EVENT_SCI1_TXI 0x17B +#define RA_ELC_EVENT_SCI1_TEI 0x17C +#define RA_ELC_EVENT_SCI1_ERI 0x17D +#define RA_ELC_EVENT_SCI1_AM 0x17E +#define RA_ELC_EVENT_SCI2_RXI 0x180 +#define RA_ELC_EVENT_SCI2_TXI 0x181 +#define RA_ELC_EVENT_SCI2_TEI 0x182 +#define RA_ELC_EVENT_SCI2_ERI 0x183 +#define RA_ELC_EVENT_SCI2_AM 0x184 +#define RA_ELC_EVENT_SCI3_RXI 0x186 +#define RA_ELC_EVENT_SCI3_TXI 0x187 +#define RA_ELC_EVENT_SCI3_TEI 0x188 +#define RA_ELC_EVENT_SCI3_ERI 0x189 +#define RA_ELC_EVENT_SCI3_AM 0x18A +#define RA_ELC_EVENT_SCI4_RXI 0x18C +#define RA_ELC_EVENT_SCI4_TXI 0x18D +#define RA_ELC_EVENT_SCI4_TEI 0x18E +#define RA_ELC_EVENT_SCI4_ERI 0x18F +#define RA_ELC_EVENT_SCI4_AM 0x190 +#define RA_ELC_EVENT_SCI5_RXI 0x192 +#define RA_ELC_EVENT_SCI5_TXI 0x193 +#define RA_ELC_EVENT_SCI5_TEI 0x194 +#define RA_ELC_EVENT_SCI5_ERI 0x195 +#define RA_ELC_EVENT_SCI5_AM 0x196 +#define RA_ELC_EVENT_SCI6_RXI 0x198 +#define RA_ELC_EVENT_SCI6_TXI 0x199 +#define RA_ELC_EVENT_SCI6_TEI 0x19A +#define RA_ELC_EVENT_SCI6_ERI 0x19B +#define RA_ELC_EVENT_SCI6_AM 0x19C +#define RA_ELC_EVENT_SCI7_RXI 0x19E +#define RA_ELC_EVENT_SCI7_TXI 0x19F +#define RA_ELC_EVENT_SCI7_TEI 0x1A0 +#define RA_ELC_EVENT_SCI7_ERI 0x1A1 +#define RA_ELC_EVENT_SCI7_AM 0x1A2 +#define RA_ELC_EVENT_SCI8_RXI 0x1A4 +#define RA_ELC_EVENT_SCI8_TXI 0x1A5 +#define RA_ELC_EVENT_SCI8_TEI 0x1A6 +#define RA_ELC_EVENT_SCI8_ERI 0x1A7 +#define RA_ELC_EVENT_SCI8_AM 0x1A8 +#define RA_ELC_EVENT_SCI9_RXI 0x1AA +#define RA_ELC_EVENT_SCI9_TXI 0x1AB +#define RA_ELC_EVENT_SCI9_TEI 0x1AC +#define RA_ELC_EVENT_SCI9_ERI 0x1AD +#define RA_ELC_EVENT_SCI9_AM 0x1AE +#define RA_ELC_EVENT_SPI0_RXI 0x1BC +#define RA_ELC_EVENT_SPI0_TXI 0x1BD +#define RA_ELC_EVENT_SPI0_IDLE 0x1BE +#define RA_ELC_EVENT_SPI0_ERI 0x1BF +#define RA_ELC_EVENT_SPI0_TEI 0x1C0 +#define RA_ELC_EVENT_SPI1_RXI 0x1C1 +#define RA_ELC_EVENT_SPI1_TXI 0x1C2 +#define RA_ELC_EVENT_SPI1_IDLE 0x1C3 +#define RA_ELC_EVENT_SPI1_ERI 0x1C4 +#define RA_ELC_EVENT_SPI1_TEI 0x1C5 +#define RA_ELC_EVENT_QSPI_INT 0x1C6 +#define RA_ELC_EVENT_SDHIMMC0_ACCS 0x1C7 +#define RA_ELC_EVENT_SDHIMMC0_SDIO 0x1C8 +#define RA_ELC_EVENT_SDHIMMC0_CARD 0x1C9 +#define RA_ELC_EVENT_SDHIMMC0_DMA_REQ 0x1CA +#define RA_ELC_EVENT_SDHIMMC1_ACCS 0x1CB +#define RA_ELC_EVENT_SDHIMMC1_SDIO 0x1CC +#define RA_ELC_EVENT_SDHIMMC1_CARD 0x1CD +#define RA_ELC_EVENT_SDHIMMC1_DMA_REQ 0x1CE + +/* Possible peripherals to be linked to event signals */ +#define RA_ELC_PERIPHERAL_GPT_A 0 +#define RA_ELC_PERIPHERAL_GPT_B 1 +#define RA_ELC_PERIPHERAL_GPT_C 2 +#define RA_ELC_PERIPHERAL_GPT_D 3 +#define RA_ELC_PERIPHERAL_GPT_E 4 +#define RA_ELC_PERIPHERAL_GPT_F 5 +#define RA_ELC_PERIPHERAL_GPT_G 6 +#define RA_ELC_PERIPHERAL_GPT_H 7 +#define RA_ELC_PERIPHERAL_ADC0 8 +#define RA_ELC_PERIPHERAL_ADC0_B 9 +#define RA_ELC_PERIPHERAL_ADC1 10 +#define RA_ELC_PERIPHERAL_ADC1_B 11 +#define RA_ELC_PERIPHERAL_DAC0 12 +#define RA_ELC_PERIPHERAL_DAC1 13 +#define RA_ELC_PERIPHERAL_IOPORT1 14 +#define RA_ELC_PERIPHERAL_IOPORT2 15 +#define RA_ELC_PERIPHERAL_IOPORT3 16 +#define RA_ELC_PERIPHERAL_IOPORT4 17 +#define RA_ELC_PERIPHERAL_CTSU 18 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6M2_ELC_H_ */ diff --git a/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6m3-elc.h b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6m3-elc.h new file mode 100644 index 00000000000..febce94793a --- /dev/null +++ b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6m3-elc.h @@ -0,0 +1,380 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6M3_ELC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6M3_ELC_H_ + +/* Sources of event signals to be linked to other peripherals or the CPU */ +#define RA_ELC_EVENT_NONE 0x0 +#define RA_ELC_EVENT_ICU_IRQ0 0x001 +#define RA_ELC_EVENT_ICU_IRQ1 0x002 +#define RA_ELC_EVENT_ICU_IRQ2 0x003 +#define RA_ELC_EVENT_ICU_IRQ3 0x004 +#define RA_ELC_EVENT_ICU_IRQ4 0x005 +#define RA_ELC_EVENT_ICU_IRQ5 0x006 +#define RA_ELC_EVENT_ICU_IRQ6 0x007 +#define RA_ELC_EVENT_ICU_IRQ7 0x008 +#define RA_ELC_EVENT_ICU_IRQ8 0x009 +#define RA_ELC_EVENT_ICU_IRQ9 0x00A +#define RA_ELC_EVENT_ICU_IRQ10 0x00B +#define RA_ELC_EVENT_ICU_IRQ11 0x00C +#define RA_ELC_EVENT_ICU_IRQ12 0x00D +#define RA_ELC_EVENT_ICU_IRQ13 0x00E +#define RA_ELC_EVENT_ICU_IRQ14 0x00F +#define RA_ELC_EVENT_ICU_IRQ15 0x010 +#define RA_ELC_EVENT_DMAC0_INT 0x020 +#define RA_ELC_EVENT_DMAC1_INT 0x021 +#define RA_ELC_EVENT_DMAC2_INT 0x022 +#define RA_ELC_EVENT_DMAC3_INT 0x023 +#define RA_ELC_EVENT_DMAC4_INT 0x024 +#define RA_ELC_EVENT_DMAC5_INT 0x025 +#define RA_ELC_EVENT_DMAC6_INT 0x026 +#define RA_ELC_EVENT_DMAC7_INT 0x027 +#define RA_ELC_EVENT_DTC_COMPLETE 0x029 +#define RA_ELC_EVENT_DTC_END 0x02A +#define RA_ELC_EVENT_ICU_SNOOZE_CANCEL 0x02D +#define RA_ELC_EVENT_FCU_FIFERR 0x030 +#define RA_ELC_EVENT_FCU_FRDYI 0x031 +#define RA_ELC_EVENT_LVD_LVD1 0x038 +#define RA_ELC_EVENT_LVD_LVD2 0x039 +#define RA_ELC_EVENT_CGC_MOSC_STOP 0x03B +#define RA_ELC_EVENT_LPM_SNOOZE_REQUEST 0x03C +#define RA_ELC_EVENT_AGT0_INT 0x040 +#define RA_ELC_EVENT_AGT0_COMPARE_A 0x041 +#define RA_ELC_EVENT_AGT0_COMPARE_B 0x042 +#define RA_ELC_EVENT_AGT1_INT 0x043 +#define RA_ELC_EVENT_AGT1_COMPARE_A 0x044 +#define RA_ELC_EVENT_AGT1_COMPARE_B 0x045 +#define RA_ELC_EVENT_IWDT_UNDERFLOW 0x046 +#define RA_ELC_EVENT_WDT_UNDERFLOW 0x047 +#define RA_ELC_EVENT_RTC_ALARM 0x048 +#define RA_ELC_EVENT_RTC_PERIOD 0x049 +#define RA_ELC_EVENT_RTC_CARRY 0x04A +#define RA_ELC_EVENT_ADC0_SCAN_END 0x04B +#define RA_ELC_EVENT_ADC0_SCAN_END_B 0x04C +#define RA_ELC_EVENT_ADC0_WINDOW_A 0x04D +#define RA_ELC_EVENT_ADC0_WINDOW_B 0x04E +#define RA_ELC_EVENT_ADC0_COMPARE_MATCH 0x04F +#define RA_ELC_EVENT_ADC0_COMPARE_MISMATCH 0x050 +#define RA_ELC_EVENT_ADC1_SCAN_END 0x051 +#define RA_ELC_EVENT_ADC1_SCAN_END_B 0x052 +#define RA_ELC_EVENT_ADC1_WINDOW_A 0x053 +#define RA_ELC_EVENT_ADC1_WINDOW_B 0x054 +#define RA_ELC_EVENT_ADC1_COMPARE_MATCH 0x055 +#define RA_ELC_EVENT_ADC1_COMPARE_MISMATCH 0x056 +#define RA_ELC_EVENT_ACMPHS0_INT 0x057 +#define RA_ELC_EVENT_ACMPHS1_INT 0x058 +#define RA_ELC_EVENT_ACMPHS2_INT 0x059 +#define RA_ELC_EVENT_ACMPHS3_INT 0x05A +#define RA_ELC_EVENT_ACMPHS4_INT 0x05B +#define RA_ELC_EVENT_ACMPHS5_INT 0x05C +#define RA_ELC_EVENT_USBFS_FIFO_0 0x05F +#define RA_ELC_EVENT_USBFS_FIFO_1 0x060 +#define RA_ELC_EVENT_USBFS_INT 0x061 +#define RA_ELC_EVENT_USBFS_RESUME 0x062 +#define RA_ELC_EVENT_IIC0_RXI 0x063 +#define RA_ELC_EVENT_IIC0_TXI 0x064 +#define RA_ELC_EVENT_IIC0_TEI 0x065 +#define RA_ELC_EVENT_IIC0_ERI 0x066 +#define RA_ELC_EVENT_IIC0_WUI 0x067 +#define RA_ELC_EVENT_IIC1_RXI 0x068 +#define RA_ELC_EVENT_IIC1_TXI 0x069 +#define RA_ELC_EVENT_IIC1_TEI 0x06A +#define RA_ELC_EVENT_IIC1_ERI 0x06B +#define RA_ELC_EVENT_IIC2_RXI 0x06D +#define RA_ELC_EVENT_IIC2_TXI 0x06E +#define RA_ELC_EVENT_IIC2_TEI 0x06F +#define RA_ELC_EVENT_IIC2_ERI 0x070 +#define RA_ELC_EVENT_SSI0_TXI 0x072 +#define RA_ELC_EVENT_SSI0_RXI 0x073 +#define RA_ELC_EVENT_SSI0_INT 0x075 +#define RA_ELC_EVENT_SSI1_TXI_RXI 0x078 +#define RA_ELC_EVENT_SSI1_TXI 0x078 +#define RA_ELC_EVENT_SSI1_RXI 0x078 +#define RA_ELC_EVENT_SSI1_INT 0x079 +#define RA_ELC_EVENT_SRC_INPUT_FIFO_EMPTY 0x07A +#define RA_ELC_EVENT_SRC_OUTPUT_FIFO_FULL 0x07B +#define RA_ELC_EVENT_SRC_OUTPUT_FIFO_OVERFLOW 0x07C +#define RA_ELC_EVENT_SRC_OUTPUT_FIFO_UNDERFLOW 0x07D +#define RA_ELC_EVENT_SRC_CONVERSION_END 0x07E +#define RA_ELC_EVENT_PDC_RECEIVE_DATA_READY 0x07F +#define RA_ELC_EVENT_PDC_FRAME_END 0x080 +#define RA_ELC_EVENT_PDC_INT 0x081 +#define RA_ELC_EVENT_CTSU_WRITE 0x082 +#define RA_ELC_EVENT_CTSU_READ 0x083 +#define RA_ELC_EVENT_CTSU_END 0x084 +#define RA_ELC_EVENT_KEY_INT 0x085 +#define RA_ELC_EVENT_DOC_INT 0x086 +#define RA_ELC_EVENT_CAC_FREQUENCY_ERROR 0x087 +#define RA_ELC_EVENT_CAC_MEASUREMENT_END 0x088 +#define RA_ELC_EVENT_CAC_OVERFLOW 0x089 +#define RA_ELC_EVENT_CAN0_ERROR 0x08A +#define RA_ELC_EVENT_CAN0_FIFO_RX 0x08B +#define RA_ELC_EVENT_CAN0_FIFO_TX 0x08C +#define RA_ELC_EVENT_CAN0_MAILBOX_RX 0x08D +#define RA_ELC_EVENT_CAN0_MAILBOX_TX 0x08E +#define RA_ELC_EVENT_CAN1_ERROR 0x08F +#define RA_ELC_EVENT_CAN1_FIFO_RX 0x090 +#define RA_ELC_EVENT_CAN1_FIFO_TX 0x091 +#define RA_ELC_EVENT_CAN1_MAILBOX_RX 0x092 +#define RA_ELC_EVENT_CAN1_MAILBOX_TX 0x093 +#define RA_ELC_EVENT_IOPORT_EVENT_1 0x094 +#define RA_ELC_EVENT_IOPORT_EVENT_2 0x095 +#define RA_ELC_EVENT_IOPORT_EVENT_3 0x096 +#define RA_ELC_EVENT_IOPORT_EVENT_4 0x097 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0 0x098 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1 0x099 +#define RA_ELC_EVENT_POEG0_EVENT 0x09A +#define RA_ELC_EVENT_POEG1_EVENT 0x09B +#define RA_ELC_EVENT_POEG2_EVENT 0x09C +#define RA_ELC_EVENT_POEG3_EVENT 0x09D +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_A 0x0B0 +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_B 0x0B1 +#define RA_ELC_EVENT_GPT0_COMPARE_C 0x0B2 +#define RA_ELC_EVENT_GPT0_COMPARE_D 0x0B3 +#define RA_ELC_EVENT_GPT0_COMPARE_E 0x0B4 +#define RA_ELC_EVENT_GPT0_COMPARE_F 0x0B5 +#define RA_ELC_EVENT_GPT0_COUNTER_OVERFLOW 0x0B6 +#define RA_ELC_EVENT_GPT0_COUNTER_UNDERFLOW 0x0B7 +#define RA_ELC_EVENT_GPT0_AD_TRIG_A 0x0B8 +#define RA_ELC_EVENT_GPT0_AD_TRIG_B 0x0B9 +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_A 0x0BA +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_B 0x0BB +#define RA_ELC_EVENT_GPT1_COMPARE_C 0x0BC +#define RA_ELC_EVENT_GPT1_COMPARE_D 0x0BD +#define RA_ELC_EVENT_GPT1_COMPARE_E 0x0BE +#define RA_ELC_EVENT_GPT1_COMPARE_F 0x0BF +#define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x0C0 +#define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x0C1 +#define RA_ELC_EVENT_GPT1_AD_TRIG_A 0x0C2 +#define RA_ELC_EVENT_GPT1_AD_TRIG_B 0x0C3 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_A 0x0C4 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_B 0x0C5 +#define RA_ELC_EVENT_GPT2_COMPARE_C 0x0C6 +#define RA_ELC_EVENT_GPT2_COMPARE_D 0x0C7 +#define RA_ELC_EVENT_GPT2_COMPARE_E 0x0C8 +#define RA_ELC_EVENT_GPT2_COMPARE_F 0x0C9 +#define RA_ELC_EVENT_GPT2_COUNTER_OVERFLOW 0x0CA +#define RA_ELC_EVENT_GPT2_COUNTER_UNDERFLOW 0x0CB +#define RA_ELC_EVENT_GPT2_AD_TRIG_A 0x0CC +#define RA_ELC_EVENT_GPT2_AD_TRIG_B 0x0CD +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_A 0x0CE +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_B 0x0CF +#define RA_ELC_EVENT_GPT3_COMPARE_C 0x0D0 +#define RA_ELC_EVENT_GPT3_COMPARE_D 0x0D1 +#define RA_ELC_EVENT_GPT3_COMPARE_E 0x0D2 +#define RA_ELC_EVENT_GPT3_COMPARE_F 0x0D3 +#define RA_ELC_EVENT_GPT3_COUNTER_OVERFLOW 0x0D4 +#define RA_ELC_EVENT_GPT3_COUNTER_UNDERFLOW 0x0D5 +#define RA_ELC_EVENT_GPT3_AD_TRIG_A 0x0D6 +#define RA_ELC_EVENT_GPT3_AD_TRIG_B 0x0D7 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_A 0x0D8 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_B 0x0D9 +#define RA_ELC_EVENT_GPT4_COMPARE_C 0x0DA +#define RA_ELC_EVENT_GPT4_COMPARE_D 0x0DB +#define RA_ELC_EVENT_GPT4_COMPARE_E 0x0DC +#define RA_ELC_EVENT_GPT4_COMPARE_F 0x0DD +#define RA_ELC_EVENT_GPT4_COUNTER_OVERFLOW 0x0DE +#define RA_ELC_EVENT_GPT4_COUNTER_UNDERFLOW 0x0DF +#define RA_ELC_EVENT_GPT4_AD_TRIG_A 0x0E0 +#define RA_ELC_EVENT_GPT4_AD_TRIG_B 0x0E1 +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_A 0x0E2 +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_B 0x0E3 +#define RA_ELC_EVENT_GPT5_COMPARE_C 0x0E4 +#define RA_ELC_EVENT_GPT5_COMPARE_D 0x0E5 +#define RA_ELC_EVENT_GPT5_COMPARE_E 0x0E6 +#define RA_ELC_EVENT_GPT5_COMPARE_F 0x0E7 +#define RA_ELC_EVENT_GPT5_COUNTER_OVERFLOW 0x0E8 +#define RA_ELC_EVENT_GPT5_COUNTER_UNDERFLOW 0x0E9 +#define RA_ELC_EVENT_GPT5_AD_TRIG_A 0x0EA +#define RA_ELC_EVENT_GPT5_AD_TRIG_B 0x0EB +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_A 0x0EC +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_B 0x0ED +#define RA_ELC_EVENT_GPT6_COMPARE_C 0x0EE +#define RA_ELC_EVENT_GPT6_COMPARE_D 0x0EF +#define RA_ELC_EVENT_GPT6_COMPARE_E 0x0F0 +#define RA_ELC_EVENT_GPT6_COMPARE_F 0x0F1 +#define RA_ELC_EVENT_GPT6_COUNTER_OVERFLOW 0x0F2 +#define RA_ELC_EVENT_GPT6_COUNTER_UNDERFLOW 0x0F3 +#define RA_ELC_EVENT_GPT6_AD_TRIG_A 0x0F4 +#define RA_ELC_EVENT_GPT6_AD_TRIG_B 0x0F5 +#define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_A 0x0F6 +#define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_B 0x0F7 +#define RA_ELC_EVENT_GPT7_COMPARE_C 0x0F8 +#define RA_ELC_EVENT_GPT7_COMPARE_D 0x0F9 +#define RA_ELC_EVENT_GPT7_COMPARE_E 0x0FA +#define RA_ELC_EVENT_GPT7_COMPARE_F 0x0FB +#define RA_ELC_EVENT_GPT7_COUNTER_OVERFLOW 0x0FC +#define RA_ELC_EVENT_GPT7_COUNTER_UNDERFLOW 0x0FD +#define RA_ELC_EVENT_GPT7_AD_TRIG_A 0x0FE +#define RA_ELC_EVENT_GPT7_AD_TRIG_B 0x0FF +#define RA_ELC_EVENT_GPT8_CAPTURE_COMPARE_A 0x100 +#define RA_ELC_EVENT_GPT8_CAPTURE_COMPARE_B 0x101 +#define RA_ELC_EVENT_GPT8_COMPARE_C 0x102 +#define RA_ELC_EVENT_GPT8_COMPARE_D 0x103 +#define RA_ELC_EVENT_GPT8_COMPARE_E 0x104 +#define RA_ELC_EVENT_GPT8_COMPARE_F 0x105 +#define RA_ELC_EVENT_GPT8_COUNTER_OVERFLOW 0x106 +#define RA_ELC_EVENT_GPT8_COUNTER_UNDERFLOW 0x107 +#define RA_ELC_EVENT_GPT9_CAPTURE_COMPARE_A 0x10A +#define RA_ELC_EVENT_GPT9_CAPTURE_COMPARE_B 0x10B +#define RA_ELC_EVENT_GPT9_COMPARE_C 0x10C +#define RA_ELC_EVENT_GPT9_COMPARE_D 0x10D +#define RA_ELC_EVENT_GPT9_COMPARE_E 0x10E +#define RA_ELC_EVENT_GPT9_COMPARE_F 0x10F +#define RA_ELC_EVENT_GPT9_COUNTER_OVERFLOW 0x110 +#define RA_ELC_EVENT_GPT9_COUNTER_UNDERFLOW 0x111 +#define RA_ELC_EVENT_GPT10_CAPTURE_COMPARE_A 0x114 +#define RA_ELC_EVENT_GPT10_CAPTURE_COMPARE_B 0x115 +#define RA_ELC_EVENT_GPT10_COMPARE_C 0x116 +#define RA_ELC_EVENT_GPT10_COMPARE_D 0x117 +#define RA_ELC_EVENT_GPT10_COMPARE_E 0x118 +#define RA_ELC_EVENT_GPT10_COMPARE_F 0x119 +#define RA_ELC_EVENT_GPT10_COUNTER_OVERFLOW 0x11A +#define RA_ELC_EVENT_GPT10_COUNTER_UNDERFLOW 0x11B +#define RA_ELC_EVENT_GPT11_CAPTURE_COMPARE_A 0x11E +#define RA_ELC_EVENT_GPT11_CAPTURE_COMPARE_B 0x11F +#define RA_ELC_EVENT_GPT11_COMPARE_C 0x120 +#define RA_ELC_EVENT_GPT11_COMPARE_D 0x121 +#define RA_ELC_EVENT_GPT11_COMPARE_E 0x122 +#define RA_ELC_EVENT_GPT11_COMPARE_F 0x123 +#define RA_ELC_EVENT_GPT11_COUNTER_OVERFLOW 0x124 +#define RA_ELC_EVENT_GPT11_COUNTER_UNDERFLOW 0x125 +#define RA_ELC_EVENT_GPT12_CAPTURE_COMPARE_A 0x128 +#define RA_ELC_EVENT_GPT12_CAPTURE_COMPARE_B 0x129 +#define RA_ELC_EVENT_GPT12_COMPARE_C 0x12A +#define RA_ELC_EVENT_GPT12_COMPARE_D 0x12B +#define RA_ELC_EVENT_GPT12_COMPARE_E 0x12C +#define RA_ELC_EVENT_GPT12_COMPARE_F 0x12D +#define RA_ELC_EVENT_GPT12_COUNTER_OVERFLOW 0x12E +#define RA_ELC_EVENT_GPT12_COUNTER_UNDERFLOW 0x12F +#define RA_ELC_EVENT_GPT13_CAPTURE_COMPARE_A 0x132 +#define RA_ELC_EVENT_GPT13_CAPTURE_COMPARE_B 0x133 +#define RA_ELC_EVENT_GPT13_COMPARE_C 0x134 +#define RA_ELC_EVENT_GPT13_COMPARE_D 0x135 +#define RA_ELC_EVENT_GPT13_COMPARE_E 0x136 +#define RA_ELC_EVENT_GPT13_COMPARE_F 0x137 +#define RA_ELC_EVENT_GPT13_COUNTER_OVERFLOW 0x138 +#define RA_ELC_EVENT_GPT13_COUNTER_UNDERFLOW 0x139 +#define RA_ELC_EVENT_OPS_UVW_EDGE 0x150 +#define RA_ELC_EVENT_EPTPC_IPLS 0x160 +#define RA_ELC_EVENT_EPTPC_MINT 0x161 +#define RA_ELC_EVENT_EPTPC_PINT 0x162 +#define RA_ELC_EVENT_EDMAC0_EINT 0x163 +#define RA_ELC_EVENT_EPTPC_TIMER0_RISE 0x165 +#define RA_ELC_EVENT_EPTPC_TIMER1_RISE 0x166 +#define RA_ELC_EVENT_EPTPC_TIMER2_RISE 0x167 +#define RA_ELC_EVENT_EPTPC_TIMER3_RISE 0x168 +#define RA_ELC_EVENT_EPTPC_TIMER4_RISE 0x169 +#define RA_ELC_EVENT_EPTPC_TIMER5_RISE 0x16A +#define RA_ELC_EVENT_EPTPC_TIMER0_FALL 0x16B +#define RA_ELC_EVENT_EPTPC_TIMER1_FALL 0x16C +#define RA_ELC_EVENT_EPTPC_TIMER2_FALL 0x16D +#define RA_ELC_EVENT_EPTPC_TIMER3_FALL 0x16E +#define RA_ELC_EVENT_EPTPC_TIMER4_FALL 0x16F +#define RA_ELC_EVENT_EPTPC_TIMER5_FALL 0x170 +#define RA_ELC_EVENT_USBHS_FIFO_0 0x171 +#define RA_ELC_EVENT_USBHS_FIFO_1 0x172 +#define RA_ELC_EVENT_USBHS_USB_INT_RESUME 0x173 +#define RA_ELC_EVENT_SCI0_RXI 0x174 +#define RA_ELC_EVENT_SCI0_TXI 0x175 +#define RA_ELC_EVENT_SCI0_TEI 0x176 +#define RA_ELC_EVENT_SCI0_ERI 0x177 +#define RA_ELC_EVENT_SCI0_AM 0x178 +#define RA_ELC_EVENT_SCI0_RXI_OR_ERI 0x179 +#define RA_ELC_EVENT_SCI1_RXI 0x17A +#define RA_ELC_EVENT_SCI1_TXI 0x17B +#define RA_ELC_EVENT_SCI1_TEI 0x17C +#define RA_ELC_EVENT_SCI1_ERI 0x17D +#define RA_ELC_EVENT_SCI1_AM 0x17E +#define RA_ELC_EVENT_SCI2_RXI 0x180 +#define RA_ELC_EVENT_SCI2_TXI 0x181 +#define RA_ELC_EVENT_SCI2_TEI 0x182 +#define RA_ELC_EVENT_SCI2_ERI 0x183 +#define RA_ELC_EVENT_SCI2_AM 0x184 +#define RA_ELC_EVENT_SCI3_RXI 0x186 +#define RA_ELC_EVENT_SCI3_TXI 0x187 +#define RA_ELC_EVENT_SCI3_TEI 0x188 +#define RA_ELC_EVENT_SCI3_ERI 0x189 +#define RA_ELC_EVENT_SCI3_AM 0x18A +#define RA_ELC_EVENT_SCI4_RXI 0x18C +#define RA_ELC_EVENT_SCI4_TXI 0x18D +#define RA_ELC_EVENT_SCI4_TEI 0x18E +#define RA_ELC_EVENT_SCI4_ERI 0x18F +#define RA_ELC_EVENT_SCI4_AM 0x190 +#define RA_ELC_EVENT_SCI5_RXI 0x192 +#define RA_ELC_EVENT_SCI5_TXI 0x193 +#define RA_ELC_EVENT_SCI5_TEI 0x194 +#define RA_ELC_EVENT_SCI5_ERI 0x195 +#define RA_ELC_EVENT_SCI5_AM 0x196 +#define RA_ELC_EVENT_SCI6_RXI 0x198 +#define RA_ELC_EVENT_SCI6_TXI 0x199 +#define RA_ELC_EVENT_SCI6_TEI 0x19A +#define RA_ELC_EVENT_SCI6_ERI 0x19B +#define RA_ELC_EVENT_SCI6_AM 0x19C +#define RA_ELC_EVENT_SCI7_RXI 0x19E +#define RA_ELC_EVENT_SCI7_TXI 0x19F +#define RA_ELC_EVENT_SCI7_TEI 0x1A0 +#define RA_ELC_EVENT_SCI7_ERI 0x1A1 +#define RA_ELC_EVENT_SCI7_AM 0x1A2 +#define RA_ELC_EVENT_SCI8_RXI 0x1A4 +#define RA_ELC_EVENT_SCI8_TXI 0x1A5 +#define RA_ELC_EVENT_SCI8_TEI 0x1A6 +#define RA_ELC_EVENT_SCI8_ERI 0x1A7 +#define RA_ELC_EVENT_SCI8_AM 0x1A8 +#define RA_ELC_EVENT_SCI9_RXI 0x1AA +#define RA_ELC_EVENT_SCI9_TXI 0x1AB +#define RA_ELC_EVENT_SCI9_TEI 0x1AC +#define RA_ELC_EVENT_SCI9_ERI 0x1AD +#define RA_ELC_EVENT_SCI9_AM 0x1AE +#define RA_ELC_EVENT_SPI0_RXI 0x1BC +#define RA_ELC_EVENT_SPI0_TXI 0x1BD +#define RA_ELC_EVENT_SPI0_IDLE 0x1BE +#define RA_ELC_EVENT_SPI0_ERI 0x1BF +#define RA_ELC_EVENT_SPI0_TEI 0x1C0 +#define RA_ELC_EVENT_SPI1_RXI 0x1C1 +#define RA_ELC_EVENT_SPI1_TXI 0x1C2 +#define RA_ELC_EVENT_SPI1_IDLE 0x1C3 +#define RA_ELC_EVENT_SPI1_ERI 0x1C4 +#define RA_ELC_EVENT_SPI1_TEI 0x1C5 +#define RA_ELC_EVENT_QSPI_INT 0x1C6 +#define RA_ELC_EVENT_SDHIMMC0_ACCS 0x1C7 +#define RA_ELC_EVENT_SDHIMMC0_SDIO 0x1C8 +#define RA_ELC_EVENT_SDHIMMC0_CARD 0x1C9 +#define RA_ELC_EVENT_SDHIMMC0_DMA_REQ 0x1CA +#define RA_ELC_EVENT_SDHIMMC1_ACCS 0x1CB +#define RA_ELC_EVENT_SDHIMMC1_SDIO 0x1CC +#define RA_ELC_EVENT_SDHIMMC1_CARD 0x1CD +#define RA_ELC_EVENT_SDHIMMC1_DMA_REQ 0x1CE +#define RA_ELC_EVENT_GLCDC_LINE_DETECT 0x1FA +#define RA_ELC_EVENT_GLCDC_UNDERFLOW_1 0x1FB +#define RA_ELC_EVENT_GLCDC_UNDERFLOW_2 0x1FC +#define RA_ELC_EVENT_DRW_INT 0x1FD +#define RA_ELC_EVENT_JPEG_JEDI 0x1FE +#define RA_ELC_EVENT_JPEG_JDTI 0x1FF + +/* Possible peripherals to be linked to event signals */ +#define RA_ELC_PERIPHERAL_GPT_A 0 +#define RA_ELC_PERIPHERAL_GPT_B 1 +#define RA_ELC_PERIPHERAL_GPT_C 2 +#define RA_ELC_PERIPHERAL_GPT_D 3 +#define RA_ELC_PERIPHERAL_GPT_E 4 +#define RA_ELC_PERIPHERAL_GPT_F 5 +#define RA_ELC_PERIPHERAL_GPT_G 6 +#define RA_ELC_PERIPHERAL_GPT_H 7 +#define RA_ELC_PERIPHERAL_ADC0 8 +#define RA_ELC_PERIPHERAL_ADC0_B 9 +#define RA_ELC_PERIPHERAL_ADC1 10 +#define RA_ELC_PERIPHERAL_ADC1_B 11 +#define RA_ELC_PERIPHERAL_DAC0 12 +#define RA_ELC_PERIPHERAL_DAC1 13 +#define RA_ELC_PERIPHERAL_IOPORT1 14 +#define RA_ELC_PERIPHERAL_IOPORT2 15 +#define RA_ELC_PERIPHERAL_IOPORT3 16 +#define RA_ELC_PERIPHERAL_IOPORT4 17 +#define RA_ELC_PERIPHERAL_CTSU 18 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6M3_ELC_H_ */ diff --git a/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6m4-elc.h b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6m4-elc.h new file mode 100644 index 00000000000..84c5c125aa1 --- /dev/null +++ b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6m4-elc.h @@ -0,0 +1,314 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6M4_ELC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6M4_ELC_H_ + +/* Sources of event signals to be linked to other peripherals or the CPU */ +#define RA_ELC_EVENT_NONE 0x0 +#define RA_ELC_EVENT_ICU_IRQ0 0x001 +#define RA_ELC_EVENT_ICU_IRQ1 0x002 +#define RA_ELC_EVENT_ICU_IRQ2 0x003 +#define RA_ELC_EVENT_ICU_IRQ3 0x004 +#define RA_ELC_EVENT_ICU_IRQ4 0x005 +#define RA_ELC_EVENT_ICU_IRQ5 0x006 +#define RA_ELC_EVENT_ICU_IRQ6 0x007 +#define RA_ELC_EVENT_ICU_IRQ7 0x008 +#define RA_ELC_EVENT_ICU_IRQ8 0x009 +#define RA_ELC_EVENT_ICU_IRQ9 0x00A +#define RA_ELC_EVENT_ICU_IRQ10 0x00B +#define RA_ELC_EVENT_ICU_IRQ11 0x00C +#define RA_ELC_EVENT_ICU_IRQ12 0x00D +#define RA_ELC_EVENT_ICU_IRQ13 0x00E +#define RA_ELC_EVENT_ICU_IRQ14 0x00F +#define RA_ELC_EVENT_ICU_IRQ15 0x010 +#define RA_ELC_EVENT_DMAC0_INT 0x020 +#define RA_ELC_EVENT_DMAC1_INT 0x021 +#define RA_ELC_EVENT_DMAC2_INT 0x022 +#define RA_ELC_EVENT_DMAC3_INT 0x023 +#define RA_ELC_EVENT_DMAC4_INT 0x024 +#define RA_ELC_EVENT_DMAC5_INT 0x025 +#define RA_ELC_EVENT_DMAC6_INT 0x026 +#define RA_ELC_EVENT_DMAC7_INT 0x027 +#define RA_ELC_EVENT_DTC_COMPLETE 0x029 +#define RA_ELC_EVENT_DTC_END 0x02A +#define RA_ELC_EVENT_DMA_TRANSERR 0x02B +#define RA_ELC_EVENT_ICU_SNOOZE_CANCEL 0x02D +#define RA_ELC_EVENT_FCU_FIFERR 0x030 +#define RA_ELC_EVENT_FCU_FRDYI 0x031 +#define RA_ELC_EVENT_LVD_LVD1 0x038 +#define RA_ELC_EVENT_LVD_LVD2 0x039 +#define RA_ELC_EVENT_CGC_MOSC_STOP 0x03B +#define RA_ELC_EVENT_LPM_SNOOZE_REQUEST 0x03C +#define RA_ELC_EVENT_AGT0_INT 0x040 +#define RA_ELC_EVENT_AGT0_COMPARE_A 0x041 +#define RA_ELC_EVENT_AGT0_COMPARE_B 0x042 +#define RA_ELC_EVENT_AGT1_INT 0x043 +#define RA_ELC_EVENT_AGT1_COMPARE_A 0x044 +#define RA_ELC_EVENT_AGT1_COMPARE_B 0x045 +#define RA_ELC_EVENT_AGT2_INT 0x046 +#define RA_ELC_EVENT_AGT2_COMPARE_A 0x047 +#define RA_ELC_EVENT_AGT2_COMPARE_B 0x048 +#define RA_ELC_EVENT_AGT3_INT 0x049 +#define RA_ELC_EVENT_AGT3_COMPARE_A 0x04A +#define RA_ELC_EVENT_AGT3_COMPARE_B 0x04B +#define RA_ELC_EVENT_AGT4_INT 0x04C +#define RA_ELC_EVENT_AGT4_COMPARE_A 0x04D +#define RA_ELC_EVENT_AGT4_COMPARE_B 0x04E +#define RA_ELC_EVENT_AGT5_INT 0x04F +#define RA_ELC_EVENT_AGT5_COMPARE_A 0x050 +#define RA_ELC_EVENT_AGT5_COMPARE_B 0x051 +#define RA_ELC_EVENT_IWDT_UNDERFLOW 0x052 +#define RA_ELC_EVENT_WDT_UNDERFLOW 0x053 +#define RA_ELC_EVENT_RTC_ALARM 0x054 +#define RA_ELC_EVENT_RTC_PERIOD 0x055 +#define RA_ELC_EVENT_RTC_CARRY 0x056 +#define RA_ELC_EVENT_USBFS_FIFO_0 0x06B +#define RA_ELC_EVENT_USBFS_FIFO_1 0x06C +#define RA_ELC_EVENT_USBFS_INT 0x06D +#define RA_ELC_EVENT_USBFS_RESUME 0x06E +#define RA_ELC_EVENT_IIC0_RXI 0x073 +#define RA_ELC_EVENT_IIC0_TXI 0x074 +#define RA_ELC_EVENT_IIC0_TEI 0x075 +#define RA_ELC_EVENT_IIC0_ERI 0x076 +#define RA_ELC_EVENT_IIC0_WUI 0x077 +#define RA_ELC_EVENT_IIC1_RXI 0x078 +#define RA_ELC_EVENT_IIC1_TXI 0x079 +#define RA_ELC_EVENT_IIC1_TEI 0x07A +#define RA_ELC_EVENT_IIC1_ERI 0x07B +#define RA_ELC_EVENT_SDHIMMC0_ACCS 0x082 +#define RA_ELC_EVENT_SDHIMMC0_SDIO 0x083 +#define RA_ELC_EVENT_SDHIMMC0_CARD 0x084 +#define RA_ELC_EVENT_SDHIMMC0_DMA_REQ 0x085 +#define RA_ELC_EVENT_SSI0_TXI 0x08A +#define RA_ELC_EVENT_SSI0_RXI 0x08B +#define RA_ELC_EVENT_SSI0_INT 0x08D +#define RA_ELC_EVENT_CTSU_WRITE 0x09A +#define RA_ELC_EVENT_CTSU_READ 0x09B +#define RA_ELC_EVENT_CTSU_END 0x09C +#define RA_ELC_EVENT_CAC_FREQUENCY_ERROR 0x09E +#define RA_ELC_EVENT_CAC_MEASUREMENT_END 0x09F +#define RA_ELC_EVENT_CAC_OVERFLOW 0x0A0 +#define RA_ELC_EVENT_CAN0_ERROR 0x0A1 +#define RA_ELC_EVENT_CAN0_FIFO_RX 0x0A2 +#define RA_ELC_EVENT_CAN0_FIFO_TX 0x0A3 +#define RA_ELC_EVENT_CAN0_MAILBOX_RX 0x0A4 +#define RA_ELC_EVENT_CAN0_MAILBOX_TX 0x0A5 +#define RA_ELC_EVENT_CAN1_ERROR 0x0A6 +#define RA_ELC_EVENT_CAN1_FIFO_RX 0x0A7 +#define RA_ELC_EVENT_CAN1_FIFO_TX 0x0A8 +#define RA_ELC_EVENT_CAN1_MAILBOX_RX 0x0A9 +#define RA_ELC_EVENT_CAN1_MAILBOX_TX 0x0AA +#define RA_ELC_EVENT_IOPORT_EVENT_1 0x0B1 +#define RA_ELC_EVENT_IOPORT_EVENT_2 0x0B2 +#define RA_ELC_EVENT_IOPORT_EVENT_3 0x0B3 +#define RA_ELC_EVENT_IOPORT_EVENT_4 0x0B4 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0 0x0B5 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1 0x0B6 +#define RA_ELC_EVENT_POEG0_EVENT 0x0B7 +#define RA_ELC_EVENT_POEG1_EVENT 0x0B8 +#define RA_ELC_EVENT_POEG2_EVENT 0x0B9 +#define RA_ELC_EVENT_POEG3_EVENT 0x0BA +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_A 0x0C0 +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_B 0x0C1 +#define RA_ELC_EVENT_GPT0_COMPARE_C 0x0C2 +#define RA_ELC_EVENT_GPT0_COMPARE_D 0x0C3 +#define RA_ELC_EVENT_GPT0_COMPARE_E 0x0C4 +#define RA_ELC_EVENT_GPT0_COMPARE_F 0x0C5 +#define RA_ELC_EVENT_GPT0_COUNTER_OVERFLOW 0x0C6 +#define RA_ELC_EVENT_GPT0_COUNTER_UNDERFLOW 0x0C7 +#define RA_ELC_EVENT_GPT0_PC 0x0C8 +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_A 0x0C9 +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_B 0x0CA +#define RA_ELC_EVENT_GPT1_COMPARE_C 0x0CB +#define RA_ELC_EVENT_GPT1_COMPARE_D 0x0CC +#define RA_ELC_EVENT_GPT1_COMPARE_E 0x0CD +#define RA_ELC_EVENT_GPT1_COMPARE_F 0x0CE +#define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x0CF +#define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x0D0 +#define RA_ELC_EVENT_GPT1_PC 0x0D1 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_A 0x0D2 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_B 0x0D3 +#define RA_ELC_EVENT_GPT2_COMPARE_C 0x0D4 +#define RA_ELC_EVENT_GPT2_COMPARE_D 0x0D5 +#define RA_ELC_EVENT_GPT2_COMPARE_E 0x0D6 +#define RA_ELC_EVENT_GPT2_COMPARE_F 0x0D7 +#define RA_ELC_EVENT_GPT2_COUNTER_OVERFLOW 0x0D8 +#define RA_ELC_EVENT_GPT2_COUNTER_UNDERFLOW 0x0D9 +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_A 0x0DB +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_B 0x0DC +#define RA_ELC_EVENT_GPT3_COMPARE_C 0x0DD +#define RA_ELC_EVENT_GPT3_COMPARE_D 0x0DE +#define RA_ELC_EVENT_GPT3_COMPARE_E 0x0DF +#define RA_ELC_EVENT_GPT3_COMPARE_F 0x0E0 +#define RA_ELC_EVENT_GPT3_COUNTER_OVERFLOW 0x0E1 +#define RA_ELC_EVENT_GPT3_COUNTER_UNDERFLOW 0x0E2 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_A 0x0E4 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_B 0x0E5 +#define RA_ELC_EVENT_GPT4_COMPARE_C 0x0E6 +#define RA_ELC_EVENT_GPT4_COMPARE_D 0x0E7 +#define RA_ELC_EVENT_GPT4_COMPARE_E 0x0E8 +#define RA_ELC_EVENT_GPT4_COMPARE_F 0x0E9 +#define RA_ELC_EVENT_GPT4_COUNTER_OVERFLOW 0x0EA +#define RA_ELC_EVENT_GPT4_COUNTER_UNDERFLOW 0x0EB +#define RA_ELC_EVENT_GPT4_PC 0x0EC +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_A 0x0ED +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_B 0x0EE +#define RA_ELC_EVENT_GPT5_COMPARE_C 0x0EF +#define RA_ELC_EVENT_GPT5_COMPARE_D 0x0F0 +#define RA_ELC_EVENT_GPT5_COMPARE_E 0x0F1 +#define RA_ELC_EVENT_GPT5_COMPARE_F 0x0F2 +#define RA_ELC_EVENT_GPT5_COUNTER_OVERFLOW 0x0F3 +#define RA_ELC_EVENT_GPT5_COUNTER_UNDERFLOW 0x0F4 +#define RA_ELC_EVENT_GPT5_PC 0x0F5 +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_A 0x0F6 +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_B 0x0F7 +#define RA_ELC_EVENT_GPT6_COMPARE_C 0x0F8 +#define RA_ELC_EVENT_GPT6_COMPARE_D 0x0F9 +#define RA_ELC_EVENT_GPT6_COMPARE_E 0x0FA +#define RA_ELC_EVENT_GPT6_COMPARE_F 0x0FB +#define RA_ELC_EVENT_GPT6_COUNTER_OVERFLOW 0x0FC +#define RA_ELC_EVENT_GPT6_COUNTER_UNDERFLOW 0x0FD +#define RA_ELC_EVENT_GPT6_PC 0x0FE +#define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_A 0x0FF +#define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_B 0x100 +#define RA_ELC_EVENT_GPT7_COMPARE_C 0x101 +#define RA_ELC_EVENT_GPT7_COMPARE_D 0x102 +#define RA_ELC_EVENT_GPT7_COMPARE_E 0x103 +#define RA_ELC_EVENT_GPT7_COMPARE_F 0x104 +#define RA_ELC_EVENT_GPT7_COUNTER_OVERFLOW 0x105 +#define RA_ELC_EVENT_GPT7_COUNTER_UNDERFLOW 0x106 +#define RA_ELC_EVENT_GPT8_CAPTURE_COMPARE_A 0x108 +#define RA_ELC_EVENT_GPT8_CAPTURE_COMPARE_B 0x109 +#define RA_ELC_EVENT_GPT8_COMPARE_C 0x10A +#define RA_ELC_EVENT_GPT8_COMPARE_D 0x10B +#define RA_ELC_EVENT_GPT8_COMPARE_E 0x10C +#define RA_ELC_EVENT_GPT8_COMPARE_F 0x10D +#define RA_ELC_EVENT_GPT8_COUNTER_OVERFLOW 0x10E +#define RA_ELC_EVENT_GPT8_COUNTER_UNDERFLOW 0x10F +#define RA_ELC_EVENT_GPT9_CAPTURE_COMPARE_A 0x111 +#define RA_ELC_EVENT_GPT9_CAPTURE_COMPARE_B 0x112 +#define RA_ELC_EVENT_GPT9_COMPARE_C 0x113 +#define RA_ELC_EVENT_GPT9_COMPARE_D 0x114 +#define RA_ELC_EVENT_GPT9_COMPARE_E 0x115 +#define RA_ELC_EVENT_GPT9_COMPARE_F 0x116 +#define RA_ELC_EVENT_GPT9_COUNTER_OVERFLOW 0x117 +#define RA_ELC_EVENT_GPT9_COUNTER_UNDERFLOW 0x118 +#define RA_ELC_EVENT_OPS_UVW_EDGE 0x150 +#define RA_ELC_EVENT_ADC0_SCAN_END 0x160 +#define RA_ELC_EVENT_ADC0_SCAN_END_B 0x161 +#define RA_ELC_EVENT_ADC0_WINDOW_A 0x162 +#define RA_ELC_EVENT_ADC0_WINDOW_B 0x163 +#define RA_ELC_EVENT_ADC0_COMPARE_MATCH 0x164 +#define RA_ELC_EVENT_ADC0_COMPARE_MISMATCH 0x165 +#define RA_ELC_EVENT_ADC1_SCAN_END 0x166 +#define RA_ELC_EVENT_ADC1_SCAN_END_B 0x167 +#define RA_ELC_EVENT_ADC1_WINDOW_A 0x168 +#define RA_ELC_EVENT_ADC1_WINDOW_B 0x169 +#define RA_ELC_EVENT_ADC1_COMPARE_MATCH 0x16A +#define RA_ELC_EVENT_ADC1_COMPARE_MISMATCH 0x16B +#define RA_ELC_EVENT_EDMAC0_EINT 0x16F +#define RA_ELC_EVENT_SCI0_RXI 0x180 +#define RA_ELC_EVENT_SCI0_TXI 0x181 +#define RA_ELC_EVENT_SCI0_TEI 0x182 +#define RA_ELC_EVENT_SCI0_ERI 0x183 +#define RA_ELC_EVENT_SCI0_AM 0x184 +#define RA_ELC_EVENT_SCI0_RXI_OR_ERI 0x185 +#define RA_ELC_EVENT_SCI1_RXI 0x186 +#define RA_ELC_EVENT_SCI1_TXI 0x187 +#define RA_ELC_EVENT_SCI1_TEI 0x188 +#define RA_ELC_EVENT_SCI1_ERI 0x189 +#define RA_ELC_EVENT_SCI2_RXI 0x18C +#define RA_ELC_EVENT_SCI2_TXI 0x18D +#define RA_ELC_EVENT_SCI2_TEI 0x18E +#define RA_ELC_EVENT_SCI2_ERI 0x18F +#define RA_ELC_EVENT_SCI3_RXI 0x192 +#define RA_ELC_EVENT_SCI3_TXI 0x193 +#define RA_ELC_EVENT_SCI3_TEI 0x194 +#define RA_ELC_EVENT_SCI3_ERI 0x195 +#define RA_ELC_EVENT_SCI3_AM 0x196 +#define RA_ELC_EVENT_SCI4_RXI 0x198 +#define RA_ELC_EVENT_SCI4_TXI 0x199 +#define RA_ELC_EVENT_SCI4_TEI 0x19A +#define RA_ELC_EVENT_SCI4_ERI 0x19B +#define RA_ELC_EVENT_SCI4_AM 0x19C +#define RA_ELC_EVENT_SCI5_RXI 0x19E +#define RA_ELC_EVENT_SCI5_TXI 0x19F +#define RA_ELC_EVENT_SCI5_TEI 0x1A0 +#define RA_ELC_EVENT_SCI5_ERI 0x1A1 +#define RA_ELC_EVENT_SCI5_AM 0x1A2 +#define RA_ELC_EVENT_SCI6_RXI 0x1A4 +#define RA_ELC_EVENT_SCI6_TXI 0x1A5 +#define RA_ELC_EVENT_SCI6_TEI 0x1A6 +#define RA_ELC_EVENT_SCI6_ERI 0x1A7 +#define RA_ELC_EVENT_SCI6_AM 0x1A8 +#define RA_ELC_EVENT_SCI7_RXI 0x1AA +#define RA_ELC_EVENT_SCI7_TXI 0x1AB +#define RA_ELC_EVENT_SCI7_TEI 0x1AC +#define RA_ELC_EVENT_SCI7_ERI 0x1AD +#define RA_ELC_EVENT_SCI7_AM 0x1AE +#define RA_ELC_EVENT_SCI8_RXI 0x1B0 +#define RA_ELC_EVENT_SCI8_TXI 0x1B1 +#define RA_ELC_EVENT_SCI8_TEI 0x1B2 +#define RA_ELC_EVENT_SCI8_ERI 0x1B3 +#define RA_ELC_EVENT_SCI8_AM 0x1B4 +#define RA_ELC_EVENT_SCI9_RXI 0x1B6 +#define RA_ELC_EVENT_SCI9_TXI 0x1B7 +#define RA_ELC_EVENT_SCI9_TEI 0x1B8 +#define RA_ELC_EVENT_SCI9_ERI 0x1B9 +#define RA_ELC_EVENT_SCI9_AM 0x1BA +#define RA_ELC_EVENT_SCIX0_SCIX0 0x1BC +#define RA_ELC_EVENT_SCI1_SCIX0 0x1BC +#define RA_ELC_EVENT_SCIX0_SCIX1 0x1BD +#define RA_ELC_EVENT_SCI1_SCIX1 0x1BD +#define RA_ELC_EVENT_SCIX0_SCIX2 0x1BE +#define RA_ELC_EVENT_SCI1_SCIX2 0x1BE +#define RA_ELC_EVENT_SCIX0_SCIX3 0x1BF +#define RA_ELC_EVENT_SCI1_SCIX3 0x1BF +#define RA_ELC_EVENT_SCIX1_SCIX0 0x1C0 +#define RA_ELC_EVENT_SCI2_SCIX0 0x1C0 +#define RA_ELC_EVENT_SCIX1_SCIX1 0x1C1 +#define RA_ELC_EVENT_SCI2_SCIX1 0x1C1 +#define RA_ELC_EVENT_SCIX1_SCIX2 0x1C2 +#define RA_ELC_EVENT_SCI2_SCIX2 0x1C2 +#define RA_ELC_EVENT_SCIX1_SCIX3 0x1C3 +#define RA_ELC_EVENT_SCI2_SCIX3 0x1C3 +#define RA_ELC_EVENT_SPI0_RXI 0x1C4 +#define RA_ELC_EVENT_SPI0_TXI 0x1C5 +#define RA_ELC_EVENT_SPI0_IDLE 0x1C6 +#define RA_ELC_EVENT_SPI0_ERI 0x1C7 +#define RA_ELC_EVENT_SPI0_TEI 0x1C8 +#define RA_ELC_EVENT_SPI1_RXI 0x1C9 +#define RA_ELC_EVENT_SPI1_TXI 0x1CA +#define RA_ELC_EVENT_SPI1_IDLE 0x1CB +#define RA_ELC_EVENT_SPI1_ERI 0x1CC +#define RA_ELC_EVENT_SPI1_TEI 0x1CD +#define RA_ELC_EVENT_OSPI_INT 0x1D9 +#define RA_ELC_EVENT_QSPI_INT 0x1DA +#define RA_ELC_EVENT_DOC_INT 0x1DB + +/* Possible peripherals to be linked to event signals */ +#define RA_ELC_PERIPHERAL_GPT_A 0 +#define RA_ELC_PERIPHERAL_GPT_B 1 +#define RA_ELC_PERIPHERAL_GPT_C 2 +#define RA_ELC_PERIPHERAL_GPT_D 3 +#define RA_ELC_PERIPHERAL_GPT_E 4 +#define RA_ELC_PERIPHERAL_GPT_F 5 +#define RA_ELC_PERIPHERAL_GPT_G 6 +#define RA_ELC_PERIPHERAL_GPT_H 7 +#define RA_ELC_PERIPHERAL_ADC0 8 +#define RA_ELC_PERIPHERAL_ADC0_B 9 +#define RA_ELC_PERIPHERAL_ADC1 10 +#define RA_ELC_PERIPHERAL_ADC1_B 11 +#define RA_ELC_PERIPHERAL_DAC0 12 +#define RA_ELC_PERIPHERAL_DAC1 13 +#define RA_ELC_PERIPHERAL_IOPORT1 14 +#define RA_ELC_PERIPHERAL_IOPORT2 15 +#define RA_ELC_PERIPHERAL_IOPORT3 16 +#define RA_ELC_PERIPHERAL_IOPORT4 17 +#define RA_ELC_PERIPHERAL_CTSU 18 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6M4_ELC_H_ */ diff --git a/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6m5-elc.h b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6m5-elc.h new file mode 100644 index 00000000000..8e64e199791 --- /dev/null +++ b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra6m5-elc.h @@ -0,0 +1,335 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6M5_ELC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6M5_ELC_H_ + +/* Sources of event signals to be linked to other peripherals or the CPU */ +#define RA_ELC_EVENT_NONE 0x0 +#define RA_ELC_EVENT_ICU_IRQ0 0x001 +#define RA_ELC_EVENT_ICU_IRQ1 0x002 +#define RA_ELC_EVENT_ICU_IRQ2 0x003 +#define RA_ELC_EVENT_ICU_IRQ3 0x004 +#define RA_ELC_EVENT_ICU_IRQ4 0x005 +#define RA_ELC_EVENT_ICU_IRQ5 0x006 +#define RA_ELC_EVENT_ICU_IRQ6 0x007 +#define RA_ELC_EVENT_ICU_IRQ7 0x008 +#define RA_ELC_EVENT_ICU_IRQ8 0x009 +#define RA_ELC_EVENT_ICU_IRQ9 0x00A +#define RA_ELC_EVENT_ICU_IRQ10 0x00B +#define RA_ELC_EVENT_ICU_IRQ11 0x00C +#define RA_ELC_EVENT_ICU_IRQ12 0x00D +#define RA_ELC_EVENT_ICU_IRQ13 0x00E +#define RA_ELC_EVENT_ICU_IRQ14 0x00F +#define RA_ELC_EVENT_ICU_IRQ15 0x010 +#define RA_ELC_EVENT_DMAC0_INT 0x020 +#define RA_ELC_EVENT_DMAC1_INT 0x021 +#define RA_ELC_EVENT_DMAC2_INT 0x022 +#define RA_ELC_EVENT_DMAC3_INT 0x023 +#define RA_ELC_EVENT_DMAC4_INT 0x024 +#define RA_ELC_EVENT_DMAC5_INT 0x025 +#define RA_ELC_EVENT_DMAC6_INT 0x026 +#define RA_ELC_EVENT_DMAC7_INT 0x027 +#define RA_ELC_EVENT_DTC_COMPLETE 0x029 +#define RA_ELC_EVENT_DTC_END 0x02A +#define RA_ELC_EVENT_DMA_TRANSERR 0x02B +#define RA_ELC_EVENT_ICU_SNOOZE_CANCEL 0x02D +#define RA_ELC_EVENT_FCU_FIFERR 0x030 +#define RA_ELC_EVENT_FCU_FRDYI 0x031 +#define RA_ELC_EVENT_LVD_LVD1 0x038 +#define RA_ELC_EVENT_LVD_LVD2 0x039 +#define RA_ELC_EVENT_CGC_MOSC_STOP 0x03B +#define RA_ELC_EVENT_LPM_SNOOZE_REQUEST 0x03C +#define RA_ELC_EVENT_AGT0_INT 0x040 +#define RA_ELC_EVENT_AGT0_COMPARE_A 0x041 +#define RA_ELC_EVENT_AGT0_COMPARE_B 0x042 +#define RA_ELC_EVENT_AGT1_INT 0x043 +#define RA_ELC_EVENT_AGT1_COMPARE_A 0x044 +#define RA_ELC_EVENT_AGT1_COMPARE_B 0x045 +#define RA_ELC_EVENT_AGT2_INT 0x046 +#define RA_ELC_EVENT_AGT2_COMPARE_A 0x047 +#define RA_ELC_EVENT_AGT2_COMPARE_B 0x048 +#define RA_ELC_EVENT_AGT3_INT 0x049 +#define RA_ELC_EVENT_AGT3_COMPARE_A 0x04A +#define RA_ELC_EVENT_AGT3_COMPARE_B 0x04B +#define RA_ELC_EVENT_AGT4_INT 0x04C +#define RA_ELC_EVENT_AGT4_COMPARE_A 0x04D +#define RA_ELC_EVENT_AGT4_COMPARE_B 0x04E +#define RA_ELC_EVENT_AGT5_INT 0x04F +#define RA_ELC_EVENT_AGT5_COMPARE_A 0x050 +#define RA_ELC_EVENT_AGT5_COMPARE_B 0x051 +#define RA_ELC_EVENT_IWDT_UNDERFLOW 0x052 +#define RA_ELC_EVENT_WDT_UNDERFLOW 0x053 +#define RA_ELC_EVENT_RTC_ALARM 0x054 +#define RA_ELC_EVENT_RTC_PERIOD 0x055 +#define RA_ELC_EVENT_RTC_CARRY 0x056 +#define RA_ELC_EVENT_CAN_RXF 0x059 +#define RA_ELC_EVENT_CAN_GLERR 0x05A +#define RA_ELC_EVENT_CAN_DMAREQ0 0x05B +#define RA_ELC_EVENT_CAN_DMAREQ1 0x05C +#define RA_ELC_EVENT_CAN_DMAREQ2 0x05D +#define RA_ELC_EVENT_CAN_DMAREQ3 0x05E +#define RA_ELC_EVENT_CAN_DMAREQ4 0x05F +#define RA_ELC_EVENT_CAN_DMAREQ5 0x060 +#define RA_ELC_EVENT_CAN_DMAREQ6 0x061 +#define RA_ELC_EVENT_CAN_DMAREQ7 0x062 +#define RA_ELC_EVENT_CAN0_TX 0x063 +#define RA_ELC_EVENT_CAN0_CHERR 0x064 +#define RA_ELC_EVENT_CAN0_COMFRX 0x065 +#define RA_ELC_EVENT_CAN0_CF_DMAREQ 0x066 +#define RA_ELC_EVENT_CAN1_TX 0x067 +#define RA_ELC_EVENT_CAN1_CHERR 0x068 +#define RA_ELC_EVENT_CAN1_COMFRX 0x069 +#define RA_ELC_EVENT_CAN1_CF_DMAREQ 0x06A +#define RA_ELC_EVENT_USBFS_FIFO_0 0x06B +#define RA_ELC_EVENT_USBFS_FIFO_1 0x06C +#define RA_ELC_EVENT_USBFS_INT 0x06D +#define RA_ELC_EVENT_USBFS_RESUME 0x06E +#define RA_ELC_EVENT_IIC0_RXI 0x073 +#define RA_ELC_EVENT_IIC0_TXI 0x074 +#define RA_ELC_EVENT_IIC0_TEI 0x075 +#define RA_ELC_EVENT_IIC0_ERI 0x076 +#define RA_ELC_EVENT_IIC0_WUI 0x077 +#define RA_ELC_EVENT_IIC1_RXI 0x078 +#define RA_ELC_EVENT_IIC1_TXI 0x079 +#define RA_ELC_EVENT_IIC1_TEI 0x07A +#define RA_ELC_EVENT_IIC1_ERI 0x07B +#define RA_ELC_EVENT_IIC2_RXI 0x07D +#define RA_ELC_EVENT_IIC2_TXI 0x07E +#define RA_ELC_EVENT_IIC2_TEI 0x07F +#define RA_ELC_EVENT_IIC2_ERI 0x080 +#define RA_ELC_EVENT_SDHIMMC0_ACCS 0x082 +#define RA_ELC_EVENT_SDHIMMC0_SDIO 0x083 +#define RA_ELC_EVENT_SDHIMMC0_CARD 0x084 +#define RA_ELC_EVENT_SDHIMMC0_DMA_REQ 0x085 +#define RA_ELC_EVENT_SSI0_TXI 0x08A +#define RA_ELC_EVENT_SSI0_RXI 0x08B +#define RA_ELC_EVENT_SSI0_INT 0x08D +#define RA_ELC_EVENT_CTSU_WRITE 0x09A +#define RA_ELC_EVENT_CTSU_READ 0x09B +#define RA_ELC_EVENT_CTSU_END 0x09C +#define RA_ELC_EVENT_CAC_FREQUENCY_ERROR 0x09E +#define RA_ELC_EVENT_CAC_MEASUREMENT_END 0x09F +#define RA_ELC_EVENT_CAC_OVERFLOW 0x0A0 +#define RA_ELC_EVENT_CEC_INTDA 0x0AB +#define RA_ELC_EVENT_CEC_INTCE 0x0AC +#define RA_ELC_EVENT_CEC_INTERR 0x0AD +#define RA_ELC_EVENT_IOPORT_EVENT_1 0x0B1 +#define RA_ELC_EVENT_IOPORT_EVENT_2 0x0B2 +#define RA_ELC_EVENT_IOPORT_EVENT_3 0x0B3 +#define RA_ELC_EVENT_IOPORT_EVENT_4 0x0B4 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0 0x0B5 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1 0x0B6 +#define RA_ELC_EVENT_POEG0_EVENT 0x0B7 +#define RA_ELC_EVENT_POEG1_EVENT 0x0B8 +#define RA_ELC_EVENT_POEG2_EVENT 0x0B9 +#define RA_ELC_EVENT_POEG3_EVENT 0x0BA +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_A 0x0C0 +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_B 0x0C1 +#define RA_ELC_EVENT_GPT0_COMPARE_C 0x0C2 +#define RA_ELC_EVENT_GPT0_COMPARE_D 0x0C3 +#define RA_ELC_EVENT_GPT0_COMPARE_E 0x0C4 +#define RA_ELC_EVENT_GPT0_COMPARE_F 0x0C5 +#define RA_ELC_EVENT_GPT0_COUNTER_OVERFLOW 0x0C6 +#define RA_ELC_EVENT_GPT0_COUNTER_UNDERFLOW 0x0C7 +#define RA_ELC_EVENT_GPT0_PC 0x0C8 +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_A 0x0C9 +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_B 0x0CA +#define RA_ELC_EVENT_GPT1_COMPARE_C 0x0CB +#define RA_ELC_EVENT_GPT1_COMPARE_D 0x0CC +#define RA_ELC_EVENT_GPT1_COMPARE_E 0x0CD +#define RA_ELC_EVENT_GPT1_COMPARE_F 0x0CE +#define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x0CF +#define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x0D0 +#define RA_ELC_EVENT_GPT1_PC 0x0D1 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_A 0x0D2 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_B 0x0D3 +#define RA_ELC_EVENT_GPT2_COMPARE_C 0x0D4 +#define RA_ELC_EVENT_GPT2_COMPARE_D 0x0D5 +#define RA_ELC_EVENT_GPT2_COMPARE_E 0x0D6 +#define RA_ELC_EVENT_GPT2_COMPARE_F 0x0D7 +#define RA_ELC_EVENT_GPT2_COUNTER_OVERFLOW 0x0D8 +#define RA_ELC_EVENT_GPT2_COUNTER_UNDERFLOW 0x0D9 +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_A 0x0DB +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_B 0x0DC +#define RA_ELC_EVENT_GPT3_COMPARE_C 0x0DD +#define RA_ELC_EVENT_GPT3_COMPARE_D 0x0DE +#define RA_ELC_EVENT_GPT3_COMPARE_E 0x0DF +#define RA_ELC_EVENT_GPT3_COMPARE_F 0x0E0 +#define RA_ELC_EVENT_GPT3_COUNTER_OVERFLOW 0x0E1 +#define RA_ELC_EVENT_GPT3_COUNTER_UNDERFLOW 0x0E2 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_A 0x0E4 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_B 0x0E5 +#define RA_ELC_EVENT_GPT4_COMPARE_C 0x0E6 +#define RA_ELC_EVENT_GPT4_COMPARE_D 0x0E7 +#define RA_ELC_EVENT_GPT4_COMPARE_E 0x0E8 +#define RA_ELC_EVENT_GPT4_COMPARE_F 0x0E9 +#define RA_ELC_EVENT_GPT4_COUNTER_OVERFLOW 0x0EA +#define RA_ELC_EVENT_GPT4_COUNTER_UNDERFLOW 0x0EB +#define RA_ELC_EVENT_GPT4_PC 0x0EC +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_A 0x0ED +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_B 0x0EE +#define RA_ELC_EVENT_GPT5_COMPARE_C 0x0EF +#define RA_ELC_EVENT_GPT5_COMPARE_D 0x0F0 +#define RA_ELC_EVENT_GPT5_COMPARE_E 0x0F1 +#define RA_ELC_EVENT_GPT5_COMPARE_F 0x0F2 +#define RA_ELC_EVENT_GPT5_COUNTER_OVERFLOW 0x0F3 +#define RA_ELC_EVENT_GPT5_COUNTER_UNDERFLOW 0x0F4 +#define RA_ELC_EVENT_GPT5_PC 0x0F5 +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_A 0x0F6 +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_B 0x0F7 +#define RA_ELC_EVENT_GPT6_COMPARE_C 0x0F8 +#define RA_ELC_EVENT_GPT6_COMPARE_D 0x0F9 +#define RA_ELC_EVENT_GPT6_COMPARE_E 0x0FA +#define RA_ELC_EVENT_GPT6_COMPARE_F 0x0FB +#define RA_ELC_EVENT_GPT6_COUNTER_OVERFLOW 0x0FC +#define RA_ELC_EVENT_GPT6_COUNTER_UNDERFLOW 0x0FD +#define RA_ELC_EVENT_GPT6_PC 0x0FE +#define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_A 0x0FF +#define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_B 0x100 +#define RA_ELC_EVENT_GPT7_COMPARE_C 0x101 +#define RA_ELC_EVENT_GPT7_COMPARE_D 0x102 +#define RA_ELC_EVENT_GPT7_COMPARE_E 0x103 +#define RA_ELC_EVENT_GPT7_COMPARE_F 0x104 +#define RA_ELC_EVENT_GPT7_COUNTER_OVERFLOW 0x105 +#define RA_ELC_EVENT_GPT7_COUNTER_UNDERFLOW 0x106 +#define RA_ELC_EVENT_GPT8_CAPTURE_COMPARE_A 0x108 +#define RA_ELC_EVENT_GPT8_CAPTURE_COMPARE_B 0x109 +#define RA_ELC_EVENT_GPT8_COMPARE_C 0x10A +#define RA_ELC_EVENT_GPT8_COMPARE_D 0x10B +#define RA_ELC_EVENT_GPT8_COMPARE_E 0x10C +#define RA_ELC_EVENT_GPT8_COMPARE_F 0x10D +#define RA_ELC_EVENT_GPT8_COUNTER_OVERFLOW 0x10E +#define RA_ELC_EVENT_GPT8_COUNTER_UNDERFLOW 0x10F +#define RA_ELC_EVENT_GPT9_CAPTURE_COMPARE_A 0x111 +#define RA_ELC_EVENT_GPT9_CAPTURE_COMPARE_B 0x112 +#define RA_ELC_EVENT_GPT9_COMPARE_C 0x113 +#define RA_ELC_EVENT_GPT9_COMPARE_D 0x114 +#define RA_ELC_EVENT_GPT9_COMPARE_E 0x115 +#define RA_ELC_EVENT_GPT9_COMPARE_F 0x116 +#define RA_ELC_EVENT_GPT9_COUNTER_OVERFLOW 0x117 +#define RA_ELC_EVENT_GPT9_COUNTER_UNDERFLOW 0x118 +#define RA_ELC_EVENT_OPS_UVW_EDGE 0x150 +#define RA_ELC_EVENT_ADC0_SCAN_END 0x160 +#define RA_ELC_EVENT_ADC0_SCAN_END_B 0x161 +#define RA_ELC_EVENT_ADC0_WINDOW_A 0x162 +#define RA_ELC_EVENT_ADC0_WINDOW_B 0x163 +#define RA_ELC_EVENT_ADC0_COMPARE_MATCH 0x164 +#define RA_ELC_EVENT_ADC0_COMPARE_MISMATCH 0x165 +#define RA_ELC_EVENT_ADC1_SCAN_END 0x166 +#define RA_ELC_EVENT_ADC1_SCAN_END_B 0x167 +#define RA_ELC_EVENT_ADC1_WINDOW_A 0x168 +#define RA_ELC_EVENT_ADC1_WINDOW_B 0x169 +#define RA_ELC_EVENT_ADC1_COMPARE_MATCH 0x16A +#define RA_ELC_EVENT_ADC1_COMPARE_MISMATCH 0x16B +#define RA_ELC_EVENT_EDMAC0_EINT 0x16F +#define RA_ELC_EVENT_USBHS_FIFO_0 0x17D +#define RA_ELC_EVENT_USBHS_FIFO_1 0x17E +#define RA_ELC_EVENT_USBHS_USB_INT_RESUME 0x17F +#define RA_ELC_EVENT_SCI0_RXI 0x180 +#define RA_ELC_EVENT_SCI0_TXI 0x181 +#define RA_ELC_EVENT_SCI0_TEI 0x182 +#define RA_ELC_EVENT_SCI0_ERI 0x183 +#define RA_ELC_EVENT_SCI0_AM 0x184 +#define RA_ELC_EVENT_SCI0_RXI_OR_ERI 0x185 +#define RA_ELC_EVENT_SCI1_RXI 0x186 +#define RA_ELC_EVENT_SCI1_TXI 0x187 +#define RA_ELC_EVENT_SCI1_TEI 0x188 +#define RA_ELC_EVENT_SCI1_ERI 0x189 +#define RA_ELC_EVENT_SCI2_RXI 0x18C +#define RA_ELC_EVENT_SCI2_TXI 0x18D +#define RA_ELC_EVENT_SCI2_TEI 0x18E +#define RA_ELC_EVENT_SCI2_ERI 0x18F +#define RA_ELC_EVENT_SCI3_RXI 0x192 +#define RA_ELC_EVENT_SCI3_TXI 0x193 +#define RA_ELC_EVENT_SCI3_TEI 0x194 +#define RA_ELC_EVENT_SCI3_ERI 0x195 +#define RA_ELC_EVENT_SCI3_AM 0x196 +#define RA_ELC_EVENT_SCI4_RXI 0x198 +#define RA_ELC_EVENT_SCI4_TXI 0x199 +#define RA_ELC_EVENT_SCI4_TEI 0x19A +#define RA_ELC_EVENT_SCI4_ERI 0x19B +#define RA_ELC_EVENT_SCI4_AM 0x19C +#define RA_ELC_EVENT_SCI5_RXI 0x19E +#define RA_ELC_EVENT_SCI5_TXI 0x19F +#define RA_ELC_EVENT_SCI5_TEI 0x1A0 +#define RA_ELC_EVENT_SCI5_ERI 0x1A1 +#define RA_ELC_EVENT_SCI5_AM 0x1A2 +#define RA_ELC_EVENT_SCI6_RXI 0x1A4 +#define RA_ELC_EVENT_SCI6_TXI 0x1A5 +#define RA_ELC_EVENT_SCI6_TEI 0x1A6 +#define RA_ELC_EVENT_SCI6_ERI 0x1A7 +#define RA_ELC_EVENT_SCI6_AM 0x1A8 +#define RA_ELC_EVENT_SCI7_RXI 0x1AA +#define RA_ELC_EVENT_SCI7_TXI 0x1AB +#define RA_ELC_EVENT_SCI7_TEI 0x1AC +#define RA_ELC_EVENT_SCI7_ERI 0x1AD +#define RA_ELC_EVENT_SCI7_AM 0x1AE +#define RA_ELC_EVENT_SCI8_RXI 0x1B0 +#define RA_ELC_EVENT_SCI8_TXI 0x1B1 +#define RA_ELC_EVENT_SCI8_TEI 0x1B2 +#define RA_ELC_EVENT_SCI8_ERI 0x1B3 +#define RA_ELC_EVENT_SCI8_AM 0x1B4 +#define RA_ELC_EVENT_SCI9_RXI 0x1B6 +#define RA_ELC_EVENT_SCI9_TXI 0x1B7 +#define RA_ELC_EVENT_SCI9_TEI 0x1B8 +#define RA_ELC_EVENT_SCI9_ERI 0x1B9 +#define RA_ELC_EVENT_SCI9_AM 0x1BA +#define RA_ELC_EVENT_SCIX0_SCIX0 0x1BC +#define RA_ELC_EVENT_SCI1_SCIX0 0x1BC +#define RA_ELC_EVENT_SCIX0_SCIX1 0x1BD +#define RA_ELC_EVENT_SCI1_SCIX1 0x1BD +#define RA_ELC_EVENT_SCIX0_SCIX2 0x1BE +#define RA_ELC_EVENT_SCI1_SCIX2 0x1BE +#define RA_ELC_EVENT_SCIX0_SCIX3 0x1BF +#define RA_ELC_EVENT_SCI1_SCIX3 0x1BF +#define RA_ELC_EVENT_SCIX1_SCIX0 0x1C0 +#define RA_ELC_EVENT_SCI2_SCIX0 0x1C0 +#define RA_ELC_EVENT_SCIX1_SCIX1 0x1C1 +#define RA_ELC_EVENT_SCI2_SCIX1 0x1C1 +#define RA_ELC_EVENT_SCIX1_SCIX2 0x1C2 +#define RA_ELC_EVENT_SCI2_SCIX2 0x1C2 +#define RA_ELC_EVENT_SCIX1_SCIX3 0x1C3 +#define RA_ELC_EVENT_SCI2_SCIX3 0x1C3 +#define RA_ELC_EVENT_SPI0_RXI 0x1C4 +#define RA_ELC_EVENT_SPI0_TXI 0x1C5 +#define RA_ELC_EVENT_SPI0_IDLE 0x1C6 +#define RA_ELC_EVENT_SPI0_ERI 0x1C7 +#define RA_ELC_EVENT_SPI0_TEI 0x1C8 +#define RA_ELC_EVENT_SPI1_RXI 0x1C9 +#define RA_ELC_EVENT_SPI1_TXI 0x1CA +#define RA_ELC_EVENT_SPI1_IDLE 0x1CB +#define RA_ELC_EVENT_SPI1_ERI 0x1CC +#define RA_ELC_EVENT_SPI1_TEI 0x1CD +#define RA_ELC_EVENT_CAN_AFLRAM0_ERI 0x1CE +#define RA_ELC_EVENT_CAN_AFLRAM1_ERI 0x1CF +#define RA_ELC_EVENT_CAN0_MRAM_ERI 0x1D0 +#define RA_ELC_EVENT_OSPI_INT 0x1D9 +#define RA_ELC_EVENT_QSPI_INT 0x1DA +#define RA_ELC_EVENT_DOC_INT 0x1DB + +/* Possible peripherals to be linked to event signals */ +#define RA_ELC_PERIPHERAL_GPT_A 0 +#define RA_ELC_PERIPHERAL_GPT_B 1 +#define RA_ELC_PERIPHERAL_GPT_C 2 +#define RA_ELC_PERIPHERAL_GPT_D 3 +#define RA_ELC_PERIPHERAL_GPT_E 4 +#define RA_ELC_PERIPHERAL_GPT_F 5 +#define RA_ELC_PERIPHERAL_GPT_G 6 +#define RA_ELC_PERIPHERAL_GPT_H 7 +#define RA_ELC_PERIPHERAL_ADC0 8 +#define RA_ELC_PERIPHERAL_ADC0_B 9 +#define RA_ELC_PERIPHERAL_ADC1 10 +#define RA_ELC_PERIPHERAL_ADC1_B 11 +#define RA_ELC_PERIPHERAL_DAC0 12 +#define RA_ELC_PERIPHERAL_DAC1 13 +#define RA_ELC_PERIPHERAL_IOPORT1 14 +#define RA_ELC_PERIPHERAL_IOPORT2 15 +#define RA_ELC_PERIPHERAL_IOPORT3 16 +#define RA_ELC_PERIPHERAL_IOPORT4 17 +#define RA_ELC_PERIPHERAL_CTSU 18 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6M5_ELC_H_ */ diff --git a/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra8d1-elc.h b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra8d1-elc.h new file mode 100644 index 00000000000..93cf07955db --- /dev/null +++ b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra8d1-elc.h @@ -0,0 +1,364 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA8D1_ELC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA8D1_ELC_H_ + +/* Sources of event signals to be linked to other peripherals or the CPU */ +#define RA_ELC_EVENT_NONE 0x0 +#define RA_ELC_EVENT_ICU_IRQ0 0x001 +#define RA_ELC_EVENT_ICU_IRQ1 0x002 +#define RA_ELC_EVENT_ICU_IRQ2 0x003 +#define RA_ELC_EVENT_ICU_IRQ3 0x004 +#define RA_ELC_EVENT_ICU_IRQ4 0x005 +#define RA_ELC_EVENT_ICU_IRQ5 0x006 +#define RA_ELC_EVENT_ICU_IRQ6 0x007 +#define RA_ELC_EVENT_ICU_IRQ7 0x008 +#define RA_ELC_EVENT_ICU_IRQ8 0x009 +#define RA_ELC_EVENT_ICU_IRQ9 0x00A +#define RA_ELC_EVENT_ICU_IRQ10 0x00B +#define RA_ELC_EVENT_ICU_IRQ11 0x00C +#define RA_ELC_EVENT_ICU_IRQ12 0x00D +#define RA_ELC_EVENT_ICU_IRQ13 0x00E +#define RA_ELC_EVENT_ICU_IRQ14 0x00F +#define RA_ELC_EVENT_ICU_IRQ15 0x010 +#define RA_ELC_EVENT_DMAC0_INT 0x011 +#define RA_ELC_EVENT_DMAC1_INT 0x012 +#define RA_ELC_EVENT_DMAC2_INT 0x013 +#define RA_ELC_EVENT_DMAC3_INT 0x014 +#define RA_ELC_EVENT_DMAC4_INT 0x015 +#define RA_ELC_EVENT_DMAC5_INT 0x016 +#define RA_ELC_EVENT_DMAC6_INT 0x017 +#define RA_ELC_EVENT_DMAC7_INT 0x018 +#define RA_ELC_EVENT_DTC_END 0x021 +#define RA_ELC_EVENT_DTC_COMPLETE 0x022 +#define RA_ELC_EVENT_DMA_TRANSERR 0x027 +#define RA_ELC_EVENT_DBG_CTIIRQ0 0x029 +#define RA_ELC_EVENT_DBG_CTIIRQ1 0x02A +#define RA_ELC_EVENT_DBG_JBRXI 0x02B +#define RA_ELC_EVENT_FCU_FIFERR 0x030 +#define RA_ELC_EVENT_FCU_FRDYI 0x031 +#define RA_ELC_EVENT_LVD_LVD1 0x038 +#define RA_ELC_EVENT_LVD_LVD2 0x039 +#define RA_ELC_EVENT_VBATT_TADI 0x03D +#define RA_ELC_EVENT_CGC_MOSC_STOP 0x03E +#define RA_ELC_EVENT_ULPT0_INT 0x040 +#define RA_ELC_EVENT_ULPT0_COMPARE_A 0x041 +#define RA_ELC_EVENT_ULPT0_COMPARE_B 0x042 +#define RA_ELC_EVENT_ULPT1_INT 0x043 +#define RA_ELC_EVENT_ULPT1_COMPARE_A 0x044 +#define RA_ELC_EVENT_ULPT1_COMPARE_B 0x045 +#define RA_ELC_EVENT_AGT0_INT 0x046 +#define RA_ELC_EVENT_AGT0_COMPARE_A 0x047 +#define RA_ELC_EVENT_AGT0_COMPARE_B 0x048 +#define RA_ELC_EVENT_AGT1_INT 0x049 +#define RA_ELC_EVENT_AGT1_COMPARE_A 0x04A +#define RA_ELC_EVENT_AGT1_COMPARE_B 0x04B +#define RA_ELC_EVENT_IWDT_UNDERFLOW 0x052 +#define RA_ELC_EVENT_WDT0_UNDERFLOW 0x053 +#define RA_ELC_EVENT_RTC_ALARM 0x055 +#define RA_ELC_EVENT_RTC_PERIOD 0x056 +#define RA_ELC_EVENT_RTC_CARRY 0x057 +#define RA_ELC_EVENT_USBFS_FIFO_0 0x058 +#define RA_ELC_EVENT_USBFS_FIFO_1 0x059 +#define RA_ELC_EVENT_USBFS_INT 0x05A +#define RA_ELC_EVENT_USBFS_RESUME 0x05B +#define RA_ELC_EVENT_IIC0_RXI 0x05C +#define RA_ELC_EVENT_IIC0_TXI 0x05D +#define RA_ELC_EVENT_IIC0_TEI 0x05E +#define RA_ELC_EVENT_IIC0_ERI 0x05F +#define RA_ELC_EVENT_IIC0_WUI 0x060 +#define RA_ELC_EVENT_IIC1_RXI 0x061 +#define RA_ELC_EVENT_IIC1_TXI 0x062 +#define RA_ELC_EVENT_IIC1_TEI 0x063 +#define RA_ELC_EVENT_IIC1_ERI 0x064 +#define RA_ELC_EVENT_SDHIMMC0_ACCS 0x06B +#define RA_ELC_EVENT_SDHIMMC0_SDIO 0x06C +#define RA_ELC_EVENT_SDHIMMC0_CARD 0x06D +#define RA_ELC_EVENT_SDHIMMC0_DMA_REQ 0x06E +#define RA_ELC_EVENT_SDHIMMC1_ACCS 0x06F +#define RA_ELC_EVENT_SDHIMMC1_SDIO 0x070 +#define RA_ELC_EVENT_SDHIMMC1_CARD 0x071 +#define RA_ELC_EVENT_SDHIMMC1_DMA_REQ 0x072 +#define RA_ELC_EVENT_SSI0_TXI 0x073 +#define RA_ELC_EVENT_SSI0_RXI 0x074 +#define RA_ELC_EVENT_SSI0_INT 0x076 +#define RA_ELC_EVENT_SSI1_TXI_RXI 0x079 +#define RA_ELC_EVENT_SSI1_TXI 0x079 +#define RA_ELC_EVENT_SSI1_RXI 0x079 +#define RA_ELC_EVENT_SSI1_INT 0x07A +#define RA_ELC_EVENT_ACMPHS0_INT 0x07B +#define RA_ELC_EVENT_ACMPHS1_INT 0x07C +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0 0x083 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1 0x084 +#define RA_ELC_EVENT_IOPORT_EVENT_1 0x088 +#define RA_ELC_EVENT_IOPORT_EVENT_2 0x089 +#define RA_ELC_EVENT_IOPORT_EVENT_3 0x08A +#define RA_ELC_EVENT_IOPORT_EVENT_4 0x08B +#define RA_ELC_EVENT_CAC_FREQUENCY_ERROR 0x08C +#define RA_ELC_EVENT_CAC_MEASUREMENT_END 0x08D +#define RA_ELC_EVENT_CAC_OVERFLOW 0x08E +#define RA_ELC_EVENT_POEG0_EVENT 0x08F +#define RA_ELC_EVENT_POEG1_EVENT 0x090 +#define RA_ELC_EVENT_POEG2_EVENT 0x091 +#define RA_ELC_EVENT_POEG3_EVENT 0x092 +#define RA_ELC_EVENT_OPS_UVW_EDGE 0x0A0 +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_A 0x0A1 +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_B 0x0A2 +#define RA_ELC_EVENT_GPT0_COMPARE_C 0x0A3 +#define RA_ELC_EVENT_GPT0_COMPARE_D 0x0A4 +#define RA_ELC_EVENT_GPT0_COMPARE_E 0x0A5 +#define RA_ELC_EVENT_GPT0_COMPARE_F 0x0A6 +#define RA_ELC_EVENT_GPT0_COUNTER_OVERFLOW 0x0A7 +#define RA_ELC_EVENT_GPT0_COUNTER_UNDERFLOW 0x0A8 +#define RA_ELC_EVENT_GPT0_PC 0x0A9 +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_A 0x0AA +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_B 0x0AB +#define RA_ELC_EVENT_GPT1_COMPARE_C 0x0AC +#define RA_ELC_EVENT_GPT1_COMPARE_D 0x0AD +#define RA_ELC_EVENT_GPT1_COMPARE_E 0x0AE +#define RA_ELC_EVENT_GPT1_COMPARE_F 0x0AF +#define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x0B0 +#define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x0B1 +#define RA_ELC_EVENT_GPT1_PC 0x0B2 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_A 0x0B3 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_B 0x0B4 +#define RA_ELC_EVENT_GPT2_COMPARE_C 0x0B5 +#define RA_ELC_EVENT_GPT2_COMPARE_D 0x0B6 +#define RA_ELC_EVENT_GPT2_COMPARE_E 0x0B7 +#define RA_ELC_EVENT_GPT2_COMPARE_F 0x0B8 +#define RA_ELC_EVENT_GPT2_COUNTER_OVERFLOW 0x0B9 +#define RA_ELC_EVENT_GPT2_COUNTER_UNDERFLOW 0x0BA +#define RA_ELC_EVENT_GPT2_PC 0x0BB +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_A 0x0BC +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_B 0x0BD +#define RA_ELC_EVENT_GPT3_COMPARE_C 0x0BE +#define RA_ELC_EVENT_GPT3_COMPARE_D 0x0BF +#define RA_ELC_EVENT_GPT3_COMPARE_E 0x0C0 +#define RA_ELC_EVENT_GPT3_COMPARE_F 0x0C1 +#define RA_ELC_EVENT_GPT3_COUNTER_OVERFLOW 0x0C2 +#define RA_ELC_EVENT_GPT3_COUNTER_UNDERFLOW 0x0C3 +#define RA_ELC_EVENT_GPT3_PC 0x0C4 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_A 0x0C5 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_B 0x0C6 +#define RA_ELC_EVENT_GPT4_COMPARE_C 0x0C7 +#define RA_ELC_EVENT_GPT4_COMPARE_D 0x0C8 +#define RA_ELC_EVENT_GPT4_COMPARE_E 0x0C9 +#define RA_ELC_EVENT_GPT4_COMPARE_F 0x0CA +#define RA_ELC_EVENT_GPT4_COUNTER_OVERFLOW 0x0CB +#define RA_ELC_EVENT_GPT4_COUNTER_UNDERFLOW 0x0CC +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_A 0x0CE +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_B 0x0CF +#define RA_ELC_EVENT_GPT5_COMPARE_C 0x0D0 +#define RA_ELC_EVENT_GPT5_COMPARE_D 0x0D1 +#define RA_ELC_EVENT_GPT5_COMPARE_E 0x0D2 +#define RA_ELC_EVENT_GPT5_COMPARE_F 0x0D3 +#define RA_ELC_EVENT_GPT5_COUNTER_OVERFLOW 0x0D4 +#define RA_ELC_EVENT_GPT5_COUNTER_UNDERFLOW 0x0D5 +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_A 0x0D7 +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_B 0x0D8 +#define RA_ELC_EVENT_GPT6_COMPARE_C 0x0D9 +#define RA_ELC_EVENT_GPT6_COMPARE_D 0x0DA +#define RA_ELC_EVENT_GPT6_COMPARE_E 0x0DB +#define RA_ELC_EVENT_GPT6_COMPARE_F 0x0DC +#define RA_ELC_EVENT_GPT6_COUNTER_OVERFLOW 0x0DD +#define RA_ELC_EVENT_GPT6_COUNTER_UNDERFLOW 0x0DE +#define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_A 0x0E0 +#define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_B 0x0E1 +#define RA_ELC_EVENT_GPT7_COMPARE_C 0x0E2 +#define RA_ELC_EVENT_GPT7_COMPARE_D 0x0E3 +#define RA_ELC_EVENT_GPT7_COMPARE_E 0x0E4 +#define RA_ELC_EVENT_GPT7_COMPARE_F 0x0E5 +#define RA_ELC_EVENT_GPT7_COUNTER_OVERFLOW 0x0E6 +#define RA_ELC_EVENT_GPT7_COUNTER_UNDERFLOW 0x0E7 +#define RA_ELC_EVENT_GPT8_CAPTURE_COMPARE_A 0x0E9 +#define RA_ELC_EVENT_GPT8_CAPTURE_COMPARE_B 0x0EA +#define RA_ELC_EVENT_GPT8_COMPARE_C 0x0EB +#define RA_ELC_EVENT_GPT8_COMPARE_D 0x0EC +#define RA_ELC_EVENT_GPT8_COMPARE_E 0x0ED +#define RA_ELC_EVENT_GPT8_COMPARE_F 0x0EE +#define RA_ELC_EVENT_GPT8_COUNTER_OVERFLOW 0x0EF +#define RA_ELC_EVENT_GPT8_COUNTER_UNDERFLOW 0x0F0 +#define RA_ELC_EVENT_GPT8_PC 0x0F1 +#define RA_ELC_EVENT_GPT9_CAPTURE_COMPARE_A 0x0F2 +#define RA_ELC_EVENT_GPT9_CAPTURE_COMPARE_B 0x0F3 +#define RA_ELC_EVENT_GPT9_COMPARE_C 0x0F4 +#define RA_ELC_EVENT_GPT9_COMPARE_D 0x0F5 +#define RA_ELC_EVENT_GPT9_COMPARE_E 0x0F6 +#define RA_ELC_EVENT_GPT9_COMPARE_F 0x0F7 +#define RA_ELC_EVENT_GPT9_COUNTER_OVERFLOW 0x0F8 +#define RA_ELC_EVENT_GPT9_COUNTER_UNDERFLOW 0x0F9 +#define RA_ELC_EVENT_GPT9_PC 0x0FA +#define RA_ELC_EVENT_GPT10_CAPTURE_COMPARE_A 0x0FB +#define RA_ELC_EVENT_GPT10_CAPTURE_COMPARE_B 0x0FC +#define RA_ELC_EVENT_GPT10_COMPARE_C 0x0FD +#define RA_ELC_EVENT_GPT10_COMPARE_D 0x0FE +#define RA_ELC_EVENT_GPT10_COMPARE_E 0x0FF +#define RA_ELC_EVENT_GPT10_COMPARE_F 0x100 +#define RA_ELC_EVENT_GPT10_COUNTER_OVERFLOW 0x101 +#define RA_ELC_EVENT_GPT10_COUNTER_UNDERFLOW 0x102 +#define RA_ELC_EVENT_GPT10_PC 0x103 +#define RA_ELC_EVENT_GPT11_CAPTURE_COMPARE_A 0x104 +#define RA_ELC_EVENT_GPT11_CAPTURE_COMPARE_B 0x105 +#define RA_ELC_EVENT_GPT11_COMPARE_C 0x106 +#define RA_ELC_EVENT_GPT11_COMPARE_D 0x107 +#define RA_ELC_EVENT_GPT11_COMPARE_E 0x108 +#define RA_ELC_EVENT_GPT11_COMPARE_F 0x109 +#define RA_ELC_EVENT_GPT11_COUNTER_OVERFLOW 0x10A +#define RA_ELC_EVENT_GPT11_COUNTER_UNDERFLOW 0x10B +#define RA_ELC_EVENT_GPT12_CAPTURE_COMPARE_A 0x10D +#define RA_ELC_EVENT_GPT12_CAPTURE_COMPARE_B 0x10E +#define RA_ELC_EVENT_GPT12_COMPARE_C 0x10F +#define RA_ELC_EVENT_GPT12_COMPARE_D 0x110 +#define RA_ELC_EVENT_GPT12_COMPARE_E 0x111 +#define RA_ELC_EVENT_GPT12_COMPARE_F 0x112 +#define RA_ELC_EVENT_GPT12_COUNTER_OVERFLOW 0x113 +#define RA_ELC_EVENT_GPT12_COUNTER_UNDERFLOW 0x114 +#define RA_ELC_EVENT_GPT13_CAPTURE_COMPARE_A 0x116 +#define RA_ELC_EVENT_GPT13_CAPTURE_COMPARE_B 0x117 +#define RA_ELC_EVENT_GPT13_COMPARE_C 0x118 +#define RA_ELC_EVENT_GPT13_COMPARE_D 0x119 +#define RA_ELC_EVENT_GPT13_COMPARE_E 0x11A +#define RA_ELC_EVENT_GPT13_COMPARE_F 0x11B +#define RA_ELC_EVENT_GPT13_COUNTER_OVERFLOW 0x11C +#define RA_ELC_EVENT_GPT13_COUNTER_UNDERFLOW 0x11D +#define RA_ELC_EVENT_EDMAC0_EINT 0x120 +#define RA_ELC_EVENT_USBHS_FIFO_0 0x121 +#define RA_ELC_EVENT_USBHS_FIFO_1 0x122 +#define RA_ELC_EVENT_USBHS_USB_INT_RESUME 0x123 +#define RA_ELC_EVENT_SCI0_RXI 0x124 +#define RA_ELC_EVENT_SCI0_TXI 0x125 +#define RA_ELC_EVENT_SCI0_TEI 0x126 +#define RA_ELC_EVENT_SCI0_ERI 0x127 +#define RA_ELC_EVENT_SCI0_AED 0x128 +#define RA_ELC_EVENT_SCI0_BFD 0x129 +#define RA_ELC_EVENT_SCI0_AM 0x12A +#define RA_ELC_EVENT_SCI1_RXI 0x12B +#define RA_ELC_EVENT_SCI1_TXI 0x12C +#define RA_ELC_EVENT_SCI1_TEI 0x12D +#define RA_ELC_EVENT_SCI1_ERI 0x12E +#define RA_ELC_EVENT_SCI1_AED 0x12F +#define RA_ELC_EVENT_SCI1_BFD 0x130 +#define RA_ELC_EVENT_SCI1_AM 0x131 +#define RA_ELC_EVENT_SCI2_RXI 0x132 +#define RA_ELC_EVENT_SCI2_TXI 0x133 +#define RA_ELC_EVENT_SCI2_TEI 0x134 +#define RA_ELC_EVENT_SCI2_ERI 0x135 +#define RA_ELC_EVENT_SCI2_AM 0x138 +#define RA_ELC_EVENT_SCI3_RXI 0x139 +#define RA_ELC_EVENT_SCI3_TXI 0x13A +#define RA_ELC_EVENT_SCI3_TEI 0x13B +#define RA_ELC_EVENT_SCI3_ERI 0x13C +#define RA_ELC_EVENT_SCI3_AM 0x13F +#define RA_ELC_EVENT_SCI4_RXI 0x140 +#define RA_ELC_EVENT_SCI4_TXI 0x141 +#define RA_ELC_EVENT_SCI4_TEI 0x142 +#define RA_ELC_EVENT_SCI4_ERI 0x143 +#define RA_ELC_EVENT_SCI4_AM 0x146 +#define RA_ELC_EVENT_SCI9_RXI 0x163 +#define RA_ELC_EVENT_SCI9_TXI 0x164 +#define RA_ELC_EVENT_SCI9_TEI 0x165 +#define RA_ELC_EVENT_SCI9_ERI 0x166 +#define RA_ELC_EVENT_SCI9_AM 0x169 +#define RA_ELC_EVENT_SPI0_RXI 0x178 +#define RA_ELC_EVENT_SPI0_TXI 0x179 +#define RA_ELC_EVENT_SPI0_IDLE 0x17A +#define RA_ELC_EVENT_SPI0_ERI 0x17B +#define RA_ELC_EVENT_SPI0_TEI 0x17C +#define RA_ELC_EVENT_SPI1_RXI 0x17D +#define RA_ELC_EVENT_SPI1_TXI 0x17E +#define RA_ELC_EVENT_SPI1_IDLE 0x17F +#define RA_ELC_EVENT_SPI1_ERI 0x180 +#define RA_ELC_EVENT_SPI1_TEI 0x181 +#define RA_ELC_EVENT_XSPI_ERR 0x182 +#define RA_ELC_EVENT_XSPI_CMP 0x183 +#define RA_ELC_EVENT_CAN_RXF 0x185 +#define RA_ELC_EVENT_CAN_GLERR 0x186 +#define RA_ELC_EVENT_CAN0_DMAREQ0 0x187 +#define RA_ELC_EVENT_CAN0_DMAREQ1 0x188 +#define RA_ELC_EVENT_CAN1_DMAREQ0 0x18B +#define RA_ELC_EVENT_CAN1_DMAREQ1 0x18C +#define RA_ELC_EVENT_CAN0_TX 0x18F +#define RA_ELC_EVENT_CAN0_CHERR 0x190 +#define RA_ELC_EVENT_CAN0_COMFRX 0x191 +#define RA_ELC_EVENT_CAN0_CF_DMAREQ 0x192 +#define RA_ELC_EVENT_CAN0_RXMB 0x193 +#define RA_ELC_EVENT_CAN1_TX 0x194 +#define RA_ELC_EVENT_CAN1_CHERR 0x195 +#define RA_ELC_EVENT_CAN1_COMFRX 0x196 +#define RA_ELC_EVENT_CAN1_CF_DMAREQ 0x197 +#define RA_ELC_EVENT_CAN1_RXMB 0x198 +#define RA_ELC_EVENT_CAN0_MRAM_ERI 0x19B +#define RA_ELC_EVENT_CAN1_MRAM_ERI 0x19C +#define RA_ELC_EVENT_I3C0_RESPONSE 0x19D +#define RA_ELC_EVENT_I3C0_COMMAND 0x19E +#define RA_ELC_EVENT_I3C0_IBI 0x19F +#define RA_ELC_EVENT_I3C0_RX 0x1A0 +#define RA_ELC_EVENT_IICB0_RXI 0x1A0 +#define RA_ELC_EVENT_I3C0_TX 0x1A1 +#define RA_ELC_EVENT_IICB0_TXI 0x1A1 +#define RA_ELC_EVENT_I3C0_RCV_STATUS 0x1A2 +#define RA_ELC_EVENT_I3C0_HRESP 0x1A3 +#define RA_ELC_EVENT_I3C0_HCMD 0x1A4 +#define RA_ELC_EVENT_I3C0_HRX 0x1A5 +#define RA_ELC_EVENT_I3C0_HTX 0x1A6 +#define RA_ELC_EVENT_I3C0_TEND 0x1A7 +#define RA_ELC_EVENT_IICB0_TEI 0x1A7 +#define RA_ELC_EVENT_I3C0_EEI 0x1A8 +#define RA_ELC_EVENT_IICB0_ERI 0x1A8 +#define RA_ELC_EVENT_I3C0_STEV 0x1A9 +#define RA_ELC_EVENT_I3C0_MREFOVF 0x1AA +#define RA_ELC_EVENT_I3C0_MREFCPT 0x1AB +#define RA_ELC_EVENT_I3C0_AMEV 0x1AC +#define RA_ELC_EVENT_I3C0_WU 0x1AD +#define RA_ELC_EVENT_ADC0_SCAN_END 0x1AE +#define RA_ELC_EVENT_ADC0_SCAN_END_B 0x1AF +#define RA_ELC_EVENT_ADC0_WINDOW_A 0x1B0 +#define RA_ELC_EVENT_ADC0_WINDOW_B 0x1B1 +#define RA_ELC_EVENT_ADC0_COMPARE_MATCH 0x1B2 +#define RA_ELC_EVENT_ADC0_COMPARE_MISMATCH 0x1B3 +#define RA_ELC_EVENT_ADC1_SCAN_END 0x1B4 +#define RA_ELC_EVENT_ADC1_SCAN_END_B 0x1B5 +#define RA_ELC_EVENT_ADC1_WINDOW_A 0x1B6 +#define RA_ELC_EVENT_ADC1_WINDOW_B 0x1B7 +#define RA_ELC_EVENT_ADC1_COMPARE_MATCH 0x1B8 +#define RA_ELC_EVENT_ADC1_COMPARE_MISMATCH 0x1B9 +#define RA_ELC_EVENT_DOC_INT 0x1BA +#define RA_ELC_EVENT_RSIP_TADI 0x1BC +#define RA_ELC_EVENT_GLCDC_LINE_DETECT 0x1CD +#define RA_ELC_EVENT_GLCDC_UNDERFLOW_1 0x1CE +#define RA_ELC_EVENT_GLCDC_UNDERFLOW_2 0x1CF +#define RA_ELC_EVENT_DRW_INT 0x1D0 +#define RA_ELC_EVENT_MIPIDSI_SEQ0 0x1D3 +#define RA_ELC_EVENT_MIPIDSI_SEQ1 0x1D4 +#define RA_ELC_EVENT_MIPIDSI_VIN1 0x1D5 +#define RA_ELC_EVENT_MIPIDSI_RCV 0x1D6 +#define RA_ELC_EVENT_MIPIDSI_FERR 0x1D7 +#define RA_ELC_EVENT_MIPIDSI_PPI 0x1D8 +#define RA_ELC_EVENT_CEU_CEUI 0x1DA + +/* Possible peripherals to be linked to event signals */ +#define RA_ELC_PERIPHERAL_GPT_A 0 +#define RA_ELC_PERIPHERAL_GPT_B 1 +#define RA_ELC_PERIPHERAL_GPT_C 2 +#define RA_ELC_PERIPHERAL_GPT_D 3 +#define RA_ELC_PERIPHERAL_GPT_E 4 +#define RA_ELC_PERIPHERAL_GPT_F 5 +#define RA_ELC_PERIPHERAL_GPT_G 6 +#define RA_ELC_PERIPHERAL_GPT_H 7 +#define RA_ELC_PERIPHERAL_ADC0 8 +#define RA_ELC_PERIPHERAL_ADC0_B 9 +#define RA_ELC_PERIPHERAL_ADC1 10 +#define RA_ELC_PERIPHERAL_ADC1_B 11 +#define RA_ELC_PERIPHERAL_DAC0 12 +#define RA_ELC_PERIPHERAL_DAC1 13 +#define RA_ELC_PERIPHERAL_IOPORT1 14 +#define RA_ELC_PERIPHERAL_IOPORT2 15 +#define RA_ELC_PERIPHERAL_IOPORT3 16 +#define RA_ELC_PERIPHERAL_IOPORT4 17 +#define RA_ELC_PERIPHERAL_I3C 30 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA8D1_ELC_H_ */ diff --git a/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra8m1-elc.h b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra8m1-elc.h new file mode 100644 index 00000000000..b23916b3c9b --- /dev/null +++ b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra8m1-elc.h @@ -0,0 +1,354 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA8M1_ELC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA8M1_ELC_H_ + +/* Sources of event signals to be linked to other peripherals or the CPU */ +#define RA_ELC_EVENT_NONE 0x0 +#define RA_ELC_EVENT_ICU_IRQ0 0x001 +#define RA_ELC_EVENT_ICU_IRQ1 0x002 +#define RA_ELC_EVENT_ICU_IRQ2 0x003 +#define RA_ELC_EVENT_ICU_IRQ3 0x004 +#define RA_ELC_EVENT_ICU_IRQ4 0x005 +#define RA_ELC_EVENT_ICU_IRQ5 0x006 +#define RA_ELC_EVENT_ICU_IRQ6 0x007 +#define RA_ELC_EVENT_ICU_IRQ7 0x008 +#define RA_ELC_EVENT_ICU_IRQ8 0x009 +#define RA_ELC_EVENT_ICU_IRQ9 0x00A +#define RA_ELC_EVENT_ICU_IRQ10 0x00B +#define RA_ELC_EVENT_ICU_IRQ11 0x00C +#define RA_ELC_EVENT_ICU_IRQ12 0x00D +#define RA_ELC_EVENT_ICU_IRQ13 0x00E +#define RA_ELC_EVENT_ICU_IRQ14 0x00F +#define RA_ELC_EVENT_ICU_IRQ15 0x010 +#define RA_ELC_EVENT_DMAC0_INT 0x011 +#define RA_ELC_EVENT_DMAC1_INT 0x012 +#define RA_ELC_EVENT_DMAC2_INT 0x013 +#define RA_ELC_EVENT_DMAC3_INT 0x014 +#define RA_ELC_EVENT_DMAC4_INT 0x015 +#define RA_ELC_EVENT_DMAC5_INT 0x016 +#define RA_ELC_EVENT_DMAC6_INT 0x017 +#define RA_ELC_EVENT_DMAC7_INT 0x018 +#define RA_ELC_EVENT_DTC_END 0x021 +#define RA_ELC_EVENT_DTC_COMPLETE 0x022 +#define RA_ELC_EVENT_DMA_TRANSERR 0x027 +#define RA_ELC_EVENT_DBG_CTIIRQ0 0x029 +#define RA_ELC_EVENT_DBG_CTIIRQ1 0x02A +#define RA_ELC_EVENT_DBG_JBRXI 0x02B +#define RA_ELC_EVENT_FCU_FIFERR 0x030 +#define RA_ELC_EVENT_FCU_FRDYI 0x031 +#define RA_ELC_EVENT_LVD_LVD1 0x038 +#define RA_ELC_EVENT_LVD_LVD2 0x039 +#define RA_ELC_EVENT_VBATT_TADI 0x03D +#define RA_ELC_EVENT_CGC_MOSC_STOP 0x03E +#define RA_ELC_EVENT_ULPT0_INT 0x040 +#define RA_ELC_EVENT_ULPT0_COMPARE_A 0x041 +#define RA_ELC_EVENT_ULPT0_COMPARE_B 0x042 +#define RA_ELC_EVENT_ULPT1_INT 0x043 +#define RA_ELC_EVENT_ULPT1_COMPARE_A 0x044 +#define RA_ELC_EVENT_ULPT1_COMPARE_B 0x045 +#define RA_ELC_EVENT_AGT0_INT 0x046 +#define RA_ELC_EVENT_AGT0_COMPARE_A 0x047 +#define RA_ELC_EVENT_AGT0_COMPARE_B 0x048 +#define RA_ELC_EVENT_AGT1_INT 0x049 +#define RA_ELC_EVENT_AGT1_COMPARE_A 0x04A +#define RA_ELC_EVENT_AGT1_COMPARE_B 0x04B +#define RA_ELC_EVENT_IWDT_UNDERFLOW 0x052 +#define RA_ELC_EVENT_WDT0_UNDERFLOW 0x053 +#define RA_ELC_EVENT_RTC_ALARM 0x055 +#define RA_ELC_EVENT_RTC_PERIOD 0x056 +#define RA_ELC_EVENT_RTC_CARRY 0x057 +#define RA_ELC_EVENT_USBFS_FIFO_0 0x058 +#define RA_ELC_EVENT_USBFS_FIFO_1 0x059 +#define RA_ELC_EVENT_USBFS_INT 0x05A +#define RA_ELC_EVENT_USBFS_RESUME 0x05B +#define RA_ELC_EVENT_IIC0_RXI 0x05C +#define RA_ELC_EVENT_IIC0_TXI 0x05D +#define RA_ELC_EVENT_IIC0_TEI 0x05E +#define RA_ELC_EVENT_IIC0_ERI 0x05F +#define RA_ELC_EVENT_IIC0_WUI 0x060 +#define RA_ELC_EVENT_IIC1_RXI 0x061 +#define RA_ELC_EVENT_IIC1_TXI 0x062 +#define RA_ELC_EVENT_IIC1_TEI 0x063 +#define RA_ELC_EVENT_IIC1_ERI 0x064 +#define RA_ELC_EVENT_SDHIMMC0_ACCS 0x06B +#define RA_ELC_EVENT_SDHIMMC0_SDIO 0x06C +#define RA_ELC_EVENT_SDHIMMC0_CARD 0x06D +#define RA_ELC_EVENT_SDHIMMC0_DMA_REQ 0x06E +#define RA_ELC_EVENT_SDHIMMC1_ACCS 0x06F +#define RA_ELC_EVENT_SDHIMMC1_SDIO 0x070 +#define RA_ELC_EVENT_SDHIMMC1_CARD 0x071 +#define RA_ELC_EVENT_SDHIMMC1_DMA_REQ 0x072 +#define RA_ELC_EVENT_SSI0_TXI 0x073 +#define RA_ELC_EVENT_SSI0_RXI 0x074 +#define RA_ELC_EVENT_SSI0_INT 0x076 +#define RA_ELC_EVENT_SSI1_TXI_RXI 0x079 +#define RA_ELC_EVENT_SSI1_TXI 0x079 +#define RA_ELC_EVENT_SSI1_RXI 0x079 +#define RA_ELC_EVENT_SSI1_INT 0x07A +#define RA_ELC_EVENT_ACMPHS0_INT 0x07B +#define RA_ELC_EVENT_ACMPHS1_INT 0x07C +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0 0x083 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1 0x084 +#define RA_ELC_EVENT_IOPORT_EVENT_1 0x088 +#define RA_ELC_EVENT_IOPORT_EVENT_2 0x089 +#define RA_ELC_EVENT_IOPORT_EVENT_3 0x08A +#define RA_ELC_EVENT_IOPORT_EVENT_4 0x08B +#define RA_ELC_EVENT_CAC_FREQUENCY_ERROR 0x08C +#define RA_ELC_EVENT_CAC_MEASUREMENT_END 0x08D +#define RA_ELC_EVENT_CAC_OVERFLOW 0x08E +#define RA_ELC_EVENT_POEG0_EVENT 0x08F +#define RA_ELC_EVENT_POEG1_EVENT 0x090 +#define RA_ELC_EVENT_POEG2_EVENT 0x091 +#define RA_ELC_EVENT_POEG3_EVENT 0x092 +#define RA_ELC_EVENT_OPS_UVW_EDGE 0x0A0 +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_A 0x0A1 +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_B 0x0A2 +#define RA_ELC_EVENT_GPT0_COMPARE_C 0x0A3 +#define RA_ELC_EVENT_GPT0_COMPARE_D 0x0A4 +#define RA_ELC_EVENT_GPT0_COMPARE_E 0x0A5 +#define RA_ELC_EVENT_GPT0_COMPARE_F 0x0A6 +#define RA_ELC_EVENT_GPT0_COUNTER_OVERFLOW 0x0A7 +#define RA_ELC_EVENT_GPT0_COUNTER_UNDERFLOW 0x0A8 +#define RA_ELC_EVENT_GPT0_PC 0x0A9 +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_A 0x0AA +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_B 0x0AB +#define RA_ELC_EVENT_GPT1_COMPARE_C 0x0AC +#define RA_ELC_EVENT_GPT1_COMPARE_D 0x0AD +#define RA_ELC_EVENT_GPT1_COMPARE_E 0x0AE +#define RA_ELC_EVENT_GPT1_COMPARE_F 0x0AF +#define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x0B0 +#define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x0B1 +#define RA_ELC_EVENT_GPT1_PC 0x0B2 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_A 0x0B3 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_B 0x0B4 +#define RA_ELC_EVENT_GPT2_COMPARE_C 0x0B5 +#define RA_ELC_EVENT_GPT2_COMPARE_D 0x0B6 +#define RA_ELC_EVENT_GPT2_COMPARE_E 0x0B7 +#define RA_ELC_EVENT_GPT2_COMPARE_F 0x0B8 +#define RA_ELC_EVENT_GPT2_COUNTER_OVERFLOW 0x0B9 +#define RA_ELC_EVENT_GPT2_COUNTER_UNDERFLOW 0x0BA +#define RA_ELC_EVENT_GPT2_PC 0x0BB +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_A 0x0BC +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_B 0x0BD +#define RA_ELC_EVENT_GPT3_COMPARE_C 0x0BE +#define RA_ELC_EVENT_GPT3_COMPARE_D 0x0BF +#define RA_ELC_EVENT_GPT3_COMPARE_E 0x0C0 +#define RA_ELC_EVENT_GPT3_COMPARE_F 0x0C1 +#define RA_ELC_EVENT_GPT3_COUNTER_OVERFLOW 0x0C2 +#define RA_ELC_EVENT_GPT3_COUNTER_UNDERFLOW 0x0C3 +#define RA_ELC_EVENT_GPT3_PC 0x0C4 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_A 0x0C5 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_B 0x0C6 +#define RA_ELC_EVENT_GPT4_COMPARE_C 0x0C7 +#define RA_ELC_EVENT_GPT4_COMPARE_D 0x0C8 +#define RA_ELC_EVENT_GPT4_COMPARE_E 0x0C9 +#define RA_ELC_EVENT_GPT4_COMPARE_F 0x0CA +#define RA_ELC_EVENT_GPT4_COUNTER_OVERFLOW 0x0CB +#define RA_ELC_EVENT_GPT4_COUNTER_UNDERFLOW 0x0CC +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_A 0x0CE +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_B 0x0CF +#define RA_ELC_EVENT_GPT5_COMPARE_C 0x0D0 +#define RA_ELC_EVENT_GPT5_COMPARE_D 0x0D1 +#define RA_ELC_EVENT_GPT5_COMPARE_E 0x0D2 +#define RA_ELC_EVENT_GPT5_COMPARE_F 0x0D3 +#define RA_ELC_EVENT_GPT5_COUNTER_OVERFLOW 0x0D4 +#define RA_ELC_EVENT_GPT5_COUNTER_UNDERFLOW 0x0D5 +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_A 0x0D7 +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_B 0x0D8 +#define RA_ELC_EVENT_GPT6_COMPARE_C 0x0D9 +#define RA_ELC_EVENT_GPT6_COMPARE_D 0x0DA +#define RA_ELC_EVENT_GPT6_COMPARE_E 0x0DB +#define RA_ELC_EVENT_GPT6_COMPARE_F 0x0DC +#define RA_ELC_EVENT_GPT6_COUNTER_OVERFLOW 0x0DD +#define RA_ELC_EVENT_GPT6_COUNTER_UNDERFLOW 0x0DE +#define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_A 0x0E0 +#define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_B 0x0E1 +#define RA_ELC_EVENT_GPT7_COMPARE_C 0x0E2 +#define RA_ELC_EVENT_GPT7_COMPARE_D 0x0E3 +#define RA_ELC_EVENT_GPT7_COMPARE_E 0x0E4 +#define RA_ELC_EVENT_GPT7_COMPARE_F 0x0E5 +#define RA_ELC_EVENT_GPT7_COUNTER_OVERFLOW 0x0E6 +#define RA_ELC_EVENT_GPT7_COUNTER_UNDERFLOW 0x0E7 +#define RA_ELC_EVENT_GPT8_CAPTURE_COMPARE_A 0x0E9 +#define RA_ELC_EVENT_GPT8_CAPTURE_COMPARE_B 0x0EA +#define RA_ELC_EVENT_GPT8_COMPARE_C 0x0EB +#define RA_ELC_EVENT_GPT8_COMPARE_D 0x0EC +#define RA_ELC_EVENT_GPT8_COMPARE_E 0x0ED +#define RA_ELC_EVENT_GPT8_COMPARE_F 0x0EE +#define RA_ELC_EVENT_GPT8_COUNTER_OVERFLOW 0x0EF +#define RA_ELC_EVENT_GPT8_COUNTER_UNDERFLOW 0x0F0 +#define RA_ELC_EVENT_GPT8_PC 0x0F1 +#define RA_ELC_EVENT_GPT9_CAPTURE_COMPARE_A 0x0F2 +#define RA_ELC_EVENT_GPT9_CAPTURE_COMPARE_B 0x0F3 +#define RA_ELC_EVENT_GPT9_COMPARE_C 0x0F4 +#define RA_ELC_EVENT_GPT9_COMPARE_D 0x0F5 +#define RA_ELC_EVENT_GPT9_COMPARE_E 0x0F6 +#define RA_ELC_EVENT_GPT9_COMPARE_F 0x0F7 +#define RA_ELC_EVENT_GPT9_COUNTER_OVERFLOW 0x0F8 +#define RA_ELC_EVENT_GPT9_COUNTER_UNDERFLOW 0x0F9 +#define RA_ELC_EVENT_GPT9_PC 0x0FA +#define RA_ELC_EVENT_GPT10_CAPTURE_COMPARE_A 0x0FB +#define RA_ELC_EVENT_GPT10_CAPTURE_COMPARE_B 0x0FC +#define RA_ELC_EVENT_GPT10_COMPARE_C 0x0FD +#define RA_ELC_EVENT_GPT10_COMPARE_D 0x0FE +#define RA_ELC_EVENT_GPT10_COMPARE_E 0x0FF +#define RA_ELC_EVENT_GPT10_COMPARE_F 0x100 +#define RA_ELC_EVENT_GPT10_COUNTER_OVERFLOW 0x101 +#define RA_ELC_EVENT_GPT10_COUNTER_UNDERFLOW 0x102 +#define RA_ELC_EVENT_GPT10_PC 0x103 +#define RA_ELC_EVENT_GPT11_CAPTURE_COMPARE_A 0x104 +#define RA_ELC_EVENT_GPT11_CAPTURE_COMPARE_B 0x105 +#define RA_ELC_EVENT_GPT11_COMPARE_C 0x106 +#define RA_ELC_EVENT_GPT11_COMPARE_D 0x107 +#define RA_ELC_EVENT_GPT11_COMPARE_E 0x108 +#define RA_ELC_EVENT_GPT11_COMPARE_F 0x109 +#define RA_ELC_EVENT_GPT11_COUNTER_OVERFLOW 0x10A +#define RA_ELC_EVENT_GPT11_COUNTER_UNDERFLOW 0x10B +#define RA_ELC_EVENT_GPT12_CAPTURE_COMPARE_A 0x10D +#define RA_ELC_EVENT_GPT12_CAPTURE_COMPARE_B 0x10E +#define RA_ELC_EVENT_GPT12_COMPARE_C 0x10F +#define RA_ELC_EVENT_GPT12_COMPARE_D 0x110 +#define RA_ELC_EVENT_GPT12_COMPARE_E 0x111 +#define RA_ELC_EVENT_GPT12_COMPARE_F 0x112 +#define RA_ELC_EVENT_GPT12_COUNTER_OVERFLOW 0x113 +#define RA_ELC_EVENT_GPT12_COUNTER_UNDERFLOW 0x114 +#define RA_ELC_EVENT_GPT13_CAPTURE_COMPARE_A 0x116 +#define RA_ELC_EVENT_GPT13_CAPTURE_COMPARE_B 0x117 +#define RA_ELC_EVENT_GPT13_COMPARE_C 0x118 +#define RA_ELC_EVENT_GPT13_COMPARE_D 0x119 +#define RA_ELC_EVENT_GPT13_COMPARE_E 0x11A +#define RA_ELC_EVENT_GPT13_COMPARE_F 0x11B +#define RA_ELC_EVENT_GPT13_COUNTER_OVERFLOW 0x11C +#define RA_ELC_EVENT_GPT13_COUNTER_UNDERFLOW 0x11D +#define RA_ELC_EVENT_EDMAC0_EINT 0x120 +#define RA_ELC_EVENT_USBHS_FIFO_0 0x121 +#define RA_ELC_EVENT_USBHS_FIFO_1 0x122 +#define RA_ELC_EVENT_USBHS_USB_INT_RESUME 0x123 +#define RA_ELC_EVENT_SCI0_RXI 0x124 +#define RA_ELC_EVENT_SCI0_TXI 0x125 +#define RA_ELC_EVENT_SCI0_TEI 0x126 +#define RA_ELC_EVENT_SCI0_ERI 0x127 +#define RA_ELC_EVENT_SCI0_AED 0x128 +#define RA_ELC_EVENT_SCI0_BFD 0x129 +#define RA_ELC_EVENT_SCI0_AM 0x12A +#define RA_ELC_EVENT_SCI1_RXI 0x12B +#define RA_ELC_EVENT_SCI1_TXI 0x12C +#define RA_ELC_EVENT_SCI1_TEI 0x12D +#define RA_ELC_EVENT_SCI1_ERI 0x12E +#define RA_ELC_EVENT_SCI1_AED 0x12F +#define RA_ELC_EVENT_SCI1_BFD 0x130 +#define RA_ELC_EVENT_SCI1_AM 0x131 +#define RA_ELC_EVENT_SCI2_RXI 0x132 +#define RA_ELC_EVENT_SCI2_TXI 0x133 +#define RA_ELC_EVENT_SCI2_TEI 0x134 +#define RA_ELC_EVENT_SCI2_ERI 0x135 +#define RA_ELC_EVENT_SCI2_AM 0x138 +#define RA_ELC_EVENT_SCI3_RXI 0x139 +#define RA_ELC_EVENT_SCI3_TXI 0x13A +#define RA_ELC_EVENT_SCI3_TEI 0x13B +#define RA_ELC_EVENT_SCI3_ERI 0x13C +#define RA_ELC_EVENT_SCI3_AM 0x13F +#define RA_ELC_EVENT_SCI4_RXI 0x140 +#define RA_ELC_EVENT_SCI4_TXI 0x141 +#define RA_ELC_EVENT_SCI4_TEI 0x142 +#define RA_ELC_EVENT_SCI4_ERI 0x143 +#define RA_ELC_EVENT_SCI4_AM 0x146 +#define RA_ELC_EVENT_SCI9_RXI 0x163 +#define RA_ELC_EVENT_SCI9_TXI 0x164 +#define RA_ELC_EVENT_SCI9_TEI 0x165 +#define RA_ELC_EVENT_SCI9_ERI 0x166 +#define RA_ELC_EVENT_SCI9_AM 0x169 +#define RA_ELC_EVENT_SPI0_RXI 0x178 +#define RA_ELC_EVENT_SPI0_TXI 0x179 +#define RA_ELC_EVENT_SPI0_IDLE 0x17A +#define RA_ELC_EVENT_SPI0_ERI 0x17B +#define RA_ELC_EVENT_SPI0_TEI 0x17C +#define RA_ELC_EVENT_SPI1_RXI 0x17D +#define RA_ELC_EVENT_SPI1_TXI 0x17E +#define RA_ELC_EVENT_SPI1_IDLE 0x17F +#define RA_ELC_EVENT_SPI1_ERI 0x180 +#define RA_ELC_EVENT_SPI1_TEI 0x181 +#define RA_ELC_EVENT_XSPI_ERR 0x182 +#define RA_ELC_EVENT_XSPI_CMP 0x183 +#define RA_ELC_EVENT_CAN_RXF 0x185 +#define RA_ELC_EVENT_CAN_GLERR 0x186 +#define RA_ELC_EVENT_CAN0_DMAREQ0 0x187 +#define RA_ELC_EVENT_CAN0_DMAREQ1 0x188 +#define RA_ELC_EVENT_CAN1_DMAREQ0 0x18B +#define RA_ELC_EVENT_CAN1_DMAREQ1 0x18C +#define RA_ELC_EVENT_CAN0_TX 0x18F +#define RA_ELC_EVENT_CAN0_CHERR 0x190 +#define RA_ELC_EVENT_CAN0_COMFRX 0x191 +#define RA_ELC_EVENT_CAN0_CF_DMAREQ 0x192 +#define RA_ELC_EVENT_CAN0_RXMB 0x193 +#define RA_ELC_EVENT_CAN1_TX 0x194 +#define RA_ELC_EVENT_CAN1_CHERR 0x195 +#define RA_ELC_EVENT_CAN1_COMFRX 0x196 +#define RA_ELC_EVENT_CAN1_CF_DMAREQ 0x197 +#define RA_ELC_EVENT_CAN1_RXMB 0x198 +#define RA_ELC_EVENT_CAN0_MRAM_ERI 0x19B +#define RA_ELC_EVENT_CAN1_MRAM_ERI 0x19C +#define RA_ELC_EVENT_I3C0_RESPONSE 0x19D +#define RA_ELC_EVENT_I3C0_COMMAND 0x19E +#define RA_ELC_EVENT_I3C0_IBI 0x19F +#define RA_ELC_EVENT_I3C0_RX 0x1A0 +#define RA_ELC_EVENT_IICB0_RXI 0x1A0 +#define RA_ELC_EVENT_I3C0_TX 0x1A1 +#define RA_ELC_EVENT_IICB0_TXI 0x1A1 +#define RA_ELC_EVENT_I3C0_RCV_STATUS 0x1A2 +#define RA_ELC_EVENT_I3C0_HRESP 0x1A3 +#define RA_ELC_EVENT_I3C0_HCMD 0x1A4 +#define RA_ELC_EVENT_I3C0_HRX 0x1A5 +#define RA_ELC_EVENT_I3C0_HTX 0x1A6 +#define RA_ELC_EVENT_I3C0_TEND 0x1A7 +#define RA_ELC_EVENT_IICB0_TEI 0x1A7 +#define RA_ELC_EVENT_I3C0_EEI 0x1A8 +#define RA_ELC_EVENT_IICB0_ERI 0x1A8 +#define RA_ELC_EVENT_I3C0_STEV 0x1A9 +#define RA_ELC_EVENT_I3C0_MREFOVF 0x1AA +#define RA_ELC_EVENT_I3C0_MREFCPT 0x1AB +#define RA_ELC_EVENT_I3C0_AMEV 0x1AC +#define RA_ELC_EVENT_I3C0_WU 0x1AD +#define RA_ELC_EVENT_ADC0_SCAN_END 0x1AE +#define RA_ELC_EVENT_ADC0_SCAN_END_B 0x1AF +#define RA_ELC_EVENT_ADC0_WINDOW_A 0x1B0 +#define RA_ELC_EVENT_ADC0_WINDOW_B 0x1B1 +#define RA_ELC_EVENT_ADC0_COMPARE_MATCH 0x1B2 +#define RA_ELC_EVENT_ADC0_COMPARE_MISMATCH 0x1B3 +#define RA_ELC_EVENT_ADC1_SCAN_END 0x1B4 +#define RA_ELC_EVENT_ADC1_SCAN_END_B 0x1B5 +#define RA_ELC_EVENT_ADC1_WINDOW_A 0x1B6 +#define RA_ELC_EVENT_ADC1_WINDOW_B 0x1B7 +#define RA_ELC_EVENT_ADC1_COMPARE_MATCH 0x1B8 +#define RA_ELC_EVENT_ADC1_COMPARE_MISMATCH 0x1B9 +#define RA_ELC_EVENT_DOC_INT 0x1BA +#define RA_ELC_EVENT_RSIP_TADI 0x1BC +#define RA_ELC_EVENT_CEU_CEUI 0x1DA + +/* Possible peripherals to be linked to event signals */ +#define RA_ELC_PERIPHERAL_GPT_A 0 +#define RA_ELC_PERIPHERAL_GPT_B 1 +#define RA_ELC_PERIPHERAL_GPT_C 2 +#define RA_ELC_PERIPHERAL_GPT_D 3 +#define RA_ELC_PERIPHERAL_GPT_E 4 +#define RA_ELC_PERIPHERAL_GPT_F 5 +#define RA_ELC_PERIPHERAL_GPT_G 6 +#define RA_ELC_PERIPHERAL_GPT_H 7 +#define RA_ELC_PERIPHERAL_ADC0 8 +#define RA_ELC_PERIPHERAL_ADC0_B 9 +#define RA_ELC_PERIPHERAL_ADC1 10 +#define RA_ELC_PERIPHERAL_ADC1_B 11 +#define RA_ELC_PERIPHERAL_DAC0 12 +#define RA_ELC_PERIPHERAL_DAC1 13 +#define RA_ELC_PERIPHERAL_IOPORT1 14 +#define RA_ELC_PERIPHERAL_IOPORT2 15 +#define RA_ELC_PERIPHERAL_IOPORT3 16 +#define RA_ELC_PERIPHERAL_IOPORT4 17 +#define RA_ELC_PERIPHERAL_I3C 30 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA8M1_ELC_H_ */ diff --git a/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra8t1-elc.h b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra8t1-elc.h new file mode 100644 index 00000000000..89efee0aff5 --- /dev/null +++ b/include/zephyr/dt-bindings/misc/renesas/ra-elc/ra8t1-elc.h @@ -0,0 +1,337 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA8T1_ELC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA8T1_ELC_H_ + +/* Sources of event signals to be linked to other peripherals or the CPU */ +#define RA_ELC_EVENT_NONE 0x0 +#define RA_ELC_EVENT_ICU_IRQ0 0x001 +#define RA_ELC_EVENT_ICU_IRQ1 0x002 +#define RA_ELC_EVENT_ICU_IRQ2 0x003 +#define RA_ELC_EVENT_ICU_IRQ3 0x004 +#define RA_ELC_EVENT_ICU_IRQ4 0x005 +#define RA_ELC_EVENT_ICU_IRQ5 0x006 +#define RA_ELC_EVENT_ICU_IRQ6 0x007 +#define RA_ELC_EVENT_ICU_IRQ7 0x008 +#define RA_ELC_EVENT_ICU_IRQ8 0x009 +#define RA_ELC_EVENT_ICU_IRQ9 0x00A +#define RA_ELC_EVENT_ICU_IRQ10 0x00B +#define RA_ELC_EVENT_ICU_IRQ11 0x00C +#define RA_ELC_EVENT_ICU_IRQ12 0x00D +#define RA_ELC_EVENT_ICU_IRQ13 0x00E +#define RA_ELC_EVENT_ICU_IRQ14 0x00F +#define RA_ELC_EVENT_ICU_IRQ15 0x010 +#define RA_ELC_EVENT_DMAC0_INT 0x011 +#define RA_ELC_EVENT_DMAC1_INT 0x012 +#define RA_ELC_EVENT_DMAC2_INT 0x013 +#define RA_ELC_EVENT_DMAC3_INT 0x014 +#define RA_ELC_EVENT_DMAC4_INT 0x015 +#define RA_ELC_EVENT_DMAC5_INT 0x016 +#define RA_ELC_EVENT_DMAC6_INT 0x017 +#define RA_ELC_EVENT_DMAC7_INT 0x018 +#define RA_ELC_EVENT_DTC_END 0x021 +#define RA_ELC_EVENT_DTC_COMPLETE 0x022 +#define RA_ELC_EVENT_DMA_TRANSERR 0x027 +#define RA_ELC_EVENT_DBG_CTIIRQ0 0x029 +#define RA_ELC_EVENT_DBG_CTIIRQ1 0x02A +#define RA_ELC_EVENT_DBG_JBRXI 0x02B +#define RA_ELC_EVENT_FCU_FIFERR 0x030 +#define RA_ELC_EVENT_FCU_FRDYI 0x031 +#define RA_ELC_EVENT_LVD_LVD1 0x038 +#define RA_ELC_EVENT_LVD_LVD2 0x039 +#define RA_ELC_EVENT_CGC_MOSC_STOP 0x03E +#define RA_ELC_EVENT_ULPT0_INT 0x040 +#define RA_ELC_EVENT_ULPT0_COMPARE_A 0x041 +#define RA_ELC_EVENT_ULPT0_COMPARE_B 0x042 +#define RA_ELC_EVENT_ULPT1_INT 0x043 +#define RA_ELC_EVENT_ULPT1_COMPARE_A 0x044 +#define RA_ELC_EVENT_ULPT1_COMPARE_B 0x045 +#define RA_ELC_EVENT_AGT0_INT 0x046 +#define RA_ELC_EVENT_AGT0_COMPARE_A 0x047 +#define RA_ELC_EVENT_AGT0_COMPARE_B 0x048 +#define RA_ELC_EVENT_AGT1_INT 0x049 +#define RA_ELC_EVENT_AGT1_COMPARE_A 0x04A +#define RA_ELC_EVENT_AGT1_COMPARE_B 0x04B +#define RA_ELC_EVENT_IWDT_UNDERFLOW 0x052 +#define RA_ELC_EVENT_WDT0_UNDERFLOW 0x053 +#define RA_ELC_EVENT_USBFS_FIFO_0 0x058 +#define RA_ELC_EVENT_USBFS_FIFO_1 0x059 +#define RA_ELC_EVENT_USBFS_INT 0x05A +#define RA_ELC_EVENT_USBFS_RESUME 0x05B +#define RA_ELC_EVENT_IIC0_RXI 0x05C +#define RA_ELC_EVENT_IIC0_TXI 0x05D +#define RA_ELC_EVENT_IIC0_TEI 0x05E +#define RA_ELC_EVENT_IIC0_ERI 0x05F +#define RA_ELC_EVENT_IIC0_WUI 0x060 +#define RA_ELC_EVENT_IIC1_RXI 0x061 +#define RA_ELC_EVENT_IIC1_TXI 0x062 +#define RA_ELC_EVENT_IIC1_TEI 0x063 +#define RA_ELC_EVENT_IIC1_ERI 0x064 +#define RA_ELC_EVENT_SDHIMMC0_ACCS 0x06B +#define RA_ELC_EVENT_SDHIMMC0_SDIO 0x06C +#define RA_ELC_EVENT_SDHIMMC0_CARD 0x06D +#define RA_ELC_EVENT_SDHIMMC0_DMA_REQ 0x06E +#define RA_ELC_EVENT_SDHIMMC1_ACCS 0x06F +#define RA_ELC_EVENT_SDHIMMC1_SDIO 0x070 +#define RA_ELC_EVENT_SDHIMMC1_CARD 0x071 +#define RA_ELC_EVENT_SDHIMMC1_DMA_REQ 0x072 +#define RA_ELC_EVENT_ACMPHS0_INT 0x07B +#define RA_ELC_EVENT_ACMPHS1_INT 0x07C +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0 0x083 +#define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1 0x084 +#define RA_ELC_EVENT_IOPORT_EVENT_1 0x088 +#define RA_ELC_EVENT_IOPORT_EVENT_2 0x089 +#define RA_ELC_EVENT_IOPORT_EVENT_3 0x08A +#define RA_ELC_EVENT_IOPORT_EVENT_4 0x08B +#define RA_ELC_EVENT_CAC_FREQUENCY_ERROR 0x08C +#define RA_ELC_EVENT_CAC_MEASUREMENT_END 0x08D +#define RA_ELC_EVENT_CAC_OVERFLOW 0x08E +#define RA_ELC_EVENT_POEG0_EVENT 0x08F +#define RA_ELC_EVENT_POEG1_EVENT 0x090 +#define RA_ELC_EVENT_POEG2_EVENT 0x091 +#define RA_ELC_EVENT_POEG3_EVENT 0x092 +#define RA_ELC_EVENT_OPS_UVW_EDGE 0x0A0 +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_A 0x0A1 +#define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_B 0x0A2 +#define RA_ELC_EVENT_GPT0_COMPARE_C 0x0A3 +#define RA_ELC_EVENT_GPT0_COMPARE_D 0x0A4 +#define RA_ELC_EVENT_GPT0_COMPARE_E 0x0A5 +#define RA_ELC_EVENT_GPT0_COMPARE_F 0x0A6 +#define RA_ELC_EVENT_GPT0_COUNTER_OVERFLOW 0x0A7 +#define RA_ELC_EVENT_GPT0_COUNTER_UNDERFLOW 0x0A8 +#define RA_ELC_EVENT_GPT0_PC 0x0A9 +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_A 0x0AA +#define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_B 0x0AB +#define RA_ELC_EVENT_GPT1_COMPARE_C 0x0AC +#define RA_ELC_EVENT_GPT1_COMPARE_D 0x0AD +#define RA_ELC_EVENT_GPT1_COMPARE_E 0x0AE +#define RA_ELC_EVENT_GPT1_COMPARE_F 0x0AF +#define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x0B0 +#define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x0B1 +#define RA_ELC_EVENT_GPT1_PC 0x0B2 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_A 0x0B3 +#define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_B 0x0B4 +#define RA_ELC_EVENT_GPT2_COMPARE_C 0x0B5 +#define RA_ELC_EVENT_GPT2_COMPARE_D 0x0B6 +#define RA_ELC_EVENT_GPT2_COMPARE_E 0x0B7 +#define RA_ELC_EVENT_GPT2_COMPARE_F 0x0B8 +#define RA_ELC_EVENT_GPT2_COUNTER_OVERFLOW 0x0B9 +#define RA_ELC_EVENT_GPT2_COUNTER_UNDERFLOW 0x0BA +#define RA_ELC_EVENT_GPT2_PC 0x0BB +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_A 0x0BC +#define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_B 0x0BD +#define RA_ELC_EVENT_GPT3_COMPARE_C 0x0BE +#define RA_ELC_EVENT_GPT3_COMPARE_D 0x0BF +#define RA_ELC_EVENT_GPT3_COMPARE_E 0x0C0 +#define RA_ELC_EVENT_GPT3_COMPARE_F 0x0C1 +#define RA_ELC_EVENT_GPT3_COUNTER_OVERFLOW 0x0C2 +#define RA_ELC_EVENT_GPT3_COUNTER_UNDERFLOW 0x0C3 +#define RA_ELC_EVENT_GPT3_PC 0x0C4 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_A 0x0C5 +#define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_B 0x0C6 +#define RA_ELC_EVENT_GPT4_COMPARE_C 0x0C7 +#define RA_ELC_EVENT_GPT4_COMPARE_D 0x0C8 +#define RA_ELC_EVENT_GPT4_COMPARE_E 0x0C9 +#define RA_ELC_EVENT_GPT4_COMPARE_F 0x0CA +#define RA_ELC_EVENT_GPT4_COUNTER_OVERFLOW 0x0CB +#define RA_ELC_EVENT_GPT4_COUNTER_UNDERFLOW 0x0CC +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_A 0x0CE +#define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_B 0x0CF +#define RA_ELC_EVENT_GPT5_COMPARE_C 0x0D0 +#define RA_ELC_EVENT_GPT5_COMPARE_D 0x0D1 +#define RA_ELC_EVENT_GPT5_COMPARE_E 0x0D2 +#define RA_ELC_EVENT_GPT5_COMPARE_F 0x0D3 +#define RA_ELC_EVENT_GPT5_COUNTER_OVERFLOW 0x0D4 +#define RA_ELC_EVENT_GPT5_COUNTER_UNDERFLOW 0x0D5 +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_A 0x0D7 +#define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_B 0x0D8 +#define RA_ELC_EVENT_GPT6_COMPARE_C 0x0D9 +#define RA_ELC_EVENT_GPT6_COMPARE_D 0x0DA +#define RA_ELC_EVENT_GPT6_COMPARE_E 0x0DB +#define RA_ELC_EVENT_GPT6_COMPARE_F 0x0DC +#define RA_ELC_EVENT_GPT6_COUNTER_OVERFLOW 0x0DD +#define RA_ELC_EVENT_GPT6_COUNTER_UNDERFLOW 0x0DE +#define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_A 0x0E0 +#define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_B 0x0E1 +#define RA_ELC_EVENT_GPT7_COMPARE_C 0x0E2 +#define RA_ELC_EVENT_GPT7_COMPARE_D 0x0E3 +#define RA_ELC_EVENT_GPT7_COMPARE_E 0x0E4 +#define RA_ELC_EVENT_GPT7_COMPARE_F 0x0E5 +#define RA_ELC_EVENT_GPT7_COUNTER_OVERFLOW 0x0E6 +#define RA_ELC_EVENT_GPT7_COUNTER_UNDERFLOW 0x0E7 +#define RA_ELC_EVENT_GPT8_CAPTURE_COMPARE_A 0x0E9 +#define RA_ELC_EVENT_GPT8_CAPTURE_COMPARE_B 0x0EA +#define RA_ELC_EVENT_GPT8_COMPARE_C 0x0EB +#define RA_ELC_EVENT_GPT8_COMPARE_D 0x0EC +#define RA_ELC_EVENT_GPT8_COMPARE_E 0x0ED +#define RA_ELC_EVENT_GPT8_COMPARE_F 0x0EE +#define RA_ELC_EVENT_GPT8_COUNTER_OVERFLOW 0x0EF +#define RA_ELC_EVENT_GPT8_COUNTER_UNDERFLOW 0x0F0 +#define RA_ELC_EVENT_GPT8_PC 0x0F1 +#define RA_ELC_EVENT_GPT9_CAPTURE_COMPARE_A 0x0F2 +#define RA_ELC_EVENT_GPT9_CAPTURE_COMPARE_B 0x0F3 +#define RA_ELC_EVENT_GPT9_COMPARE_C 0x0F4 +#define RA_ELC_EVENT_GPT9_COMPARE_D 0x0F5 +#define RA_ELC_EVENT_GPT9_COMPARE_E 0x0F6 +#define RA_ELC_EVENT_GPT9_COMPARE_F 0x0F7 +#define RA_ELC_EVENT_GPT9_COUNTER_OVERFLOW 0x0F8 +#define RA_ELC_EVENT_GPT9_COUNTER_UNDERFLOW 0x0F9 +#define RA_ELC_EVENT_GPT9_PC 0x0FA +#define RA_ELC_EVENT_GPT10_CAPTURE_COMPARE_A 0x0FB +#define RA_ELC_EVENT_GPT10_CAPTURE_COMPARE_B 0x0FC +#define RA_ELC_EVENT_GPT10_COMPARE_C 0x0FD +#define RA_ELC_EVENT_GPT10_COMPARE_D 0x0FE +#define RA_ELC_EVENT_GPT10_COMPARE_E 0x0FF +#define RA_ELC_EVENT_GPT10_COMPARE_F 0x100 +#define RA_ELC_EVENT_GPT10_COUNTER_OVERFLOW 0x101 +#define RA_ELC_EVENT_GPT10_COUNTER_UNDERFLOW 0x102 +#define RA_ELC_EVENT_GPT10_PC 0x103 +#define RA_ELC_EVENT_GPT11_CAPTURE_COMPARE_A 0x104 +#define RA_ELC_EVENT_GPT11_CAPTURE_COMPARE_B 0x105 +#define RA_ELC_EVENT_GPT11_COMPARE_C 0x106 +#define RA_ELC_EVENT_GPT11_COMPARE_D 0x107 +#define RA_ELC_EVENT_GPT11_COMPARE_E 0x108 +#define RA_ELC_EVENT_GPT11_COMPARE_F 0x109 +#define RA_ELC_EVENT_GPT11_COUNTER_OVERFLOW 0x10A +#define RA_ELC_EVENT_GPT11_COUNTER_UNDERFLOW 0x10B +#define RA_ELC_EVENT_GPT12_CAPTURE_COMPARE_A 0x10D +#define RA_ELC_EVENT_GPT12_CAPTURE_COMPARE_B 0x10E +#define RA_ELC_EVENT_GPT12_COMPARE_C 0x10F +#define RA_ELC_EVENT_GPT12_COMPARE_D 0x110 +#define RA_ELC_EVENT_GPT12_COMPARE_E 0x111 +#define RA_ELC_EVENT_GPT12_COMPARE_F 0x112 +#define RA_ELC_EVENT_GPT12_COUNTER_OVERFLOW 0x113 +#define RA_ELC_EVENT_GPT12_COUNTER_UNDERFLOW 0x114 +#define RA_ELC_EVENT_GPT13_CAPTURE_COMPARE_A 0x116 +#define RA_ELC_EVENT_GPT13_CAPTURE_COMPARE_B 0x117 +#define RA_ELC_EVENT_GPT13_COMPARE_C 0x118 +#define RA_ELC_EVENT_GPT13_COMPARE_D 0x119 +#define RA_ELC_EVENT_GPT13_COMPARE_E 0x11A +#define RA_ELC_EVENT_GPT13_COMPARE_F 0x11B +#define RA_ELC_EVENT_GPT13_COUNTER_OVERFLOW 0x11C +#define RA_ELC_EVENT_GPT13_COUNTER_UNDERFLOW 0x11D +#define RA_ELC_EVENT_EDMAC0_EINT 0x120 +#define RA_ELC_EVENT_SCI0_RXI 0x124 +#define RA_ELC_EVENT_SCI0_TXI 0x125 +#define RA_ELC_EVENT_SCI0_TEI 0x126 +#define RA_ELC_EVENT_SCI0_ERI 0x127 +#define RA_ELC_EVENT_SCI0_AED 0x128 +#define RA_ELC_EVENT_SCI0_BFD 0x129 +#define RA_ELC_EVENT_SCI0_AM 0x12A +#define RA_ELC_EVENT_SCI1_RXI 0x12B +#define RA_ELC_EVENT_SCI1_TXI 0x12C +#define RA_ELC_EVENT_SCI1_TEI 0x12D +#define RA_ELC_EVENT_SCI1_ERI 0x12E +#define RA_ELC_EVENT_SCI1_AED 0x12F +#define RA_ELC_EVENT_SCI1_BFD 0x130 +#define RA_ELC_EVENT_SCI1_AM 0x131 +#define RA_ELC_EVENT_SCI2_RXI 0x132 +#define RA_ELC_EVENT_SCI2_TXI 0x133 +#define RA_ELC_EVENT_SCI2_TEI 0x134 +#define RA_ELC_EVENT_SCI2_ERI 0x135 +#define RA_ELC_EVENT_SCI2_AM 0x138 +#define RA_ELC_EVENT_SCI3_RXI 0x139 +#define RA_ELC_EVENT_SCI3_TXI 0x13A +#define RA_ELC_EVENT_SCI3_TEI 0x13B +#define RA_ELC_EVENT_SCI3_ERI 0x13C +#define RA_ELC_EVENT_SCI3_AM 0x13F +#define RA_ELC_EVENT_SCI4_RXI 0x140 +#define RA_ELC_EVENT_SCI4_TXI 0x141 +#define RA_ELC_EVENT_SCI4_TEI 0x142 +#define RA_ELC_EVENT_SCI4_ERI 0x143 +#define RA_ELC_EVENT_SCI4_AM 0x146 +#define RA_ELC_EVENT_SCI9_RXI 0x163 +#define RA_ELC_EVENT_SCI9_TXI 0x164 +#define RA_ELC_EVENT_SCI9_TEI 0x165 +#define RA_ELC_EVENT_SCI9_ERI 0x166 +#define RA_ELC_EVENT_SCI9_AM 0x169 +#define RA_ELC_EVENT_SPI0_RXI 0x178 +#define RA_ELC_EVENT_SPI0_TXI 0x179 +#define RA_ELC_EVENT_SPI0_IDLE 0x17A +#define RA_ELC_EVENT_SPI0_ERI 0x17B +#define RA_ELC_EVENT_SPI0_TEI 0x17C +#define RA_ELC_EVENT_SPI1_RXI 0x17D +#define RA_ELC_EVENT_SPI1_TXI 0x17E +#define RA_ELC_EVENT_SPI1_IDLE 0x17F +#define RA_ELC_EVENT_SPI1_ERI 0x180 +#define RA_ELC_EVENT_SPI1_TEI 0x181 +#define RA_ELC_EVENT_CAN_RXF 0x185 +#define RA_ELC_EVENT_CAN_GLERR 0x186 +#define RA_ELC_EVENT_CAN0_DMAREQ0 0x187 +#define RA_ELC_EVENT_CAN0_DMAREQ1 0x188 +#define RA_ELC_EVENT_CAN1_DMAREQ0 0x18B +#define RA_ELC_EVENT_CAN1_DMAREQ1 0x18C +#define RA_ELC_EVENT_CAN0_TX 0x18F +#define RA_ELC_EVENT_CAN0_CHERR 0x190 +#define RA_ELC_EVENT_CAN0_COMFRX 0x191 +#define RA_ELC_EVENT_CAN0_CF_DMAREQ 0x192 +#define RA_ELC_EVENT_CAN0_RXMB 0x193 +#define RA_ELC_EVENT_CAN1_TX 0x194 +#define RA_ELC_EVENT_CAN1_CHERR 0x195 +#define RA_ELC_EVENT_CAN1_COMFRX 0x196 +#define RA_ELC_EVENT_CAN1_CF_DMAREQ 0x197 +#define RA_ELC_EVENT_CAN1_RXMB 0x198 +#define RA_ELC_EVENT_CAN0_MRAM_ERI 0x19B +#define RA_ELC_EVENT_CAN1_MRAM_ERI 0x19C +#define RA_ELC_EVENT_I3C0_RESPONSE 0x19D +#define RA_ELC_EVENT_I3C0_COMMAND 0x19E +#define RA_ELC_EVENT_I3C0_IBI 0x19F +#define RA_ELC_EVENT_I3C0_RX 0x1A0 +#define RA_ELC_EVENT_IICB0_RXI 0x1A0 +#define RA_ELC_EVENT_I3C0_TX 0x1A1 +#define RA_ELC_EVENT_IICB0_TXI 0x1A1 +#define RA_ELC_EVENT_I3C0_RCV_STATUS 0x1A2 +#define RA_ELC_EVENT_I3C0_HRESP 0x1A3 +#define RA_ELC_EVENT_I3C0_HCMD 0x1A4 +#define RA_ELC_EVENT_I3C0_HRX 0x1A5 +#define RA_ELC_EVENT_I3C0_HTX 0x1A6 +#define RA_ELC_EVENT_I3C0_TEND 0x1A7 +#define RA_ELC_EVENT_IICB0_TEI 0x1A7 +#define RA_ELC_EVENT_I3C0_EEI 0x1A8 +#define RA_ELC_EVENT_IICB0_ERI 0x1A8 +#define RA_ELC_EVENT_I3C0_STEV 0x1A9 +#define RA_ELC_EVENT_I3C0_MREFOVF 0x1AA +#define RA_ELC_EVENT_I3C0_MREFCPT 0x1AB +#define RA_ELC_EVENT_I3C0_AMEV 0x1AC +#define RA_ELC_EVENT_I3C0_WU 0x1AD +#define RA_ELC_EVENT_ADC0_SCAN_END 0x1AE +#define RA_ELC_EVENT_ADC0_SCAN_END_B 0x1AF +#define RA_ELC_EVENT_ADC0_WINDOW_A 0x1B0 +#define RA_ELC_EVENT_ADC0_WINDOW_B 0x1B1 +#define RA_ELC_EVENT_ADC0_COMPARE_MATCH 0x1B2 +#define RA_ELC_EVENT_ADC0_COMPARE_MISMATCH 0x1B3 +#define RA_ELC_EVENT_ADC1_SCAN_END 0x1B4 +#define RA_ELC_EVENT_ADC1_SCAN_END_B 0x1B5 +#define RA_ELC_EVENT_ADC1_WINDOW_A 0x1B6 +#define RA_ELC_EVENT_ADC1_WINDOW_B 0x1B7 +#define RA_ELC_EVENT_ADC1_COMPARE_MATCH 0x1B8 +#define RA_ELC_EVENT_ADC1_COMPARE_MISMATCH 0x1B9 +#define RA_ELC_EVENT_DOC_INT 0x1BA +#define RA_ELC_EVENT_RSIP_TADI 0x1BC + +/* Possible peripherals to be linked to event signals */ +#define RA_ELC_PERIPHERAL_GPT_A 0 +#define RA_ELC_PERIPHERAL_GPT_B 1 +#define RA_ELC_PERIPHERAL_GPT_C 2 +#define RA_ELC_PERIPHERAL_GPT_D 3 +#define RA_ELC_PERIPHERAL_GPT_E 4 +#define RA_ELC_PERIPHERAL_GPT_F 5 +#define RA_ELC_PERIPHERAL_GPT_G 6 +#define RA_ELC_PERIPHERAL_GPT_H 7 +#define RA_ELC_PERIPHERAL_ADC0 8 +#define RA_ELC_PERIPHERAL_ADC0_B 9 +#define RA_ELC_PERIPHERAL_ADC1 10 +#define RA_ELC_PERIPHERAL_ADC1_B 11 +#define RA_ELC_PERIPHERAL_DAC0 12 +#define RA_ELC_PERIPHERAL_DAC1 13 +#define RA_ELC_PERIPHERAL_IOPORT1 14 +#define RA_ELC_PERIPHERAL_IOPORT2 15 +#define RA_ELC_PERIPHERAL_IOPORT3 16 +#define RA_ELC_PERIPHERAL_IOPORT4 17 +#define RA_ELC_PERIPHERAL_I3C 30 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA8T1_ELC_H_ */